| #!/usr/bin/env python |
| |
| # Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com> |
| |
| from __future__ import print_function |
| from capstone import * |
| from capstone.arm64 import * |
| from xprint import to_hex, to_x |
| |
| |
| ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" |
| |
| all_tests = ( |
| (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"), |
| ) |
| |
| |
| def print_insn_detail(insn): |
| # print address, mnemonic and operands |
| print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) |
| |
| # "data" instruction generated by SKIPDATA option has no detail |
| if insn.id == 0: |
| return |
| |
| if len(insn.operands) > 0: |
| print("\top_count: %u" % len(insn.operands)) |
| c = -1 |
| for i in insn.operands: |
| c += 1 |
| if i.type == ARM64_OP_REG: |
| print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) |
| if i.type == ARM64_OP_IMM: |
| print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) |
| if i.type == ARM64_OP_CIMM: |
| print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm)) |
| if i.type == ARM64_OP_FP: |
| print("\t\toperands[%u].type: FP = %f" % (c, i.fp)) |
| if i.type == ARM64_OP_MEM: |
| print("\t\toperands[%u].type: MEM" % c) |
| if i.mem.base != 0: |
| print("\t\t\toperands[%u].mem.base: REG = %s" \ |
| % (c, insn.reg_name(i.mem.base))) |
| if i.mem.index != 0: |
| print("\t\t\toperands[%u].mem.index: REG = %s" \ |
| % (c, insn.reg_name(i.mem.index))) |
| if i.mem.disp != 0: |
| print("\t\t\toperands[%u].mem.disp: 0x%s" \ |
| % (c, to_x(i.mem.disp))) |
| if i.type == ARM64_OP_REG_MRS: |
| print("\t\toperands[%u].type: REG_MRS = 0x%x" % (c, i.reg)) |
| if i.type == ARM64_OP_REG_MSR: |
| print("\t\toperands[%u].type: REG_MSR = 0x%x" % (c, i.reg)) |
| if i.type == ARM64_OP_PSTATE: |
| print("\t\toperands[%u].type: PSTATE = 0x%x" % (c, i.pstate)) |
| if i.type == ARM64_OP_SYS: |
| print("\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys)) |
| if i.type == ARM64_OP_PREFETCH: |
| print("\t\toperands[%u].type: PREFETCH = 0x%x" % (c, i.prefetch)) |
| if i.type == ARM64_OP_BARRIER: |
| print("\t\toperands[%u].type: BARRIER = 0x%x" % (c, i.barrier)) |
| |
| if i.shift.type != ARM64_SFT_INVALID and i.shift.value: |
| print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value)) |
| |
| if i.ext != ARM64_EXT_INVALID: |
| print("\t\t\tExt: %u" % i.ext) |
| |
| if i.vas != ARM64_VAS_INVALID: |
| print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas) |
| |
| if i.vess != ARM64_VESS_INVALID: |
| print("\t\t\tVector Element Size Specifier: %u" % i.vess) |
| |
| if i.vector_index != -1: |
| print("\t\t\tVector Index: %u" % i.vector_index) |
| |
| if insn.writeback: |
| print("\tWrite-back: True") |
| if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]: |
| print("\tCode condition: %u" % insn.cc) |
| if insn.update_flags: |
| print("\tUpdate-flags: True") |
| |
| |
| # ## Test class Cs |
| def test_class(): |
| |
| for (arch, mode, code, comment) in all_tests: |
| print("*" * 16) |
| print("Platform: %s" % comment) |
| print("Code: %s" % to_hex(code)) |
| print("Disasm:") |
| |
| try: |
| md = Cs(arch, mode) |
| md.detail = True |
| for insn in md.disasm(code, 0x2c): |
| print_insn_detail(insn) |
| print () |
| print("0x%x:\n" % (insn.address + insn.size)) |
| except CsError as e: |
| print("ERROR: %s" % e) |
| |
| |
| if __name__ == '__main__': |
| test_class() |