| /* Capstone Disassembly Engine */ |
| /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
| |
| #ifdef CAPSTONE_HAS_ARM64 |
| |
| #include <stdio.h> // debug |
| #include <string.h> |
| |
| #include "../../utils.h" |
| |
| #include "AArch64Mapping.h" |
| |
| #define GET_INSTRINFO_ENUM |
| #include "AArch64GenInstrInfo.inc" |
| |
| #ifndef CAPSTONE_DIET |
| static name_map reg_name_maps[] = { |
| { ARM64_REG_INVALID, NULL }, |
| |
| { ARM64_REG_X29, "x29"}, |
| { ARM64_REG_X30, "x30"}, |
| { ARM64_REG_NZCV, "nzcv"}, |
| { ARM64_REG_SP, "sp"}, |
| { ARM64_REG_WSP, "wsp"}, |
| { ARM64_REG_WZR, "wzr"}, |
| { ARM64_REG_XZR, "xzr"}, |
| { ARM64_REG_B0, "b0"}, |
| { ARM64_REG_B1, "b1"}, |
| { ARM64_REG_B2, "b2"}, |
| { ARM64_REG_B3, "b3"}, |
| { ARM64_REG_B4, "b4"}, |
| { ARM64_REG_B5, "b5"}, |
| { ARM64_REG_B6, "b6"}, |
| { ARM64_REG_B7, "b7"}, |
| { ARM64_REG_B8, "b8"}, |
| { ARM64_REG_B9, "b9"}, |
| { ARM64_REG_B10, "b10"}, |
| { ARM64_REG_B11, "b11"}, |
| { ARM64_REG_B12, "b12"}, |
| { ARM64_REG_B13, "b13"}, |
| { ARM64_REG_B14, "b14"}, |
| { ARM64_REG_B15, "b15"}, |
| { ARM64_REG_B16, "b16"}, |
| { ARM64_REG_B17, "b17"}, |
| { ARM64_REG_B18, "b18"}, |
| { ARM64_REG_B19, "b19"}, |
| { ARM64_REG_B20, "b20"}, |
| { ARM64_REG_B21, "b21"}, |
| { ARM64_REG_B22, "b22"}, |
| { ARM64_REG_B23, "b23"}, |
| { ARM64_REG_B24, "b24"}, |
| { ARM64_REG_B25, "b25"}, |
| { ARM64_REG_B26, "b26"}, |
| { ARM64_REG_B27, "b27"}, |
| { ARM64_REG_B28, "b28"}, |
| { ARM64_REG_B29, "b29"}, |
| { ARM64_REG_B30, "b30"}, |
| { ARM64_REG_B31, "b31"}, |
| { ARM64_REG_D0, "d0"}, |
| { ARM64_REG_D1, "d1"}, |
| { ARM64_REG_D2, "d2"}, |
| { ARM64_REG_D3, "d3"}, |
| { ARM64_REG_D4, "d4"}, |
| { ARM64_REG_D5, "d5"}, |
| { ARM64_REG_D6, "d6"}, |
| { ARM64_REG_D7, "d7"}, |
| { ARM64_REG_D8, "d8"}, |
| { ARM64_REG_D9, "d9"}, |
| { ARM64_REG_D10, "d10"}, |
| { ARM64_REG_D11, "d11"}, |
| { ARM64_REG_D12, "d12"}, |
| { ARM64_REG_D13, "d13"}, |
| { ARM64_REG_D14, "d14"}, |
| { ARM64_REG_D15, "d15"}, |
| { ARM64_REG_D16, "d16"}, |
| { ARM64_REG_D17, "d17"}, |
| { ARM64_REG_D18, "d18"}, |
| { ARM64_REG_D19, "d19"}, |
| { ARM64_REG_D20, "d20"}, |
| { ARM64_REG_D21, "d21"}, |
| { ARM64_REG_D22, "d22"}, |
| { ARM64_REG_D23, "d23"}, |
| { ARM64_REG_D24, "d24"}, |
| { ARM64_REG_D25, "d25"}, |
| { ARM64_REG_D26, "d26"}, |
| { ARM64_REG_D27, "d27"}, |
| { ARM64_REG_D28, "d28"}, |
| { ARM64_REG_D29, "d29"}, |
| { ARM64_REG_D30, "d30"}, |
| { ARM64_REG_D31, "d31"}, |
| { ARM64_REG_H0, "h0"}, |
| { ARM64_REG_H1, "h1"}, |
| { ARM64_REG_H2, "h2"}, |
| { ARM64_REG_H3, "h3"}, |
| { ARM64_REG_H4, "h4"}, |
| { ARM64_REG_H5, "h5"}, |
| { ARM64_REG_H6, "h6"}, |
| { ARM64_REG_H7, "h7"}, |
| { ARM64_REG_H8, "h8"}, |
| { ARM64_REG_H9, "h9"}, |
| { ARM64_REG_H10, "h10"}, |
| { ARM64_REG_H11, "h11"}, |
| { ARM64_REG_H12, "h12"}, |
| { ARM64_REG_H13, "h13"}, |
| { ARM64_REG_H14, "h14"}, |
| { ARM64_REG_H15, "h15"}, |
| { ARM64_REG_H16, "h16"}, |
| { ARM64_REG_H17, "h17"}, |
| { ARM64_REG_H18, "h18"}, |
| { ARM64_REG_H19, "h19"}, |
| { ARM64_REG_H20, "h20"}, |
| { ARM64_REG_H21, "h21"}, |
| { ARM64_REG_H22, "h22"}, |
| { ARM64_REG_H23, "h23"}, |
| { ARM64_REG_H24, "h24"}, |
| { ARM64_REG_H25, "h25"}, |
| { ARM64_REG_H26, "h26"}, |
| { ARM64_REG_H27, "h27"}, |
| { ARM64_REG_H28, "h28"}, |
| { ARM64_REG_H29, "h29"}, |
| { ARM64_REG_H30, "h30"}, |
| { ARM64_REG_H31, "h31"}, |
| { ARM64_REG_Q0, "q0"}, |
| { ARM64_REG_Q1, "q1"}, |
| { ARM64_REG_Q2, "q2"}, |
| { ARM64_REG_Q3, "q3"}, |
| { ARM64_REG_Q4, "q4"}, |
| { ARM64_REG_Q5, "q5"}, |
| { ARM64_REG_Q6, "q6"}, |
| { ARM64_REG_Q7, "q7"}, |
| { ARM64_REG_Q8, "q8"}, |
| { ARM64_REG_Q9, "q9"}, |
| { ARM64_REG_Q10, "q10"}, |
| { ARM64_REG_Q11, "q11"}, |
| { ARM64_REG_Q12, "q12"}, |
| { ARM64_REG_Q13, "q13"}, |
| { ARM64_REG_Q14, "q14"}, |
| { ARM64_REG_Q15, "q15"}, |
| { ARM64_REG_Q16, "q16"}, |
| { ARM64_REG_Q17, "q17"}, |
| { ARM64_REG_Q18, "q18"}, |
| { ARM64_REG_Q19, "q19"}, |
| { ARM64_REG_Q20, "q20"}, |
| { ARM64_REG_Q21, "q21"}, |
| { ARM64_REG_Q22, "q22"}, |
| { ARM64_REG_Q23, "q23"}, |
| { ARM64_REG_Q24, "q24"}, |
| { ARM64_REG_Q25, "q25"}, |
| { ARM64_REG_Q26, "q26"}, |
| { ARM64_REG_Q27, "q27"}, |
| { ARM64_REG_Q28, "q28"}, |
| { ARM64_REG_Q29, "q29"}, |
| { ARM64_REG_Q30, "q30"}, |
| { ARM64_REG_Q31, "q31"}, |
| { ARM64_REG_S0, "s0"}, |
| { ARM64_REG_S1, "s1"}, |
| { ARM64_REG_S2, "s2"}, |
| { ARM64_REG_S3, "s3"}, |
| { ARM64_REG_S4, "s4"}, |
| { ARM64_REG_S5, "s5"}, |
| { ARM64_REG_S6, "s6"}, |
| { ARM64_REG_S7, "s7"}, |
| { ARM64_REG_S8, "s8"}, |
| { ARM64_REG_S9, "s9"}, |
| { ARM64_REG_S10, "s10"}, |
| { ARM64_REG_S11, "s11"}, |
| { ARM64_REG_S12, "s12"}, |
| { ARM64_REG_S13, "s13"}, |
| { ARM64_REG_S14, "s14"}, |
| { ARM64_REG_S15, "s15"}, |
| { ARM64_REG_S16, "s16"}, |
| { ARM64_REG_S17, "s17"}, |
| { ARM64_REG_S18, "s18"}, |
| { ARM64_REG_S19, "s19"}, |
| { ARM64_REG_S20, "s20"}, |
| { ARM64_REG_S21, "s21"}, |
| { ARM64_REG_S22, "s22"}, |
| { ARM64_REG_S23, "s23"}, |
| { ARM64_REG_S24, "s24"}, |
| { ARM64_REG_S25, "s25"}, |
| { ARM64_REG_S26, "s26"}, |
| { ARM64_REG_S27, "s27"}, |
| { ARM64_REG_S28, "s28"}, |
| { ARM64_REG_S29, "s29"}, |
| { ARM64_REG_S30, "s30"}, |
| { ARM64_REG_S31, "s31"}, |
| { ARM64_REG_W0, "w0"}, |
| { ARM64_REG_W1, "w1"}, |
| { ARM64_REG_W2, "w2"}, |
| { ARM64_REG_W3, "w3"}, |
| { ARM64_REG_W4, "w4"}, |
| { ARM64_REG_W5, "w5"}, |
| { ARM64_REG_W6, "w6"}, |
| { ARM64_REG_W7, "w7"}, |
| { ARM64_REG_W8, "w8"}, |
| { ARM64_REG_W9, "w9"}, |
| { ARM64_REG_W10, "w10"}, |
| { ARM64_REG_W11, "w11"}, |
| { ARM64_REG_W12, "w12"}, |
| { ARM64_REG_W13, "w13"}, |
| { ARM64_REG_W14, "w14"}, |
| { ARM64_REG_W15, "w15"}, |
| { ARM64_REG_W16, "w16"}, |
| { ARM64_REG_W17, "w17"}, |
| { ARM64_REG_W18, "w18"}, |
| { ARM64_REG_W19, "w19"}, |
| { ARM64_REG_W20, "w20"}, |
| { ARM64_REG_W21, "w21"}, |
| { ARM64_REG_W22, "w22"}, |
| { ARM64_REG_W23, "w23"}, |
| { ARM64_REG_W24, "w24"}, |
| { ARM64_REG_W25, "w25"}, |
| { ARM64_REG_W26, "w26"}, |
| { ARM64_REG_W27, "w27"}, |
| { ARM64_REG_W28, "w28"}, |
| { ARM64_REG_W29, "w29"}, |
| { ARM64_REG_W30, "w30"}, |
| { ARM64_REG_X0, "x0"}, |
| { ARM64_REG_X1, "x1"}, |
| { ARM64_REG_X2, "x2"}, |
| { ARM64_REG_X3, "x3"}, |
| { ARM64_REG_X4, "x4"}, |
| { ARM64_REG_X5, "x5"}, |
| { ARM64_REG_X6, "x6"}, |
| { ARM64_REG_X7, "x7"}, |
| { ARM64_REG_X8, "x8"}, |
| { ARM64_REG_X9, "x9"}, |
| { ARM64_REG_X10, "x10"}, |
| { ARM64_REG_X11, "x11"}, |
| { ARM64_REG_X12, "x12"}, |
| { ARM64_REG_X13, "x13"}, |
| { ARM64_REG_X14, "x14"}, |
| { ARM64_REG_X15, "x15"}, |
| { ARM64_REG_X16, "x16"}, |
| { ARM64_REG_X17, "x17"}, |
| { ARM64_REG_X18, "x18"}, |
| { ARM64_REG_X19, "x19"}, |
| { ARM64_REG_X20, "x20"}, |
| { ARM64_REG_X21, "x21"}, |
| { ARM64_REG_X22, "x22"}, |
| { ARM64_REG_X23, "x23"}, |
| { ARM64_REG_X24, "x24"}, |
| { ARM64_REG_X25, "x25"}, |
| { ARM64_REG_X26, "x26"}, |
| { ARM64_REG_X27, "x27"}, |
| { ARM64_REG_X28, "x28"}, |
| |
| { ARM64_REG_V0, "v0"}, |
| { ARM64_REG_V1, "v1"}, |
| { ARM64_REG_V2, "v2"}, |
| { ARM64_REG_V3, "v3"}, |
| { ARM64_REG_V4, "v4"}, |
| { ARM64_REG_V5, "v5"}, |
| { ARM64_REG_V6, "v6"}, |
| { ARM64_REG_V7, "v7"}, |
| { ARM64_REG_V8, "v8"}, |
| { ARM64_REG_V9, "v9"}, |
| { ARM64_REG_V10, "v10"}, |
| { ARM64_REG_V11, "v11"}, |
| { ARM64_REG_V12, "v12"}, |
| { ARM64_REG_V13, "v13"}, |
| { ARM64_REG_V14, "v14"}, |
| { ARM64_REG_V15, "v15"}, |
| { ARM64_REG_V16, "v16"}, |
| { ARM64_REG_V17, "v17"}, |
| { ARM64_REG_V18, "v18"}, |
| { ARM64_REG_V19, "v19"}, |
| { ARM64_REG_V20, "v20"}, |
| { ARM64_REG_V21, "v21"}, |
| { ARM64_REG_V22, "v22"}, |
| { ARM64_REG_V23, "v23"}, |
| { ARM64_REG_V24, "v24"}, |
| { ARM64_REG_V25, "v25"}, |
| { ARM64_REG_V26, "v26"}, |
| { ARM64_REG_V27, "v27"}, |
| { ARM64_REG_V28, "v28"}, |
| { ARM64_REG_V29, "v29"}, |
| { ARM64_REG_V30, "v30"}, |
| { ARM64_REG_V31, "v31"}, |
| }; |
| #endif |
| |
| const char *AArch64_reg_name(csh handle, unsigned int reg) |
| { |
| #ifndef CAPSTONE_DIET |
| if (reg >= ARM64_REG_ENDING) |
| return NULL; |
| |
| return reg_name_maps[reg].name; |
| #else |
| return NULL; |
| #endif |
| } |
| |
| static insn_map insns[] = { |
| // dummy item |
| { |
| 0, 0, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { 0 }, 0, 0 |
| #endif |
| }, |
| |
| #include "AArch64MappingInsn.inc" |
| }; |
| |
| // some alias instruction only need to be defined locally to satisfy |
| // some lookup functions |
| // just make sure these IDs never reuse any other IDs ARM_INS_* |
| #define ARM64_INS_NEGS (unsigned short)-1 |
| #define ARM64_INS_NGCS (unsigned short)-2 |
| |
| // given internal insn id, return public instruction info |
| void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) |
| { |
| int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); |
| if (i != 0) { |
| insn->id = insns[i].mapid; |
| |
| if (h->detail) { |
| #ifndef CAPSTONE_DIET |
| cs_struct handle; |
| handle.detail = h->detail; |
| |
| memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); |
| insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); |
| |
| memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); |
| insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); |
| |
| memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); |
| insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); |
| |
| insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV); |
| #endif |
| } |
| } |
| } |
| |
| static name_map insn_name_maps[] = { |
| { ARM64_INS_INVALID, NULL }, |
| |
| { ARM64_INS_ABS, "abs" }, |
| { ARM64_INS_ADC, "adc" }, |
| { ARM64_INS_ADDHN, "addhn" }, |
| { ARM64_INS_ADDHN2, "addhn2" }, |
| { ARM64_INS_ADDP, "addp" }, |
| { ARM64_INS_ADD, "add" }, |
| { ARM64_INS_ADDV, "addv" }, |
| { ARM64_INS_ADR, "adr" }, |
| { ARM64_INS_ADRP, "adrp" }, |
| { ARM64_INS_AESD, "aesd" }, |
| { ARM64_INS_AESE, "aese" }, |
| { ARM64_INS_AESIMC, "aesimc" }, |
| { ARM64_INS_AESMC, "aesmc" }, |
| { ARM64_INS_AND, "and" }, |
| { ARM64_INS_ASR, "asr" }, |
| { ARM64_INS_B, "b" }, |
| { ARM64_INS_BFM, "bfm" }, |
| { ARM64_INS_BIC, "bic" }, |
| { ARM64_INS_BIF, "bif" }, |
| { ARM64_INS_BIT, "bit" }, |
| { ARM64_INS_BL, "bl" }, |
| { ARM64_INS_BLR, "blr" }, |
| { ARM64_INS_BR, "br" }, |
| { ARM64_INS_BRK, "brk" }, |
| { ARM64_INS_BSL, "bsl" }, |
| { ARM64_INS_CBNZ, "cbnz" }, |
| { ARM64_INS_CBZ, "cbz" }, |
| { ARM64_INS_CCMN, "ccmn" }, |
| { ARM64_INS_CCMP, "ccmp" }, |
| { ARM64_INS_CLREX, "clrex" }, |
| { ARM64_INS_CLS, "cls" }, |
| { ARM64_INS_CLZ, "clz" }, |
| { ARM64_INS_CMEQ, "cmeq" }, |
| { ARM64_INS_CMGE, "cmge" }, |
| { ARM64_INS_CMGT, "cmgt" }, |
| { ARM64_INS_CMHI, "cmhi" }, |
| { ARM64_INS_CMHS, "cmhs" }, |
| { ARM64_INS_CMLE, "cmle" }, |
| { ARM64_INS_CMLT, "cmlt" }, |
| { ARM64_INS_CMTST, "cmtst" }, |
| { ARM64_INS_CNT, "cnt" }, |
| { ARM64_INS_MOV, "mov" }, |
| { ARM64_INS_CRC32B, "crc32b" }, |
| { ARM64_INS_CRC32CB, "crc32cb" }, |
| { ARM64_INS_CRC32CH, "crc32ch" }, |
| { ARM64_INS_CRC32CW, "crc32cw" }, |
| { ARM64_INS_CRC32CX, "crc32cx" }, |
| { ARM64_INS_CRC32H, "crc32h" }, |
| { ARM64_INS_CRC32W, "crc32w" }, |
| { ARM64_INS_CRC32X, "crc32x" }, |
| { ARM64_INS_CSEL, "csel" }, |
| { ARM64_INS_CSINC, "csinc" }, |
| { ARM64_INS_CSINV, "csinv" }, |
| { ARM64_INS_CSNEG, "csneg" }, |
| { ARM64_INS_DCPS1, "dcps1" }, |
| { ARM64_INS_DCPS2, "dcps2" }, |
| { ARM64_INS_DCPS3, "dcps3" }, |
| { ARM64_INS_DMB, "dmb" }, |
| { ARM64_INS_DRPS, "drps" }, |
| { ARM64_INS_DSB, "dsb" }, |
| { ARM64_INS_DUP, "dup" }, |
| { ARM64_INS_EON, "eon" }, |
| { ARM64_INS_EOR, "eor" }, |
| { ARM64_INS_ERET, "eret" }, |
| { ARM64_INS_EXTR, "extr" }, |
| { ARM64_INS_EXT, "ext" }, |
| { ARM64_INS_FABD, "fabd" }, |
| { ARM64_INS_FABS, "fabs" }, |
| { ARM64_INS_FACGE, "facge" }, |
| { ARM64_INS_FACGT, "facgt" }, |
| { ARM64_INS_FADD, "fadd" }, |
| { ARM64_INS_FADDP, "faddp" }, |
| { ARM64_INS_FCCMP, "fccmp" }, |
| { ARM64_INS_FCCMPE, "fccmpe" }, |
| { ARM64_INS_FCMEQ, "fcmeq" }, |
| { ARM64_INS_FCMGE, "fcmge" }, |
| { ARM64_INS_FCMGT, "fcmgt" }, |
| { ARM64_INS_FCMLE, "fcmle" }, |
| { ARM64_INS_FCMLT, "fcmlt" }, |
| { ARM64_INS_FCMP, "fcmp" }, |
| { ARM64_INS_FCMPE, "fcmpe" }, |
| { ARM64_INS_FCSEL, "fcsel" }, |
| { ARM64_INS_FCVTAS, "fcvtas" }, |
| { ARM64_INS_FCVTAU, "fcvtau" }, |
| { ARM64_INS_FCVT, "fcvt" }, |
| { ARM64_INS_FCVTL, "fcvtl" }, |
| { ARM64_INS_FCVTL2, "fcvtl2" }, |
| { ARM64_INS_FCVTMS, "fcvtms" }, |
| { ARM64_INS_FCVTMU, "fcvtmu" }, |
| { ARM64_INS_FCVTNS, "fcvtns" }, |
| { ARM64_INS_FCVTNU, "fcvtnu" }, |
| { ARM64_INS_FCVTN, "fcvtn" }, |
| { ARM64_INS_FCVTN2, "fcvtn2" }, |
| { ARM64_INS_FCVTPS, "fcvtps" }, |
| { ARM64_INS_FCVTPU, "fcvtpu" }, |
| { ARM64_INS_FCVTXN, "fcvtxn" }, |
| { ARM64_INS_FCVTXN2, "fcvtxn2" }, |
| { ARM64_INS_FCVTZS, "fcvtzs" }, |
| { ARM64_INS_FCVTZU, "fcvtzu" }, |
| { ARM64_INS_FDIV, "fdiv" }, |
| { ARM64_INS_FMADD, "fmadd" }, |
| { ARM64_INS_FMAX, "fmax" }, |
| { ARM64_INS_FMAXNM, "fmaxnm" }, |
| { ARM64_INS_FMAXNMP, "fmaxnmp" }, |
| { ARM64_INS_FMAXNMV, "fmaxnmv" }, |
| { ARM64_INS_FMAXP, "fmaxp" }, |
| { ARM64_INS_FMAXV, "fmaxv" }, |
| { ARM64_INS_FMIN, "fmin" }, |
| { ARM64_INS_FMINNM, "fminnm" }, |
| { ARM64_INS_FMINNMP, "fminnmp" }, |
| { ARM64_INS_FMINNMV, "fminnmv" }, |
| { ARM64_INS_FMINP, "fminp" }, |
| { ARM64_INS_FMINV, "fminv" }, |
| { ARM64_INS_FMLA, "fmla" }, |
| { ARM64_INS_FMLS, "fmls" }, |
| { ARM64_INS_FMOV, "fmov" }, |
| { ARM64_INS_FMSUB, "fmsub" }, |
| { ARM64_INS_FMUL, "fmul" }, |
| { ARM64_INS_FMULX, "fmulx" }, |
| { ARM64_INS_FNEG, "fneg" }, |
| { ARM64_INS_FNMADD, "fnmadd" }, |
| { ARM64_INS_FNMSUB, "fnmsub" }, |
| { ARM64_INS_FNMUL, "fnmul" }, |
| { ARM64_INS_FRECPE, "frecpe" }, |
| { ARM64_INS_FRECPS, "frecps" }, |
| { ARM64_INS_FRECPX, "frecpx" }, |
| { ARM64_INS_FRINTA, "frinta" }, |
| { ARM64_INS_FRINTI, "frinti" }, |
| { ARM64_INS_FRINTM, "frintm" }, |
| { ARM64_INS_FRINTN, "frintn" }, |
| { ARM64_INS_FRINTP, "frintp" }, |
| { ARM64_INS_FRINTX, "frintx" }, |
| { ARM64_INS_FRINTZ, "frintz" }, |
| { ARM64_INS_FRSQRTE, "frsqrte" }, |
| { ARM64_INS_FRSQRTS, "frsqrts" }, |
| { ARM64_INS_FSQRT, "fsqrt" }, |
| { ARM64_INS_FSUB, "fsub" }, |
| { ARM64_INS_HINT, "hint" }, |
| { ARM64_INS_HLT, "hlt" }, |
| { ARM64_INS_HVC, "hvc" }, |
| { ARM64_INS_INS, "ins" }, |
| { ARM64_INS_ISB, "isb" }, |
| { ARM64_INS_LD1, "ld1" }, |
| { ARM64_INS_LD1R, "ld1r" }, |
| { ARM64_INS_LD2R, "ld2r" }, |
| { ARM64_INS_LD2, "ld2" }, |
| { ARM64_INS_LD3R, "ld3r" }, |
| { ARM64_INS_LD3, "ld3" }, |
| { ARM64_INS_LD4, "ld4" }, |
| { ARM64_INS_LD4R, "ld4r" }, |
| { ARM64_INS_LDARB, "ldarb" }, |
| { ARM64_INS_LDARH, "ldarh" }, |
| { ARM64_INS_LDAR, "ldar" }, |
| { ARM64_INS_LDAXP, "ldaxp" }, |
| { ARM64_INS_LDAXRB, "ldaxrb" }, |
| { ARM64_INS_LDAXRH, "ldaxrh" }, |
| { ARM64_INS_LDAXR, "ldaxr" }, |
| { ARM64_INS_LDNP, "ldnp" }, |
| { ARM64_INS_LDP, "ldp" }, |
| { ARM64_INS_LDPSW, "ldpsw" }, |
| { ARM64_INS_LDRB, "ldrb" }, |
| { ARM64_INS_LDR, "ldr" }, |
| { ARM64_INS_LDRH, "ldrh" }, |
| { ARM64_INS_LDRSB, "ldrsb" }, |
| { ARM64_INS_LDRSH, "ldrsh" }, |
| { ARM64_INS_LDRSW, "ldrsw" }, |
| { ARM64_INS_LDTRB, "ldtrb" }, |
| { ARM64_INS_LDTRH, "ldtrh" }, |
| { ARM64_INS_LDTRSB, "ldtrsb" }, |
| { ARM64_INS_LDTRSH, "ldtrsh" }, |
| { ARM64_INS_LDTRSW, "ldtrsw" }, |
| { ARM64_INS_LDTR, "ldtr" }, |
| { ARM64_INS_LDURB, "ldurb" }, |
| { ARM64_INS_LDUR, "ldur" }, |
| { ARM64_INS_LDURH, "ldurh" }, |
| { ARM64_INS_LDURSB, "ldursb" }, |
| { ARM64_INS_LDURSH, "ldursh" }, |
| { ARM64_INS_LDURSW, "ldursw" }, |
| { ARM64_INS_LDXP, "ldxp" }, |
| { ARM64_INS_LDXRB, "ldxrb" }, |
| { ARM64_INS_LDXRH, "ldxrh" }, |
| { ARM64_INS_LDXR, "ldxr" }, |
| { ARM64_INS_LSL, "lsl" }, |
| { ARM64_INS_LSR, "lsr" }, |
| { ARM64_INS_MADD, "madd" }, |
| { ARM64_INS_MLA, "mla" }, |
| { ARM64_INS_MLS, "mls" }, |
| { ARM64_INS_MOVI, "movi" }, |
| { ARM64_INS_MOVK, "movk" }, |
| { ARM64_INS_MOVN, "movn" }, |
| { ARM64_INS_MOVZ, "movz" }, |
| { ARM64_INS_MRS, "mrs" }, |
| { ARM64_INS_MSR, "msr" }, |
| { ARM64_INS_MSUB, "msub" }, |
| { ARM64_INS_MUL, "mul" }, |
| { ARM64_INS_MVNI, "mvni" }, |
| { ARM64_INS_NEG, "neg" }, |
| { ARM64_INS_NOT, "not" }, |
| { ARM64_INS_ORN, "orn" }, |
| { ARM64_INS_ORR, "orr" }, |
| { ARM64_INS_PMULL2, "pmull2" }, |
| { ARM64_INS_PMULL, "pmull" }, |
| { ARM64_INS_PMUL, "pmul" }, |
| { ARM64_INS_PRFM, "prfm" }, |
| { ARM64_INS_PRFUM, "prfum" }, |
| { ARM64_INS_RADDHN, "raddhn" }, |
| { ARM64_INS_RADDHN2, "raddhn2" }, |
| { ARM64_INS_RBIT, "rbit" }, |
| { ARM64_INS_RET, "ret" }, |
| { ARM64_INS_REV16, "rev16" }, |
| { ARM64_INS_REV32, "rev32" }, |
| { ARM64_INS_REV64, "rev64" }, |
| { ARM64_INS_REV, "rev" }, |
| { ARM64_INS_ROR, "ror" }, |
| { ARM64_INS_RSHRN2, "rshrn2" }, |
| { ARM64_INS_RSHRN, "rshrn" }, |
| { ARM64_INS_RSUBHN, "rsubhn" }, |
| { ARM64_INS_RSUBHN2, "rsubhn2" }, |
| { ARM64_INS_SABAL2, "sabal2" }, |
| { ARM64_INS_SABAL, "sabal" }, |
| { ARM64_INS_SABA, "saba" }, |
| { ARM64_INS_SABDL2, "sabdl2" }, |
| { ARM64_INS_SABDL, "sabdl" }, |
| { ARM64_INS_SABD, "sabd" }, |
| { ARM64_INS_SADALP, "sadalp" }, |
| { ARM64_INS_SADDLP, "saddlp" }, |
| { ARM64_INS_SADDLV, "saddlv" }, |
| { ARM64_INS_SADDL2, "saddl2" }, |
| { ARM64_INS_SADDL, "saddl" }, |
| { ARM64_INS_SADDW2, "saddw2" }, |
| { ARM64_INS_SADDW, "saddw" }, |
| { ARM64_INS_SBC, "sbc" }, |
| { ARM64_INS_SBFM, "sbfm" }, |
| { ARM64_INS_SCVTF, "scvtf" }, |
| { ARM64_INS_SDIV, "sdiv" }, |
| { ARM64_INS_SHA1C, "sha1c" }, |
| { ARM64_INS_SHA1H, "sha1h" }, |
| { ARM64_INS_SHA1M, "sha1m" }, |
| { ARM64_INS_SHA1P, "sha1p" }, |
| { ARM64_INS_SHA1SU0, "sha1su0" }, |
| { ARM64_INS_SHA1SU1, "sha1su1" }, |
| { ARM64_INS_SHA256H2, "sha256h2" }, |
| { ARM64_INS_SHA256H, "sha256h" }, |
| { ARM64_INS_SHA256SU0, "sha256su0" }, |
| { ARM64_INS_SHA256SU1, "sha256su1" }, |
| { ARM64_INS_SHADD, "shadd" }, |
| { ARM64_INS_SHLL2, "shll2" }, |
| { ARM64_INS_SHLL, "shll" }, |
| { ARM64_INS_SHL, "shl" }, |
| { ARM64_INS_SHRN2, "shrn2" }, |
| { ARM64_INS_SHRN, "shrn" }, |
| { ARM64_INS_SHSUB, "shsub" }, |
| { ARM64_INS_SLI, "sli" }, |
| { ARM64_INS_SMADDL, "smaddl" }, |
| { ARM64_INS_SMAXP, "smaxp" }, |
| { ARM64_INS_SMAXV, "smaxv" }, |
| { ARM64_INS_SMAX, "smax" }, |
| { ARM64_INS_SMC, "smc" }, |
| { ARM64_INS_SMINP, "sminp" }, |
| { ARM64_INS_SMINV, "sminv" }, |
| { ARM64_INS_SMIN, "smin" }, |
| { ARM64_INS_SMLAL2, "smlal2" }, |
| { ARM64_INS_SMLAL, "smlal" }, |
| { ARM64_INS_SMLSL2, "smlsl2" }, |
| { ARM64_INS_SMLSL, "smlsl" }, |
| { ARM64_INS_SMOV, "smov" }, |
| { ARM64_INS_SMSUBL, "smsubl" }, |
| { ARM64_INS_SMULH, "smulh" }, |
| { ARM64_INS_SMULL2, "smull2" }, |
| { ARM64_INS_SMULL, "smull" }, |
| { ARM64_INS_SQABS, "sqabs" }, |
| { ARM64_INS_SQADD, "sqadd" }, |
| { ARM64_INS_SQDMLAL, "sqdmlal" }, |
| { ARM64_INS_SQDMLAL2, "sqdmlal2" }, |
| { ARM64_INS_SQDMLSL, "sqdmlsl" }, |
| { ARM64_INS_SQDMLSL2, "sqdmlsl2" }, |
| { ARM64_INS_SQDMULH, "sqdmulh" }, |
| { ARM64_INS_SQDMULL, "sqdmull" }, |
| { ARM64_INS_SQDMULL2, "sqdmull2" }, |
| { ARM64_INS_SQNEG, "sqneg" }, |
| { ARM64_INS_SQRDMULH, "sqrdmulh" }, |
| { ARM64_INS_SQRSHL, "sqrshl" }, |
| { ARM64_INS_SQRSHRN, "sqrshrn" }, |
| { ARM64_INS_SQRSHRN2, "sqrshrn2" }, |
| { ARM64_INS_SQRSHRUN, "sqrshrun" }, |
| { ARM64_INS_SQRSHRUN2, "sqrshrun2" }, |
| { ARM64_INS_SQSHLU, "sqshlu" }, |
| { ARM64_INS_SQSHL, "sqshl" }, |
| { ARM64_INS_SQSHRN, "sqshrn" }, |
| { ARM64_INS_SQSHRN2, "sqshrn2" }, |
| { ARM64_INS_SQSHRUN, "sqshrun" }, |
| { ARM64_INS_SQSHRUN2, "sqshrun2" }, |
| { ARM64_INS_SQSUB, "sqsub" }, |
| { ARM64_INS_SQXTN2, "sqxtn2" }, |
| { ARM64_INS_SQXTN, "sqxtn" }, |
| { ARM64_INS_SQXTUN2, "sqxtun2" }, |
| { ARM64_INS_SQXTUN, "sqxtun" }, |
| { ARM64_INS_SRHADD, "srhadd" }, |
| { ARM64_INS_SRI, "sri" }, |
| { ARM64_INS_SRSHL, "srshl" }, |
| { ARM64_INS_SRSHR, "srshr" }, |
| { ARM64_INS_SRSRA, "srsra" }, |
| { ARM64_INS_SSHLL2, "sshll2" }, |
| { ARM64_INS_SSHLL, "sshll" }, |
| { ARM64_INS_SSHL, "sshl" }, |
| { ARM64_INS_SSHR, "sshr" }, |
| { ARM64_INS_SSRA, "ssra" }, |
| { ARM64_INS_SSUBL2, "ssubl2" }, |
| { ARM64_INS_SSUBL, "ssubl" }, |
| { ARM64_INS_SSUBW2, "ssubw2" }, |
| { ARM64_INS_SSUBW, "ssubw" }, |
| { ARM64_INS_ST1, "st1" }, |
| { ARM64_INS_ST2, "st2" }, |
| { ARM64_INS_ST3, "st3" }, |
| { ARM64_INS_ST4, "st4" }, |
| { ARM64_INS_STLRB, "stlrb" }, |
| { ARM64_INS_STLRH, "stlrh" }, |
| { ARM64_INS_STLR, "stlr" }, |
| { ARM64_INS_STLXP, "stlxp" }, |
| { ARM64_INS_STLXRB, "stlxrb" }, |
| { ARM64_INS_STLXRH, "stlxrh" }, |
| { ARM64_INS_STLXR, "stlxr" }, |
| { ARM64_INS_STNP, "stnp" }, |
| { ARM64_INS_STP, "stp" }, |
| { ARM64_INS_STRB, "strb" }, |
| { ARM64_INS_STR, "str" }, |
| { ARM64_INS_STRH, "strh" }, |
| { ARM64_INS_STTRB, "sttrb" }, |
| { ARM64_INS_STTRH, "sttrh" }, |
| { ARM64_INS_STTR, "sttr" }, |
| { ARM64_INS_STURB, "sturb" }, |
| { ARM64_INS_STUR, "stur" }, |
| { ARM64_INS_STURH, "sturh" }, |
| { ARM64_INS_STXP, "stxp" }, |
| { ARM64_INS_STXRB, "stxrb" }, |
| { ARM64_INS_STXRH, "stxrh" }, |
| { ARM64_INS_STXR, "stxr" }, |
| { ARM64_INS_SUBHN, "subhn" }, |
| { ARM64_INS_SUBHN2, "subhn2" }, |
| { ARM64_INS_SUB, "sub" }, |
| { ARM64_INS_SUQADD, "suqadd" }, |
| { ARM64_INS_SVC, "svc" }, |
| { ARM64_INS_SYSL, "sysl" }, |
| { ARM64_INS_SYS, "sys" }, |
| { ARM64_INS_TBL, "tbl" }, |
| { ARM64_INS_TBNZ, "tbnz" }, |
| { ARM64_INS_TBX, "tbx" }, |
| { ARM64_INS_TBZ, "tbz" }, |
| { ARM64_INS_TRN1, "trn1" }, |
| { ARM64_INS_TRN2, "trn2" }, |
| { ARM64_INS_UABAL2, "uabal2" }, |
| { ARM64_INS_UABAL, "uabal" }, |
| { ARM64_INS_UABA, "uaba" }, |
| { ARM64_INS_UABDL2, "uabdl2" }, |
| { ARM64_INS_UABDL, "uabdl" }, |
| { ARM64_INS_UABD, "uabd" }, |
| { ARM64_INS_UADALP, "uadalp" }, |
| { ARM64_INS_UADDLP, "uaddlp" }, |
| { ARM64_INS_UADDLV, "uaddlv" }, |
| { ARM64_INS_UADDL2, "uaddl2" }, |
| { ARM64_INS_UADDL, "uaddl" }, |
| { ARM64_INS_UADDW2, "uaddw2" }, |
| { ARM64_INS_UADDW, "uaddw" }, |
| { ARM64_INS_UBFM, "ubfm" }, |
| { ARM64_INS_UCVTF, "ucvtf" }, |
| { ARM64_INS_UDIV, "udiv" }, |
| { ARM64_INS_UHADD, "uhadd" }, |
| { ARM64_INS_UHSUB, "uhsub" }, |
| { ARM64_INS_UMADDL, "umaddl" }, |
| { ARM64_INS_UMAXP, "umaxp" }, |
| { ARM64_INS_UMAXV, "umaxv" }, |
| { ARM64_INS_UMAX, "umax" }, |
| { ARM64_INS_UMINP, "uminp" }, |
| { ARM64_INS_UMINV, "uminv" }, |
| { ARM64_INS_UMIN, "umin" }, |
| { ARM64_INS_UMLAL2, "umlal2" }, |
| { ARM64_INS_UMLAL, "umlal" }, |
| { ARM64_INS_UMLSL2, "umlsl2" }, |
| { ARM64_INS_UMLSL, "umlsl" }, |
| { ARM64_INS_UMOV, "umov" }, |
| { ARM64_INS_UMSUBL, "umsubl" }, |
| { ARM64_INS_UMULH, "umulh" }, |
| { ARM64_INS_UMULL2, "umull2" }, |
| { ARM64_INS_UMULL, "umull" }, |
| { ARM64_INS_UQADD, "uqadd" }, |
| { ARM64_INS_UQRSHL, "uqrshl" }, |
| { ARM64_INS_UQRSHRN, "uqrshrn" }, |
| { ARM64_INS_UQRSHRN2, "uqrshrn2" }, |
| { ARM64_INS_UQSHL, "uqshl" }, |
| { ARM64_INS_UQSHRN, "uqshrn" }, |
| { ARM64_INS_UQSHRN2, "uqshrn2" }, |
| { ARM64_INS_UQSUB, "uqsub" }, |
| { ARM64_INS_UQXTN2, "uqxtn2" }, |
| { ARM64_INS_UQXTN, "uqxtn" }, |
| { ARM64_INS_URECPE, "urecpe" }, |
| { ARM64_INS_URHADD, "urhadd" }, |
| { ARM64_INS_URSHL, "urshl" }, |
| { ARM64_INS_URSHR, "urshr" }, |
| { ARM64_INS_URSQRTE, "ursqrte" }, |
| { ARM64_INS_URSRA, "ursra" }, |
| { ARM64_INS_USHLL2, "ushll2" }, |
| { ARM64_INS_USHLL, "ushll" }, |
| { ARM64_INS_USHL, "ushl" }, |
| { ARM64_INS_USHR, "ushr" }, |
| { ARM64_INS_USQADD, "usqadd" }, |
| { ARM64_INS_USRA, "usra" }, |
| { ARM64_INS_USUBL2, "usubl2" }, |
| { ARM64_INS_USUBL, "usubl" }, |
| { ARM64_INS_USUBW2, "usubw2" }, |
| { ARM64_INS_USUBW, "usubw" }, |
| { ARM64_INS_UZP1, "uzp1" }, |
| { ARM64_INS_UZP2, "uzp2" }, |
| { ARM64_INS_XTN2, "xtn2" }, |
| { ARM64_INS_XTN, "xtn" }, |
| { ARM64_INS_ZIP1, "zip1" }, |
| { ARM64_INS_ZIP2, "zip2" }, |
| }; |
| |
| // map *S & alias instructions back to original id |
| static name_map alias_insn_name_maps[] = { |
| { ARM64_INS_ADC, "adcs" }, |
| { ARM64_INS_AND, "ands" }, |
| { ARM64_INS_ADD, "adds" }, |
| { ARM64_INS_BIC, "bics" }, |
| { ARM64_INS_SBC, "sbcs" }, |
| { ARM64_INS_SUB, "subs" }, |
| |
| // alias insn |
| { ARM64_INS_MNEG, "mneg" }, |
| { ARM64_INS_UMNEGL, "umnegl" }, |
| { ARM64_INS_SMNEGL, "smnegl" }, |
| { ARM64_INS_NOP, "nop" }, |
| { ARM64_INS_YIELD, "yield" }, |
| { ARM64_INS_WFE, "wfe" }, |
| { ARM64_INS_WFI, "wfi" }, |
| { ARM64_INS_SEV, "sev" }, |
| { ARM64_INS_SEVL, "sevl" }, |
| { ARM64_INS_NGC, "ngc" }, |
| { ARM64_INS_NGCS, "ngcs" }, |
| { ARM64_INS_NEGS, "negs" }, |
| |
| { ARM64_INS_SBFIZ, "sbfiz" }, |
| { ARM64_INS_UBFIZ, "ubfiz" }, |
| { ARM64_INS_SBFX, "sbfx" }, |
| { ARM64_INS_UBFX, "ubfx" }, |
| { ARM64_INS_BFI, "bfi" }, |
| { ARM64_INS_BFXIL, "bfxil" }, |
| { ARM64_INS_CMN, "cmn" }, |
| { ARM64_INS_MVN, "mvn" }, |
| { ARM64_INS_TST, "tst" }, |
| { ARM64_INS_CSET, "cset" }, |
| { ARM64_INS_CINC, "cinc" }, |
| { ARM64_INS_CSETM, "csetm" }, |
| { ARM64_INS_CINV, "cinv" }, |
| { ARM64_INS_CNEG, "cneg" }, |
| { ARM64_INS_SXTB, "sxtb" }, |
| { ARM64_INS_SXTH, "sxth" }, |
| { ARM64_INS_SXTW, "sxtw" }, |
| { ARM64_INS_CMP, "cmp" }, |
| { ARM64_INS_UXTB, "uxtb" }, |
| { ARM64_INS_UXTH, "uxth" }, |
| { ARM64_INS_UXTW, "uxtw" }, |
| |
| { ARM64_INS_IC, "ic" }, |
| { ARM64_INS_DC, "dc" }, |
| { ARM64_INS_AT, "at" }, |
| { ARM64_INS_TLBI, "tlbi" }, |
| }; |
| |
| const char *AArch64_insn_name(csh handle, unsigned int id) |
| { |
| #ifndef CAPSTONE_DIET |
| unsigned int i; |
| |
| if (id >= ARM64_INS_ENDING) |
| return NULL; |
| |
| if (id < ARR_SIZE(insn_name_maps)) |
| return insn_name_maps[id].name; |
| |
| // then find alias insn |
| for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { |
| if (alias_insn_name_maps[i].id == id) |
| return alias_insn_name_maps[i].name; |
| } |
| |
| // not found |
| return NULL; |
| #else |
| return NULL; |
| #endif |
| } |
| |
| #ifndef CAPSTONE_DIET |
| static name_map group_name_maps[] = { |
| // generic groups |
| { ARM64_GRP_INVALID, NULL }, |
| { ARM64_GRP_JUMP, "jump" }, |
| { ARM64_GRP_CALL, "call" }, |
| { ARM64_GRP_RET, "return" }, |
| { ARM64_GRP_PRIVILEGE, "privilege" }, |
| { ARM64_GRP_INT, "int" }, |
| |
| // architecture-specific groups |
| { ARM64_GRP_CRYPTO, "crypto" }, |
| { ARM64_GRP_FPARMV8, "fparmv8" }, |
| { ARM64_GRP_NEON, "neon" }, |
| { ARM64_GRP_CRC, "crc" }, |
| }; |
| #endif |
| |
| const char *AArch64_group_name(csh handle, unsigned int id) |
| { |
| #ifndef CAPSTONE_DIET |
| return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); |
| #else |
| return NULL; |
| #endif |
| } |
| |
| // map instruction name to public instruction ID |
| arm64_reg AArch64_map_insn(const char *name) |
| { |
| // NOTE: skip first NULL name in insn_name_maps |
| int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); |
| |
| if (i == -1) |
| // try again with 'special' insn that is not available in insn_name_maps |
| i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name); |
| |
| return (i != -1)? i : ARM64_REG_INVALID; |
| } |
| |
| // map internal raw vregister to 'public' register |
| arm64_reg AArch64_map_vregister(unsigned int r) |
| { |
| // for some reasons different Arm64 can map different register number to |
| // the same register. this function handles the issue for exposing Mips |
| // operands by mapping internal registers to 'public' register. |
| unsigned int map[] = { 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, ARM64_REG_V0, |
| ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, |
| ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, |
| ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, |
| ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, |
| ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, |
| ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, |
| ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1, |
| ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, |
| ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, |
| ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, |
| ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, |
| ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, |
| ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, |
| 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, |
| ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, |
| ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, |
| ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, |
| ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, |
| ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, |
| ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, |
| ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, |
| ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, |
| ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, |
| ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, |
| ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, |
| ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, |
| ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, |
| ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, |
| ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, |
| ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, |
| ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, |
| ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, |
| ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, |
| ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, |
| ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, |
| ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, |
| ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, |
| ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, |
| ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, |
| ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, |
| ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, |
| ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, |
| ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, |
| ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, |
| ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, |
| ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, |
| ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, |
| ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, |
| ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, |
| ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, |
| ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, |
| ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, }; |
| |
| if (r < ARR_SIZE(map)) |
| return map[r]; |
| |
| // cannot find this register |
| return 0; |
| } |
| |
| void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp) |
| { |
| if (MI->csh->detail) { |
| MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp; |
| } |
| } |
| |
| void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp) |
| { |
| if (MI->csh->detail) { |
| MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vess = sp; |
| } |
| } |
| |
| void arm64_op_addFP(MCInst *MI, float fp) |
| { |
| if (MI->csh->detail) { |
| MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; |
| MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp; |
| MI->flat_insn->detail->arm64.op_count++; |
| } |
| } |
| |
| void arm64_op_addImm(MCInst *MI, int64_t imm) |
| { |
| if (MI->csh->detail) { |
| MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; |
| MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm; |
| MI->flat_insn->detail->arm64.op_count++; |
| } |
| } |
| |
| #if 0 |
| |
| // map instruction to its characteristics |
| typedef struct insn_op { |
| unsigned int eflags_update; // how this instruction update status flags |
| cs_ac_type operands[4]; |
| } insn_op; |
| |
| static insn_op insn_ops[] = { |
| { /* AArch64_ABSv16i8, ARM64_INS_ABS: abs.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ABSv1i64, ARM64_INS_ABS: abs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ABSv2i32, ARM64_INS_ABS: abs.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ABSv2i64, ARM64_INS_ABS: abs.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ABSv4i16, ARM64_INS_ABS: abs.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ABSv4i32, ARM64_INS_ABS: abs.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ABSv8i16, ARM64_INS_ABS: abs.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ABSv8i8, ARM64_INS_ABS: abs.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADCSWr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADCSXr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADCWr, ARM64_INS_ADC: adc $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADCXr, ARM64_INS_ADC: adc $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN: addhn.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2: addhn2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN: addhn.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2: addhn2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2: addhn2.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN: addhn.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDPv16i8, ARM64_INS_ADDP: addp.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDPv2i32, ARM64_INS_ADDP: addp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDPv2i64, ARM64_INS_ADDP: addp.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDPv2i64p, ARM64_INS_ADDP: addp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDPv4i16, ARM64_INS_ADDP: addp.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDPv4i32, ARM64_INS_ADDP: addp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDPv8i16, ARM64_INS_ADDP: addp.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDPv8i8, ARM64_INS_ADDP: addp.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDSWri, ARM64_INS_ADDS: adds $rd, $rn, $imm */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ,0 } |
| }, |
| { /* AArch64_ADDSWrs, ARM64_INS_ADDS: adds $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDSWrx, ARM64_INS_ADDS: adds $r1, $r2, $r3 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDSXri, ARM64_INS_ADDS: adds $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDSXrs, ARM64_INS_ADDS: adds $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDSXrx, ARM64_INS_ADDS: adds $r1, $r2, $r3 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDSXrx64, ARM64_INS_ADDS: adds $rd, $rn, $rm$ext */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDVv16i8v, ARM64_INS_ADDV: addv.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDVv4i16v, ARM64_INS_ADDV: addv.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDVv4i32v, ARM64_INS_ADDV: addv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDVv8i16v, ARM64_INS_ADDV: addv.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDVv8i8v, ARM64_INS_ADDV: addv.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDWri, ARM64_INS_ADD: add $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDWrs, ARM64_INS_ADD: add $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDWrx, ARM64_INS_ADD: add $r1, $r2, $r3 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDXri, ARM64_INS_ADD: add $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDXrs, ARM64_INS_ADD: add $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDXrx, ARM64_INS_ADD: add $r1, $r2, $r3 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDXrx64, ARM64_INS_ADD: add $rd, $rn, $rm$ext */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDv16i8, ARM64_INS_ADD: add.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDv1i64, ARM64_INS_ADD: add $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDv2i32, ARM64_INS_ADD: add.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDv2i64, ARM64_INS_ADD: add.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDv4i16, ARM64_INS_ADD: add.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDv4i32, ARM64_INS_ADD: add.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDv8i16, ARM64_INS_ADD: add.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADDv8i8, ARM64_INS_ADD: add.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADR, ARM64_INS_ADR: adr $xd, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ADRP, ARM64_INS_ADRP: adrp $xd, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_AESDrr, ARM64_INS_AESD: aesd.16b $rd, $rn */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_AESErr, ARM64_INS_AESE: aese.16b $rd, $rn */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_AESIMCrr, ARM64_INS_AESIMC: aesimc.16b $rd, $rn */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_AESMCrr, ARM64_INS_AESMC: aesmc.16b $rd, $rn */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDSWri, ARM64_INS_ANDS: ands $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDSWrs, ARM64_INS_ANDS: ands $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDSXri, ARM64_INS_ANDS: ands $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDSXrs, ARM64_INS_ANDS: ands $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDWri, ARM64_INS_AND: and $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDWrs, ARM64_INS_AND: and $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDXri, ARM64_INS_AND: and $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDXrs, ARM64_INS_AND: and $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDv16i8, ARM64_INS_AND: and.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ANDv8i8, ARM64_INS_AND: and.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ASRVWr, ARM64_INS_ASR: asr $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ASRVXr, ARM64_INS_ASR: asr $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_B, ARM64_INS_B: b $addr */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BFMWri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BFMXri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICSWrs, ARM64_INS_BICS: bics $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICSXrs, ARM64_INS_BICS: bics $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICWrs, ARM64_INS_BIC: bic $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICXrs, ARM64_INS_BIC: bic $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICv16i8, ARM64_INS_BIC: bic.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICv2i32, ARM64_INS_BIC: bic.2s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICv4i16, ARM64_INS_BIC: bic.4h $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICv4i32, ARM64_INS_BIC: bic.4s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICv8i16, ARM64_INS_BIC: bic.8h $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BICv8i8, ARM64_INS_BIC: bic.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BIFv16i8, ARM64_INS_BIF: bif.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BIFv8i8, ARM64_INS_BIF: bif.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BITv16i8, ARM64_INS_BIT: bit.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BITv8i8, ARM64_INS_BIT: bit.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BL, ARM64_INS_BL: bl $addr */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BLR, ARM64_INS_BLR: blr $rn */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BR, ARM64_INS_BR: br $rn */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BRK, ARM64_INS_BRK: brk $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BSLv16i8, ARM64_INS_BSL: bsl.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_BSLv8i8, ARM64_INS_BSL: bsl.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_Bcc, ARM64_INS_B: b.$cond $target */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CBNZW, ARM64_INS_CBNZ: cbnz $rt, $target */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CBNZX, ARM64_INS_CBNZ: cbnz $rt, $target */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CBZW, ARM64_INS_CBZ: cbz $rt, $target */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CBZX, ARM64_INS_CBZ: cbz $rt, $target */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CCMNWi, ARM64_INS_CCMN: ccmn $rn, $imm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CCMNWr, ARM64_INS_CCMN: ccmn $rn, $rm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CCMNXi, ARM64_INS_CCMN: ccmn $rn, $imm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CCMNXr, ARM64_INS_CCMN: ccmn $rn, $rm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CCMPWi, ARM64_INS_CCMP: ccmp $rn, $imm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CCMPWr, ARM64_INS_CCMP: ccmp $rn, $rm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CCMPXi, ARM64_INS_CCMP: ccmp $rn, $imm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CCMPXr, ARM64_INS_CCMP: ccmp $rn, $rm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLREX, ARM64_INS_CLREX: clrex $crm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLSWr, ARM64_INS_CLS: cls $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLSXr, ARM64_INS_CLS: cls $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLSv16i8, ARM64_INS_CLS: cls.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLSv2i32, ARM64_INS_CLS: cls.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLSv4i16, ARM64_INS_CLS: cls.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLSv4i32, ARM64_INS_CLS: cls.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLSv8i16, ARM64_INS_CLS: cls.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLSv8i8, ARM64_INS_CLS: cls.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLZWr, ARM64_INS_CLZ: clz $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLZXr, ARM64_INS_CLZ: clz $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLZv16i8, ARM64_INS_CLZ: clz.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLZv2i32, ARM64_INS_CLZ: clz.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLZv4i16, ARM64_INS_CLZ: clz.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLZv4i32, ARM64_INS_CLZ: clz.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLZv8i16, ARM64_INS_CLZ: clz.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CLZv8i8, ARM64_INS_CLZ: clz.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv16i8, ARM64_INS_CMEQ: cmeq.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv16i8rz, ARM64_INS_CMEQ: cmeq.16b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv1i64, ARM64_INS_CMEQ: cmeq $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv1i64rz, ARM64_INS_CMEQ: cmeq $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv2i32, ARM64_INS_CMEQ: cmeq.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv2i32rz, ARM64_INS_CMEQ: cmeq.2s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv2i64, ARM64_INS_CMEQ: cmeq.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv2i64rz, ARM64_INS_CMEQ: cmeq.2d $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv4i16, ARM64_INS_CMEQ: cmeq.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv4i16rz, ARM64_INS_CMEQ: cmeq.4h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv4i32, ARM64_INS_CMEQ: cmeq.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv4i32rz, ARM64_INS_CMEQ: cmeq.4s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv8i16, ARM64_INS_CMEQ: cmeq.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv8i16rz, ARM64_INS_CMEQ: cmeq.8h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv8i8, ARM64_INS_CMEQ: cmeq.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMEQv8i8rz, ARM64_INS_CMEQ: cmeq.8b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv16i8, ARM64_INS_CMGE: cmge.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv16i8rz, ARM64_INS_CMGE: cmge.16b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv1i64, ARM64_INS_CMGE: cmge $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv1i64rz, ARM64_INS_CMGE: cmge $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv2i32, ARM64_INS_CMGE: cmge.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv2i32rz, ARM64_INS_CMGE: cmge.2s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv2i64, ARM64_INS_CMGE: cmge.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv2i64rz, ARM64_INS_CMGE: cmge.2d $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv4i16, ARM64_INS_CMGE: cmge.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv4i16rz, ARM64_INS_CMGE: cmge.4h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv4i32, ARM64_INS_CMGE: cmge.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv4i32rz, ARM64_INS_CMGE: cmge.4s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv8i16, ARM64_INS_CMGE: cmge.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv8i16rz, ARM64_INS_CMGE: cmge.8h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv8i8, ARM64_INS_CMGE: cmge.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGEv8i8rz, ARM64_INS_CMGE: cmge.8b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv16i8, ARM64_INS_CMGT: cmgt.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv16i8rz, ARM64_INS_CMGT: cmgt.16b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv1i64, ARM64_INS_CMGT: cmgt $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv1i64rz, ARM64_INS_CMGT: cmgt $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv2i32, ARM64_INS_CMGT: cmgt.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv2i32rz, ARM64_INS_CMGT: cmgt.2s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv2i64, ARM64_INS_CMGT: cmgt.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv2i64rz, ARM64_INS_CMGT: cmgt.2d $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv4i16, ARM64_INS_CMGT: cmgt.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv4i16rz, ARM64_INS_CMGT: cmgt.4h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv4i32, ARM64_INS_CMGT: cmgt.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv4i32rz, ARM64_INS_CMGT: cmgt.4s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv8i16, ARM64_INS_CMGT: cmgt.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv8i16rz, ARM64_INS_CMGT: cmgt.8h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv8i8, ARM64_INS_CMGT: cmgt.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMGTv8i8rz, ARM64_INS_CMGT: cmgt.8b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHIv16i8, ARM64_INS_CMHI: cmhi.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHIv1i64, ARM64_INS_CMHI: cmhi $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHIv2i32, ARM64_INS_CMHI: cmhi.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHIv2i64, ARM64_INS_CMHI: cmhi.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHIv4i16, ARM64_INS_CMHI: cmhi.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHIv4i32, ARM64_INS_CMHI: cmhi.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHIv8i16, ARM64_INS_CMHI: cmhi.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHIv8i8, ARM64_INS_CMHI: cmhi.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHSv16i8, ARM64_INS_CMHS: cmhs.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHSv1i64, ARM64_INS_CMHS: cmhs $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHSv2i32, ARM64_INS_CMHS: cmhs.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHSv2i64, ARM64_INS_CMHS: cmhs.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHSv4i16, ARM64_INS_CMHS: cmhs.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHSv4i32, ARM64_INS_CMHS: cmhs.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHSv8i16, ARM64_INS_CMHS: cmhs.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMHSv8i8, ARM64_INS_CMHS: cmhs.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLEv16i8rz, ARM64_INS_CMLE: cmle.16b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLEv1i64rz, ARM64_INS_CMLE: cmle $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLEv2i32rz, ARM64_INS_CMLE: cmle.2s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLEv2i64rz, ARM64_INS_CMLE: cmle.2d $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLEv4i16rz, ARM64_INS_CMLE: cmle.4h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLEv4i32rz, ARM64_INS_CMLE: cmle.4s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLEv8i16rz, ARM64_INS_CMLE: cmle.8h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLEv8i8rz, ARM64_INS_CMLE: cmle.8b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLTv16i8rz, ARM64_INS_CMLT: cmlt.16b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLTv1i64rz, ARM64_INS_CMLT: cmlt $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLTv2i32rz, ARM64_INS_CMLT: cmlt.2s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLTv2i64rz, ARM64_INS_CMLT: cmlt.2d $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLTv4i16rz, ARM64_INS_CMLT: cmlt.4h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLTv4i32rz, ARM64_INS_CMLT: cmlt.4s $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLTv8i16rz, ARM64_INS_CMLT: cmlt.8h $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMLTv8i8rz, ARM64_INS_CMLT: cmlt.8b $rd, $rn, #0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMTSTv16i8, ARM64_INS_CMTST: cmtst.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMTSTv1i64, ARM64_INS_CMTST: cmtst $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMTSTv2i32, ARM64_INS_CMTST: cmtst.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMTSTv2i64, ARM64_INS_CMTST: cmtst.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMTSTv4i16, ARM64_INS_CMTST: cmtst.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMTSTv4i32, ARM64_INS_CMTST: cmtst.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMTSTv8i16, ARM64_INS_CMTST: cmtst.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CMTSTv8i8, ARM64_INS_CMTST: cmtst.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CNTv16i8, ARM64_INS_CNT: cnt.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CNTv8i8, ARM64_INS_CNT: cnt.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CPYi16, ARM64_INS_MOV: mov $dst, $src$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CPYi32, ARM64_INS_MOV: mov $dst, $src$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CPYi64, ARM64_INS_MOV: mov $dst, $src$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CPYi8, ARM64_INS_MOV: mov $dst, $src$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CRC32Brr, ARM64_INS_CRC32B: crc32b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CRC32CBrr, ARM64_INS_CRC32CB: crc32cb $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CRC32CHrr, ARM64_INS_CRC32CH: crc32ch $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CRC32CWrr, ARM64_INS_CRC32CW: crc32cw $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CRC32CXrr, ARM64_INS_CRC32CX: crc32cx $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CRC32Hrr, ARM64_INS_CRC32H: crc32h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CRC32Wrr, ARM64_INS_CRC32W: crc32w $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CRC32Xrr, ARM64_INS_CRC32X: crc32x $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CSELWr, ARM64_INS_CSEL: csel $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CSELXr, ARM64_INS_CSEL: csel $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CSINCWr, ARM64_INS_CSINC: csinc $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CSINCXr, ARM64_INS_CSINC: csinc $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CSINVWr, ARM64_INS_CSINV: csinv $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CSINVXr, ARM64_INS_CSINV: csinv $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CSNEGWr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_CSNEGXr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DCPS1, ARM64_INS_DCPS1: dcps1 $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DCPS2, ARM64_INS_DCPS2: dcps2 $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DCPS3, ARM64_INS_DCPS3: dcps3 $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DMB, ARM64_INS_DMB: dmb $crm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DRPS, ARM64_INS_DRPS: drps */ |
| 0, |
| { 0 } |
| }, |
| { /* AArch64_DSB, ARM64_INS_DSB: dsb $crm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv16i8gpr, ARM64_INS_DUP: dup.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv16i8lane, ARM64_INS_DUP: dup.16b $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv2i32gpr, ARM64_INS_DUP: dup.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv2i32lane, ARM64_INS_DUP: dup.2s $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv2i64gpr, ARM64_INS_DUP: dup.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv2i64lane, ARM64_INS_DUP: dup.2d $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv4i16gpr, ARM64_INS_DUP: dup.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv4i16lane, ARM64_INS_DUP: dup.4h $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv4i32gpr, ARM64_INS_DUP: dup.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv4i32lane, ARM64_INS_DUP: dup.4s $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv8i16gpr, ARM64_INS_DUP: dup.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv8i16lane, ARM64_INS_DUP: dup.8h $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv8i8gpr, ARM64_INS_DUP: dup.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_DUPv8i8lane, ARM64_INS_DUP: dup.8b $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EONWrs, ARM64_INS_EON: eon $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EONXrs, ARM64_INS_EON: eon $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EORWri, ARM64_INS_EOR: eor $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EORWrs, ARM64_INS_EOR: eor $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EORXri, ARM64_INS_EOR: eor $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EORXrs, ARM64_INS_EOR: eor $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EORv16i8, ARM64_INS_EOR: eor.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EORv8i8, ARM64_INS_EOR: eor.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ERET, ARM64_INS_ERET: eret */ |
| 0, |
| { 0 } |
| }, |
| { /* AArch64_EXTRWrri, ARM64_INS_EXTR: extr $rd, $rn, $rm, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EXTRXrri, ARM64_INS_EXTR: extr $rd, $rn, $rm, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EXTv16i8, ARM64_INS_EXT: ext.16b $rd, $rn, $rm, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_EXTv8i8, ARM64_INS_EXT: ext.8b $rd, $rn, $rm, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABD32, ARM64_INS_FABD: fabd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABD64, ARM64_INS_FABD: fabd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABDv2f32, ARM64_INS_FABD: fabd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABDv2f64, ARM64_INS_FABD: fabd.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABDv4f32, ARM64_INS_FABD: fabd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABSDr, ARM64_INS_FABS: fabs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABSSr, ARM64_INS_FABS: fabs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABSv2f32, ARM64_INS_FABS: fabs.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABSv2f64, ARM64_INS_FABS: fabs.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FABSv4f32, ARM64_INS_FABS: fabs.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGE32, ARM64_INS_FACGE: facge $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGE64, ARM64_INS_FACGE: facge $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGEv2f32, ARM64_INS_FACGE: facge.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGEv2f64, ARM64_INS_FACGE: facge.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGEv4f32, ARM64_INS_FACGE: facge.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGT32, ARM64_INS_FACGT: facgt $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGT64, ARM64_INS_FACGT: facgt $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGTv2f32, ARM64_INS_FACGT: facgt.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGTv2f64, ARM64_INS_FACGT: facgt.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FACGTv4f32, ARM64_INS_FACGT: facgt.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDDrr, ARM64_INS_FADD: fadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDPv2f32, ARM64_INS_FADDP: faddp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDPv2f64, ARM64_INS_FADDP: faddp.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDPv2i32p, ARM64_INS_FADDP: faddp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDPv2i64p, ARM64_INS_FADDP: faddp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDPv4f32, ARM64_INS_FADDP: faddp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDSrr, ARM64_INS_FADD: fadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDv2f32, ARM64_INS_FADD: fadd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDv2f64, ARM64_INS_FADD: fadd.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FADDv4f32, ARM64_INS_FADD: fadd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCCMPDrr, ARM64_INS_FCCMP: fccmp $rn, $rm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCCMPEDrr, ARM64_INS_FCCMPE: fccmpe $rn, $rm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCCMPESrr, ARM64_INS_FCCMPE: fccmpe $rn, $rm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCCMPSrr, ARM64_INS_FCCMP: fccmp $rn, $rm, $nzcv, $cond */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQ32, ARM64_INS_FCMEQ: fcmeq $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQ64, ARM64_INS_FCMEQ: fcmeq $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ: fcmeq $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ: fcmeq $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQv2f32, ARM64_INS_FCMEQ: fcmeq.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQv2f64, ARM64_INS_FCMEQ: fcmeq.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ: fcmeq.2s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ: fcmeq.2d $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQv4f32, ARM64_INS_FCMEQ: fcmeq.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ: fcmeq.4s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGE32, ARM64_INS_FCMGE: fcmge $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGE64, ARM64_INS_FCMGE: fcmge $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE: fcmge $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE: fcmge $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGEv2f32, ARM64_INS_FCMGE: fcmge.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGEv2f64, ARM64_INS_FCMGE: fcmge.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE: fcmge.2s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE: fcmge.2d $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGEv4f32, ARM64_INS_FCMGE: fcmge.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE: fcmge.4s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGT32, ARM64_INS_FCMGT: fcmgt $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGT64, ARM64_INS_FCMGT: fcmgt $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT: fcmgt $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT: fcmgt $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGTv2f32, ARM64_INS_FCMGT: fcmgt.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGTv2f64, ARM64_INS_FCMGT: fcmgt.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT: fcmgt.2s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT: fcmgt.2d $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGTv4f32, ARM64_INS_FCMGT: fcmgt.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT: fcmgt.4s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE: fcmle $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE: fcmle $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE: fcmle.2s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE: fcmle.2d $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE: fcmle.4s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT: fcmlt $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT: fcmlt $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT: fcmlt.2s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT: fcmlt.2d $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT: fcmlt.4s $rd, $rn, #0.0 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMPDri, ARM64_INS_FCMP: fcmp $rn, #0.0 */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMPDrr, ARM64_INS_FCMP: fcmp $rn, $rm */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMPEDri, ARM64_INS_FCMPE: fcmpe $rn, #0.0 */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMPEDrr, ARM64_INS_FCMPE: fcmpe $rn, $rm */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMPESri, ARM64_INS_FCMPE: fcmpe $rn, #0.0 */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMPESrr, ARM64_INS_FCMPE: fcmpe $rn, $rm */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMPSri, ARM64_INS_FCMP: fcmp $rn, #0.0 */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCMPSrr, ARM64_INS_FCMP: fcmp $rn, $rm */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCSELDrrr, ARM64_INS_FCSEL: fcsel $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCSELSrrr, ARM64_INS_FCSEL: fcsel $rd, $rn, $rm, $cond */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASUWDr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASUWSr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASUXDr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASUXSr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASv1i32, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASv1i64, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASv2f32, ARM64_INS_FCVTAS: fcvtas.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASv2f64, ARM64_INS_FCVTAS: fcvtas.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTASv4f32, ARM64_INS_FCVTAS: fcvtas.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU: fcvtau.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU: fcvtau.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU: fcvtau.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTDHr, ARM64_INS_FCVT: fcvt $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTDSr, ARM64_INS_FCVT: fcvt $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTHDr, ARM64_INS_FCVT: fcvt $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTHSr, ARM64_INS_FCVT: fcvt $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTLv2i32, ARM64_INS_FCVTL: fcvtl $rd.2d, $rn.2s */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTLv4i16, ARM64_INS_FCVTL: fcvtl $rd.4s, $rn.4h */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTLv4i32, ARM64_INS_FCVTL2: fcvtl2 $rd.2d, $rn.4s */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTLv8i16, ARM64_INS_FCVTL2: fcvtl2 $rd.4s, $rn.8h */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS: fcvtms.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS: fcvtms.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS: fcvtms.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU: fcvtmu.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU: fcvtmu.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU: fcvtmu.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS: fcvtns.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS: fcvtns.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS: fcvtns.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU: fcvtnu.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU: fcvtnu.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU: fcvtnu.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNv2i32, ARM64_INS_FCVTN: fcvtn $rd.2s, $rn.2d */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNv4i16, ARM64_INS_FCVTN: fcvtn $rd.4h, $rn.4s */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNv4i32, ARM64_INS_FCVTN2: fcvtn2 $rd.4s, $rn.2d */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTNv8i16, ARM64_INS_FCVTN2: fcvtn2 $rd.8h, $rn.4s */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS: fcvtps.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS: fcvtps.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS: fcvtps.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU: fcvtpu.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU: fcvtpu.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU: fcvtpu.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTSDr, ARM64_INS_FCVT: fcvt $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTSHr, ARM64_INS_FCVT: fcvt $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN: fcvtxn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN: fcvtxn $rd.2s, $rn.2d */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2: fcvtxn2 $rd.4s, $rn.2d */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_IntSWDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_IntSWSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_IntSXDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_IntSXSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_IntUWDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_IntUWSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_IntUXDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_IntUXSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_Intv2f32, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_Intv2f64, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZS_Intv4f32, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSd, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSs, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_IntSWDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_IntSWSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_IntSXDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_IntSXSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_IntUWDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_IntUWSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_IntUXDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_IntUXSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_Intv2f32, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_Intv2f64, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZU_Intv4f32, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUd, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUs, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FDIVDrr, ARM64_INS_FDIV: fdiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FDIVSrr, ARM64_INS_FDIV: fdiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FDIVv2f32, ARM64_INS_FDIV: fdiv.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FDIVv2f64, ARM64_INS_FDIV: fdiv.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FDIVv4f32, ARM64_INS_FDIV: fdiv.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMADDDrrr, ARM64_INS_FMADD: fmadd $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMADDSrrr, ARM64_INS_FMADD: fmadd $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXDrr, ARM64_INS_FMAX: fmax $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMDrr, ARM64_INS_FMAXNM: fmaxnm $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP: fmaxnmp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP: fmaxnmp.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP: fmaxnmp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP: fmaxnmp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP: fmaxnmp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMSrr, ARM64_INS_FMAXNM: fmaxnm $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV: fmaxnmv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM: fmaxnm.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM: fmaxnm.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM: fmaxnm.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXPv2f32, ARM64_INS_FMAXP: fmaxp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXPv2f64, ARM64_INS_FMAXP: fmaxp.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXPv2i32p, ARM64_INS_FMAXP: fmaxp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXPv2i64p, ARM64_INS_FMAXP: fmaxp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXPv4f32, ARM64_INS_FMAXP: fmaxp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXSrr, ARM64_INS_FMAX: fmax $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXVv4i32v, ARM64_INS_FMAXV: fmaxv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXv2f32, ARM64_INS_FMAX: fmax.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXv2f64, ARM64_INS_FMAX: fmax.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMAXv4f32, ARM64_INS_FMAX: fmax.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINDrr, ARM64_INS_FMIN: fmin $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMDrr, ARM64_INS_FMINNM: fminnm $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP: fminnmp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP: fminnmp.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP: fminnmp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP: fminnmp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP: fminnmp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMSrr, ARM64_INS_FMINNM: fminnm $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV: fminnmv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMv2f32, ARM64_INS_FMINNM: fminnm.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMv2f64, ARM64_INS_FMINNM: fminnm.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINNMv4f32, ARM64_INS_FMINNM: fminnm.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINPv2f32, ARM64_INS_FMINP: fminp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINPv2f64, ARM64_INS_FMINP: fminp.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINPv2i32p, ARM64_INS_FMINP: fminp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINPv2i64p, ARM64_INS_FMINP: fminp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINPv4f32, ARM64_INS_FMINP: fminp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINSrr, ARM64_INS_FMIN: fmin $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINVv4i32v, ARM64_INS_FMINV: fminv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINv2f32, ARM64_INS_FMIN: fmin.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINv2f64, ARM64_INS_FMIN: fmin.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMINv4f32, ARM64_INS_FMIN: fmin.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA: fmla.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA: fmla.d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLAv2f32, ARM64_INS_FMLA: fmla.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLAv2f64, ARM64_INS_FMLA: fmla.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA: fmla.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA: fmla.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLAv4f32, ARM64_INS_FMLA: fmla.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA: fmla.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS: fmls.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS: fmls.d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLSv2f32, ARM64_INS_FMLS: fmls.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLSv2f64, ARM64_INS_FMLS: fmls.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS: fmls.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS: fmls.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLSv4f32, ARM64_INS_FMLS: fmls.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS: fmls.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVDXHighr, ARM64_INS_FMOV: fmov.d $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVDXr, ARM64_INS_FMOV: fmov $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVDi, ARM64_INS_FMOV: fmov $rd, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVDr, ARM64_INS_FMOV: fmov $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVSWr, ARM64_INS_FMOV: fmov $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVSi, ARM64_INS_FMOV: fmov $rd, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVSr, ARM64_INS_FMOV: fmov $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVWSr, ARM64_INS_FMOV: fmov $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVXDHighr, ARM64_INS_FMOV: fmov.d $rd$idx, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVXDr, ARM64_INS_FMOV: fmov $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMOVv2f32_ns, ARM64_INS_FMOV: fmov.2s $rd, $imm8 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } |
| }, |
| { /* AArch64_FMOVv2f64_ns, ARM64_INS_FMOV: fmov.2d $rd, $imm8 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } |
| }, |
| { /* AArch64_FMOVv4f32_ns, ARM64_INS_FMOV: fmov.4s $rd, $imm8 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } |
| }, |
| { /* AArch64_FMSUBDrrr, ARM64_INS_FMSUB: fmsub $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMSUBSrrr, ARM64_INS_FMSUB: fmsub $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULDrr, ARM64_INS_FMUL: fmul $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULSrr, ARM64_INS_FMUL: fmul $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULX32, ARM64_INS_FMULX: fmulx $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULX64, ARM64_INS_FMULX: fmulx $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX: fmulx.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX: fmulx.d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULXv2f32, ARM64_INS_FMULX: fmulx.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULXv2f64, ARM64_INS_FMULX: fmulx.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX: fmulx.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX: fmulx.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULXv4f32, ARM64_INS_FMULX: fmulx.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX: fmulx.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULv1i32_indexed, ARM64_INS_FMUL: fmul.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULv1i64_indexed, ARM64_INS_FMUL: fmul.d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULv2f32, ARM64_INS_FMUL: fmul.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULv2f64, ARM64_INS_FMUL: fmul.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULv2i32_indexed, ARM64_INS_FMUL: fmul.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULv2i64_indexed, ARM64_INS_FMUL: fmul.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULv4f32, ARM64_INS_FMUL: fmul.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FMULv4i32_indexed, ARM64_INS_FMUL: fmul.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNEGDr, ARM64_INS_FNEG: fneg $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNEGSr, ARM64_INS_FNEG: fneg $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNEGv2f32, ARM64_INS_FNEG: fneg.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNEGv2f64, ARM64_INS_FNEG: fneg.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNEGv4f32, ARM64_INS_FNEG: fneg.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNMADDDrrr, ARM64_INS_FNMADD: fnmadd $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNMADDSrrr, ARM64_INS_FNMADD: fnmadd $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB: fnmsub $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB: fnmsub $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNMULDrr, ARM64_INS_FNMUL: fnmul $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FNMULSrr, ARM64_INS_FNMUL: fnmul $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPEv1i32, ARM64_INS_FRECPE: frecpe $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPEv1i64, ARM64_INS_FRECPE: frecpe $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPEv2f32, ARM64_INS_FRECPE: frecpe.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPEv2f64, ARM64_INS_FRECPE: frecpe.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPEv4f32, ARM64_INS_FRECPE: frecpe.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPS32, ARM64_INS_FRECPS: frecps $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPS64, ARM64_INS_FRECPS: frecps $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPSv2f32, ARM64_INS_FRECPS: frecps.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPSv2f64, ARM64_INS_FRECPS: frecps.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPSv4f32, ARM64_INS_FRECPS: frecps.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPXv1i32, ARM64_INS_FRECPX: frecpx $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRECPXv1i64, ARM64_INS_FRECPX: frecpx $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTADr, ARM64_INS_FRINTA: frinta $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTASr, ARM64_INS_FRINTA: frinta $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTAv2f32, ARM64_INS_FRINTA: frinta.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTAv2f64, ARM64_INS_FRINTA: frinta.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTAv4f32, ARM64_INS_FRINTA: frinta.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTIDr, ARM64_INS_FRINTI: frinti $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTISr, ARM64_INS_FRINTI: frinti $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTIv2f32, ARM64_INS_FRINTI: frinti.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTIv2f64, ARM64_INS_FRINTI: frinti.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTIv4f32, ARM64_INS_FRINTI: frinti.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTMDr, ARM64_INS_FRINTM: frintm $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTMSr, ARM64_INS_FRINTM: frintm $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTMv2f32, ARM64_INS_FRINTM: frintm.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTMv2f64, ARM64_INS_FRINTM: frintm.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTMv4f32, ARM64_INS_FRINTM: frintm.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTNDr, ARM64_INS_FRINTN: frintn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTNSr, ARM64_INS_FRINTN: frintn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTNv2f32, ARM64_INS_FRINTN: frintn.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTNv2f64, ARM64_INS_FRINTN: frintn.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTNv4f32, ARM64_INS_FRINTN: frintn.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTPDr, ARM64_INS_FRINTP: frintp $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTPSr, ARM64_INS_FRINTP: frintp $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTPv2f32, ARM64_INS_FRINTP: frintp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTPv2f64, ARM64_INS_FRINTP: frintp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTPv4f32, ARM64_INS_FRINTP: frintp.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTXDr, ARM64_INS_FRINTX: frintx $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTXSr, ARM64_INS_FRINTX: frintx $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTXv2f32, ARM64_INS_FRINTX: frintx.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTXv2f64, ARM64_INS_FRINTX: frintx.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTXv4f32, ARM64_INS_FRINTX: frintx.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTZDr, ARM64_INS_FRINTZ: frintz $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTZSr, ARM64_INS_FRINTZ: frintz $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTZv2f32, ARM64_INS_FRINTZ: frintz.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTZv2f64, ARM64_INS_FRINTZ: frintz.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRINTZv4f32, ARM64_INS_FRINTZ: frintz.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE: frsqrte $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE: frsqrte $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE: frsqrte.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE: frsqrte.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE: frsqrte.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTS32, ARM64_INS_FRSQRTS: frsqrts $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTS64, ARM64_INS_FRSQRTS: frsqrts $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS: frsqrts.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS: frsqrts.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS: frsqrts.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSQRTDr, ARM64_INS_FSQRT: fsqrt $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSQRTSr, ARM64_INS_FSQRT: fsqrt $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSQRTv2f32, ARM64_INS_FSQRT: fsqrt.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSQRTv2f64, ARM64_INS_FSQRT: fsqrt.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSQRTv4f32, ARM64_INS_FSQRT: fsqrt.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSUBDrr, ARM64_INS_FSUB: fsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSUBSrr, ARM64_INS_FSUB: fsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSUBv2f32, ARM64_INS_FSUB: fsub.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSUBv2f64, ARM64_INS_FSUB: fsub.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_FSUBv4f32, ARM64_INS_FSUB: fsub.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_HINT, ARM64_INS_HINT: hint $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_HLT, ARM64_INS_HLT: hlt $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_HVC, ARM64_INS_HVC: hvc $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_INSvi16gpr, ARM64_INS_INS: ins.h $rd$idx, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_INSvi16lane, ARM64_INS_INS: ins.h $rd$idx, $rn$idx2 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_INSvi32gpr, ARM64_INS_INS: ins.s $rd$idx, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_INSvi32lane, ARM64_INS_INS: ins.s $rd$idx, $rn$idx2 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_INSvi64gpr, ARM64_INS_INS: ins.d $rd$idx, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_INSvi64lane, ARM64_INS_INS: ins.d $rd$idx, $rn$idx2 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_INSvi8gpr, ARM64_INS_INS: ins.b $rd$idx, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_INSvi8lane, ARM64_INS_INS: ins.b $rd$idx, $rn$idx2 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ISB, ARM64_INS_ISB: isb $crm */ |
| 0, |
| { 0 } |
| }, |
| { /* AArch64_LD1Fourv16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Fourv8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ0 } |
| }, |
| { /* AArch64_LD1Onev2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Onev8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv16b, ARM64_INS_LD1R: ld1r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv16b_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv1d, ARM64_INS_LD1R: ld1r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv1d_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv2d, ARM64_INS_LD1R: ld1r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv2d_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv2s, ARM64_INS_LD1R: ld1r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv2s_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv4h, ARM64_INS_LD1R: ld1r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv4h_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv4s, ARM64_INS_LD1R: ld1r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv4s_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv8b, ARM64_INS_LD1R: ld1r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv8b_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv8h, ARM64_INS_LD1R: ld1r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Rv8h_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Threev8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1Twov8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1i16, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1i16_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1i32, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1i32_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1i64, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1i64_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1i8, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD1i8_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv16b, ARM64_INS_LD2R: ld2r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv16b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv1d, ARM64_INS_LD2R: ld2r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv1d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv2d, ARM64_INS_LD2R: ld2r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv2d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv2s, ARM64_INS_LD2R: ld2r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv2s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv4h, ARM64_INS_LD2R: ld2r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv4h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv4s, ARM64_INS_LD2R: ld2r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv4s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv8b, ARM64_INS_LD2R: ld2r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv8b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv8h, ARM64_INS_LD2R: ld2r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Rv8h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD2Twov16b, ARM64_INS_LD2: ld2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov16b_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov2d, ARM64_INS_LD2: ld2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov2d_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov2s, ARM64_INS_LD2: ld2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov2s_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov4h, ARM64_INS_LD2: ld2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov4h_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov4s, ARM64_INS_LD2: ld2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov4s_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov8b, ARM64_INS_LD2: ld2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov8b_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov8h, ARM64_INS_LD2: ld2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2Twov8h_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2i16, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2i16_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2i32, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2i32_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2i64, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2i64_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2i8, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD2i8_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LD3Rv16b, ARM64_INS_LD3R: ld3r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv16b_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv1d, ARM64_INS_LD3R: ld3r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv1d_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv2d, ARM64_INS_LD3R: ld3r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv2d_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv2s, ARM64_INS_LD3R: ld3r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv2s_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv4h, ARM64_INS_LD3R: ld3r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv4h_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv4s, ARM64_INS_LD3R: ld3r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv4s_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv8b, ARM64_INS_LD3R: ld3r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv8b_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv8h, ARM64_INS_LD3R: ld3r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Rv8h_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev16b, ARM64_INS_LD3: ld3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev16b_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev2d, ARM64_INS_LD3: ld3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev2d_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev2s, ARM64_INS_LD3: ld3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev2s_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev4h, ARM64_INS_LD3: ld3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev4h_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev4s, ARM64_INS_LD3: ld3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev4s_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev8b, ARM64_INS_LD3: ld3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev8b_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev8h, ARM64_INS_LD3: ld3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3Threev8h_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3i16, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3i16_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3i32, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3i32_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3i64, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3i64_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3i8, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD3i8_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv16b, ARM64_INS_LD4: ld4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv16b_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv2d, ARM64_INS_LD4: ld4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv2d_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv2s, ARM64_INS_LD4: ld4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv2s_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv4h, ARM64_INS_LD4: ld4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv4h_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv4s, ARM64_INS_LD4: ld4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv4s_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv8b, ARM64_INS_LD4: ld4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv8b_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv8h, ARM64_INS_LD4: ld4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Fourv8h_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv16b, ARM64_INS_LD4R: ld4r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv16b_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv1d, ARM64_INS_LD4R: ld4r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv1d_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv2d, ARM64_INS_LD4R: ld4r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv2d_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv2s, ARM64_INS_LD4R: ld4r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv2s_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv4h, ARM64_INS_LD4R: ld4r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv4h_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv4s, ARM64_INS_LD4R: ld4r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv4s_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv8b, ARM64_INS_LD4R: ld4r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv8b_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv8h, ARM64_INS_LD4R: ld4r $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4Rv8h_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4i16, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4i16_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4i32, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4i32_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4i64, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4i64_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4i8, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LD4i8_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDARB, ARM64_INS_LDARB: ldarb $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDARH, ARM64_INS_LDARH: ldarh $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDARW, ARM64_INS_LDAR: ldar $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDARX, ARM64_INS_LDAR: ldar $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDAXPW, ARM64_INS_LDAXP: ldaxp $rt, $rt2, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDAXPX, ARM64_INS_LDAXP: ldaxp $rt, $rt2, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDAXRB, ARM64_INS_LDAXRB: ldaxrb $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDAXRH, ARM64_INS_LDAXRH: ldaxrh $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDAXRW, ARM64_INS_LDAXR: ldaxr $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDAXRX, ARM64_INS_LDAXR: ldaxr $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDNPDi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDNPQi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDNPSi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDNPWi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDNPXi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPDi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPDpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPDpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPQi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPQpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPQpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPSWi, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPSWpost, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPSWpre, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPSi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPSpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPSpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPWi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPWpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPWpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPXi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPXpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDPXpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBBpost, ARM64_INS_LDRB: ldrb $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBBpre, ARM64_INS_LDRB: ldrb $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBBroW, ARM64_INS_LDRB: ldrb $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBBroX, ARM64_INS_LDRB: ldrb $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBBui, ARM64_INS_LDRB: ldrb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRBui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRDl, ARM64_INS_LDR: ldr $rt, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRDpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRDpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRDroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRDroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRDui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHHpost, ARM64_INS_LDRH: ldrh $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHHpre, ARM64_INS_LDRH: ldrh $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHHroW, ARM64_INS_LDRH: ldrh $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHHroX, ARM64_INS_LDRH: ldrh $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHHui, ARM64_INS_LDRH: ldrh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRHui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRQl, ARM64_INS_LDR: ldr $rt, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRQpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRQpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRQroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRQroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRQui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBWpost, ARM64_INS_LDRSB: ldrsb $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBWpre, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBWroW, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBWroX, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBWui, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBXpost, ARM64_INS_LDRSB: ldrsb $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBXpre, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBXroW, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBXroX, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSBXui, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHWpost, ARM64_INS_LDRSH: ldrsh $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHWpre, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHWroW, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHWroX, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHWui, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHXpost, ARM64_INS_LDRSH: ldrsh $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHXpre, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHXroW, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHXroX, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSHXui, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSWl, ARM64_INS_LDRSW: ldrsw $rt, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSWpost, ARM64_INS_LDRSW: ldrsw $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSWpre, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSWroW, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSWroX, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSWui, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSl, ARM64_INS_LDR: ldr $rt, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRSui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRWl, ARM64_INS_LDR: ldr $rt, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRWpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRWpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRWroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRWroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRWui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRXl, ARM64_INS_LDR: ldr $rt, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRXpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRXpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRXroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRXroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDRXui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDTRBi, ARM64_INS_LDTRB: ldtrb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDTRHi, ARM64_INS_LDTRH: ldtrh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDTRSBWi, ARM64_INS_LDTRSB: ldtrsb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDTRSBXi, ARM64_INS_LDTRSB: ldtrsb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDTRSHWi, ARM64_INS_LDTRSH: ldtrsh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDTRSHXi, ARM64_INS_LDTRSH: ldtrsh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDTRSWi, ARM64_INS_LDTRSW: ldtrsw $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDTRWi, ARM64_INS_LDTR: ldtr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDTRXi, ARM64_INS_LDTR: ldtr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURBBi, ARM64_INS_LDURB: ldurb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURBi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURDi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURHHi, ARM64_INS_LDURH: ldurh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURHi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURQi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURSBWi, ARM64_INS_LDURSB: ldursb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURSBXi, ARM64_INS_LDURSB: ldursb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURSHWi, ARM64_INS_LDURSH: ldursh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURSHXi, ARM64_INS_LDURSH: ldursh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURSWi, ARM64_INS_LDURSW: ldursw $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURSi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURWi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDURXi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_LDXPW, ARM64_INS_LDXP: ldxp $rt, $rt2, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDXPX, ARM64_INS_LDXP: ldxp $rt, $rt2, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDXRB, ARM64_INS_LDXRB: ldxrb $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDXRH, ARM64_INS_LDXRH: ldxrh $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDXRW, ARM64_INS_LDXR: ldxr $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LDXRX, ARM64_INS_LDXR: ldxr $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LSLVWr, ARM64_INS_LSL: lsl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LSLVXr, ARM64_INS_LSL: lsl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LSRVWr, ARM64_INS_LSR: lsr $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_LSRVXr, ARM64_INS_LSR: lsr $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MADDWrrr, ARM64_INS_MADD: madd $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MADDXrrr, ARM64_INS_MADD: madd $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv16i8, ARM64_INS_MLA: mla.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv2i32, ARM64_INS_MLA: mla.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv2i32_indexed, ARM64_INS_MLA: mla.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv4i16, ARM64_INS_MLA: mla.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv4i16_indexed, ARM64_INS_MLA: mla.4h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv4i32, ARM64_INS_MLA: mla.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv4i32_indexed, ARM64_INS_MLA: mla.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv8i16, ARM64_INS_MLA: mla.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv8i16_indexed, ARM64_INS_MLA: mla.8h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLAv8i8, ARM64_INS_MLA: mla.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv16i8, ARM64_INS_MLS: mls.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv2i32, ARM64_INS_MLS: mls.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv2i32_indexed, ARM64_INS_MLS: mls.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv4i16, ARM64_INS_MLS: mls.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv4i16_indexed, ARM64_INS_MLS: mls.4h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv4i32, ARM64_INS_MLS: mls.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv4i32_indexed, ARM64_INS_MLS: mls.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv8i16, ARM64_INS_MLS: mls.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv8i16_indexed, ARM64_INS_MLS: mls.8h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MLSv8i8, ARM64_INS_MLS: mls.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVID, ARM64_INS_MOVI: movi $rd, $imm8 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv16b_ns, ARM64_INS_MOVI: movi.16b $rd, $imm8 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv2d_ns, ARM64_INS_MOVI: movi.2d $rd, $imm8 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv2i32, ARM64_INS_MOVI: movi.2s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv2s_msl, ARM64_INS_MOVI: movi.2s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv4i16, ARM64_INS_MOVI: movi.4h $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv4i32, ARM64_INS_MOVI: movi.4s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv4s_msl, ARM64_INS_MOVI: movi.4s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv8b_ns, ARM64_INS_MOVI: movi.8b $rd, $imm8 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVIv8i16, ARM64_INS_MOVI: movi.8h $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVKWi, ARM64_INS_MOVK: movk $rd, $imm$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVKXi, ARM64_INS_MOVK: movk $rd, $imm$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVNWi, ARM64_INS_MOVN: movn $rd, $imm$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVNXi, ARM64_INS_MOVN: movn $rd, $imm$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVZWi, ARM64_INS_MOVZ: movz $rd, $imm$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MOVZXi, ARM64_INS_MOVZ: movz $rd, $imm$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MRS, ARM64_INS_MRS: mrs $rt, $systemreg */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MSR, ARM64_INS_MSR: msr $systemreg, $rt */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MSRpstate, ARM64_INS_MSR: msr $pstate_field, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MSUBWrrr, ARM64_INS_MSUB: msub $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MSUBXrrr, ARM64_INS_MSUB: msub $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv16i8, ARM64_INS_MUL: mul.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv2i32, ARM64_INS_MUL: mul.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv2i32_indexed, ARM64_INS_MUL: mul.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv4i16, ARM64_INS_MUL: mul.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv4i16_indexed, ARM64_INS_MUL: mul.4h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv4i32, ARM64_INS_MUL: mul.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv4i32_indexed, ARM64_INS_MUL: mul.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv8i16, ARM64_INS_MUL: mul.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv8i16_indexed, ARM64_INS_MUL: mul.8h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MULv8i8, ARM64_INS_MUL: mul.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MVNIv2i32, ARM64_INS_MVNI: mvni.2s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MVNIv2s_msl, ARM64_INS_MVNI: mvni.2s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MVNIv4i16, ARM64_INS_MVNI: mvni.4h $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MVNIv4i32, ARM64_INS_MVNI: mvni.4s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MVNIv4s_msl, ARM64_INS_MVNI: mvni.4s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_MVNIv8i16, ARM64_INS_MVNI: mvni.8h $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NEGv16i8, ARM64_INS_NEG: neg.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NEGv1i64, ARM64_INS_NEG: neg $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NEGv2i32, ARM64_INS_NEG: neg.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NEGv2i64, ARM64_INS_NEG: neg.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NEGv4i16, ARM64_INS_NEG: neg.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NEGv4i32, ARM64_INS_NEG: neg.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NEGv8i16, ARM64_INS_NEG: neg.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NEGv8i8, ARM64_INS_NEG: neg.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NOTv16i8, ARM64_INS_NOT: not.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_NOTv8i8, ARM64_INS_NOT: not.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORNWrs, ARM64_INS_ORN: orn $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORNXrs, ARM64_INS_ORN: orn $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORNv16i8, ARM64_INS_ORN: orn.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORNv8i8, ARM64_INS_ORN: orn.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRWri, ARM64_INS_ORR: orr $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, , CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRWrs, ARM64_INS_ORR: orr $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRXri, ARM64_INS_ORR: orr $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, , CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRXrs, ARM64_INS_ORR: orr $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRv16i8, ARM64_INS_ORR: orr.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRv2i32, ARM64_INS_ORR: orr.2s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRv4i16, ARM64_INS_ORR: orr.4h $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRv4i32, ARM64_INS_ORR: orr.4s $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRv8i16, ARM64_INS_ORR: orr.8h $rd, $imm8$shift */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ORRv8i8, ARM64_INS_ORR: orr.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_PMULLv16i8, ARM64_INS_PMULL2: pmull2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_PMULLv1i64, ARM64_INS_PMULL: pmull.1q $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_PMULLv2i64, ARM64_INS_PMULL2: pmull2.1q $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_PMULLv8i8, ARM64_INS_PMULL: pmull.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_PMULv16i8, ARM64_INS_PMUL: pmul.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_PMULv8i8, ARM64_INS_PMUL: pmul.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_PRFMl, ARM64_INS_PRFM: prfm $rt, $label */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_PRFMroW, ARM64_INS_PRFM: prfm $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_PRFMroX, ARM64_INS_PRFM: prfm $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_PRFMui, ARM64_INS_PRFM: prfm $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_PRFUMi, ARM64_INS_PRFUM: prfum $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN: raddhn.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2: raddhn2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN: raddhn.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2: raddhn2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2: raddhn2.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN: raddhn.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RBITWr, ARM64_INS_RBIT: rbit $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RBITXr, ARM64_INS_RBIT: rbit $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RBITv16i8, ARM64_INS_RBIT: rbit.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RBITv8i8, ARM64_INS_RBIT: rbit.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RET, ARM64_INS_RET: ret $rn */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_REV16Wr, ARM64_INS_REV16: rev16 $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV16Xr, ARM64_INS_REV16: rev16 $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV16v16i8, ARM64_INS_REV16: rev16.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV16v8i8, ARM64_INS_REV16: rev16.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV32Xr, ARM64_INS_REV32: rev32 $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV32v16i8, ARM64_INS_REV32: rev32.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV32v4i16, ARM64_INS_REV32: rev32.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV32v8i16, ARM64_INS_REV32: rev32.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV32v8i8, ARM64_INS_REV32: rev32.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV64v16i8, ARM64_INS_REV64: rev64.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV64v2i32, ARM64_INS_REV64: rev64.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV64v4i16, ARM64_INS_REV64: rev64.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV64v4i32, ARM64_INS_REV64: rev64.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV64v8i16, ARM64_INS_REV64: rev64.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REV64v8i8, ARM64_INS_REV64: rev64.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REVWr, ARM64_INS_REV: rev $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_REVXr, ARM64_INS_REV: rev $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RORVWr, ARM64_INS_ROR: ror $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RORVXr, ARM64_INS_ROR: ror $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2: rshrn2.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN: rshrn.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN: rshrn.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2: rshrn2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2: rshrn2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN: rshrn.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN: rsubhn.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2: rsubhn2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN: rsubhn.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2: rsubhn2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2: rsubhn2.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN: rsubhn.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2: sabal2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL: sabal.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL: sabal.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2: sabal2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2: sabal2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL: sabal.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABAv16i8, ARM64_INS_SABA: saba.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABAv2i32, ARM64_INS_SABA: saba.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABAv4i16, ARM64_INS_SABA: saba.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABAv4i32, ARM64_INS_SABA: saba.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABAv8i16, ARM64_INS_SABA: saba.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABAv8i8, ARM64_INS_SABA: saba.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2: sabdl2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL: sabdl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL: sabdl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2: sabdl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2: sabdl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL: sabdl.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDv16i8, ARM64_INS_SABD: sabd.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDv2i32, ARM64_INS_SABD: sabd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDv4i16, ARM64_INS_SABD: sabd.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDv4i32, ARM64_INS_SABD: sabd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDv8i16, ARM64_INS_SABD: sabd.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SABDv8i8, ARM64_INS_SABD: sabd.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP: sadalp.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP: sadalp.1d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP: sadalp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP: sadalp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP: sadalp.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP: sadalp.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP: saddlp.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP: saddlp.1d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP: saddlp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP: saddlp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP: saddlp.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP: saddlp.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLVv16i8v, ARM64_INS_SADDLV: saddlv.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLVv4i16v, ARM64_INS_SADDLV: saddlv.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLVv4i32v, ARM64_INS_SADDLV: saddlv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLVv8i16v, ARM64_INS_SADDLV: saddlv.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLVv8i8v, ARM64_INS_SADDLV: saddlv.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2: saddl2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL: saddl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL: saddl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2: saddl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2: saddl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL: saddl.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2: saddw2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW: saddw.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW: saddw.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2: saddw2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2: saddw2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW: saddw.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SBCSWr, ARM64_INS_SBCS: sbcs $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SBCSXr, ARM64_INS_SBCS: sbcs $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SBCWr, ARM64_INS_SBC: sbc $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SBCXr, ARM64_INS_SBC: sbc $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SBFMWri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SBFMXri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SCVTFSWDri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFSWSri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFSXDri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFSXSri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFUWDri, ARM64_INS_SCVTF: scvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFUWSri, ARM64_INS_SCVTF: scvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFUXDri, ARM64_INS_SCVTF: scvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFUXSri, ARM64_INS_SCVTF: scvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFd, ARM64_INS_SCVTF: scvtf $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFs, ARM64_INS_SCVTF: scvtf $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFv1i32, ARM64_INS_SCVTF: scvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFv1i64, ARM64_INS_SCVTF: scvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFv2f32, ARM64_INS_SCVTF: scvtf.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFv2f64, ARM64_INS_SCVTF: scvtf.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF: scvtf.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF: scvtf.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFv4f32, ARM64_INS_SCVTF: scvtf.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF: scvtf.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SDIVWr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SDIVXr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SDIV_IntWr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SDIV_IntXr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHA1Crrr, ARM64_INS_SHA1C: sha1c.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA1Hrr, ARM64_INS_SHA1H: sha1h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA1Mrrr, ARM64_INS_SHA1M: sha1m.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA1Prrr, ARM64_INS_SHA1P: sha1p.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0: sha1su0.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1: sha1su1.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA256H2rrr, ARM64_INS_SHA256H2: sha256h2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA256Hrrr, ARM64_INS_SHA256H: sha256h.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0: sha256su0.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1: sha256su1.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SHADDv16i8, ARM64_INS_SHADD: shadd.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHADDv2i32, ARM64_INS_SHADD: shadd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHADDv4i16, ARM64_INS_SHADD: shadd.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHADDv4i32, ARM64_INS_SHADD: shadd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHADDv8i16, ARM64_INS_SHADD: shadd.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHADDv8i8, ARM64_INS_SHADD: shadd.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLLv16i8, ARM64_INS_SHLL2: shll2.8h $rd, $rn, #8 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLLv2i32, ARM64_INS_SHLL: shll.2d $rd, $rn, #32 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLLv4i16, ARM64_INS_SHLL: shll.4s $rd, $rn, #16 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLLv4i32, ARM64_INS_SHLL2: shll2.2d $rd, $rn, #32 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLLv8i16, ARM64_INS_SHLL2: shll2.4s $rd, $rn, #16 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLLv8i8, ARM64_INS_SHLL: shll.8h $rd, $rn, #8 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLd, ARM64_INS_SHL: shl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLv16i8_shift, ARM64_INS_SHL: shl.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLv2i32_shift, ARM64_INS_SHL: shl.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLv2i64_shift, ARM64_INS_SHL: shl.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLv4i16_shift, ARM64_INS_SHL: shl.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLv4i32_shift, ARM64_INS_SHL: shl.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLv8i16_shift, ARM64_INS_SHL: shl.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHLv8i8_shift, ARM64_INS_SHL: shl.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2: shrn2.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHRNv2i32_shift, ARM64_INS_SHRN: shrn.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHRNv4i16_shift, ARM64_INS_SHRN: shrn.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2: shrn2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2: shrn2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHRNv8i8_shift, ARM64_INS_SHRN: shrn.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHSUBv16i8, ARM64_INS_SHSUB: shsub.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHSUBv2i32, ARM64_INS_SHSUB: shsub.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHSUBv4i16, ARM64_INS_SHSUB: shsub.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHSUBv4i32, ARM64_INS_SHSUB: shsub.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHSUBv8i16, ARM64_INS_SHSUB: shsub.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SHSUBv8i8, ARM64_INS_SHSUB: shsub.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SLId, ARM64_INS_SLI: sli $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SLIv16i8_shift, ARM64_INS_SLI: sli.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SLIv2i32_shift, ARM64_INS_SLI: sli.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SLIv2i64_shift, ARM64_INS_SLI: sli.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SLIv4i16_shift, ARM64_INS_SLI: sli.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SLIv4i32_shift, ARM64_INS_SLI: sli.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SLIv8i16_shift, ARM64_INS_SLI: sli.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SLIv8i8_shift, ARM64_INS_SLI: sli.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} |
| }, |
| { /* AArch64_SMADDLrrr, ARM64_INS_SMADDL: smaddl $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXPv16i8, ARM64_INS_SMAXP: smaxp.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXPv2i32, ARM64_INS_SMAXP: smaxp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXPv4i16, ARM64_INS_SMAXP: smaxp.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXPv4i32, ARM64_INS_SMAXP: smaxp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXPv8i16, ARM64_INS_SMAXP: smaxp.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXPv8i8, ARM64_INS_SMAXP: smaxp.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXVv16i8v, ARM64_INS_SMAXV: smaxv.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXVv4i16v, ARM64_INS_SMAXV: smaxv.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXVv4i32v, ARM64_INS_SMAXV: smaxv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXVv8i16v, ARM64_INS_SMAXV: smaxv.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXVv8i8v, ARM64_INS_SMAXV: smaxv.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXv16i8, ARM64_INS_SMAX: smax.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXv2i32, ARM64_INS_SMAX: smax.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXv4i16, ARM64_INS_SMAX: smax.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXv4i32, ARM64_INS_SMAX: smax.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXv8i16, ARM64_INS_SMAX: smax.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMAXv8i8, ARM64_INS_SMAX: smax.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMC, ARM64_INS_SMC: smc $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINPv16i8, ARM64_INS_SMINP: sminp.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINPv2i32, ARM64_INS_SMINP: sminp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINPv4i16, ARM64_INS_SMINP: sminp.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINPv4i32, ARM64_INS_SMINP: sminp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINPv8i16, ARM64_INS_SMINP: sminp.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINPv8i8, ARM64_INS_SMINP: sminp.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINVv16i8v, ARM64_INS_SMINV: sminv.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINVv4i16v, ARM64_INS_SMINV: sminv.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINVv4i32v, ARM64_INS_SMINV: sminv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINVv8i16v, ARM64_INS_SMINV: sminv.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINVv8i8v, ARM64_INS_SMINV: sminv.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINv16i8, ARM64_INS_SMIN: smin.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINv2i32, ARM64_INS_SMIN: smin.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINv4i16, ARM64_INS_SMIN: smin.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINv4i32, ARM64_INS_SMIN: smin.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINv8i16, ARM64_INS_SMIN: smin.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMINv8i8, ARM64_INS_SMIN: smin.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2: smlal2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL: smlal.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL: smlal.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL: smlal.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL: smlal.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2: smlal2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2: smlal2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2: smlal2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2: smlal2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL: smlal.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2: smlsl2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL: smlsl.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL: smlsl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL: smlsl.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL: smlsl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2: smlsl2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2: smlsl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2: smlsl2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2: smlsl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL: smlsl.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMOVvi16to32, ARM64_INS_SMOV: smov.h $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMOVvi16to64, ARM64_INS_SMOV: smov.h $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMOVvi32to64, ARM64_INS_SMOV: smov.s $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMOVvi8to32, ARM64_INS_SMOV: smov.b $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMOVvi8to64, ARM64_INS_SMOV: smov.b $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMSUBLrrr, ARM64_INS_SMSUBL: smsubl $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULHrr, ARM64_INS_SMULH: smulh $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2: smull2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL: smull.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL: smull.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL: smull.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL: smull.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2: smull2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2: smull2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2: smull2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2: smull2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL: smull.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv16i8, ARM64_INS_SQABS: sqabs.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv1i16, ARM64_INS_SQABS: sqabs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv1i32, ARM64_INS_SQABS: sqabs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv1i64, ARM64_INS_SQABS: sqabs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv1i8, ARM64_INS_SQABS: sqabs $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv2i32, ARM64_INS_SQABS: sqabs.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv2i64, ARM64_INS_SQABS: sqabs.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv4i16, ARM64_INS_SQABS: sqabs.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv4i32, ARM64_INS_SQABS: sqabs.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv8i16, ARM64_INS_SQABS: sqabs.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQABSv8i8, ARM64_INS_SQABS: sqabs.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv16i8, ARM64_INS_SQADD: sqadd.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv1i16, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv1i32, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv1i64, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv1i8, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv2i32, ARM64_INS_SQADD: sqadd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv2i64, ARM64_INS_SQADD: sqadd.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv4i16, ARM64_INS_SQADD: sqadd.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv4i32, ARM64_INS_SQADD: sqadd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv8i16, ARM64_INS_SQADD: sqadd.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQADDv8i8, ARM64_INS_SQADD: sqadd.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALi16, ARM64_INS_SQDMLAL: sqdmlal $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALi32, ARM64_INS_SQDMLAL: sqdmlal $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL: sqdmlal.h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL: sqdmlal.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL: sqdmlal.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL: sqdmlal.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL: sqdmlal.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL: sqdmlal.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2: sqdmlal2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2: sqdmlal2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2: sqdmlal2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2: sqdmlal2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL: sqdmlsl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL: sqdmlsl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL: sqdmlsl.h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL: sqdmlsl.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL: sqdmlsl.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL: sqdmlsl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL: sqdmlsl.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL: sqdmlsl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2: sqdmlsl2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2: sqdmlsl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2: sqdmlsl2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2: sqdmlsl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH: sqdmulh $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH: sqdmulh.h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH: sqdmulh $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH: sqdmulh.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH: sqdmulh.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH: sqdmulh.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH: sqdmulh.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH: sqdmulh.4h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH: sqdmulh.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH: sqdmulh.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH: sqdmulh.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH: sqdmulh.8h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLi16, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLi32, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL: sqdmull.h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL: sqdmull.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2: sqdmull2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2: sqdmull2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2: sqdmull2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2: sqdmull2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv16i8, ARM64_INS_SQNEG: sqneg.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv1i16, ARM64_INS_SQNEG: sqneg $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv1i32, ARM64_INS_SQNEG: sqneg $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv1i64, ARM64_INS_SQNEG: sqneg $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv1i8, ARM64_INS_SQNEG: sqneg $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv2i32, ARM64_INS_SQNEG: sqneg.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv2i64, ARM64_INS_SQNEG: sqneg.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv4i16, ARM64_INS_SQNEG: sqneg.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv4i32, ARM64_INS_SQNEG: sqneg.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv8i16, ARM64_INS_SQNEG: sqneg.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQNEGv8i8, ARM64_INS_SQNEG: sqneg.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH: sqrdmulh $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH: sqrdmulh $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH: sqrdmulh.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.2s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH: sqrdmulh.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.4h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH: sqrdmulh.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH: sqrdmulh.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.8h $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL: sqrshl.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL: sqrshl.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL: sqrshl.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL: sqrshl.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL: sqrshl.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL: sqrshl.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL: sqrshl.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNb, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNh, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNs, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2: sqrshrn2.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN: sqrshrn.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN: sqrshrn.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2: sqrshrn2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2: sqrshrn2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN: sqrshrn.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN: sqrshrun.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN: sqrshrun.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN: sqrshrun.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUb, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUd, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUh, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUs, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU: sqshlu.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU: sqshlu.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU: sqshlu.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU: sqshlu.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU: sqshlu.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU: sqshlu.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU: sqshlu.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLb, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLd, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLh, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLs, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv16i8, ARM64_INS_SQSHL: sqshl.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL: sqshl.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv1i16, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv1i32, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv1i64, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv1i8, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv2i32, ARM64_INS_SQSHL: sqshl.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL: sqshl.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv2i64, ARM64_INS_SQSHL: sqshl.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL: sqshl.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv4i16, ARM64_INS_SQSHL: sqshl.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL: sqshl.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv4i32, ARM64_INS_SQSHL: sqshl.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL: sqshl.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv8i16, ARM64_INS_SQSHL: sqshl.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL: sqshl.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv8i8, ARM64_INS_SQSHL: sqshl.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL: sqshl.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNb, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNh, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNs, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2: sqshrn2.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN: sqshrn.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN: sqshrn.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2: sqshrn2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2: sqshrn2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN: sqshrn.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNb, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNh, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNs, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2: sqshrun2.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN: sqshrun.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN: sqshrun.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2: sqshrun2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2: sqshrun2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN: sqshrun.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv16i8, ARM64_INS_SQSUB: sqsub.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv1i16, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv1i32, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv1i64, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv1i8, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv2i32, ARM64_INS_SQSUB: sqsub.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv2i64, ARM64_INS_SQSUB: sqsub.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv4i16, ARM64_INS_SQSUB: sqsub.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv4i32, ARM64_INS_SQSUB: sqsub.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv8i16, ARM64_INS_SQSUB: sqsub.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQSUBv8i8, ARM64_INS_SQSUB: sqsub.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv16i8, ARM64_INS_SQXTN2: sqxtn2.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv1i16, ARM64_INS_SQXTN: sqxtn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv1i32, ARM64_INS_SQXTN: sqxtn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv1i8, ARM64_INS_SQXTN: sqxtn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv2i32, ARM64_INS_SQXTN: sqxtn.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv4i16, ARM64_INS_SQXTN: sqxtn.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv4i32, ARM64_INS_SQXTN2: sqxtn2.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv8i16, ARM64_INS_SQXTN2: sqxtn2.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTNv8i8, ARM64_INS_SQXTN: sqxtn.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2: sqxtun2.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN: sqxtun.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN: sqxtun.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2: sqxtun2.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2: sqxtun2.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN: sqxtun.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRHADDv16i8, ARM64_INS_SRHADD: srhadd.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRHADDv2i32, ARM64_INS_SRHADD: srhadd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRHADDv4i16, ARM64_INS_SRHADD: srhadd.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRHADDv4i32, ARM64_INS_SRHADD: srhadd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRHADDv8i16, ARM64_INS_SRHADD: srhadd.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRHADDv8i8, ARM64_INS_SRHADD: srhadd.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRId, ARM64_INS_SRI: sri $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRIv16i8_shift, ARM64_INS_SRI: sri.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRIv2i32_shift, ARM64_INS_SRI: sri.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRIv2i64_shift, ARM64_INS_SRI: sri.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRIv4i16_shift, ARM64_INS_SRI: sri.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRIv4i32_shift, ARM64_INS_SRI: sri.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRIv8i16_shift, ARM64_INS_SRI: sri.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRIv8i8_shift, ARM64_INS_SRI: sri.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHLv16i8, ARM64_INS_SRSHL: srshl.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHLv1i64, ARM64_INS_SRSHL: srshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHLv2i32, ARM64_INS_SRSHL: srshl.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHLv2i64, ARM64_INS_SRSHL: srshl.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHLv4i16, ARM64_INS_SRSHL: srshl.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHLv4i32, ARM64_INS_SRSHL: srshl.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHLv8i16, ARM64_INS_SRSHL: srshl.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHLv8i8, ARM64_INS_SRSHL: srshl.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHRd, ARM64_INS_SRSHR: srshr $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR: srshr.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR: srshr.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR: srshr.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR: srshr.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR: srshr.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR: srshr.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR: srshr.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSRAd, ARM64_INS_SRSRA: srsra $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA: srsra.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA: srsra.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA: srsra.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA: srsra.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA: srsra.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA: srsra.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA: srsra.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2: sshll2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL: sshll.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL: sshll.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2: sshll2.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2: sshll2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL: sshll.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLv16i8, ARM64_INS_SSHL: sshl.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLv1i64, ARM64_INS_SSHL: sshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLv2i32, ARM64_INS_SSHL: sshl.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLv2i64, ARM64_INS_SSHL: sshl.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLv4i16, ARM64_INS_SSHL: sshl.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLv4i32, ARM64_INS_SSHL: sshl.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLv8i16, ARM64_INS_SSHL: sshl.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHLv8i8, ARM64_INS_SSHL: sshl.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHRd, ARM64_INS_SSHR: sshr $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHRv16i8_shift, ARM64_INS_SSHR: sshr.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHRv2i32_shift, ARM64_INS_SSHR: sshr.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHRv2i64_shift, ARM64_INS_SSHR: sshr.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHRv4i16_shift, ARM64_INS_SSHR: sshr.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHRv4i32_shift, ARM64_INS_SSHR: sshr.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHRv8i16_shift, ARM64_INS_SSHR: sshr.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSHRv8i8_shift, ARM64_INS_SSHR: sshr.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSRAd, ARM64_INS_SSRA: ssra $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSRAv16i8_shift, ARM64_INS_SSRA: ssra.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSRAv2i32_shift, ARM64_INS_SSRA: ssra.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSRAv2i64_shift, ARM64_INS_SSRA: ssra.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSRAv4i16_shift, ARM64_INS_SSRA: ssra.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSRAv4i32_shift, ARM64_INS_SSRA: ssra.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSRAv8i16_shift, ARM64_INS_SSRA: ssra.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSRAv8i8_shift, ARM64_INS_SSRA: ssra.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2: ssubl2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL: ssubl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL: ssubl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2: ssubl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2: ssubl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL: ssubl.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2: ssubw2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW: ssubw.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW: ssubw.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2: ssubw2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2: ssubw2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW: ssubw.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv16b, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv1d, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv2d, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv2s, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv4h, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv4s, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv8b, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv8h, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Fourv8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev16b, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev1d, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev2d, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev2s, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev4h, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev4s, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev8b, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev8h, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Onev8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev16b, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev1d, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev2d, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev2s, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev4h, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev4s, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev8b, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev8h, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Threev8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov16b, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov1d, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov2d, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov2s, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov4h, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov4s, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov8b, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov8h, ARM64_INS_ST1: st1 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1Twov8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1i16, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1i16_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1i32, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1i32_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1i64, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1i64_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1i8, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST1i8_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov16b, ARM64_INS_ST2: st2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov16b_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov2d, ARM64_INS_ST2: st2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov2d_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov2s, ARM64_INS_ST2: st2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov2s_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov4h, ARM64_INS_ST2: st2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov4h_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov4s, ARM64_INS_ST2: st2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov4s_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov8b, ARM64_INS_ST2: st2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov8b_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov8h, ARM64_INS_ST2: st2 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2Twov8h_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2i16, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2i16_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2i32, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2i32_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2i64, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2i64_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2i8, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST2i8_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev16b, ARM64_INS_ST3: st3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev16b_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev2d, ARM64_INS_ST3: st3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev2d_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev2s, ARM64_INS_ST3: st3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev2s_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev4h, ARM64_INS_ST3: st3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev4h_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev4s, ARM64_INS_ST3: st3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev4s_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev8b, ARM64_INS_ST3: st3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev8b_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev8h, ARM64_INS_ST3: st3 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3Threev8h_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3i16, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3i16_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3i32, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3i32_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3i64, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3i64_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3i8, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST3i8_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv16b, ARM64_INS_ST4: st4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv16b_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv2d, ARM64_INS_ST4: st4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv2d_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv2s, ARM64_INS_ST4: st4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv2s_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv4h, ARM64_INS_ST4: st4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv4h_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv4s, ARM64_INS_ST4: st4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv4s_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv8b, ARM64_INS_ST4: st4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv8b_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv8h, ARM64_INS_ST4: st4 $vt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4Fourv8h_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4i16, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4i16_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4i32, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4i32_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4i64, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4i64_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4i8, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ST4i8_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLRB, ARM64_INS_STLRB: stlrb $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLRH, ARM64_INS_STLRH: stlrh $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLRW, ARM64_INS_STLR: stlr $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLRX, ARM64_INS_STLR: stlr $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLXPW, ARM64_INS_STLXP: stlxp $ws, $rt, $rt2, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLXPX, ARM64_INS_STLXP: stlxp $ws, $rt, $rt2, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLXRB, ARM64_INS_STLXRB: stlxrb $ws, $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLXRH, ARM64_INS_STLXRH: stlxrh $ws, $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLXRW, ARM64_INS_STLXR: stlxr $ws, $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STLXRX, ARM64_INS_STLXR: stlxr $ws, $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STNPDi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STNPQi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STNPSi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STNPWi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STNPXi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPDi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPDpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPDpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPQi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPQpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPQpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPSi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPSpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPSpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPWi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPWpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPWpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPXi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPXpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STPXpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBBpost, ARM64_INS_STRB: strb $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBBpre, ARM64_INS_STRB: strb $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBBroW, ARM64_INS_STRB: strb $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBBroX, ARM64_INS_STRB: strb $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBBui, ARM64_INS_STRB: strb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBpost, ARM64_INS_STR: str $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRBui, ARM64_INS_STR: str $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRDpost, ARM64_INS_STR: str $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRDpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRDroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRDroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRDui, ARM64_INS_STR: str $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHHpost, ARM64_INS_STRH: strh $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHHpre, ARM64_INS_STRH: strh $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHHroW, ARM64_INS_STRH: strh $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHHroX, ARM64_INS_STRH: strh $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHHui, ARM64_INS_STRH: strh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHpost, ARM64_INS_STR: str $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRHui, ARM64_INS_STR: str $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRQpost, ARM64_INS_STR: str $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRQpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRQroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRQroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRQui, ARM64_INS_STR: str $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRSpost, ARM64_INS_STR: str $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRSpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRSroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRSroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRSui, ARM64_INS_STR: str $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRWpost, ARM64_INS_STR: str $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRWpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRWroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRWroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRWui, ARM64_INS_STR: str $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRXpost, ARM64_INS_STR: str $rt, [$rn], $offset */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRXpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRXroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRXroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STRXui, ARM64_INS_STR: str $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STTRBi, ARM64_INS_STTRB: sttrb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STTRHi, ARM64_INS_STTRH: sttrh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STTRWi, ARM64_INS_STTR: sttr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STTRXi, ARM64_INS_STTR: sttr $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURBBi, ARM64_INS_STURB: sturb $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURBi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURDi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURHHi, ARM64_INS_STURH: sturh $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURHi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURQi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURSi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURWi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STURXi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STXPW, ARM64_INS_STXP: stxp $ws, $rt, $rt2, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STXPX, ARM64_INS_STXP: stxp $ws, $rt, $rt2, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STXRB, ARM64_INS_STXRB: stxrb $ws, $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STXRH, ARM64_INS_STXRH: stxrh $ws, $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STXRW, ARM64_INS_STXR: stxr $ws, $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_STXRX, ARM64_INS_STXR: stxr $ws, $rt, [$rn] */ |
| 0, |
| { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN: subhn.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2: subhn2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN: subhn.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2: subhn2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2: subhn2.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN: subhn.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBSWri, ARM64_INS_SUBS: subs $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBSWrs, ARM64_INS_SUBS: subs $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBSWrx, ARM64_INS_SUBS: subs $r1, $r2, $r3 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBSXri, ARM64_INS_SUBS: subs $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBSXrs, ARM64_INS_SUBS: subs $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBSXrx, ARM64_INS_SUBS: subs $r1, $r2, $r3 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBSXrx64, ARM64_INS_SUBS: subs $rd, $rn, $rm$ext */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBWri, ARM64_INS_SUB: sub $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBWrs, ARM64_INS_SUB: sub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBWrx, ARM64_INS_SUB: sub $r1, $r2, $r3 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBXri, ARM64_INS_SUB: sub $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBXrs, ARM64_INS_SUB: sub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBXrx, ARM64_INS_SUB: sub $r1, $r2, $r3 */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBXrx64, ARM64_INS_SUB: sub $rd, $rn, $rm$ext */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBv16i8, ARM64_INS_SUB: sub.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBv1i64, ARM64_INS_SUB: sub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBv2i32, ARM64_INS_SUB: sub.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBv2i64, ARM64_INS_SUB: sub.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBv4i16, ARM64_INS_SUB: sub.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBv4i32, ARM64_INS_SUB: sub.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBv8i16, ARM64_INS_SUB: sub.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUBv8i8, ARM64_INS_SUB: sub.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv16i8, ARM64_INS_SUQADD: suqadd.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv1i16, ARM64_INS_SUQADD: suqadd $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv1i32, ARM64_INS_SUQADD: suqadd $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv1i64, ARM64_INS_SUQADD: suqadd $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv1i8, ARM64_INS_SUQADD: suqadd $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv2i32, ARM64_INS_SUQADD: suqadd.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv2i64, ARM64_INS_SUQADD: suqadd.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv4i16, ARM64_INS_SUQADD: suqadd.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv4i32, ARM64_INS_SUQADD: suqadd.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv8i16, ARM64_INS_SUQADD: suqadd.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SUQADDv8i8, ARM64_INS_SUQADD: suqadd.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SVC, ARM64_INS_SVC: svc $imm */ |
| 0, |
| { CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SYSLxt, ARM64_INS_SYSL: sysl $rt, $op1, $cn, $cm, $op2 */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_SYSxt, ARM64_INS_SYS: sys $op1, $cn, $cm, $op2, $rt */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBLv16i8Four, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBLv16i8One, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBLv16i8Three, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBLv16i8Two, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBLv8i8Four, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBLv8i8One, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBLv8i8Three, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBLv8i8Two, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBNZW, ARM64_INS_TBNZ: tbnz $rt, $bit_off, $target */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBNZX, ARM64_INS_TBNZ: tbnz $rt, $bit_off, $target */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBXv16i8Four, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBXv16i8One, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBXv16i8Three, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBXv16i8Two, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBXv8i8Four, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBXv8i8One, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBXv8i8Three, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBXv8i8Two, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBZW, ARM64_INS_TBZ: tbz $rt, $bit_off, $target */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TBZX, ARM64_INS_TBZ: tbz $rt, $bit_off, $target */ |
| 0, |
| { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN1v16i8, ARM64_INS_TRN1: trn1.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN1v2i32, ARM64_INS_TRN1: trn1.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN1v2i64, ARM64_INS_TRN1: trn1.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN1v4i16, ARM64_INS_TRN1: trn1.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN1v4i32, ARM64_INS_TRN1: trn1.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN1v8i16, ARM64_INS_TRN1: trn1.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN1v8i8, ARM64_INS_TRN1: trn1.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN2v16i8, ARM64_INS_TRN2: trn2.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN2v2i32, ARM64_INS_TRN2: trn2.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN2v2i64, ARM64_INS_TRN2: trn2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN2v4i16, ARM64_INS_TRN2: trn2.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN2v4i32, ARM64_INS_TRN2: trn2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN2v8i16, ARM64_INS_TRN2: trn2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_TRN2v8i8, ARM64_INS_TRN2: trn2.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2: uabal2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL: uabal.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL: uabal.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2: uabal2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2: uabal2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL: uabal.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABAv16i8, ARM64_INS_UABA: uaba.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABAv2i32, ARM64_INS_UABA: uaba.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABAv4i16, ARM64_INS_UABA: uaba.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABAv4i32, ARM64_INS_UABA: uaba.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABAv8i16, ARM64_INS_UABA: uaba.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABAv8i8, ARM64_INS_UABA: uaba.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2: uabdl2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL: uabdl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL: uabdl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2: uabdl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2: uabdl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL: uabdl.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDv16i8, ARM64_INS_UABD: uabd.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDv2i32, ARM64_INS_UABD: uabd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDv4i16, ARM64_INS_UABD: uabd.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDv4i32, ARM64_INS_UABD: uabd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDv8i16, ARM64_INS_UABD: uabd.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UABDv8i8, ARM64_INS_UABD: uabd.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP: uadalp.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP: uadalp.1d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP: uadalp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP: uadalp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP: uadalp.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP: uadalp.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP: uaddlp.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP: uaddlp.1d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP: uaddlp.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP: uaddlp.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP: uaddlp.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP: uaddlp.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLVv16i8v, ARM64_INS_UADDLV: uaddlv.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLVv4i16v, ARM64_INS_UADDLV: uaddlv.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLVv4i32v, ARM64_INS_UADDLV: uaddlv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLVv8i16v, ARM64_INS_UADDLV: uaddlv.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLVv8i8v, ARM64_INS_UADDLV: uaddlv.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2: uaddl2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL: uaddl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL: uaddl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2: uaddl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2: uaddl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL: uaddl.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2: uaddw2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW: uaddw.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW: uaddw.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2: uaddw2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2: uaddw2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW: uaddw.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UBFMWri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UBFMXri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFSWDri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFSWSri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFSXDri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFSXSri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFUWDri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFUWSri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFUXDri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFUXSri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFd, ARM64_INS_UCVTF: ucvtf $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFs, ARM64_INS_UCVTF: ucvtf $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFv1i32, ARM64_INS_UCVTF: ucvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFv1i64, ARM64_INS_UCVTF: ucvtf $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFv2f32, ARM64_INS_UCVTF: ucvtf.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFv2f64, ARM64_INS_UCVTF: ucvtf.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF: ucvtf.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF: ucvtf.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFv4f32, ARM64_INS_UCVTF: ucvtf.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF: ucvtf.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UDIVWr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UDIVXr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UDIV_IntWr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UDIV_IntXr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHADDv16i8, ARM64_INS_UHADD: uhadd.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHADDv2i32, ARM64_INS_UHADD: uhadd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHADDv4i16, ARM64_INS_UHADD: uhadd.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHADDv4i32, ARM64_INS_UHADD: uhadd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHADDv8i16, ARM64_INS_UHADD: uhadd.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHADDv8i8, ARM64_INS_UHADD: uhadd.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHSUBv16i8, ARM64_INS_UHSUB: uhsub.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHSUBv2i32, ARM64_INS_UHSUB: uhsub.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHSUBv4i16, ARM64_INS_UHSUB: uhsub.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHSUBv4i32, ARM64_INS_UHSUB: uhsub.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHSUBv8i16, ARM64_INS_UHSUB: uhsub.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UHSUBv8i8, ARM64_INS_UHSUB: uhsub.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMADDLrrr, ARM64_INS_UMADDL: umaddl $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXPv16i8, ARM64_INS_UMAXP: umaxp.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXPv2i32, ARM64_INS_UMAXP: umaxp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXPv4i16, ARM64_INS_UMAXP: umaxp.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXPv4i32, ARM64_INS_UMAXP: umaxp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXPv8i16, ARM64_INS_UMAXP: umaxp.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXPv8i8, ARM64_INS_UMAXP: umaxp.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXVv16i8v, ARM64_INS_UMAXV: umaxv.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXVv4i16v, ARM64_INS_UMAXV: umaxv.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXVv4i32v, ARM64_INS_UMAXV: umaxv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXVv8i16v, ARM64_INS_UMAXV: umaxv.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXVv8i8v, ARM64_INS_UMAXV: umaxv.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXv16i8, ARM64_INS_UMAX: umax.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXv2i32, ARM64_INS_UMAX: umax.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXv4i16, ARM64_INS_UMAX: umax.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXv4i32, ARM64_INS_UMAX: umax.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXv8i16, ARM64_INS_UMAX: umax.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMAXv8i8, ARM64_INS_UMAX: umax.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINPv16i8, ARM64_INS_UMINP: uminp.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINPv2i32, ARM64_INS_UMINP: uminp.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINPv4i16, ARM64_INS_UMINP: uminp.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINPv4i32, ARM64_INS_UMINP: uminp.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINPv8i16, ARM64_INS_UMINP: uminp.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINPv8i8, ARM64_INS_UMINP: uminp.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINVv16i8v, ARM64_INS_UMINV: uminv.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINVv4i16v, ARM64_INS_UMINV: uminv.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINVv4i32v, ARM64_INS_UMINV: uminv.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINVv8i16v, ARM64_INS_UMINV: uminv.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINVv8i8v, ARM64_INS_UMINV: uminv.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINv16i8, ARM64_INS_UMIN: umin.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINv2i32, ARM64_INS_UMIN: umin.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINv4i16, ARM64_INS_UMIN: umin.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINv4i32, ARM64_INS_UMIN: umin.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINv8i16, ARM64_INS_UMIN: umin.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMINv8i8, ARM64_INS_UMIN: umin.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2: umlal2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL: umlal.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL: umlal.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL: umlal.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL: umlal.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2: umlal2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2: umlal2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2: umlal2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2: umlal2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL: umlal.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2: umlsl2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL: umlsl.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL: umlsl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL: umlsl.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL: umlsl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2: umlsl2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2: umlsl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2: umlsl2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2: umlsl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL: umlsl.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMOVvi16, ARM64_INS_UMOV: umov.h $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMOVvi32, ARM64_INS_UMOV: umov.s $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMOVvi64, ARM64_INS_UMOV: umov.d $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMOVvi8, ARM64_INS_UMOV: umov.b $rd, $rn$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMSUBLrrr, ARM64_INS_UMSUBL: umsubl $rd, $rn, $rm, $ra */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULHrr, ARM64_INS_UMULH: umulh $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2: umull2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL: umull.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL: umull.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL: umull.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL: umull.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2: umull2.2d $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2: umull2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2: umull2.4s $rd, $rn, $rm$idx */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2: umull2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL: umull.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv16i8, ARM64_INS_UQADD: uqadd.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv1i16, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv1i32, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv1i64, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv1i8, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv2i32, ARM64_INS_UQADD: uqadd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv2i64, ARM64_INS_UQADD: uqadd.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv4i16, ARM64_INS_UQADD: uqadd.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv4i32, ARM64_INS_UQADD: uqadd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv8i16, ARM64_INS_UQADD: uqadd.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQADDv8i8, ARM64_INS_UQADD: uqadd.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL: uqrshl.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL: uqrshl.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL: uqrshl.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL: uqrshl.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL: uqrshl.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL: uqrshl.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL: uqrshl.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNb, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNh, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNs, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2: uqrshrn2.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN: uqrshrn.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN: uqrshrn.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2: uqrshrn2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2: uqrshrn2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN: uqrshrn.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLb, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLd, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLh, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLs, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv16i8, ARM64_INS_UQSHL: uqshl.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL: uqshl.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv1i16, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv1i32, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv1i64, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv1i8, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv2i32, ARM64_INS_UQSHL: uqshl.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL: uqshl.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv2i64, ARM64_INS_UQSHL: uqshl.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL: uqshl.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv4i16, ARM64_INS_UQSHL: uqshl.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL: uqshl.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv4i32, ARM64_INS_UQSHL: uqshl.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL: uqshl.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv8i16, ARM64_INS_UQSHL: uqshl.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL: uqshl.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv8i8, ARM64_INS_UQSHL: uqshl.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL: uqshl.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNb, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNh, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNs, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2: uqshrn2.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN: uqshrn.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN: uqshrn.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2: uqshrn2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2: uqshrn2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN: uqshrn.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv16i8, ARM64_INS_UQSUB: uqsub.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv1i16, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv1i32, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv1i64, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv1i8, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv2i32, ARM64_INS_UQSUB: uqsub.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv2i64, ARM64_INS_UQSUB: uqsub.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv4i16, ARM64_INS_UQSUB: uqsub.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv4i32, ARM64_INS_UQSUB: uqsub.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv8i16, ARM64_INS_UQSUB: uqsub.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQSUBv8i8, ARM64_INS_UQSUB: uqsub.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv16i8, ARM64_INS_UQXTN2: uqxtn2.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv1i16, ARM64_INS_UQXTN: uqxtn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv1i32, ARM64_INS_UQXTN: uqxtn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv1i8, ARM64_INS_UQXTN: uqxtn $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv2i32, ARM64_INS_UQXTN: uqxtn.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv4i16, ARM64_INS_UQXTN: uqxtn.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv4i32, ARM64_INS_UQXTN2: uqxtn2.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv8i16, ARM64_INS_UQXTN2: uqxtn2.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UQXTNv8i8, ARM64_INS_UQXTN: uqxtn.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URECPEv2i32, ARM64_INS_URECPE: urecpe.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URECPEv4i32, ARM64_INS_URECPE: urecpe.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URHADDv16i8, ARM64_INS_URHADD: urhadd.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URHADDv2i32, ARM64_INS_URHADD: urhadd.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URHADDv4i16, ARM64_INS_URHADD: urhadd.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URHADDv4i32, ARM64_INS_URHADD: urhadd.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URHADDv8i16, ARM64_INS_URHADD: urhadd.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URHADDv8i8, ARM64_INS_URHADD: urhadd.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHLv16i8, ARM64_INS_URSHL: urshl.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHLv1i64, ARM64_INS_URSHL: urshl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHLv2i32, ARM64_INS_URSHL: urshl.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHLv2i64, ARM64_INS_URSHL: urshl.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHLv4i16, ARM64_INS_URSHL: urshl.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHLv4i32, ARM64_INS_URSHL: urshl.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHLv8i16, ARM64_INS_URSHL: urshl.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHLv8i8, ARM64_INS_URSHL: urshl.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHRd, ARM64_INS_URSHR: urshr $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHRv16i8_shift, ARM64_INS_URSHR: urshr.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHRv2i32_shift, ARM64_INS_URSHR: urshr.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHRv2i64_shift, ARM64_INS_URSHR: urshr.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHRv4i16_shift, ARM64_INS_URSHR: urshr.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHRv4i32_shift, ARM64_INS_URSHR: urshr.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHRv8i16_shift, ARM64_INS_URSHR: urshr.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSHRv8i8_shift, ARM64_INS_URSHR: urshr.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE: ursqrte.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE: ursqrte.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSRAd, ARM64_INS_URSRA: ursra $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSRAv16i8_shift, ARM64_INS_URSRA: ursra.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSRAv2i32_shift, ARM64_INS_URSRA: ursra.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSRAv2i64_shift, ARM64_INS_URSRA: ursra.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSRAv4i16_shift, ARM64_INS_URSRA: ursra.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSRAv4i32_shift, ARM64_INS_URSRA: ursra.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSRAv8i16_shift, ARM64_INS_URSRA: ursra.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_URSRAv8i8_shift, ARM64_INS_URSRA: ursra.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2: ushll2.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLLv2i32_shift, ARM64_INS_USHLL: ushll.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLLv4i16_shift, ARM64_INS_USHLL: ushll.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2: ushll2.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2: ushll2.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLLv8i8_shift, ARM64_INS_USHLL: ushll.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLv16i8, ARM64_INS_USHL: ushl.16b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLv1i64, ARM64_INS_USHL: ushl $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLv2i32, ARM64_INS_USHL: ushl.2s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLv2i64, ARM64_INS_USHL: ushl.2d $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLv4i16, ARM64_INS_USHL: ushl.4h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLv4i32, ARM64_INS_USHL: ushl.4s $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLv8i16, ARM64_INS_USHL: ushl.8h $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHLv8i8, ARM64_INS_USHL: ushl.8b $rd, $rn, $rm| */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHRd, ARM64_INS_USHR: ushr $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHRv16i8_shift, ARM64_INS_USHR: ushr.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHRv2i32_shift, ARM64_INS_USHR: ushr.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHRv2i64_shift, ARM64_INS_USHR: ushr.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHRv4i16_shift, ARM64_INS_USHR: ushr.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHRv4i32_shift, ARM64_INS_USHR: ushr.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHRv8i16_shift, ARM64_INS_USHR: ushr.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USHRv8i8_shift, ARM64_INS_USHR: ushr.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv16i8, ARM64_INS_USQADD: usqadd.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv1i16, ARM64_INS_USQADD: usqadd $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv1i32, ARM64_INS_USQADD: usqadd $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv1i64, ARM64_INS_USQADD: usqadd $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv1i8, ARM64_INS_USQADD: usqadd $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv2i32, ARM64_INS_USQADD: usqadd.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv2i64, ARM64_INS_USQADD: usqadd.2d $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv4i16, ARM64_INS_USQADD: usqadd.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv4i32, ARM64_INS_USQADD: usqadd.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv8i16, ARM64_INS_USQADD: usqadd.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USQADDv8i8, ARM64_INS_USQADD: usqadd.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USRAd, ARM64_INS_USRA: usra $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USRAv16i8_shift, ARM64_INS_USRA: usra.16b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USRAv2i32_shift, ARM64_INS_USRA: usra.2s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USRAv2i64_shift, ARM64_INS_USRA: usra.2d $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USRAv4i16_shift, ARM64_INS_USRA: usra.4h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USRAv4i32_shift, ARM64_INS_USRA: usra.4s $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USRAv8i16_shift, ARM64_INS_USRA: usra.8h $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USRAv8i8_shift, ARM64_INS_USRA: usra.8b $rd, $rn, $imm */ |
| 0, |
| { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2: usubl2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL: usubl.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL: usubl.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2: usubl2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2: usubl2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL: usubl.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2: usubw2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW: usubw.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW: usubw.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2: usubw2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2: usubw2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW: usubw.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP1v16i8, ARM64_INS_UZP1: uzp1.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP1v2i32, ARM64_INS_UZP1: uzp1.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP1v2i64, ARM64_INS_UZP1: uzp1.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP1v4i16, ARM64_INS_UZP1: uzp1.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP1v4i32, ARM64_INS_UZP1: uzp1.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP1v8i16, ARM64_INS_UZP1: uzp1.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP1v8i8, ARM64_INS_UZP1: uzp1.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP2v16i8, ARM64_INS_UZP2: uzp2.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP2v2i32, ARM64_INS_UZP2: uzp2.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP2v2i64, ARM64_INS_UZP2: uzp2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP2v4i16, ARM64_INS_UZP2: uzp2.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP2v4i32, ARM64_INS_UZP2: uzp2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP2v8i16, ARM64_INS_UZP2: uzp2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_UZP2v8i8, ARM64_INS_UZP2: uzp2.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_XTNv16i8, ARM64_INS_XTN2: xtn2.16b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_XTNv2i32, ARM64_INS_XTN: xtn.2s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_XTNv4i16, ARM64_INS_XTN: xtn.4h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_XTNv4i32, ARM64_INS_XTN2: xtn2.4s $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_XTNv8i16, ARM64_INS_XTN2: xtn2.8h $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_XTNv8i8, ARM64_INS_XTN: xtn.8b $rd, $rn */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP1v16i8, ARM64_INS_ZIP1: zip1.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP1v2i32, ARM64_INS_ZIP1: zip1.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP1v2i64, ARM64_INS_ZIP1: zip1.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP1v4i16, ARM64_INS_ZIP1: zip1.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP1v4i32, ARM64_INS_ZIP1: zip1.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP1v8i16, ARM64_INS_ZIP1: zip1.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP1v8i8, ARM64_INS_ZIP1: zip1.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP2v16i8, ARM64_INS_ZIP2: zip2.16b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP2v2i32, ARM64_INS_ZIP2: zip2.2s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP2v2i64, ARM64_INS_ZIP2: zip2.2d $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP2v4i16, ARM64_INS_ZIP2: zip2.4h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP2v4i32, ARM64_INS_ZIP2: zip2.4s $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP2v8i16, ARM64_INS_ZIP2: zip2.8h $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| }, |
| { /* AArch64_ZIP2v8i8, ARM64_INS_ZIP2: zip2.8b $rd, $rn, $rm */ |
| 0, |
| { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| } |
| }; |
| #endif |
| |
| #endif |