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gerrit-public.fairphone.software / platform / external / capstone / 1182d2575952de60877a35eeb2f2ff8ec57b445e / . / arch / AArch64 / AArch64GenRegisterInfo.inc
blob: 7e82bb5b5a9155c0cd1f806f3711b70f5eaf9c9b [file] [log] [blame]
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|*Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]9/* Capstone Disassembly Engine, http://www.capstone-engine.org */
Nguyen Anh Quynhbfcaba52015-03-04 17:45:23 +0800[diff] [blame]10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]11
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]12
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]13#ifdef GET_REGINFO_ENUM
14#undef GET_REGINFO_ENUM
15
16enum {
17 AArch64_NoRegister,
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]18 AArch64_FP = 1,
19 AArch64_LR = 2,
20 AArch64_NZCV = 3,
21 AArch64_SP = 4,
22 AArch64_WSP = 5,
23 AArch64_WZR = 6,
24 AArch64_XZR = 7,
25 AArch64_B0 = 8,
26 AArch64_B1 = 9,
27 AArch64_B2 = 10,
28 AArch64_B3 = 11,
29 AArch64_B4 = 12,
30 AArch64_B5 = 13,
31 AArch64_B6 = 14,
32 AArch64_B7 = 15,
33 AArch64_B8 = 16,
34 AArch64_B9 = 17,
35 AArch64_B10 = 18,
36 AArch64_B11 = 19,
37 AArch64_B12 = 20,
38 AArch64_B13 = 21,
39 AArch64_B14 = 22,
40 AArch64_B15 = 23,
41 AArch64_B16 = 24,
42 AArch64_B17 = 25,
43 AArch64_B18 = 26,
44 AArch64_B19 = 27,
45 AArch64_B20 = 28,
46 AArch64_B21 = 29,
47 AArch64_B22 = 30,
48 AArch64_B23 = 31,
49 AArch64_B24 = 32,
50 AArch64_B25 = 33,
51 AArch64_B26 = 34,
52 AArch64_B27 = 35,
53 AArch64_B28 = 36,
54 AArch64_B29 = 37,
55 AArch64_B30 = 38,
56 AArch64_B31 = 39,
57 AArch64_D0 = 40,
58 AArch64_D1 = 41,
59 AArch64_D2 = 42,
60 AArch64_D3 = 43,
61 AArch64_D4 = 44,
62 AArch64_D5 = 45,
63 AArch64_D6 = 46,
64 AArch64_D7 = 47,
65 AArch64_D8 = 48,
66 AArch64_D9 = 49,
67 AArch64_D10 = 50,
68 AArch64_D11 = 51,
69 AArch64_D12 = 52,
70 AArch64_D13 = 53,
71 AArch64_D14 = 54,
72 AArch64_D15 = 55,
73 AArch64_D16 = 56,
74 AArch64_D17 = 57,
75 AArch64_D18 = 58,
76 AArch64_D19 = 59,
77 AArch64_D20 = 60,
78 AArch64_D21 = 61,
79 AArch64_D22 = 62,
80 AArch64_D23 = 63,
81 AArch64_D24 = 64,
82 AArch64_D25 = 65,
83 AArch64_D26 = 66,
84 AArch64_D27 = 67,
85 AArch64_D28 = 68,
86 AArch64_D29 = 69,
87 AArch64_D30 = 70,
88 AArch64_D31 = 71,
89 AArch64_H0 = 72,
90 AArch64_H1 = 73,
91 AArch64_H2 = 74,
92 AArch64_H3 = 75,
93 AArch64_H4 = 76,
94 AArch64_H5 = 77,
95 AArch64_H6 = 78,
96 AArch64_H7 = 79,
97 AArch64_H8 = 80,
98 AArch64_H9 = 81,
99 AArch64_H10 = 82,
100 AArch64_H11 = 83,
101 AArch64_H12 = 84,
102 AArch64_H13 = 85,
103 AArch64_H14 = 86,
104 AArch64_H15 = 87,
105 AArch64_H16 = 88,
106 AArch64_H17 = 89,
107 AArch64_H18 = 90,
108 AArch64_H19 = 91,
109 AArch64_H20 = 92,
110 AArch64_H21 = 93,
111 AArch64_H22 = 94,
112 AArch64_H23 = 95,
113 AArch64_H24 = 96,
114 AArch64_H25 = 97,
115 AArch64_H26 = 98,
116 AArch64_H27 = 99,
117 AArch64_H28 = 100,
118 AArch64_H29 = 101,
119 AArch64_H30 = 102,
120 AArch64_H31 = 103,
121 AArch64_Q0 = 104,
122 AArch64_Q1 = 105,
123 AArch64_Q2 = 106,
124 AArch64_Q3 = 107,
125 AArch64_Q4 = 108,
126 AArch64_Q5 = 109,
127 AArch64_Q6 = 110,
128 AArch64_Q7 = 111,
129 AArch64_Q8 = 112,
130 AArch64_Q9 = 113,
131 AArch64_Q10 = 114,
132 AArch64_Q11 = 115,
133 AArch64_Q12 = 116,
134 AArch64_Q13 = 117,
135 AArch64_Q14 = 118,
136 AArch64_Q15 = 119,
137 AArch64_Q16 = 120,
138 AArch64_Q17 = 121,
139 AArch64_Q18 = 122,
140 AArch64_Q19 = 123,
141 AArch64_Q20 = 124,
142 AArch64_Q21 = 125,
143 AArch64_Q22 = 126,
144 AArch64_Q23 = 127,
145 AArch64_Q24 = 128,
146 AArch64_Q25 = 129,
147 AArch64_Q26 = 130,
148 AArch64_Q27 = 131,
149 AArch64_Q28 = 132,
150 AArch64_Q29 = 133,
151 AArch64_Q30 = 134,
152 AArch64_Q31 = 135,
153 AArch64_S0 = 136,
154 AArch64_S1 = 137,
155 AArch64_S2 = 138,
156 AArch64_S3 = 139,
157 AArch64_S4 = 140,
158 AArch64_S5 = 141,
159 AArch64_S6 = 142,
160 AArch64_S7 = 143,
161 AArch64_S8 = 144,
162 AArch64_S9 = 145,
163 AArch64_S10 = 146,
164 AArch64_S11 = 147,
165 AArch64_S12 = 148,
166 AArch64_S13 = 149,
167 AArch64_S14 = 150,
168 AArch64_S15 = 151,
169 AArch64_S16 = 152,
170 AArch64_S17 = 153,
171 AArch64_S18 = 154,
172 AArch64_S19 = 155,
173 AArch64_S20 = 156,
174 AArch64_S21 = 157,
175 AArch64_S22 = 158,
176 AArch64_S23 = 159,
177 AArch64_S24 = 160,
178 AArch64_S25 = 161,
179 AArch64_S26 = 162,
180 AArch64_S27 = 163,
181 AArch64_S28 = 164,
182 AArch64_S29 = 165,
183 AArch64_S30 = 166,
184 AArch64_S31 = 167,
185 AArch64_W0 = 168,
186 AArch64_W1 = 169,
187 AArch64_W2 = 170,
188 AArch64_W3 = 171,
189 AArch64_W4 = 172,
190 AArch64_W5 = 173,
191 AArch64_W6 = 174,
192 AArch64_W7 = 175,
193 AArch64_W8 = 176,
194 AArch64_W9 = 177,
195 AArch64_W10 = 178,
196 AArch64_W11 = 179,
197 AArch64_W12 = 180,
198 AArch64_W13 = 181,
199 AArch64_W14 = 182,
200 AArch64_W15 = 183,
201 AArch64_W16 = 184,
202 AArch64_W17 = 185,
203 AArch64_W18 = 186,
204 AArch64_W19 = 187,
205 AArch64_W20 = 188,
206 AArch64_W21 = 189,
207 AArch64_W22 = 190,
208 AArch64_W23 = 191,
209 AArch64_W24 = 192,
210 AArch64_W25 = 193,
211 AArch64_W26 = 194,
212 AArch64_W27 = 195,
213 AArch64_W28 = 196,
214 AArch64_W29 = 197,
215 AArch64_W30 = 198,
216 AArch64_X0 = 199,
217 AArch64_X1 = 200,
218 AArch64_X2 = 201,
219 AArch64_X3 = 202,
220 AArch64_X4 = 203,
221 AArch64_X5 = 204,
222 AArch64_X6 = 205,
223 AArch64_X7 = 206,
224 AArch64_X8 = 207,
225 AArch64_X9 = 208,
226 AArch64_X10 = 209,
227 AArch64_X11 = 210,
228 AArch64_X12 = 211,
229 AArch64_X13 = 212,
230 AArch64_X14 = 213,
231 AArch64_X15 = 214,
232 AArch64_X16 = 215,
233 AArch64_X17 = 216,
234 AArch64_X18 = 217,
235 AArch64_X19 = 218,
236 AArch64_X20 = 219,
237 AArch64_X21 = 220,
238 AArch64_X22 = 221,
239 AArch64_X23 = 222,
240 AArch64_X24 = 223,
241 AArch64_X25 = 224,
242 AArch64_X26 = 225,
243 AArch64_X27 = 226,
244 AArch64_X28 = 227,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]245 AArch64_D0_D1 = 228,
246 AArch64_D1_D2 = 229,
247 AArch64_D2_D3 = 230,
248 AArch64_D3_D4 = 231,
249 AArch64_D4_D5 = 232,
250 AArch64_D5_D6 = 233,
251 AArch64_D6_D7 = 234,
252 AArch64_D7_D8 = 235,
253 AArch64_D8_D9 = 236,
254 AArch64_D9_D10 = 237,
255 AArch64_D10_D11 = 238,
256 AArch64_D11_D12 = 239,
257 AArch64_D12_D13 = 240,
258 AArch64_D13_D14 = 241,
259 AArch64_D14_D15 = 242,
260 AArch64_D15_D16 = 243,
261 AArch64_D16_D17 = 244,
262 AArch64_D17_D18 = 245,
263 AArch64_D18_D19 = 246,
264 AArch64_D19_D20 = 247,
265 AArch64_D20_D21 = 248,
266 AArch64_D21_D22 = 249,
267 AArch64_D22_D23 = 250,
268 AArch64_D23_D24 = 251,
269 AArch64_D24_D25 = 252,
270 AArch64_D25_D26 = 253,
271 AArch64_D26_D27 = 254,
272 AArch64_D27_D28 = 255,
273 AArch64_D28_D29 = 256,
274 AArch64_D29_D30 = 257,
275 AArch64_D30_D31 = 258,
276 AArch64_D31_D0 = 259,
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]277 AArch64_D0_D1_D2_D3 = 260,
278 AArch64_D1_D2_D3_D4 = 261,
279 AArch64_D2_D3_D4_D5 = 262,
280 AArch64_D3_D4_D5_D6 = 263,
281 AArch64_D4_D5_D6_D7 = 264,
282 AArch64_D5_D6_D7_D8 = 265,
283 AArch64_D6_D7_D8_D9 = 266,
284 AArch64_D7_D8_D9_D10 = 267,
285 AArch64_D8_D9_D10_D11 = 268,
286 AArch64_D9_D10_D11_D12 = 269,
287 AArch64_D10_D11_D12_D13 = 270,
288 AArch64_D11_D12_D13_D14 = 271,
289 AArch64_D12_D13_D14_D15 = 272,
290 AArch64_D13_D14_D15_D16 = 273,
291 AArch64_D14_D15_D16_D17 = 274,
292 AArch64_D15_D16_D17_D18 = 275,
293 AArch64_D16_D17_D18_D19 = 276,
294 AArch64_D17_D18_D19_D20 = 277,
295 AArch64_D18_D19_D20_D21 = 278,
296 AArch64_D19_D20_D21_D22 = 279,
297 AArch64_D20_D21_D22_D23 = 280,
298 AArch64_D21_D22_D23_D24 = 281,
299 AArch64_D22_D23_D24_D25 = 282,
300 AArch64_D23_D24_D25_D26 = 283,
301 AArch64_D24_D25_D26_D27 = 284,
302 AArch64_D25_D26_D27_D28 = 285,
303 AArch64_D26_D27_D28_D29 = 286,
304 AArch64_D27_D28_D29_D30 = 287,
305 AArch64_D28_D29_D30_D31 = 288,
306 AArch64_D29_D30_D31_D0 = 289,
307 AArch64_D30_D31_D0_D1 = 290,
308 AArch64_D31_D0_D1_D2 = 291,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]309 AArch64_D0_D1_D2 = 292,
310 AArch64_D1_D2_D3 = 293,
311 AArch64_D2_D3_D4 = 294,
312 AArch64_D3_D4_D5 = 295,
313 AArch64_D4_D5_D6 = 296,
314 AArch64_D5_D6_D7 = 297,
315 AArch64_D6_D7_D8 = 298,
316 AArch64_D7_D8_D9 = 299,
317 AArch64_D8_D9_D10 = 300,
318 AArch64_D9_D10_D11 = 301,
319 AArch64_D10_D11_D12 = 302,
320 AArch64_D11_D12_D13 = 303,
321 AArch64_D12_D13_D14 = 304,
322 AArch64_D13_D14_D15 = 305,
323 AArch64_D14_D15_D16 = 306,
324 AArch64_D15_D16_D17 = 307,
325 AArch64_D16_D17_D18 = 308,
326 AArch64_D17_D18_D19 = 309,
327 AArch64_D18_D19_D20 = 310,
328 AArch64_D19_D20_D21 = 311,
329 AArch64_D20_D21_D22 = 312,
330 AArch64_D21_D22_D23 = 313,
331 AArch64_D22_D23_D24 = 314,
332 AArch64_D23_D24_D25 = 315,
333 AArch64_D24_D25_D26 = 316,
334 AArch64_D25_D26_D27 = 317,
335 AArch64_D26_D27_D28 = 318,
336 AArch64_D27_D28_D29 = 319,
337 AArch64_D28_D29_D30 = 320,
338 AArch64_D29_D30_D31 = 321,
339 AArch64_D30_D31_D0 = 322,
340 AArch64_D31_D0_D1 = 323,
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]341 AArch64_Q0_Q1 = 324,
342 AArch64_Q1_Q2 = 325,
343 AArch64_Q2_Q3 = 326,
344 AArch64_Q3_Q4 = 327,
345 AArch64_Q4_Q5 = 328,
346 AArch64_Q5_Q6 = 329,
347 AArch64_Q6_Q7 = 330,
348 AArch64_Q7_Q8 = 331,
349 AArch64_Q8_Q9 = 332,
350 AArch64_Q9_Q10 = 333,
351 AArch64_Q10_Q11 = 334,
352 AArch64_Q11_Q12 = 335,
353 AArch64_Q12_Q13 = 336,
354 AArch64_Q13_Q14 = 337,
355 AArch64_Q14_Q15 = 338,
356 AArch64_Q15_Q16 = 339,
357 AArch64_Q16_Q17 = 340,
358 AArch64_Q17_Q18 = 341,
359 AArch64_Q18_Q19 = 342,
360 AArch64_Q19_Q20 = 343,
361 AArch64_Q20_Q21 = 344,
362 AArch64_Q21_Q22 = 345,
363 AArch64_Q22_Q23 = 346,
364 AArch64_Q23_Q24 = 347,
365 AArch64_Q24_Q25 = 348,
366 AArch64_Q25_Q26 = 349,
367 AArch64_Q26_Q27 = 350,
368 AArch64_Q27_Q28 = 351,
369 AArch64_Q28_Q29 = 352,
370 AArch64_Q29_Q30 = 353,
371 AArch64_Q30_Q31 = 354,
372 AArch64_Q31_Q0 = 355,
373 AArch64_Q0_Q1_Q2_Q3 = 356,
374 AArch64_Q1_Q2_Q3_Q4 = 357,
375 AArch64_Q2_Q3_Q4_Q5 = 358,
376 AArch64_Q3_Q4_Q5_Q6 = 359,
377 AArch64_Q4_Q5_Q6_Q7 = 360,
378 AArch64_Q5_Q6_Q7_Q8 = 361,
379 AArch64_Q6_Q7_Q8_Q9 = 362,
380 AArch64_Q7_Q8_Q9_Q10 = 363,
381 AArch64_Q8_Q9_Q10_Q11 = 364,
382 AArch64_Q9_Q10_Q11_Q12 = 365,
383 AArch64_Q10_Q11_Q12_Q13 = 366,
384 AArch64_Q11_Q12_Q13_Q14 = 367,
385 AArch64_Q12_Q13_Q14_Q15 = 368,
386 AArch64_Q13_Q14_Q15_Q16 = 369,
387 AArch64_Q14_Q15_Q16_Q17 = 370,
388 AArch64_Q15_Q16_Q17_Q18 = 371,
389 AArch64_Q16_Q17_Q18_Q19 = 372,
390 AArch64_Q17_Q18_Q19_Q20 = 373,
391 AArch64_Q18_Q19_Q20_Q21 = 374,
392 AArch64_Q19_Q20_Q21_Q22 = 375,
393 AArch64_Q20_Q21_Q22_Q23 = 376,
394 AArch64_Q21_Q22_Q23_Q24 = 377,
395 AArch64_Q22_Q23_Q24_Q25 = 378,
396 AArch64_Q23_Q24_Q25_Q26 = 379,
397 AArch64_Q24_Q25_Q26_Q27 = 380,
398 AArch64_Q25_Q26_Q27_Q28 = 381,
399 AArch64_Q26_Q27_Q28_Q29 = 382,
400 AArch64_Q27_Q28_Q29_Q30 = 383,
401 AArch64_Q28_Q29_Q30_Q31 = 384,
402 AArch64_Q29_Q30_Q31_Q0 = 385,
403 AArch64_Q30_Q31_Q0_Q1 = 386,
404 AArch64_Q31_Q0_Q1_Q2 = 387,
405 AArch64_Q0_Q1_Q2 = 388,
406 AArch64_Q1_Q2_Q3 = 389,
407 AArch64_Q2_Q3_Q4 = 390,
408 AArch64_Q3_Q4_Q5 = 391,
409 AArch64_Q4_Q5_Q6 = 392,
410 AArch64_Q5_Q6_Q7 = 393,
411 AArch64_Q6_Q7_Q8 = 394,
412 AArch64_Q7_Q8_Q9 = 395,
413 AArch64_Q8_Q9_Q10 = 396,
414 AArch64_Q9_Q10_Q11 = 397,
415 AArch64_Q10_Q11_Q12 = 398,
416 AArch64_Q11_Q12_Q13 = 399,
417 AArch64_Q12_Q13_Q14 = 400,
418 AArch64_Q13_Q14_Q15 = 401,
419 AArch64_Q14_Q15_Q16 = 402,
420 AArch64_Q15_Q16_Q17 = 403,
421 AArch64_Q16_Q17_Q18 = 404,
422 AArch64_Q17_Q18_Q19 = 405,
423 AArch64_Q18_Q19_Q20 = 406,
424 AArch64_Q19_Q20_Q21 = 407,
425 AArch64_Q20_Q21_Q22 = 408,
426 AArch64_Q21_Q22_Q23 = 409,
427 AArch64_Q22_Q23_Q24 = 410,
428 AArch64_Q23_Q24_Q25 = 411,
429 AArch64_Q24_Q25_Q26 = 412,
430 AArch64_Q25_Q26_Q27 = 413,
431 AArch64_Q26_Q27_Q28 = 414,
432 AArch64_Q27_Q28_Q29 = 415,
433 AArch64_Q28_Q29_Q30 = 416,
434 AArch64_Q29_Q30_Q31 = 417,
435 AArch64_Q30_Q31_Q0 = 418,
436 AArch64_Q31_Q0_Q1 = 419,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]437 AArch64_NUM_TARGET_REGS // 420
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]438};
439
440// Register classes
441enum {
442 AArch64_FPR8RegClassID = 0,
443 AArch64_FPR16RegClassID = 1,
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]444 AArch64_GPR32allRegClassID = 2,
445 AArch64_FPR32RegClassID = 3,
446 AArch64_GPR32RegClassID = 4,
447 AArch64_GPR32spRegClassID = 5,
448 AArch64_GPR32commonRegClassID = 6,
449 AArch64_CCRRegClassID = 7,
450 AArch64_GPR32sponlyRegClassID = 8,
451 AArch64_GPR64allRegClassID = 9,
452 AArch64_FPR64RegClassID = 10,
453 AArch64_GPR64RegClassID = 11,
454 AArch64_GPR64spRegClassID = 12,
455 AArch64_GPR64commonRegClassID = 13,
456 AArch64_tcGPR64RegClassID = 14,
457 AArch64_GPR64sponlyRegClassID = 15,
458 AArch64_DDRegClassID = 16,
459 AArch64_FPR128RegClassID = 17,
460 AArch64_FPR128_loRegClassID = 18,
461 AArch64_DDDRegClassID = 19,
462 AArch64_DDDDRegClassID = 20,
463 AArch64_QQRegClassID = 21,
464 AArch64_QQ_with_qsub0_in_FPR128_loRegClassID = 22,
465 AArch64_QQ_with_qsub1_in_FPR128_loRegClassID = 23,
466 AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 24,
467 AArch64_QQQRegClassID = 25,
468 AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID = 26,
469 AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID = 27,
470 AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID = 28,
471 AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 29,
472 AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 30,
473 AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 31,
474 AArch64_QQQQRegClassID = 32,
475 AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID = 33,
476 AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID = 34,
477 AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID = 35,
478 AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID = 36,
479 AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 37,
480 AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 38,
481 AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 39,
482 AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 40,
483 AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 41,
Nguyen Anh Quynh3e4c3572015-03-03 22:58:54 +0800[diff] [blame]484 AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 42,
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]485};
486
487// Register alternate name indices
488enum {
489 AArch64_NoRegAltName, // 0
490 AArch64_vlist1, // 1
491 AArch64_vreg, // 2
492 AArch64_NUM_TARGET_REG_ALT_NAMES = 3
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]493};
494
495// Subregister indices
496enum {
497 AArch64_NoSubRegister,
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]498 AArch64_bsub, // 1
499 AArch64_dsub, // 2
500 AArch64_dsub0, // 3
501 AArch64_dsub1, // 4
502 AArch64_dsub2, // 5
503 AArch64_dsub3, // 6
504 AArch64_hsub, // 7
505 AArch64_qhisub, // 8
506 AArch64_qsub, // 9
507 AArch64_qsub0, // 10
508 AArch64_qsub1, // 11
509 AArch64_qsub2, // 12
510 AArch64_qsub3, // 13
511 AArch64_ssub, // 14
512 AArch64_sub_32, // 15
513 AArch64_dsub1_then_bsub, // 16
514 AArch64_dsub1_then_hsub, // 17
515 AArch64_dsub1_then_ssub, // 18
516 AArch64_dsub3_then_bsub, // 19
517 AArch64_dsub3_then_hsub, // 20
518 AArch64_dsub3_then_ssub, // 21
519 AArch64_dsub2_then_bsub, // 22
520 AArch64_dsub2_then_hsub, // 23
521 AArch64_dsub2_then_ssub, // 24
522 AArch64_qsub1_then_bsub, // 25
523 AArch64_qsub1_then_dsub, // 26
524 AArch64_qsub1_then_hsub, // 27
525 AArch64_qsub1_then_ssub, // 28
526 AArch64_qsub3_then_bsub, // 29
527 AArch64_qsub3_then_dsub, // 30
528 AArch64_qsub3_then_hsub, // 31
529 AArch64_qsub3_then_ssub, // 32
530 AArch64_qsub2_then_bsub, // 33
531 AArch64_qsub2_then_dsub, // 34
532 AArch64_qsub2_then_hsub, // 35
533 AArch64_qsub2_then_ssub, // 36
534 AArch64_dsub0_dsub1, // 37
535 AArch64_dsub0_dsub1_dsub2, // 38
536 AArch64_dsub1_dsub2, // 39
537 AArch64_dsub1_dsub2_dsub3, // 40
538 AArch64_dsub2_dsub3, // 41
539 AArch64_dsub_qsub1_then_dsub, // 42
540 AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 43
541 AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub, // 44
542 AArch64_qsub0_qsub1, // 45
543 AArch64_qsub0_qsub1_qsub2, // 46
544 AArch64_qsub1_qsub2, // 47
545 AArch64_qsub1_qsub2_qsub3, // 48
546 AArch64_qsub2_qsub3, // 49
547 AArch64_qsub1_then_dsub_qsub2_then_dsub, // 50
548 AArch64_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 51
549 AArch64_qsub2_then_dsub_qsub3_then_dsub, // 52
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]550 AArch64_NUM_TARGET_SUBREGS
551};
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]552
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]553#endif // GET_REGINFO_ENUM
554
555/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
556|* *|
557|*MC Register Information *|
558|* *|
559|* Automatically generated file, do not edit! *|
560|* *|
561\*===----------------------------------------------------------------------===*/
562
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]563/* Capstone Disassembly Engine, http://www.capstone-engine.org */
Nguyen Anh Quynhbfcaba52015-03-04 17:45:23 +0800[diff] [blame]564/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]565
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]566
567#ifdef GET_REGINFO_MC_DESC
568#undef GET_REGINFO_MC_DESC
569
570static MCPhysReg AArch64RegDiffLists[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]571 /* 0 */ 65185, 1, 1, 1, 0,
572 /* 5 */ 65281, 1, 1, 1, 0,
573 /* 10 */ 5, 29, 1, 1, 0,
574 /* 15 */ 65153, 1, 1, 0,
575 /* 19 */ 65249, 1, 1, 0,
576 /* 23 */ 5, 1, 29, 1, 0,
577 /* 28 */ 5, 30, 1, 0,
578 /* 32 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 218, 1, 0,
579 /* 47 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 250, 1, 0,
580 /* 62 */ 65217, 1, 0,
581 /* 65 */ 65313, 1, 0,
582 /* 68 */ 64, 64, 65440, 64, 123, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
583 /* 91 */ 219, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
584 /* 101 */ 64, 64, 65440, 64, 124, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
585 /* 124 */ 220, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
586 /* 134 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 0,
587 /* 146 */ 64, 64, 65440, 64, 123, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
588 /* 169 */ 219, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
589 /* 179 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 0,
590 /* 191 */ 65503, 1, 128, 65503, 1, 0,
591 /* 197 */ 3, 0,
592 /* 199 */ 4, 0,
593 /* 201 */ 5, 1, 1, 29, 0,
594 /* 206 */ 64, 64, 65440, 64, 123, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
595 /* 229 */ 219, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
596 /* 239 */ 5, 1, 30, 0,
597 /* 243 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 0,
598 /* 255 */ 5, 31, 0,
599 /* 258 */ 65504, 31, 97, 65504, 31, 0,
600 /* 264 */ 96, 0,
601 /* 266 */ 196, 0,
602 /* 268 */ 65316, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 219, 0,
603 /* 280 */ 65316, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 251, 0,
604 /* 292 */ 65339, 0,
605 /* 294 */ 65340, 0,
606 /* 296 */ 65374, 0,
607 /* 298 */ 65405, 0,
608 /* 300 */ 65437, 0,
609 /* 302 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 218, 64, 32, 1, 65440, 0,
610 /* 323 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 250, 64, 32, 1, 65440, 0,
611 /* 344 */ 65252, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 250, 64, 32, 65505, 65440, 0,
612 /* 365 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
613 /* 397 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65473, 64, 65441, 0,
614 /* 419 */ 65469, 0,
615 /* 421 */ 65348, 96, 65472, 65472, 1, 96, 65472, 65472, 0,
616 /* 430 */ 65348, 96, 65472, 65472, 33, 96, 65472, 65472, 0,
617 /* 439 */ 65472, 96, 65472, 65472, 0,
618 /* 444 */ 65284, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
619 /* 476 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 217, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
620 /* 508 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
621 /* 540 */ 65316, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65441, 64, 65473, 0,
622 /* 562 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 217, 64, 65473, 64, 65473, 0,
623 /* 584 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 249, 64, 65473, 64, 65473, 0,
624 /* 606 */ 65501, 0,
625 /* 608 */ 65284, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 250, 65505, 0,
626 /* 623 */ 65533, 0,
627 /* 625 */ 65535, 0,
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]628};
629
630static uint16_t AArch64SubRegIdxLists[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]631 /* 0 */ 2, 14, 7, 1, 0,
632 /* 5 */ 15, 0,
633 /* 7 */ 3, 14, 7, 1, 4, 18, 17, 16, 0,
634 /* 16 */ 3, 14, 7, 1, 4, 18, 17, 16, 5, 24, 23, 22, 37, 39, 0,
635 /* 31 */ 3, 14, 7, 1, 4, 18, 17, 16, 5, 24, 23, 22, 6, 21, 20, 19, 37, 38, 39, 40, 41, 0,
636 /* 53 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 42, 0,
637 /* 65 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 42, 44, 45, 47, 50, 0,
638 /* 86 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 13, 30, 32, 31, 29, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 0,
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]639};
640
641static MCRegisterDesc AArch64RegDesc[] = { // Descriptors
Nguyen Anh Quynh3e4c3572015-03-03 22:58:54 +0800[diff] [blame]642 { 3, 0, 0, 0, 0, 0 },
643 { 1518, 266, 4, 5, 10001, 26 },
644 { 1525, 266, 4, 5, 10001, 26 },
645 { 1536, 4, 4, 4, 10001, 0 },
646 { 1522, 3, 4, 5, 3152, 26 },
647 { 1521, 4, 625, 4, 3152, 0 },
648 { 1528, 4, 3, 4, 3184, 0 },
649 { 1532, 625, 4, 5, 3184, 26 },
650 { 146, 4, 101, 4, 9969, 0 },
651 { 335, 4, 146, 4, 9969, 0 },
652 { 480, 4, 206, 4, 9969, 0 },
653 { 625, 4, 68, 4, 9969, 0 },
654 { 768, 4, 68, 4, 9969, 0 },
655 { 911, 4, 68, 4, 9969, 0 },
656 { 1054, 4, 68, 4, 9969, 0 },
657 { 1197, 4, 68, 4, 9969, 0 },
658 { 1340, 4, 68, 4, 9969, 0 },
659 { 1479, 4, 68, 4, 9969, 0 },
660 { 0, 4, 68, 4, 9969, 0 },
661 { 191, 4, 68, 4, 9969, 0 },
662 { 378, 4, 68, 4, 9969, 0 },
663 { 521, 4, 68, 4, 9969, 0 },
664 { 664, 4, 68, 4, 9969, 0 },
665 { 807, 4, 68, 4, 9969, 0 },
666 { 950, 4, 68, 4, 9969, 0 },
667 { 1093, 4, 68, 4, 9969, 0 },
668 { 1236, 4, 68, 4, 9969, 0 },
669 { 1379, 4, 68, 4, 9969, 0 },
670 { 46, 4, 68, 4, 9969, 0 },
671 { 239, 4, 68, 4, 9969, 0 },
672 { 428, 4, 68, 4, 9969, 0 },
673 { 573, 4, 68, 4, 9969, 0 },
674 { 716, 4, 68, 4, 9969, 0 },
675 { 859, 4, 68, 4, 9969, 0 },
676 { 1002, 4, 68, 4, 9969, 0 },
677 { 1145, 4, 68, 4, 9969, 0 },
678 { 1288, 4, 68, 4, 9969, 0 },
679 { 1431, 4, 68, 4, 9969, 0 },
680 { 98, 4, 68, 4, 9969, 0 },
681 { 291, 4, 68, 4, 9969, 0 },
682 { 161, 426, 104, 1, 9697, 3 },
683 { 349, 426, 149, 1, 9697, 3 },
684 { 493, 426, 209, 1, 9697, 3 },
685 { 637, 426, 71, 1, 9697, 3 },
686 { 780, 426, 71, 1, 9697, 3 },
687 { 923, 426, 71, 1, 9697, 3 },
688 { 1066, 426, 71, 1, 9697, 3 },
689 { 1209, 426, 71, 1, 9697, 3 },
690 { 1352, 426, 71, 1, 9697, 3 },
691 { 1491, 426, 71, 1, 9697, 3 },
692 { 13, 426, 71, 1, 9697, 3 },
693 { 205, 426, 71, 1, 9697, 3 },
694 { 393, 426, 71, 1, 9697, 3 },
695 { 537, 426, 71, 1, 9697, 3 },
696 { 680, 426, 71, 1, 9697, 3 },
697 { 823, 426, 71, 1, 9697, 3 },
698 { 966, 426, 71, 1, 9697, 3 },
699 { 1109, 426, 71, 1, 9697, 3 },
700 { 1252, 426, 71, 1, 9697, 3 },
701 { 1395, 426, 71, 1, 9697, 3 },
702 { 62, 426, 71, 1, 9697, 3 },
703 { 255, 426, 71, 1, 9697, 3 },
704 { 444, 426, 71, 1, 9697, 3 },
705 { 589, 426, 71, 1, 9697, 3 },
706 { 732, 426, 71, 1, 9697, 3 },
707 { 875, 426, 71, 1, 9697, 3 },
708 { 1018, 426, 71, 1, 9697, 3 },
709 { 1161, 426, 71, 1, 9697, 3 },
710 { 1304, 426, 71, 1, 9697, 3 },
711 { 1447, 426, 71, 1, 9697, 3 },
712 { 114, 426, 71, 1, 9697, 3 },
713 { 307, 426, 71, 1, 9697, 3 },
714 { 164, 428, 102, 3, 6705, 3 },
715 { 352, 428, 147, 3, 6705, 3 },
716 { 496, 428, 207, 3, 6705, 3 },
717 { 640, 428, 69, 3, 6705, 3 },
718 { 783, 428, 69, 3, 6705, 3 },
719 { 926, 428, 69, 3, 6705, 3 },
720 { 1069, 428, 69, 3, 6705, 3 },
721 { 1212, 428, 69, 3, 6705, 3 },
722 { 1355, 428, 69, 3, 6705, 3 },
723 { 1494, 428, 69, 3, 6705, 3 },
724 { 17, 428, 69, 3, 6705, 3 },
725 { 209, 428, 69, 3, 6705, 3 },
726 { 397, 428, 69, 3, 6705, 3 },
727 { 541, 428, 69, 3, 6705, 3 },
728 { 684, 428, 69, 3, 6705, 3 },
729 { 827, 428, 69, 3, 6705, 3 },
730 { 970, 428, 69, 3, 6705, 3 },
731 { 1113, 428, 69, 3, 6705, 3 },
732 { 1256, 428, 69, 3, 6705, 3 },
733 { 1399, 428, 69, 3, 6705, 3 },
734 { 66, 428, 69, 3, 6705, 3 },
735 { 259, 428, 69, 3, 6705, 3 },
736 { 448, 428, 69, 3, 6705, 3 },
737 { 593, 428, 69, 3, 6705, 3 },
738 { 736, 428, 69, 3, 6705, 3 },
739 { 879, 428, 69, 3, 6705, 3 },
740 { 1022, 428, 69, 3, 6705, 3 },
741 { 1165, 428, 69, 3, 6705, 3 },
742 { 1308, 428, 69, 3, 6705, 3 },
743 { 1451, 428, 69, 3, 6705, 3 },
744 { 118, 428, 69, 3, 6705, 3 },
745 { 311, 428, 69, 3, 6705, 3 },
746 { 179, 439, 124, 0, 4801, 3 },
747 { 366, 439, 169, 0, 4801, 3 },
748 { 509, 439, 229, 0, 4801, 3 },
749 { 652, 439, 91, 0, 4801, 3 },
750 { 795, 439, 91, 0, 4801, 3 },
751 { 938, 439, 91, 0, 4801, 3 },
752 { 1081, 439, 91, 0, 4801, 3 },
753 { 1224, 439, 91, 0, 4801, 3 },
754 { 1367, 439, 91, 0, 4801, 3 },
755 { 1506, 439, 91, 0, 4801, 3 },
756 { 30, 439, 91, 0, 4801, 3 },
757 { 223, 439, 91, 0, 4801, 3 },
758 { 412, 439, 91, 0, 4801, 3 },
759 { 557, 439, 91, 0, 4801, 3 },
760 { 700, 439, 91, 0, 4801, 3 },
761 { 843, 439, 91, 0, 4801, 3 },
762 { 986, 439, 91, 0, 4801, 3 },
763 { 1129, 439, 91, 0, 4801, 3 },
764 { 1272, 439, 91, 0, 4801, 3 },
765 { 1415, 439, 91, 0, 4801, 3 },
766 { 82, 439, 91, 0, 4801, 3 },
767 { 275, 439, 91, 0, 4801, 3 },
768 { 464, 439, 91, 0, 4801, 3 },
769 { 609, 439, 91, 0, 4801, 3 },
770 { 752, 439, 91, 0, 4801, 3 },
771 { 895, 439, 91, 0, 4801, 3 },
772 { 1038, 439, 91, 0, 4801, 3 },
773 { 1181, 439, 91, 0, 4801, 3 },
774 { 1324, 439, 91, 0, 4801, 3 },
775 { 1467, 439, 91, 0, 4801, 3 },
776 { 134, 439, 91, 0, 4801, 3 },
777 { 327, 439, 91, 0, 4801, 3 },
778 { 182, 427, 103, 2, 4769, 3 },
779 { 369, 427, 148, 2, 4769, 3 },
780 { 512, 427, 208, 2, 4769, 3 },
781 { 655, 427, 70, 2, 4769, 3 },
782 { 798, 427, 70, 2, 4769, 3 },
783 { 941, 427, 70, 2, 4769, 3 },
784 { 1084, 427, 70, 2, 4769, 3 },
785 { 1227, 427, 70, 2, 4769, 3 },
786 { 1370, 427, 70, 2, 4769, 3 },
787 { 1509, 427, 70, 2, 4769, 3 },
788 { 34, 427, 70, 2, 4769, 3 },
789 { 227, 427, 70, 2, 4769, 3 },
790 { 416, 427, 70, 2, 4769, 3 },
791 { 561, 427, 70, 2, 4769, 3 },
792 { 704, 427, 70, 2, 4769, 3 },
793 { 847, 427, 70, 2, 4769, 3 },
794 { 990, 427, 70, 2, 4769, 3 },
795 { 1133, 427, 70, 2, 4769, 3 },
796 { 1276, 427, 70, 2, 4769, 3 },
797 { 1419, 427, 70, 2, 4769, 3 },
798 { 86, 427, 70, 2, 4769, 3 },
799 { 279, 427, 70, 2, 4769, 3 },
800 { 468, 427, 70, 2, 4769, 3 },
801 { 613, 427, 70, 2, 4769, 3 },
802 { 756, 427, 70, 2, 4769, 3 },
803 { 899, 427, 70, 2, 4769, 3 },
804 { 1042, 427, 70, 2, 4769, 3 },
805 { 1185, 427, 70, 2, 4769, 3 },
806 { 1328, 427, 70, 2, 4769, 3 },
807 { 1471, 427, 70, 2, 4769, 3 },
808 { 138, 427, 70, 2, 4769, 3 },
809 { 331, 427, 70, 2, 4769, 3 },
810 { 185, 4, 256, 4, 4769, 0 },
811 { 372, 4, 256, 4, 4769, 0 },
812 { 515, 4, 256, 4, 4769, 0 },
813 { 658, 4, 256, 4, 4769, 0 },
814 { 801, 4, 256, 4, 4769, 0 },
815 { 944, 4, 256, 4, 4769, 0 },
816 { 1087, 4, 256, 4, 4769, 0 },
817 { 1230, 4, 256, 4, 4769, 0 },
818 { 1373, 4, 256, 4, 4769, 0 },
819 { 1512, 4, 256, 4, 4769, 0 },
820 { 38, 4, 256, 4, 4769, 0 },
821 { 231, 4, 256, 4, 4769, 0 },
822 { 420, 4, 256, 4, 4769, 0 },
823 { 565, 4, 256, 4, 4769, 0 },
824 { 708, 4, 256, 4, 4769, 0 },
825 { 851, 4, 256, 4, 4769, 0 },
826 { 994, 4, 256, 4, 4769, 0 },
827 { 1137, 4, 256, 4, 4769, 0 },
828 { 1280, 4, 256, 4, 4769, 0 },
829 { 1423, 4, 256, 4, 4769, 0 },
830 { 90, 4, 256, 4, 4769, 0 },
831 { 283, 4, 256, 4, 4769, 0 },
832 { 472, 4, 256, 4, 4769, 0 },
833 { 617, 4, 256, 4, 4769, 0 },
834 { 760, 4, 256, 4, 4769, 0 },
835 { 903, 4, 256, 4, 4769, 0 },
836 { 1046, 4, 256, 4, 4769, 0 },
837 { 1189, 4, 256, 4, 4769, 0 },
838 { 1332, 4, 256, 4, 4769, 0 },
839 { 1475, 4, 294, 4, 4673, 0 },
840 { 142, 4, 294, 4, 4673, 0 },
841 { 188, 621, 4, 5, 4737, 26 },
842 { 375, 621, 4, 5, 4737, 26 },
843 { 518, 621, 4, 5, 4737, 26 },
844 { 661, 621, 4, 5, 4737, 26 },
845 { 804, 621, 4, 5, 4737, 26 },
846 { 947, 621, 4, 5, 4737, 26 },
847 { 1090, 621, 4, 5, 4737, 26 },
848 { 1233, 621, 4, 5, 4737, 26 },
849 { 1376, 621, 4, 5, 4737, 26 },
850 { 1515, 621, 4, 5, 4737, 26 },
851 { 42, 621, 4, 5, 4737, 26 },
852 { 235, 621, 4, 5, 4737, 26 },
853 { 424, 621, 4, 5, 4737, 26 },
854 { 569, 621, 4, 5, 4737, 26 },
855 { 712, 621, 4, 5, 4737, 26 },
856 { 855, 621, 4, 5, 4737, 26 },
857 { 998, 621, 4, 5, 4737, 26 },
858 { 1141, 621, 4, 5, 4737, 26 },
859 { 1284, 621, 4, 5, 4737, 26 },
860 { 1427, 621, 4, 5, 4737, 26 },
861 { 94, 621, 4, 5, 4737, 26 },
862 { 287, 621, 4, 5, 4737, 26 },
863 { 476, 621, 4, 5, 4737, 26 },
864 { 621, 621, 4, 5, 4737, 26 },
865 { 764, 621, 4, 5, 4737, 26 },
866 { 907, 621, 4, 5, 4737, 26 },
867 { 1050, 621, 4, 5, 4737, 26 },
868 { 1193, 621, 4, 5, 4737, 26 },
869 { 1336, 621, 4, 5, 4737, 26 },
870 { 346, 430, 179, 7, 1041, 30 },
871 { 490, 430, 243, 7, 1041, 30 },
872 { 634, 430, 134, 7, 1041, 30 },
873 { 777, 430, 134, 7, 1041, 30 },
874 { 920, 430, 134, 7, 1041, 30 },
875 { 1063, 430, 134, 7, 1041, 30 },
876 { 1206, 430, 134, 7, 1041, 30 },
877 { 1349, 430, 134, 7, 1041, 30 },
878 { 1488, 430, 134, 7, 1041, 30 },
879 { 10, 430, 134, 7, 1041, 30 },
880 { 201, 430, 134, 7, 1041, 30 },
881 { 389, 430, 134, 7, 1041, 30 },
882 { 533, 430, 134, 7, 1041, 30 },
883 { 676, 430, 134, 7, 1041, 30 },
884 { 819, 430, 134, 7, 1041, 30 },
885 { 962, 430, 134, 7, 1041, 30 },
886 { 1105, 430, 134, 7, 1041, 30 },
887 { 1248, 430, 134, 7, 1041, 30 },
888 { 1391, 430, 134, 7, 1041, 30 },
889 { 58, 430, 134, 7, 1041, 30 },
890 { 251, 430, 134, 7, 1041, 30 },
891 { 440, 430, 134, 7, 1041, 30 },
892 { 585, 430, 134, 7, 1041, 30 },
893 { 728, 430, 134, 7, 1041, 30 },
894 { 871, 430, 134, 7, 1041, 30 },
895 { 1014, 430, 134, 7, 1041, 30 },
896 { 1157, 430, 134, 7, 1041, 30 },
897 { 1300, 430, 134, 7, 1041, 30 },
898 { 1443, 430, 134, 7, 1041, 30 },
899 { 110, 430, 134, 7, 1041, 30 },
900 { 303, 430, 134, 7, 1041, 30 },
901 { 157, 421, 134, 7, 4080, 2 },
902 { 628, 562, 264, 31, 81, 37 },
903 { 771, 562, 264, 31, 81, 37 },
904 { 914, 562, 264, 31, 81, 37 },
905 { 1057, 562, 264, 31, 81, 37 },
906 { 1200, 562, 264, 31, 81, 37 },
907 { 1343, 562, 264, 31, 81, 37 },
908 { 1482, 562, 264, 31, 81, 37 },
909 { 4, 562, 264, 31, 81, 37 },
910 { 195, 562, 264, 31, 81, 37 },
911 { 382, 562, 264, 31, 81, 37 },
912 { 525, 562, 264, 31, 81, 37 },
913 { 668, 562, 264, 31, 81, 37 },
914 { 811, 562, 264, 31, 81, 37 },
915 { 954, 562, 264, 31, 81, 37 },
916 { 1097, 562, 264, 31, 81, 37 },
917 { 1240, 562, 264, 31, 81, 37 },
918 { 1383, 562, 264, 31, 81, 37 },
919 { 50, 562, 264, 31, 81, 37 },
920 { 243, 562, 264, 31, 81, 37 },
921 { 432, 562, 264, 31, 81, 37 },
922 { 577, 562, 264, 31, 81, 37 },
923 { 720, 562, 264, 31, 81, 37 },
924 { 863, 562, 264, 31, 81, 37 },
925 { 1006, 562, 264, 31, 81, 37 },
926 { 1149, 562, 264, 31, 81, 37 },
927 { 1292, 562, 264, 31, 81, 37 },
928 { 1435, 562, 264, 31, 81, 37 },
929 { 102, 562, 264, 31, 81, 37 },
930 { 295, 562, 264, 31, 81, 37 },
931 { 149, 584, 264, 31, 160, 42 },
932 { 338, 397, 264, 31, 368, 28 },
933 { 483, 540, 264, 31, 3216, 5 },
934 { 487, 32, 258, 16, 305, 43 },
935 { 631, 32, 191, 16, 305, 43 },
936 { 774, 32, 191, 16, 305, 43 },
937 { 917, 32, 191, 16, 305, 43 },
938 { 1060, 32, 191, 16, 305, 43 },
939 { 1203, 32, 191, 16, 305, 43 },
940 { 1346, 32, 191, 16, 305, 43 },
941 { 1485, 32, 191, 16, 305, 43 },
942 { 7, 32, 191, 16, 305, 43 },
943 { 198, 32, 191, 16, 305, 43 },
944 { 385, 32, 191, 16, 305, 43 },
945 { 529, 32, 191, 16, 305, 43 },
946 { 672, 32, 191, 16, 305, 43 },
947 { 815, 32, 191, 16, 305, 43 },
948 { 958, 32, 191, 16, 305, 43 },
949 { 1101, 32, 191, 16, 305, 43 },
950 { 1244, 32, 191, 16, 305, 43 },
951 { 1387, 32, 191, 16, 305, 43 },
952 { 54, 32, 191, 16, 305, 43 },
953 { 247, 32, 191, 16, 305, 43 },
954 { 436, 32, 191, 16, 305, 43 },
955 { 581, 32, 191, 16, 305, 43 },
956 { 724, 32, 191, 16, 305, 43 },
957 { 867, 32, 191, 16, 305, 43 },
958 { 1010, 32, 191, 16, 305, 43 },
959 { 1153, 32, 191, 16, 305, 43 },
960 { 1296, 32, 191, 16, 305, 43 },
961 { 1439, 32, 191, 16, 305, 43 },
962 { 106, 32, 191, 16, 305, 43 },
963 { 299, 32, 191, 16, 305, 43 },
964 { 153, 47, 191, 16, 448, 33 },
965 { 342, 608, 191, 16, 3824, 10 },
966 { 363, 268, 185, 53, 993, 49 },
967 { 506, 268, 249, 53, 993, 49 },
968 { 649, 268, 140, 53, 993, 49 },
969 { 792, 268, 140, 53, 993, 49 },
970 { 935, 268, 140, 53, 993, 49 },
971 { 1078, 268, 140, 53, 993, 49 },
972 { 1221, 268, 140, 53, 993, 49 },
973 { 1364, 268, 140, 53, 993, 49 },
974 { 1503, 268, 140, 53, 993, 49 },
975 { 27, 268, 140, 53, 993, 49 },
976 { 219, 268, 140, 53, 993, 49 },
977 { 408, 268, 140, 53, 993, 49 },
978 { 553, 268, 140, 53, 993, 49 },
979 { 696, 268, 140, 53, 993, 49 },
980 { 839, 268, 140, 53, 993, 49 },
981 { 982, 268, 140, 53, 993, 49 },
982 { 1125, 268, 140, 53, 993, 49 },
983 { 1268, 268, 140, 53, 993, 49 },
984 { 1411, 268, 140, 53, 993, 49 },
985 { 78, 268, 140, 53, 993, 49 },
986 { 271, 268, 140, 53, 993, 49 },
987 { 460, 268, 140, 53, 993, 49 },
988 { 605, 268, 140, 53, 993, 49 },
989 { 748, 268, 140, 53, 993, 49 },
990 { 891, 268, 140, 53, 993, 49 },
991 { 1034, 268, 140, 53, 993, 49 },
992 { 1177, 268, 140, 53, 993, 49 },
993 { 1320, 268, 140, 53, 993, 49 },
994 { 1463, 268, 140, 53, 993, 49 },
995 { 130, 268, 140, 53, 993, 49 },
996 { 323, 268, 140, 53, 993, 49 },
997 { 175, 280, 140, 53, 4080, 14 },
998 { 643, 476, 4, 86, 1, 56 },
999 { 786, 476, 4, 86, 1, 56 },
1000 { 929, 476, 4, 86, 1, 56 },
1001 { 1072, 476, 4, 86, 1, 56 },
1002 { 1215, 476, 4, 86, 1, 56 },
1003 { 1358, 476, 4, 86, 1, 56 },
1004 { 1497, 476, 4, 86, 1, 56 },
1005 { 21, 476, 4, 86, 1, 56 },
1006 { 213, 476, 4, 86, 1, 56 },
1007 { 401, 476, 4, 86, 1, 56 },
1008 { 545, 476, 4, 86, 1, 56 },
1009 { 688, 476, 4, 86, 1, 56 },
1010 { 831, 476, 4, 86, 1, 56 },
1011 { 974, 476, 4, 86, 1, 56 },
1012 { 1117, 476, 4, 86, 1, 56 },
1013 { 1260, 476, 4, 86, 1, 56 },
1014 { 1403, 476, 4, 86, 1, 56 },
1015 { 70, 476, 4, 86, 1, 56 },
1016 { 263, 476, 4, 86, 1, 56 },
1017 { 452, 476, 4, 86, 1, 56 },
1018 { 597, 476, 4, 86, 1, 56 },
1019 { 740, 476, 4, 86, 1, 56 },
1020 { 883, 476, 4, 86, 1, 56 },
1021 { 1026, 476, 4, 86, 1, 56 },
1022 { 1169, 476, 4, 86, 1, 56 },
1023 { 1312, 476, 4, 86, 1, 56 },
1024 { 1455, 476, 4, 86, 1, 56 },
1025 { 122, 476, 4, 86, 1, 56 },
1026 { 315, 476, 4, 86, 1, 56 },
1027 { 167, 508, 4, 86, 160, 61 },
1028 { 355, 365, 4, 86, 368, 47 },
1029 { 499, 444, 4, 86, 3216, 17 },
1030 { 503, 302, 261, 65, 241, 62 },
1031 { 646, 302, 88, 65, 241, 62 },
1032 { 789, 302, 88, 65, 241, 62 },
1033 { 932, 302, 88, 65, 241, 62 },
1034 { 1075, 302, 88, 65, 241, 62 },
1035 { 1218, 302, 88, 65, 241, 62 },
1036 { 1361, 302, 88, 65, 241, 62 },
1037 { 1500, 302, 88, 65, 241, 62 },
1038 { 24, 302, 88, 65, 241, 62 },
1039 { 216, 302, 88, 65, 241, 62 },
1040 { 404, 302, 88, 65, 241, 62 },
1041 { 549, 302, 88, 65, 241, 62 },
1042 { 692, 302, 88, 65, 241, 62 },
1043 { 835, 302, 88, 65, 241, 62 },
1044 { 978, 302, 88, 65, 241, 62 },
1045 { 1121, 302, 88, 65, 241, 62 },
1046 { 1264, 302, 88, 65, 241, 62 },
1047 { 1407, 302, 88, 65, 241, 62 },
1048 { 74, 302, 88, 65, 241, 62 },
1049 { 267, 302, 88, 65, 241, 62 },
1050 { 456, 302, 88, 65, 241, 62 },
1051 { 601, 302, 88, 65, 241, 62 },
1052 { 744, 302, 88, 65, 241, 62 },
1053 { 887, 302, 88, 65, 241, 62 },
1054 { 1030, 302, 88, 65, 241, 62 },
1055 { 1173, 302, 88, 65, 241, 62 },
1056 { 1316, 302, 88, 65, 241, 62 },
1057 { 1459, 302, 88, 65, 241, 62 },
1058 { 126, 302, 88, 65, 241, 62 },
1059 { 319, 302, 88, 65, 241, 62 },
1060 { 171, 323, 88, 65, 448, 52 },
1061 { 359, 344, 88, 65, 3824, 22 },
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1062};
1063
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1064 // FPR8 Register Class...
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1065 static MCPhysReg FPR8[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1066 AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31,
1067 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1068
1069 // FPR8 Bit set.
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1070 static uint8_t FPR8Bits[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1071 0x00, 0xff, 0xff, 0xff, 0xff,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1072 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1073
1074 // FPR16 Register Class...
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1075 static MCPhysReg FPR16[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1076 AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31,
1077 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1078
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1079 // FPR16 Bit set.
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1080 static uint8_t FPR16Bits[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1081 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
1082 };
1083
1084 // GPR32all Register Class...
1085 static MCPhysReg GPR32all[] = {
1086 AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, AArch64_WSP,
1087 };
1088
1089 // GPR32all Bit set.
1090 static uint8_t GPR32allBits[] = {
1091 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1092 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1093
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1094 // FPR32 Register Class...
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1095 static MCPhysReg FPR32[] = {
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1096 AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31,
1097 };
1098
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1099 // FPR32 Bit set.
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1100 static uint8_t FPR32Bits[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1101 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1102 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1103
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1104 // GPR32 Register Class...
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1105 static MCPhysReg GPR32[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1106 AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR,
1107 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1108
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1109 // GPR32 Bit set.
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1110 static uint8_t GPR32Bits[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1111 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1112 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1113
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1114 // GPR32sp Register Class...
1115 static MCPhysReg GPR32sp[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1116 AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP,
1117 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1118
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1119 // GPR32sp Bit set.
1120 static uint8_t GPR32spBits[] = {
1121 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1122 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1123
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1124 // GPR32common Register Class...
1125 static MCPhysReg GPR32common[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1126 AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30,
1127 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1128
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1129 // GPR32common Bit set.
1130 static uint8_t GPR32commonBits[] = {
1131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1132 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1133
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1134 // CCR Register Class...
1135 static MCPhysReg CCR[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1136 AArch64_NZCV,
1137 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1138
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1139 // CCR Bit set.
1140 static uint8_t CCRBits[] = {
1141 0x08,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1142 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1143
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1144 // GPR32sponly Register Class...
1145 static MCPhysReg GPR32sponly[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1146 AArch64_WSP,
1147 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1148
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1149 // GPR32sponly Bit set.
1150 static uint8_t GPR32sponlyBits[] = {
1151 0x20,
1152 };
1153
1154 // GPR64all Register Class...
1155 static MCPhysReg GPR64all[] = {
1156 AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, AArch64_SP,
1157 };
1158
1159 // GPR64all Bit set.
1160 static uint8_t GPR64allBits[] = {
1161 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1162 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1163
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1164 // FPR64 Register Class...
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1165 static MCPhysReg FPR64[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1166 AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31,
1167 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1168
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1169 // FPR64 Bit set.
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1170 static uint8_t FPR64Bits[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1171 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1172 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1173
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1174 // GPR64 Register Class...
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1175 static MCPhysReg GPR64[] = {
1176 AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1177 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1178
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1179 // GPR64 Bit set.
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1180 static uint8_t GPR64Bits[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1181 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1182 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1183
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1184 // GPR64sp Register Class...
1185 static MCPhysReg GPR64sp[] = {
1186 AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_SP,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1187 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1188
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1189 // GPR64sp Bit set.
1190 static uint8_t GPR64spBits[] = {
1191 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1192 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1193
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1194 // GPR64common Register Class...
1195 static MCPhysReg GPR64common[] = {
1196 AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1197 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1198
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1199 // GPR64common Bit set.
1200 static uint8_t GPR64commonBits[] = {
1201 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1202 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1203
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1204 // tcGPR64 Register Class...
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1205 static MCPhysReg tcGPR64[] = {
1206 AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1207 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1208
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1209 // tcGPR64 Bit set.
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1210 static uint8_t tcGPR64Bits[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1211 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1212 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1213
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1214 // GPR64sponly Register Class...
1215 static MCPhysReg GPR64sponly[] = {
1216 AArch64_SP,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1217 };
1218
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1219 // GPR64sponly Bit set.
1220 static uint8_t GPR64sponlyBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1221 0x10,
1222 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1223
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1224 // DD Register Class...
1225 static MCPhysReg DD[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1226 AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0,
1227 };
1228
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1229 // DD Bit set.
1230 static uint8_t DDBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1231 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1232 };
1233
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1234 // FPR128 Register Class...
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1235 static MCPhysReg FPR128[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1236 AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31,
1237 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1238
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1239 // FPR128 Bit set.
Nguyen Anh Quynhcbb10ba2014-01-15 12:38:38 +0800[diff] [blame]1240 static uint8_t FPR128Bits[] = {
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1241 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1242 };
1243
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1244 // FPR128_lo Register Class...
1245 static MCPhysReg FPR128_lo[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1246 AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15,
1247 };
1248
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1249 // FPR128_lo Bit set.
1250 static uint8_t FPR128_loBits[] = {
1251 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1252 };
1253
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1254 // DDD Register Class...
1255 static MCPhysReg DDD[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1256 AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1,
1257 };
1258
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1259 // DDD Bit set.
1260 static uint8_t DDDBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1262 };
1263
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1264 // DDDD Register Class...
1265 static MCPhysReg DDDD[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1266 AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2,
1267 };
1268
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1269 // DDDD Bit set.
1270 static uint8_t DDDDBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1271 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1272 };
1273
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1274 // QQ Register Class...
1275 static MCPhysReg QQ[] = {
1276 AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1277 };
1278
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1279 // QQ Bit set.
1280 static uint8_t QQBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1281 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1282 };
1283
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1284 // QQ_with_qsub0_in_FPR128_lo Register Class...
1285 static MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
1286 AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1287 };
1288
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1289 // QQ_with_qsub0_in_FPR128_lo Bit set.
1290 static uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1292 };
1293
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1294 // QQ_with_qsub1_in_FPR128_lo Register Class...
1295 static MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
1296 AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1297 };
1298
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1299 // QQ_with_qsub1_in_FPR128_lo Bit set.
1300 static uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1301 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
1302 };
1303
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1304 // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
1305 static MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
1306 AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1307 };
1308
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1309 // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
1310 static uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1311 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1312 };
1313
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1314 // QQQ Register Class...
1315 static MCPhysReg QQQ[] = {
1316 AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1317 };
1318
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1319 // QQQ Bit set.
1320 static uint8_t QQQBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1322 };
1323
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1324 // QQQ_with_qsub0_in_FPR128_lo Register Class...
1325 static MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
1326 AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1327 };
1328
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1329 // QQQ_with_qsub0_in_FPR128_lo Bit set.
1330 static uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1331 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1332 };
1333
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1334 // QQQ_with_qsub1_in_FPR128_lo Register Class...
1335 static MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
1336 AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q31_Q0_Q1,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1337 };
1338
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1339 // QQQ_with_qsub1_in_FPR128_lo Bit set.
1340 static uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
1342 };
1343
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1344 // QQQ_with_qsub2_in_FPR128_lo Register Class...
1345 static MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
1346 AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1347 };
1348
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1349 // QQQ_with_qsub2_in_FPR128_lo Bit set.
1350 static uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1351 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c,
1352 };
1353
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1354 // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
1355 static MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
1356 AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1357 };
1358
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1359 // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
1360 static uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1361 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1362 };
1363
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1364 // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
1365 static MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
1366 AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1367 };
1368
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1369 // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
1370 static uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08,
1372 };
1373
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1374 // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
1375 static MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
1376 AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1377 };
1378
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1379 // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
1380 static uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03,
1382 };
1383
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1384 // QQQQ Register Class...
1385 static MCPhysReg QQQQ[] = {
1386 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
1387 };
1388
1389 // QQQQ Bit set.
1390 static uint8_t QQQQBits[] = {
1391 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1392 };
1393
1394 // QQQQ_with_qsub0_in_FPR128_lo Register Class...
1395 static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
1396 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18,
1397 };
1398
1399 // QQQQ_with_qsub0_in_FPR128_lo Bit set.
1400 static uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
1401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1402 };
1403
1404 // QQQQ_with_qsub1_in_FPR128_lo Register Class...
1405 static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
1406 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q31_Q0_Q1_Q2,
1407 };
1408
1409 // QQQQ_with_qsub1_in_FPR128_lo Bit set.
1410 static uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
1411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
1412 };
1413
1414 // QQQQ_with_qsub2_in_FPR128_lo Register Class...
1415 static MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
1416 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
1417 };
1418
1419 // QQQQ_with_qsub2_in_FPR128_lo Bit set.
1420 static uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
1421 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c,
1422 };
1423
1424 // QQQQ_with_qsub3_in_FPR128_lo Register Class...
1425 static MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
1426 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
1427 };
1428
1429 // QQQQ_with_qsub3_in_FPR128_lo Bit set.
1430 static uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
1431 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e,
1432 };
1433
1434 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
1435 static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
1436 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17,
1437 };
1438
1439 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
1440 static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
1441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1442 };
1443
1444 // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
1445 static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
1446 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q31_Q0_Q1_Q2,
1447 };
1448
1449 // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
1450 static uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
1451 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08,
1452 };
1453
1454 // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
1455 static MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
1456 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
1457 };
1458
1459 // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
1460 static uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
1461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c,
1462 };
1463
1464 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
1465 static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
1466 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16,
1467 };
1468
1469 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
1470 static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
1471 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03,
1472 };
1473
1474 // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
1475 static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1476 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2,
1477 };
1478
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1479 // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
1480 static uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
1481 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1482 };
1483
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1484 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
1485 static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1486 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15,
1487 };
1488
Nguyen Anh Quynh46a74e52014-08-25 16:47:12 +0800[diff] [blame]1489 // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
1490 static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
1491 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
Nguyen Anh Quynh731bf2a2013-12-08 15:13:47 +0800[diff] [blame]1492 };
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1493
1494static MCRegisterClass AArch64MCRegisterClasses[] = {
Nguyen Anh Quynh3e4c3572015-03-03 22:58:54 +0800[diff] [blame]1495 { FPR8, FPR8Bits, 39, 32, sizeof(FPR8Bits), AArch64_FPR8RegClassID, 1, 1, 1, 1 },
1496 { FPR16, FPR16Bits, 26, 32, sizeof(FPR16Bits), AArch64_FPR16RegClassID, 2, 2, 1, 1 },
1497 { GPR32all, GPR32allBits, 58, 33, sizeof(GPR32allBits), AArch64_GPR32allRegClassID, 4, 4, 1, 1 },
1498 { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64_FPR32RegClassID, 4, 4, 1, 1 },
1499 { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64_GPR32RegClassID, 4, 4, 1, 1 },
1500 { GPR32sp, GPR32spBits, 739, 32, sizeof(GPR32spBits), AArch64_GPR32spRegClassID, 4, 4, 1, 1 },
1501 { GPR32common, GPR32commonBits, 76, 31, sizeof(GPR32commonBits), AArch64_GPR32commonRegClassID, 4, 4, 1, 1 },
1502 { CCR, CCRBits, 54, 1, sizeof(CCRBits), AArch64_CCRRegClassID, 4, 4, -1, 0 },
1503 { GPR32sponly, GPR32sponlyBits, 755, 1, sizeof(GPR32sponlyBits), AArch64_GPR32sponlyRegClassID, 4, 4, 1, 1 },
1504 { GPR64all, GPR64allBits, 67, 33, sizeof(GPR64allBits), AArch64_GPR64allRegClassID, 8, 8, 1, 1 },
1505 { FPR64, FPR64Bits, 12, 32, sizeof(FPR64Bits), AArch64_FPR64RegClassID, 8, 8, 1, 1 },
1506 { GPR64, GPR64Bits, 20, 32, sizeof(GPR64Bits), AArch64_GPR64RegClassID, 8, 8, 1, 1 },
1507 { GPR64sp, GPR64spBits, 747, 32, sizeof(GPR64spBits), AArch64_GPR64spRegClassID, 8, 8, 1, 1 },
1508 { GPR64common, GPR64commonBits, 88, 31, sizeof(GPR64commonBits), AArch64_GPR64commonRegClassID, 8, 8, 1, 1 },
1509 { tcGPR64, tcGPR64Bits, 18, 19, sizeof(tcGPR64Bits), AArch64_tcGPR64RegClassID, 8, 8, 1, 1 },
1510 { GPR64sponly, GPR64sponlyBits, 767, 1, sizeof(GPR64sponlyBits), AArch64_GPR64sponlyRegClassID, 8, 8, 1, 1 },
1511 { DD, DDBits, 46, 32, sizeof(DDBits), AArch64_DDRegClassID, 16, 8, 1, 1 },
1512 { FPR128, FPR128Bits, 32, 32, sizeof(FPR128Bits), AArch64_FPR128RegClassID, 16, 16, 1, 1 },
1513 { FPR128_lo, FPR128_loBits, 119, 16, sizeof(FPR128_loBits), AArch64_FPR128_loRegClassID, 16, 16, 1, 1 },
1514 { DDD, DDDBits, 45, 32, sizeof(DDDBits), AArch64_DDDRegClassID, 24, 8, 1, 1 },
1515 { DDDD, DDDDBits, 44, 32, sizeof(DDDDBits), AArch64_DDDDRegClassID, 32, 8, 1, 1 },
1516 { QQ, QQBits, 51, 32, sizeof(QQBits), AArch64_QQRegClassID, 32, 16, 1, 1 },
1517 { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 102, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_loRegClassID, 32, 16, 1, 1 },
1518 { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 164, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 },
1519 { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 251, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 },
1520 { QQQ, QQQBits, 50, 32, sizeof(QQQBits), AArch64_QQQRegClassID, 48, 16, 1, 1 },
1521 { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 101, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 16, 1, 1 },
1522 { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 163, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 },
1523 { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 343, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
1524 { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 191, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 },
1525 { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 493, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
1526 { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 433, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
1527 { QQQQ, QQQQBits, 49, 32, sizeof(QQQQBits), AArch64_QQQQRegClassID, 64, 16, 1, 1 },
1528 { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 100, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1529 { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 162, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1530 { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 342, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1531 { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 586, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1532 { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 129, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1533 { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 371, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1534 { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 677, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1535 { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 309, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1536 { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 615, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
1537 { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 553, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800[diff] [blame]1538};
1539
1540#endif // GET_REGINFO_MC_DESC