Pranith Kumar | 653827b | 2016-01-06 15:52:12 -0400 | [diff] [blame] | 1 | // This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) |
| 2 | // By Nguyen Anh Quynh <aquynh@gmail.com> |
| 3 | |
| 4 | { /* ARM_ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ |
| 5 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6 | }, |
| 7 | { /* ARM_ADCrr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $rm */ |
| 8 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 9 | }, |
| 10 | { /* ARM_ADCrsi, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ |
| 11 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 12 | }, |
| 13 | { /* ARM_ADCrsr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ |
| 14 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 15 | }, |
| 16 | { /* ARM_ADDri, ARM_INS_ADD: add${s}${p} $rd, $rn, $imm */ |
| 17 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 18 | }, |
| 19 | { /* ARM_ADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ |
| 20 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 21 | }, |
| 22 | { /* ARM_ADDrsi, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ |
| 23 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 24 | }, |
| 25 | { /* ARM_ADDrsr, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ |
| 26 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 27 | }, |
| 28 | { /* ARM_ADR, ARM_INS_ADR: adr${p} $rd, $label */ |
| 29 | { CS_AC_WRITE, 0 } |
| 30 | }, |
| 31 | { /* ARM_AESD, ARM_INS_AESD: aesd.8 $vd, $vm */ |
| 32 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 33 | }, |
| 34 | { /* ARM_AESE, ARM_INS_AESE: aese.8 $vd, $vm */ |
| 35 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 36 | }, |
| 37 | { /* ARM_AESIMC, ARM_INS_AESIMC: aesimc.8 $vd, $vm */ |
| 38 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 39 | }, |
| 40 | { /* ARM_AESMC, ARM_INS_AESMC: aesmc.8 $vd, $vm */ |
| 41 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 42 | }, |
| 43 | { /* ARM_ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ |
| 44 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 45 | }, |
| 46 | { /* ARM_ANDrr, ARM_INS_AND: and${s}${p} $rd, $rn, $rm */ |
| 47 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 48 | }, |
| 49 | { /* ARM_ANDrsi, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ |
| 50 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 51 | }, |
| 52 | { /* ARM_ANDrsr, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ |
| 53 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 54 | }, |
| 55 | { /* ARM_BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ |
| 56 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 57 | }, |
| 58 | { /* ARM_BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ |
| 59 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 60 | }, |
| 61 | { /* ARM_BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ |
| 62 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 63 | }, |
| 64 | { /* ARM_BICrr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $rm */ |
| 65 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 66 | }, |
| 67 | { /* ARM_BICrsi, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ |
| 68 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 69 | }, |
| 70 | { /* ARM_BICrsr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ |
| 71 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 72 | }, |
| 73 | { /* ARM_BKPT, ARM_INS_BKPT: bkpt $val */ |
| 74 | { 0 } |
| 75 | }, |
| 76 | { /* ARM_BL, ARM_INS_BL: bl $func */ |
| 77 | { 0 } |
| 78 | }, |
| 79 | { /* ARM_BLX, ARM_INS_BLX: blx $func */ |
| 80 | { CS_AC_READ, 0 } |
| 81 | }, |
| 82 | { /* ARM_BLX_pred, ARM_INS_BLX: blx${p} $func */ |
| 83 | { CS_AC_READ, 0 } |
| 84 | }, |
| 85 | { /* ARM_BLXi, ARM_INS_BLX: blx $target */ |
| 86 | { 0 } |
| 87 | }, |
| 88 | { /* ARM_BL_pred, ARM_INS_BL: bl${p} $func */ |
| 89 | { 0 } |
| 90 | }, |
| 91 | { /* ARM_BX, ARM_INS_BX: bx $dst */ |
| 92 | { CS_AC_READ, 0 } |
| 93 | }, |
| 94 | { /* ARM_BXJ, ARM_INS_BXJ: bxj${p} $func */ |
| 95 | { CS_AC_READ, 0 } |
| 96 | }, |
| 97 | { /* ARM_BX_RET, ARM_INS_BX: bx${p} lr */ |
| 98 | { 0 } |
| 99 | }, |
| 100 | { /* ARM_BX_pred, ARM_INS_BX: bx${p} $dst */ |
| 101 | { CS_AC_READ, 0 } |
| 102 | }, |
| 103 | { /* ARM_Bcc, ARM_INS_B: b${p} $target */ |
| 104 | { 0 } |
| 105 | }, |
| 106 | { /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ |
| 107 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 108 | }, |
| 109 | { /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */ |
| 110 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 111 | }, |
| 112 | { /* ARM_CLREX, ARM_INS_CLREX: clrex */ |
| 113 | { 0 } |
| 114 | }, |
| 115 | { /* ARM_CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ |
| 116 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 117 | }, |
| 118 | { /* ARM_CMNri, ARM_INS_CMN: cmn${p} $rn, $imm */ |
| 119 | { CS_AC_READ, 0 } |
| 120 | }, |
| 121 | { /* ARM_CMNzrr, ARM_INS_CMN: cmn${p} $rn, $rm */ |
| 122 | { CS_AC_READ, CS_AC_READ, 0 } |
| 123 | }, |
| 124 | { /* ARM_CMNzrsi, ARM_INS_CMN: cmn${p} $rn, $shift */ |
| 125 | { CS_AC_READ, 0 } |
| 126 | }, |
| 127 | { /* ARM_CMNzrsr, ARM_INS_CMN: cmn${p} $rn, $shift */ |
| 128 | { CS_AC_READ, CS_AC_READ, 0 } |
| 129 | }, |
| 130 | { /* ARM_CMPri, ARM_INS_CMP: cmp${p} $rn, $imm */ |
| 131 | { CS_AC_READ, 0 } |
| 132 | }, |
| 133 | { /* ARM_CMPrr, ARM_INS_CMP: cmp${p} $rn, $rm */ |
| 134 | { CS_AC_READ, CS_AC_READ, 0 } |
| 135 | }, |
| 136 | { /* ARM_CMPrsi, ARM_INS_CMP: cmp${p} $rn, $shift */ |
| 137 | { CS_AC_READ, 0 } |
| 138 | }, |
| 139 | { /* ARM_CMPrsr, ARM_INS_CMP: cmp${p} $rn, $shift */ |
| 140 | { CS_AC_READ, CS_AC_READ, 0 } |
| 141 | }, |
| 142 | { /* ARM_CPS1p, ARM_INS_CPS: cps $mode */ |
| 143 | { 0 } |
| 144 | }, |
| 145 | { /* ARM_CPS2p, ARM_INS_CPS: cps$imod $iflags */ |
| 146 | { 0 } |
| 147 | }, |
| 148 | { /* ARM_CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ |
| 149 | { 0 } |
| 150 | }, |
| 151 | { /* ARM_CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ |
| 152 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 153 | }, |
| 154 | { /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ |
| 155 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 156 | }, |
| 157 | { /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ |
| 158 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 159 | }, |
| 160 | { /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ |
| 161 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 162 | }, |
| 163 | { /* ARM_CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ |
| 164 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 165 | }, |
| 166 | { /* ARM_CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ |
| 167 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 168 | }, |
| 169 | { /* ARM_DBG, ARM_INS_DBG: dbg${p} $opt */ |
| 170 | { 0 } |
| 171 | }, |
| 172 | { /* ARM_DMB, ARM_INS_DMB: dmb $opt */ |
| 173 | { 0 } |
| 174 | }, |
| 175 | { /* ARM_DSB, ARM_INS_DSB: dsb $opt */ |
| 176 | { 0 } |
| 177 | }, |
| 178 | { /* ARM_EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ |
| 179 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 180 | }, |
| 181 | { /* ARM_EORrr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $rm */ |
| 182 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 183 | }, |
| 184 | { /* ARM_EORrsi, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ |
| 185 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 186 | }, |
| 187 | { /* ARM_EORrsr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ |
| 188 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 189 | }, |
| 190 | { /* ARM_ERET, ARM_INS_ERET: eret${p} */ |
| 191 | { 0 } |
| 192 | }, |
| 193 | { /* ARM_FCONSTD, ARM_INS_VMOV: vmov${p}.f64 $dd, $imm */ |
| 194 | { CS_AC_WRITE, 0 } |
| 195 | }, |
| 196 | { /* ARM_FCONSTS, ARM_INS_VMOV: vmov${p}.f32 $sd, $imm */ |
| 197 | { CS_AC_WRITE, 0 } |
| 198 | }, |
| 199 | { /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx${p} $rn!, $regs */ |
| 200 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 201 | }, |
| 202 | { /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax${p} $rn, $regs */ |
| 203 | { CS_AC_READ, 0 } |
| 204 | }, |
| 205 | { /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax${p} $rn!, $regs */ |
| 206 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 207 | }, |
| 208 | { /* ARM_FMSTAT, ARM_INS_VMRS: vmrs${p} apsr_nzcv, fpscr */ |
| 209 | { 0 } |
| 210 | }, |
| 211 | { /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx${p} $rn!, $regs */ |
| 212 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 213 | }, |
| 214 | { /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax${p} $rn, $regs */ |
| 215 | { CS_AC_READ, 0 } |
| 216 | }, |
| 217 | { /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax${p} $rn!, $regs */ |
| 218 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 219 | }, |
| 220 | { /* ARM_HINT, ARM_INS_HINT: hint${p} $imm */ |
| 221 | { 0 } |
| 222 | }, |
| 223 | { /* ARM_HLT, ARM_INS_HLT: hlt $val */ |
| 224 | { 0 } |
| 225 | }, |
| 226 | { /* ARM_HVC, ARM_INS_HVC: hvc $imm */ |
| 227 | { 0 } |
| 228 | }, |
| 229 | { /* ARM_ISB, ARM_INS_ISB: isb $opt */ |
| 230 | { 0 } |
| 231 | }, |
| 232 | { /* ARM_LDA, ARM_INS_LDA: lda${p} $rt, $addr */ |
| 233 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 234 | }, |
| 235 | { /* ARM_LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ |
| 236 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 237 | }, |
| 238 | { /* ARM_LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ |
| 239 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 240 | }, |
| 241 | { /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ |
| 242 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 243 | }, |
| 244 | { /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $addr */ |
| 245 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 246 | }, |
| 247 | { /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ |
| 248 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 249 | }, |
| 250 | { /* ARM_LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ |
| 251 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 252 | }, |
| 253 | { /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr */ |
| 254 | { CS_AC_READ, CS_AC_READ, 0 } |
| 255 | }, |
| 256 | { /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $option */ |
| 257 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 258 | }, |
| 259 | { /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $offset */ |
| 260 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 261 | }, |
| 262 | { /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr! */ |
| 263 | { CS_AC_READ, CS_AC_READ, 0 } |
| 264 | }, |
| 265 | { /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 $cop, $crd, $addr */ |
| 266 | { CS_AC_READ, CS_AC_READ, 0 } |
| 267 | }, |
| 268 | { /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $option */ |
| 269 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 270 | }, |
| 271 | { /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $offset */ |
| 272 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 273 | }, |
| 274 | { /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 $cop, $crd, $addr! */ |
| 275 | { CS_AC_READ, CS_AC_READ, 0 } |
| 276 | }, |
| 277 | { /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ |
| 278 | { CS_AC_READ, CS_AC_READ, 0 } |
| 279 | }, |
| 280 | { /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ |
| 281 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 282 | }, |
| 283 | { /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ |
| 284 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 285 | }, |
| 286 | { /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ |
| 287 | { CS_AC_READ, CS_AC_READ, 0 } |
| 288 | }, |
| 289 | { /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ |
| 290 | { CS_AC_READ, CS_AC_READ, 0 } |
| 291 | }, |
| 292 | { /* ARM_LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ |
| 293 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 294 | }, |
| 295 | { /* ARM_LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ |
| 296 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 297 | }, |
| 298 | { /* ARM_LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ |
| 299 | { CS_AC_READ, CS_AC_READ, 0 } |
| 300 | }, |
| 301 | { /* ARM_LDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs */ |
| 302 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 303 | }, |
| 304 | { /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs */ |
| 305 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 306 | }, |
| 307 | { /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ |
| 308 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 309 | }, |
| 310 | { /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ |
| 311 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 312 | }, |
| 313 | { /* ARM_LDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ |
| 314 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 315 | }, |
| 316 | { /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs */ |
| 317 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 318 | }, |
| 319 | { /* ARM_LDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs */ |
| 320 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 321 | }, |
| 322 | { /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs */ |
| 323 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 324 | }, |
| 325 | { /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ |
| 326 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 327 | }, |
| 328 | { /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ |
| 329 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 330 | }, |
| 331 | { /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ |
| 332 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 333 | }, |
| 334 | { /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ |
| 335 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 336 | }, |
| 337 | { /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ |
| 338 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 339 | }, |
| 340 | { /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ |
| 341 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 342 | }, |
| 343 | { /* ARM_LDRBi12, ARM_INS_LDRB: ldrb${p} $rt, $addr */ |
| 344 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 345 | }, |
| 346 | { /* ARM_LDRBrs, ARM_INS_LDRB: ldrb${p} $rt, $shift */ |
| 347 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 348 | }, |
| 349 | { /* ARM_LDRD, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ |
| 350 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 351 | }, |
| 352 | { /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr, $offset */ |
| 353 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 354 | }, |
| 355 | { /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ |
| 356 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 357 | }, |
| 358 | { /* ARM_LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ |
| 359 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 360 | }, |
| 361 | { /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ |
| 362 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 363 | }, |
| 364 | { /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $addr */ |
| 365 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 366 | }, |
| 367 | { /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ |
| 368 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 369 | }, |
| 370 | { /* ARM_LDRH, ARM_INS_LDRH: ldrh${p} $rt, $addr */ |
| 371 | { CS_AC_WRITE, 0 } |
| 372 | }, |
| 373 | { /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $offset */ |
| 374 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 375 | }, |
| 376 | { /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $rm */ |
| 377 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 378 | }, |
| 379 | { /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $addr, $offset */ |
| 380 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 381 | }, |
| 382 | { /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ |
| 383 | { CS_AC_WRITE, 0 } |
| 384 | }, |
| 385 | { /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ |
| 386 | { CS_AC_WRITE, 0 } |
| 387 | }, |
| 388 | { /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $offset */ |
| 389 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 390 | }, |
| 391 | { /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $rm */ |
| 392 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 393 | }, |
| 394 | { /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $addr, $offset */ |
| 395 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 396 | }, |
| 397 | { /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ |
| 398 | { CS_AC_WRITE, 0 } |
| 399 | }, |
| 400 | { /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ |
| 401 | { CS_AC_WRITE, 0 } |
| 402 | }, |
| 403 | { /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $offset */ |
| 404 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 405 | }, |
| 406 | { /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $rm */ |
| 407 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 408 | }, |
| 409 | { /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $addr, $offset */ |
| 410 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 411 | }, |
| 412 | { /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ |
| 413 | { CS_AC_WRITE, 0 } |
| 414 | }, |
| 415 | { /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ |
| 416 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 417 | }, |
| 418 | { /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ |
| 419 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 420 | }, |
| 421 | { /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ |
| 422 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 423 | }, |
| 424 | { /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ |
| 425 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 426 | }, |
| 427 | { /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr${p} $rt, $addr! */ |
| 428 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 429 | }, |
| 430 | { /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr${p} $rt, $addr! */ |
| 431 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 432 | }, |
| 433 | { /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| 434 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 435 | }, |
| 436 | { /* ARM_LDRi12, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| 437 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 438 | }, |
| 439 | { /* ARM_LDRrs, ARM_INS_LDR: ldr${p} $rt, $shift */ |
| 440 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 441 | }, |
| 442 | { /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| 443 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 444 | }, |
| 445 | { /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| 446 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 447 | }, |
| 448 | { /* ARM_MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ |
| 449 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 450 | }, |
| 451 | { /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 $cop, $opc1, $rt, $rt2, $crm */ |
| 452 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 453 | }, |
| 454 | { /* ARM_MLA, ARM_INS_MLA: mla${s}${p} $rd, $rn, $rm, $ra */ |
| 455 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 456 | }, |
| 457 | { /* ARM_MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ |
| 458 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 459 | }, |
| 460 | { /* ARM_MOVPCLR, ARM_INS_MOV: mov${p} pc, lr */ |
| 461 | { 0 } |
| 462 | }, |
| 463 | { /* ARM_MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ |
| 464 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 465 | }, |
| 466 | { /* ARM_MOVi, ARM_INS_MOV: mov${s}${p} $rd, $imm */ |
| 467 | { CS_AC_WRITE, 0 } |
| 468 | }, |
| 469 | { /* ARM_MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ |
| 470 | { CS_AC_WRITE, 0 } |
| 471 | }, |
| 472 | { /* ARM_MOVr, ARM_INS_MOV: mov${s}${p} $rd, $rm */ |
| 473 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 474 | }, |
| 475 | { /* ARM_MOVr_TC, ARM_INS_MOV: mov${s}${p} $rd, $rm */ |
| 476 | { 0 } |
| 477 | }, |
| 478 | { /* ARM_MOVsi, ARM_INS_MOV: mov${s}${p} $rd, $src */ |
| 479 | { CS_AC_WRITE, 0 } |
| 480 | }, |
| 481 | { /* ARM_MOVsr, ARM_INS_MOV: mov${s}${p} $rd, $src */ |
| 482 | { CS_AC_WRITE, 0 } |
| 483 | }, |
| 484 | { /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| 485 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 486 | }, |
| 487 | { /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| 488 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 489 | }, |
| 490 | { /* ARM_MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ |
| 491 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 492 | }, |
| 493 | { /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 $cop, $opc1, $rt, $rt2, $crm */ |
| 494 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 495 | }, |
| 496 | { /* ARM_MRS, ARM_INS_MRS: mrs${p} $rd, apsr */ |
| 497 | { CS_AC_WRITE, 0 } |
| 498 | }, |
| 499 | { /* ARM_MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ |
| 500 | { CS_AC_WRITE, 0 } |
| 501 | }, |
| 502 | { /* ARM_MRSsys, ARM_INS_MRS: mrs${p} $rd, spsr */ |
| 503 | { CS_AC_WRITE, 0 } |
| 504 | }, |
| 505 | { /* ARM_MSR, ARM_INS_MSR: msr${p} $mask, $rn */ |
| 506 | { CS_AC_READ, 0 } |
| 507 | }, |
| 508 | { /* ARM_MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ |
| 509 | { CS_AC_READ, 0 } |
| 510 | }, |
| 511 | { /* ARM_MSRi, ARM_INS_MSR: msr${p} $mask, $imm */ |
| 512 | { 0 } |
| 513 | }, |
| 514 | { /* ARM_MUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ |
| 515 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 516 | }, |
| 517 | { /* ARM_MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ |
| 518 | { CS_AC_WRITE, 0 } |
| 519 | }, |
| 520 | { /* ARM_MVNr, ARM_INS_MVN: mvn${s}${p} $rd, $rm */ |
| 521 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 522 | }, |
| 523 | { /* ARM_MVNsi, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ |
| 524 | { CS_AC_WRITE, 0 } |
| 525 | }, |
| 526 | { /* ARM_MVNsr, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ |
| 527 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 528 | }, |
| 529 | { /* ARM_ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ |
| 530 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 531 | }, |
| 532 | { /* ARM_ORRrr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $rm */ |
| 533 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 534 | }, |
| 535 | { /* ARM_ORRrsi, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ |
| 536 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 537 | }, |
| 538 | { /* ARM_ORRrsr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ |
| 539 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 540 | }, |
| 541 | { /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ |
| 542 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 543 | }, |
| 544 | { /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ |
| 545 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 546 | }, |
| 547 | { /* ARM_PLDWi12, ARM_INS_PLDW: pldw $addr */ |
| 548 | { CS_AC_READ, 0 } |
| 549 | }, |
| 550 | { /* ARM_PLDWrs, ARM_INS_PLDW: pldw $shift */ |
| 551 | { CS_AC_READ, 0 } |
| 552 | }, |
| 553 | { /* ARM_PLDi12, ARM_INS_PLD: pld $addr */ |
| 554 | { CS_AC_READ, 0 } |
| 555 | }, |
| 556 | { /* ARM_PLDrs, ARM_INS_PLD: pld $shift */ |
| 557 | { CS_AC_READ, 0 } |
| 558 | }, |
| 559 | { /* ARM_PLIi12, ARM_INS_PLI: pli $addr */ |
| 560 | { CS_AC_READ, 0 } |
| 561 | }, |
| 562 | { /* ARM_PLIrs, ARM_INS_PLI: pli $shift */ |
| 563 | { CS_AC_READ, 0 } |
| 564 | }, |
| 565 | { /* ARM_QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ |
| 566 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 567 | }, |
| 568 | { /* ARM_QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ |
| 569 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 570 | }, |
| 571 | { /* ARM_QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ |
| 572 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 573 | }, |
| 574 | { /* ARM_QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ |
| 575 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 576 | }, |
| 577 | { /* ARM_QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ |
| 578 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 579 | }, |
| 580 | { /* ARM_QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ |
| 581 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 582 | }, |
| 583 | { /* ARM_QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ |
| 584 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 585 | }, |
| 586 | { /* ARM_QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ |
| 587 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 588 | }, |
| 589 | { /* ARM_QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ |
| 590 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 591 | }, |
| 592 | { /* ARM_QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ |
| 593 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 594 | }, |
| 595 | { /* ARM_RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ |
| 596 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 597 | }, |
| 598 | { /* ARM_REV, ARM_INS_REV: rev${p} $rd, $rm */ |
| 599 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 600 | }, |
| 601 | { /* ARM_REV16, ARM_INS_REV16: rev16${p} $rd, $rm */ |
| 602 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 603 | }, |
| 604 | { /* ARM_REVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ |
| 605 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 606 | }, |
| 607 | { /* ARM_RFEDA, ARM_INS_RFEDA: rfeda $rn */ |
| 608 | { CS_AC_READ, 0 } |
| 609 | }, |
| 610 | { /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda $rn! */ |
| 611 | { CS_AC_READ, 0 } |
| 612 | }, |
| 613 | { /* ARM_RFEDB, ARM_INS_RFEDB: rfedb $rn */ |
| 614 | { CS_AC_READ, 0 } |
| 615 | }, |
| 616 | { /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb $rn! */ |
| 617 | { CS_AC_READ, 0 } |
| 618 | }, |
| 619 | { /* ARM_RFEIA, ARM_INS_RFEIA: rfeia $rn */ |
| 620 | { CS_AC_READ, 0 } |
| 621 | }, |
| 622 | { /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia $rn! */ |
| 623 | { CS_AC_READ, 0 } |
| 624 | }, |
| 625 | { /* ARM_RFEIB, ARM_INS_RFEIB: rfeib $rn */ |
| 626 | { CS_AC_READ, 0 } |
| 627 | }, |
| 628 | { /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib $rn! */ |
| 629 | { CS_AC_READ, 0 } |
| 630 | }, |
| 631 | { /* ARM_RSBri, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $imm */ |
| 632 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 633 | }, |
| 634 | { /* ARM_RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ |
| 635 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 636 | }, |
| 637 | { /* ARM_RSBrsi, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ |
| 638 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 639 | }, |
| 640 | { /* ARM_RSBrsr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ |
| 641 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 642 | }, |
| 643 | { /* ARM_RSCri, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $imm */ |
| 644 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 645 | }, |
| 646 | { /* ARM_RSCrr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $rm */ |
| 647 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 648 | }, |
| 649 | { /* ARM_RSCrsi, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ |
| 650 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 651 | }, |
| 652 | { /* ARM_RSCrsr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ |
| 653 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 654 | }, |
| 655 | { /* ARM_SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ |
| 656 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 657 | }, |
| 658 | { /* ARM_SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ |
| 659 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 660 | }, |
| 661 | { /* ARM_SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ |
| 662 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 663 | }, |
| 664 | { /* ARM_SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ |
| 665 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 666 | }, |
| 667 | { /* ARM_SBCrr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $rm */ |
| 668 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 669 | }, |
| 670 | { /* ARM_SBCrsi, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ |
| 671 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 672 | }, |
| 673 | { /* ARM_SBCrsr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ |
| 674 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 675 | }, |
| 676 | { /* ARM_SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $width */ |
| 677 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 678 | }, |
| 679 | { /* ARM_SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ |
| 680 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 681 | }, |
| 682 | { /* ARM_SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ |
| 683 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 684 | }, |
| 685 | { /* ARM_SETEND, ARM_INS_SETEND: setend $end */ |
| 686 | { 0 } |
| 687 | }, |
| 688 | { /* ARM_SHA1C, ARM_INS_SHA1C: sha1c.32 $vd, $vn, $vm */ |
| 689 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 690 | }, |
| 691 | { /* ARM_SHA1H, ARM_INS_SHA1H: sha1h.32 $vd, $vm */ |
| 692 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 693 | }, |
| 694 | { /* ARM_SHA1M, ARM_INS_SHA1M: sha1m.32 $vd, $vn, $vm */ |
| 695 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 696 | }, |
| 697 | { /* ARM_SHA1P, ARM_INS_SHA1P: sha1p.32 $vd, $vn, $vm */ |
| 698 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 699 | }, |
| 700 | { /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0.32 $vd, $vn, $vm */ |
| 701 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 702 | }, |
| 703 | { /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1.32 $vd, $vm */ |
| 704 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 705 | }, |
| 706 | { /* ARM_SHA256H, ARM_INS_SHA256H: sha256h.32 $vd, $vn, $vm */ |
| 707 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 708 | }, |
| 709 | { /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2.32 $vd, $vn, $vm */ |
| 710 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 711 | }, |
| 712 | { /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0.32 $vd, $vm */ |
| 713 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 714 | }, |
| 715 | { /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1.32 $vd, $vn, $vm */ |
| 716 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 717 | }, |
| 718 | { /* ARM_SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ |
| 719 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 720 | }, |
| 721 | { /* ARM_SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ |
| 722 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 723 | }, |
| 724 | { /* ARM_SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ |
| 725 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 726 | }, |
| 727 | { /* ARM_SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ |
| 728 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 729 | }, |
| 730 | { /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ |
| 731 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 732 | }, |
| 733 | { /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ |
| 734 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 735 | }, |
| 736 | { /* ARM_SMC, ARM_INS_SMC: smc${p} $opt */ |
| 737 | { 0 } |
| 738 | }, |
| 739 | { /* ARM_SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ |
| 740 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 741 | }, |
| 742 | { /* ARM_SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ |
| 743 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 744 | }, |
| 745 | { /* ARM_SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ |
| 746 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 747 | }, |
| 748 | { /* ARM_SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ |
| 749 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 750 | }, |
| 751 | { /* ARM_SMLAL, ARM_INS_SMLAL: smlal${s}${p} $rdlo, $rdhi, $rn, $rm */ |
| 752 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 753 | }, |
| 754 | { /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $rdlo, $rdhi, $rn, $rm */ |
| 755 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 756 | }, |
| 757 | { /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $rdlo, $rdhi, $rn, $rm */ |
| 758 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 759 | }, |
| 760 | { /* ARM_SMLALD, ARM_INS_SMLALD: smlald${p} $rdlo, $rdhi, $rn, $rm */ |
| 761 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 762 | }, |
| 763 | { /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $rdlo, $rdhi, $rn, $rm */ |
| 764 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 765 | }, |
| 766 | { /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $rdlo, $rdhi, $rn, $rm */ |
| 767 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 768 | }, |
| 769 | { /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $rdlo, $rdhi, $rn, $rm */ |
| 770 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 771 | }, |
| 772 | { /* ARM_SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ |
| 773 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 774 | }, |
| 775 | { /* ARM_SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ |
| 776 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 777 | }, |
| 778 | { /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ |
| 779 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 780 | }, |
| 781 | { /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ |
| 782 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 783 | }, |
| 784 | { /* ARM_SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ |
| 785 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 786 | }, |
| 787 | { /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ |
| 788 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 789 | }, |
| 790 | { /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld${p} $rdlo, $rdhi, $rn, $rm */ |
| 791 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 792 | }, |
| 793 | { /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $rdlo, $rdhi, $rn, $rm */ |
| 794 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 795 | }, |
| 796 | { /* ARM_SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ |
| 797 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 798 | }, |
| 799 | { /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ |
| 800 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 801 | }, |
| 802 | { /* ARM_SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ |
| 803 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 804 | }, |
| 805 | { /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ |
| 806 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 807 | }, |
| 808 | { /* ARM_SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ |
| 809 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 810 | }, |
| 811 | { /* ARM_SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ |
| 812 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 813 | }, |
| 814 | { /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ |
| 815 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 816 | }, |
| 817 | { /* ARM_SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ |
| 818 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 819 | }, |
| 820 | { /* ARM_SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ |
| 821 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 822 | }, |
| 823 | { /* ARM_SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ |
| 824 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 825 | }, |
| 826 | { /* ARM_SMULL, ARM_INS_SMULL: smull${s}${p} $rdlo, $rdhi, $rn, $rm */ |
| 827 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 828 | }, |
| 829 | { /* ARM_SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ |
| 830 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 831 | }, |
| 832 | { /* ARM_SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ |
| 833 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 834 | }, |
| 835 | { /* ARM_SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ |
| 836 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 837 | }, |
| 838 | { /* ARM_SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ |
| 839 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 840 | }, |
| 841 | { /* ARM_SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ |
| 842 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 843 | }, |
| 844 | { /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ |
| 845 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 846 | }, |
| 847 | { /* ARM_SRSDA, ARM_INS_SRSDA: srsda sp, $mode */ |
| 848 | { 0 } |
| 849 | }, |
| 850 | { /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda sp!, $mode */ |
| 851 | { 0 } |
| 852 | }, |
| 853 | { /* ARM_SRSDB, ARM_INS_SRSDB: srsdb sp, $mode */ |
| 854 | { 0 } |
| 855 | }, |
| 856 | { /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb sp!, $mode */ |
| 857 | { 0 } |
| 858 | }, |
| 859 | { /* ARM_SRSIA, ARM_INS_SRSIA: srsia sp, $mode */ |
| 860 | { 0 } |
| 861 | }, |
| 862 | { /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia sp!, $mode */ |
| 863 | { 0 } |
| 864 | }, |
| 865 | { /* ARM_SRSIB, ARM_INS_SRSIB: srsib sp, $mode */ |
| 866 | { 0 } |
| 867 | }, |
| 868 | { /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib sp!, $mode */ |
| 869 | { 0 } |
| 870 | }, |
| 871 | { /* ARM_SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ |
| 872 | { CS_AC_WRITE, 0 } |
| 873 | }, |
| 874 | { /* ARM_SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ |
| 875 | { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } |
| 876 | }, |
| 877 | { /* ARM_SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ |
| 878 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 879 | }, |
| 880 | { /* ARM_SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ |
| 881 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 882 | }, |
| 883 | { /* ARM_SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ |
| 884 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 885 | }, |
| 886 | { /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l $cop, $crd, $addr */ |
| 887 | { CS_AC_READ, CS_AC_READ, 0 } |
| 888 | }, |
| 889 | { /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $option */ |
| 890 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 891 | }, |
| 892 | { /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $offset */ |
| 893 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 894 | }, |
| 895 | { /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l $cop, $crd, $addr! */ |
| 896 | { CS_AC_READ, CS_AC_READ, 0 } |
| 897 | }, |
| 898 | { /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 $cop, $crd, $addr */ |
| 899 | { CS_AC_READ, CS_AC_READ, 0 } |
| 900 | }, |
| 901 | { /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 $cop, $crd, $addr, $option */ |
| 902 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 903 | }, |
| 904 | { /* ARM_STC2_POST, ARM_INS_STC2: stc2 $cop, $crd, $addr, $offset */ |
| 905 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 906 | }, |
| 907 | { /* ARM_STC2_PRE, ARM_INS_STC2: stc2 $cop, $crd, $addr! */ |
| 908 | { CS_AC_READ, CS_AC_READ, 0 } |
| 909 | }, |
| 910 | { /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ |
| 911 | { CS_AC_READ, CS_AC_READ, 0 } |
| 912 | }, |
| 913 | { /* ARM_STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ |
| 914 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 915 | }, |
| 916 | { /* ARM_STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ |
| 917 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 918 | }, |
| 919 | { /* ARM_STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ |
| 920 | { CS_AC_READ, CS_AC_READ, 0 } |
| 921 | }, |
| 922 | { /* ARM_STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ |
| 923 | { CS_AC_READ, CS_AC_READ, 0 } |
| 924 | }, |
| 925 | { /* ARM_STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ |
| 926 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 927 | }, |
| 928 | { /* ARM_STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ |
| 929 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 930 | }, |
| 931 | { /* ARM_STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ |
| 932 | { CS_AC_READ, CS_AC_READ, 0 } |
| 933 | }, |
| 934 | { /* ARM_STL, ARM_INS_STL: stl${p} $rt, $addr */ |
| 935 | { CS_AC_READ, CS_AC_READ, 0 } |
| 936 | }, |
| 937 | { /* ARM_STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ |
| 938 | { CS_AC_READ, CS_AC_READ, 0 } |
| 939 | }, |
| 940 | { /* ARM_STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ |
| 941 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 942 | }, |
| 943 | { /* ARM_STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ |
| 944 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 945 | }, |
| 946 | { /* ARM_STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $addr */ |
| 947 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 948 | }, |
| 949 | { /* ARM_STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ |
| 950 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 951 | }, |
| 952 | { /* ARM_STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ |
| 953 | { CS_AC_READ, CS_AC_READ, 0 } |
| 954 | }, |
| 955 | { /* ARM_STMDA, ARM_INS_STMDA: stmda${p} $rn, $regs */ |
| 956 | { CS_AC_READ, CS_AC_READ, 0 } |
| 957 | }, |
| 958 | { /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs */ |
| 959 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 960 | }, |
| 961 | { /* ARM_STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ |
| 962 | { CS_AC_READ, CS_AC_READ, 0 } |
| 963 | }, |
| 964 | { /* ARM_STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ |
| 965 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 966 | }, |
| 967 | { /* ARM_STMIA, ARM_INS_STM: stm${p} $rn, $regs */ |
| 968 | { CS_AC_READ, CS_AC_READ, 0 } |
| 969 | }, |
| 970 | { /* ARM_STMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ |
| 971 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 972 | }, |
| 973 | { /* ARM_STMIB, ARM_INS_STMIB: stmib${p} $rn, $regs */ |
| 974 | { CS_AC_READ, CS_AC_READ, 0 } |
| 975 | }, |
| 976 | { /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs */ |
| 977 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 978 | }, |
| 979 | { /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ |
| 980 | { CS_AC_READ, CS_AC_READ, 0 } |
| 981 | }, |
| 982 | { /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ |
| 983 | { CS_AC_READ, CS_AC_READ, 0 } |
| 984 | }, |
| 985 | { /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ |
| 986 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 987 | }, |
| 988 | { /* ARM_STRB_POST_REG, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ |
| 989 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 990 | }, |
| 991 | { /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb${p} $rt, $addr! */ |
| 992 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 993 | }, |
| 994 | { /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb${p} $rt, $addr! */ |
| 995 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 996 | }, |
| 997 | { /* ARM_STRBi12, ARM_INS_STRB: strb${p} $rt, $addr */ |
| 998 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 999 | }, |
| 1000 | { /* ARM_STRBrs, ARM_INS_STRB: strb${p} $rt, $shift */ |
| 1001 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1002 | }, |
| 1003 | { /* ARM_STRD, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ |
| 1004 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1005 | }, |
| 1006 | { /* ARM_STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr, $offset */ |
| 1007 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 1008 | }, |
| 1009 | { /* ARM_STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ |
| 1010 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 1011 | }, |
| 1012 | { /* ARM_STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ |
| 1013 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1014 | }, |
| 1015 | { /* ARM_STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ |
| 1016 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1017 | }, |
| 1018 | { /* ARM_STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $addr */ |
| 1019 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1020 | }, |
| 1021 | { /* ARM_STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ |
| 1022 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1023 | }, |
| 1024 | { /* ARM_STRH, ARM_INS_STRH: strh${p} $rt, $addr */ |
| 1025 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1026 | }, |
| 1027 | { /* ARM_STRHTi, ARM_INS_STRHT: strht${p} $rt, $addr, $offset */ |
| 1028 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1029 | }, |
| 1030 | { /* ARM_STRHTr, ARM_INS_STRHT: strht${p} $rt, $addr, $rm */ |
| 1031 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 1032 | }, |
| 1033 | { /* ARM_STRH_POST, ARM_INS_STRH: strh${p} $rt, $addr, $offset */ |
| 1034 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1035 | }, |
| 1036 | { /* ARM_STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ |
| 1037 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1038 | }, |
| 1039 | { /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ |
| 1040 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1041 | }, |
| 1042 | { /* ARM_STRT_POST_REG, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ |
| 1043 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1044 | }, |
| 1045 | { /* ARM_STR_POST_IMM, ARM_INS_STR: str${p} $rt, $addr, $offset */ |
| 1046 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1047 | }, |
| 1048 | { /* ARM_STR_POST_REG, ARM_INS_STR: str${p} $rt, $addr, $offset */ |
| 1049 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1050 | }, |
| 1051 | { /* ARM_STR_PRE_IMM, ARM_INS_STR: str${p} $rt, $addr! */ |
| 1052 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1053 | }, |
| 1054 | { /* ARM_STR_PRE_REG, ARM_INS_STR: str${p} $rt, $addr! */ |
| 1055 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1056 | }, |
| 1057 | { /* ARM_STRi12, ARM_INS_STR: str${p} $rt, $addr */ |
| 1058 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 1059 | }, |
| 1060 | { /* ARM_STRrs, ARM_INS_STR: str${p} $rt, $shift */ |
| 1061 | { CS_AC_READ, 0 } |
| 1062 | }, |
| 1063 | { /* ARM_SUBri, ARM_INS_SUB: sub${s}${p} $rd, $rn, $imm */ |
| 1064 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1065 | }, |
| 1066 | { /* ARM_SUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ |
| 1067 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1068 | }, |
| 1069 | { /* ARM_SUBrsi, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ |
| 1070 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1071 | }, |
| 1072 | { /* ARM_SUBrsr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ |
| 1073 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1074 | }, |
| 1075 | { /* ARM_SVC, ARM_INS_SVC: svc${p} $svc */ |
| 1076 | { 0 } |
| 1077 | }, |
| 1078 | { /* ARM_SWP, ARM_INS_SWP: swp${p} $rt, $rt2, $addr */ |
| 1079 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1080 | }, |
| 1081 | { /* ARM_SWPB, ARM_INS_SWPB: swpb${p} $rt, $rt2, $addr */ |
| 1082 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1083 | }, |
| 1084 | { /* ARM_SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ |
| 1085 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1086 | }, |
| 1087 | { /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ |
| 1088 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1089 | }, |
| 1090 | { /* ARM_SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ |
| 1091 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1092 | }, |
| 1093 | { /* ARM_SXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm$rot */ |
| 1094 | { CS_AC_WRITE, 0 } |
| 1095 | }, |
| 1096 | { /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ |
| 1097 | { CS_AC_WRITE, 0 } |
| 1098 | }, |
| 1099 | { /* ARM_SXTH, ARM_INS_SXTH: sxth${p} $rd, $rm$rot */ |
| 1100 | { CS_AC_WRITE, 0 } |
| 1101 | }, |
| 1102 | { /* ARM_TEQri, ARM_INS_TEQ: teq${p} $rn, $imm */ |
| 1103 | { CS_AC_READ, 0 } |
| 1104 | }, |
| 1105 | { /* ARM_TEQrr, ARM_INS_TEQ: teq${p} $rn, $rm */ |
| 1106 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1107 | }, |
| 1108 | { /* ARM_TEQrsi, ARM_INS_TEQ: teq${p} $rn, $shift */ |
| 1109 | { CS_AC_READ, 0 } |
| 1110 | }, |
| 1111 | { /* ARM_TEQrsr, ARM_INS_TEQ: teq${p} $rn, $shift */ |
| 1112 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1113 | }, |
| 1114 | { /* ARM_TRAP, ARM_INS_TRAP: trap */ |
| 1115 | { 0 } |
| 1116 | }, |
| 1117 | { /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ |
| 1118 | { 0 } |
| 1119 | }, |
| 1120 | { /* ARM_TSTri, ARM_INS_TST: tst${p} $rn, $imm */ |
| 1121 | { CS_AC_READ, 0 } |
| 1122 | }, |
| 1123 | { /* ARM_TSTrr, ARM_INS_TST: tst${p} $rn, $rm */ |
| 1124 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1125 | }, |
| 1126 | { /* ARM_TSTrsi, ARM_INS_TST: tst${p} $rn, $shift */ |
| 1127 | { CS_AC_READ, 0 } |
| 1128 | }, |
| 1129 | { /* ARM_TSTrsr, ARM_INS_TST: tst${p} $rn, $shift */ |
| 1130 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1131 | }, |
| 1132 | { /* ARM_UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ |
| 1133 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1134 | }, |
| 1135 | { /* ARM_UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ |
| 1136 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1137 | }, |
| 1138 | { /* ARM_UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ |
| 1139 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1140 | }, |
| 1141 | { /* ARM_UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $width */ |
| 1142 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1143 | }, |
| 1144 | { /* ARM_UDF, ARM_INS_UDF: udf $imm16 */ |
| 1145 | { 0 } |
| 1146 | }, |
| 1147 | { /* ARM_UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ |
| 1148 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1149 | }, |
| 1150 | { /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ |
| 1151 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1152 | }, |
| 1153 | { /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ |
| 1154 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1155 | }, |
| 1156 | { /* ARM_UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ |
| 1157 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1158 | }, |
| 1159 | { /* ARM_UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ |
| 1160 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1161 | }, |
| 1162 | { /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ |
| 1163 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1164 | }, |
| 1165 | { /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ |
| 1166 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1167 | }, |
| 1168 | { /* ARM_UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ |
| 1169 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1170 | }, |
| 1171 | { /* ARM_UMLAL, ARM_INS_UMLAL: umlal${s}${p} $rdlo, $rdhi, $rn, $rm */ |
| 1172 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1173 | }, |
| 1174 | { /* ARM_UMULL, ARM_INS_UMULL: umull${s}${p} $rdlo, $rdhi, $rn, $rm */ |
| 1175 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1176 | }, |
| 1177 | { /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ |
| 1178 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1179 | }, |
| 1180 | { /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ |
| 1181 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1182 | }, |
| 1183 | { /* ARM_UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ |
| 1184 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1185 | }, |
| 1186 | { /* ARM_UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ |
| 1187 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1188 | }, |
| 1189 | { /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ |
| 1190 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1191 | }, |
| 1192 | { /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ |
| 1193 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1194 | }, |
| 1195 | { /* ARM_USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ |
| 1196 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1197 | }, |
| 1198 | { /* ARM_USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ |
| 1199 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 1200 | }, |
| 1201 | { /* ARM_USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ |
| 1202 | { CS_AC_WRITE, 0 } |
| 1203 | }, |
| 1204 | { /* ARM_USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ |
| 1205 | { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } |
| 1206 | }, |
| 1207 | { /* ARM_USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ |
| 1208 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1209 | }, |
| 1210 | { /* ARM_USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ |
| 1211 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1212 | }, |
| 1213 | { /* ARM_USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ |
| 1214 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1215 | }, |
| 1216 | { /* ARM_UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ |
| 1217 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1218 | }, |
| 1219 | { /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ |
| 1220 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1221 | }, |
| 1222 | { /* ARM_UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ |
| 1223 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1224 | }, |
| 1225 | { /* ARM_UXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm$rot */ |
| 1226 | { CS_AC_WRITE, 0 } |
| 1227 | }, |
| 1228 | { /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ |
| 1229 | { CS_AC_WRITE, 0 } |
| 1230 | }, |
| 1231 | { /* ARM_UXTH, ARM_INS_UXTH: uxth${p} $rd, $rm$rot */ |
| 1232 | { CS_AC_WRITE, 0 } |
| 1233 | }, |
| 1234 | { /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal${p}.s32 $vd, $vn, $vm */ |
| 1235 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1236 | }, |
| 1237 | { /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal${p}.s16 $vd, $vn, $vm */ |
| 1238 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1239 | }, |
| 1240 | { /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal${p}.s8 $vd, $vn, $vm */ |
| 1241 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1242 | }, |
| 1243 | { /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal${p}.u32 $vd, $vn, $vm */ |
| 1244 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1245 | }, |
| 1246 | { /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal${p}.u16 $vd, $vn, $vm */ |
| 1247 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1248 | }, |
| 1249 | { /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal${p}.u8 $vd, $vn, $vm */ |
| 1250 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1251 | }, |
| 1252 | { /* ARM_VABAsv16i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ |
| 1253 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1254 | }, |
| 1255 | { /* ARM_VABAsv2i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ |
| 1256 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1257 | }, |
| 1258 | { /* ARM_VABAsv4i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ |
| 1259 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1260 | }, |
| 1261 | { /* ARM_VABAsv4i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ |
| 1262 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1263 | }, |
| 1264 | { /* ARM_VABAsv8i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ |
| 1265 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1266 | }, |
| 1267 | { /* ARM_VABAsv8i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ |
| 1268 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1269 | }, |
| 1270 | { /* ARM_VABAuv16i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ |
| 1271 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1272 | }, |
| 1273 | { /* ARM_VABAuv2i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ |
| 1274 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1275 | }, |
| 1276 | { /* ARM_VABAuv4i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ |
| 1277 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1278 | }, |
| 1279 | { /* ARM_VABAuv4i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ |
| 1280 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1281 | }, |
| 1282 | { /* ARM_VABAuv8i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ |
| 1283 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1284 | }, |
| 1285 | { /* ARM_VABAuv8i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ |
| 1286 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1287 | }, |
| 1288 | { /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl${p}.s32 $vd, $vn, $vm */ |
| 1289 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1290 | }, |
| 1291 | { /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl${p}.s16 $vd, $vn, $vm */ |
| 1292 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1293 | }, |
| 1294 | { /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl${p}.s8 $vd, $vn, $vm */ |
| 1295 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1296 | }, |
| 1297 | { /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl${p}.u32 $vd, $vn, $vm */ |
| 1298 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1299 | }, |
| 1300 | { /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl${p}.u16 $vd, $vn, $vm */ |
| 1301 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1302 | }, |
| 1303 | { /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl${p}.u8 $vd, $vn, $vm */ |
| 1304 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1305 | }, |
| 1306 | { /* ARM_VABDfd, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ |
| 1307 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1308 | }, |
| 1309 | { /* ARM_VABDfq, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ |
| 1310 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1311 | }, |
| 1312 | { /* ARM_VABDsv16i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ |
| 1313 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1314 | }, |
| 1315 | { /* ARM_VABDsv2i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ |
| 1316 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1317 | }, |
| 1318 | { /* ARM_VABDsv4i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ |
| 1319 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1320 | }, |
| 1321 | { /* ARM_VABDsv4i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ |
| 1322 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1323 | }, |
| 1324 | { /* ARM_VABDsv8i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ |
| 1325 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1326 | }, |
| 1327 | { /* ARM_VABDsv8i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ |
| 1328 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1329 | }, |
| 1330 | { /* ARM_VABDuv16i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ |
| 1331 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1332 | }, |
| 1333 | { /* ARM_VABDuv2i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ |
| 1334 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1335 | }, |
| 1336 | { /* ARM_VABDuv4i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ |
| 1337 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1338 | }, |
| 1339 | { /* ARM_VABDuv4i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ |
| 1340 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1341 | }, |
| 1342 | { /* ARM_VABDuv8i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ |
| 1343 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1344 | }, |
| 1345 | { /* ARM_VABDuv8i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ |
| 1346 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1347 | }, |
| 1348 | { /* ARM_VABSD, ARM_INS_VABS: vabs${p}.f64 $dd, $dm */ |
| 1349 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1350 | }, |
| 1351 | { /* ARM_VABSS, ARM_INS_VABS: vabs${p}.f32 $sd, $sm */ |
| 1352 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1353 | }, |
| 1354 | { /* ARM_VABSfd, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ |
| 1355 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1356 | }, |
| 1357 | { /* ARM_VABSfq, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ |
| 1358 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1359 | }, |
| 1360 | { /* ARM_VABSv16i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ |
| 1361 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1362 | }, |
| 1363 | { /* ARM_VABSv2i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ |
| 1364 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1365 | }, |
| 1366 | { /* ARM_VABSv4i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ |
| 1367 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1368 | }, |
| 1369 | { /* ARM_VABSv4i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ |
| 1370 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1371 | }, |
| 1372 | { /* ARM_VABSv8i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ |
| 1373 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1374 | }, |
| 1375 | { /* ARM_VABSv8i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ |
| 1376 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1377 | }, |
| 1378 | { /* ARM_VACGEd, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ |
| 1379 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1380 | }, |
| 1381 | { /* ARM_VACGEq, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ |
| 1382 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1383 | }, |
| 1384 | { /* ARM_VACGTd, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ |
| 1385 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1386 | }, |
| 1387 | { /* ARM_VACGTq, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ |
| 1388 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1389 | }, |
| 1390 | { /* ARM_VADDD, ARM_INS_VADD: vadd${p}.f64 $dd, $dn, $dm */ |
| 1391 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1392 | }, |
| 1393 | { /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn${p}.i64 $vd, $vn, $vm */ |
| 1394 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1395 | }, |
| 1396 | { /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn${p}.i32 $vd, $vn, $vm */ |
| 1397 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1398 | }, |
| 1399 | { /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn${p}.i16 $vd, $vn, $vm */ |
| 1400 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1401 | }, |
| 1402 | { /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl${p}.s32 $vd, $vn, $vm */ |
| 1403 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1404 | }, |
| 1405 | { /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl${p}.s16 $vd, $vn, $vm */ |
| 1406 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1407 | }, |
| 1408 | { /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl${p}.s8 $vd, $vn, $vm */ |
| 1409 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1410 | }, |
| 1411 | { /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl${p}.u32 $vd, $vn, $vm */ |
| 1412 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1413 | }, |
| 1414 | { /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl${p}.u16 $vd, $vn, $vm */ |
| 1415 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1416 | }, |
| 1417 | { /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl${p}.u8 $vd, $vn, $vm */ |
| 1418 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1419 | }, |
| 1420 | { /* ARM_VADDS, ARM_INS_VADD: vadd${p}.f32 $sd, $sn, $sm */ |
| 1421 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1422 | }, |
| 1423 | { /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw${p}.s32 $vd, $vn, $vm */ |
| 1424 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1425 | }, |
| 1426 | { /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw${p}.s16 $vd, $vn, $vm */ |
| 1427 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1428 | }, |
| 1429 | { /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw${p}.s8 $vd, $vn, $vm */ |
| 1430 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1431 | }, |
| 1432 | { /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw${p}.u32 $vd, $vn, $vm */ |
| 1433 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1434 | }, |
| 1435 | { /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw${p}.u16 $vd, $vn, $vm */ |
| 1436 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1437 | }, |
| 1438 | { /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw${p}.u8 $vd, $vn, $vm */ |
| 1439 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1440 | }, |
| 1441 | { /* ARM_VADDfd, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ |
| 1442 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1443 | }, |
| 1444 | { /* ARM_VADDfq, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ |
| 1445 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1446 | }, |
| 1447 | { /* ARM_VADDv16i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ |
| 1448 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1449 | }, |
| 1450 | { /* ARM_VADDv1i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ |
| 1451 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1452 | }, |
| 1453 | { /* ARM_VADDv2i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ |
| 1454 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1455 | }, |
| 1456 | { /* ARM_VADDv2i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ |
| 1457 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1458 | }, |
| 1459 | { /* ARM_VADDv4i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ |
| 1460 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1461 | }, |
| 1462 | { /* ARM_VADDv4i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ |
| 1463 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1464 | }, |
| 1465 | { /* ARM_VADDv8i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ |
| 1466 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1467 | }, |
| 1468 | { /* ARM_VADDv8i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ |
| 1469 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1470 | }, |
| 1471 | { /* ARM_VANDd, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ |
| 1472 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1473 | }, |
| 1474 | { /* ARM_VANDq, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ |
| 1475 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1476 | }, |
| 1477 | { /* ARM_VBICd, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ |
| 1478 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1479 | }, |
| 1480 | { /* ARM_VBICiv2i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ |
| 1481 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 1482 | }, |
| 1483 | { /* ARM_VBICiv4i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ |
| 1484 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 1485 | }, |
| 1486 | { /* ARM_VBICiv4i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ |
| 1487 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 1488 | }, |
| 1489 | { /* ARM_VBICiv8i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ |
| 1490 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 1491 | }, |
| 1492 | { /* ARM_VBICq, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ |
| 1493 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1494 | }, |
| 1495 | { /* ARM_VBIFd, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ |
| 1496 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1497 | }, |
| 1498 | { /* ARM_VBIFq, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ |
| 1499 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1500 | }, |
| 1501 | { /* ARM_VBITd, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ |
| 1502 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1503 | }, |
| 1504 | { /* ARM_VBITq, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ |
| 1505 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1506 | }, |
| 1507 | { /* ARM_VBSLd, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ |
| 1508 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1509 | }, |
| 1510 | { /* ARM_VBSLq, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ |
| 1511 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1512 | }, |
| 1513 | { /* ARM_VCEQfd, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ |
| 1514 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1515 | }, |
| 1516 | { /* ARM_VCEQfq, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ |
| 1517 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1518 | }, |
| 1519 | { /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ |
| 1520 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1521 | }, |
| 1522 | { /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ |
| 1523 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1524 | }, |
| 1525 | { /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ |
| 1526 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1527 | }, |
| 1528 | { /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ |
| 1529 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1530 | }, |
| 1531 | { /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ |
| 1532 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1533 | }, |
| 1534 | { /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ |
| 1535 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1536 | }, |
| 1537 | { /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ |
| 1538 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1539 | }, |
| 1540 | { /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ |
| 1541 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1542 | }, |
| 1543 | { /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ |
| 1544 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1545 | }, |
| 1546 | { /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ |
| 1547 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1548 | }, |
| 1549 | { /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ |
| 1550 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1551 | }, |
| 1552 | { /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ |
| 1553 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1554 | }, |
| 1555 | { /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ |
| 1556 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1557 | }, |
| 1558 | { /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ |
| 1559 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1560 | }, |
| 1561 | { /* ARM_VCGEfd, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ |
| 1562 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1563 | }, |
| 1564 | { /* ARM_VCGEfq, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ |
| 1565 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1566 | }, |
| 1567 | { /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ |
| 1568 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1569 | }, |
| 1570 | { /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ |
| 1571 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1572 | }, |
| 1573 | { /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ |
| 1574 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1575 | }, |
| 1576 | { /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ |
| 1577 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1578 | }, |
| 1579 | { /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ |
| 1580 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1581 | }, |
| 1582 | { /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ |
| 1583 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1584 | }, |
| 1585 | { /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ |
| 1586 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1587 | }, |
| 1588 | { /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ |
| 1589 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1590 | }, |
| 1591 | { /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ |
| 1592 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1593 | }, |
| 1594 | { /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ |
| 1595 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1596 | }, |
| 1597 | { /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ |
| 1598 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1599 | }, |
| 1600 | { /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ |
| 1601 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1602 | }, |
| 1603 | { /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ |
| 1604 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1605 | }, |
| 1606 | { /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ |
| 1607 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1608 | }, |
| 1609 | { /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ |
| 1610 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1611 | }, |
| 1612 | { /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ |
| 1613 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1614 | }, |
| 1615 | { /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ |
| 1616 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1617 | }, |
| 1618 | { /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ |
| 1619 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1620 | }, |
| 1621 | { /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ |
| 1622 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1623 | }, |
| 1624 | { /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ |
| 1625 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1626 | }, |
| 1627 | { /* ARM_VCGTfd, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ |
| 1628 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1629 | }, |
| 1630 | { /* ARM_VCGTfq, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ |
| 1631 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1632 | }, |
| 1633 | { /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ |
| 1634 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1635 | }, |
| 1636 | { /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ |
| 1637 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1638 | }, |
| 1639 | { /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ |
| 1640 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1641 | }, |
| 1642 | { /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ |
| 1643 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1644 | }, |
| 1645 | { /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ |
| 1646 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1647 | }, |
| 1648 | { /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ |
| 1649 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1650 | }, |
| 1651 | { /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ |
| 1652 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1653 | }, |
| 1654 | { /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ |
| 1655 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1656 | }, |
| 1657 | { /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ |
| 1658 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1659 | }, |
| 1660 | { /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ |
| 1661 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1662 | }, |
| 1663 | { /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ |
| 1664 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1665 | }, |
| 1666 | { /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ |
| 1667 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1668 | }, |
| 1669 | { /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ |
| 1670 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1671 | }, |
| 1672 | { /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ |
| 1673 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1674 | }, |
| 1675 | { /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ |
| 1676 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1677 | }, |
| 1678 | { /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ |
| 1679 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1680 | }, |
| 1681 | { /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ |
| 1682 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1683 | }, |
| 1684 | { /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ |
| 1685 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1686 | }, |
| 1687 | { /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ |
| 1688 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1689 | }, |
| 1690 | { /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ |
| 1691 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1692 | }, |
| 1693 | { /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ |
| 1694 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1695 | }, |
| 1696 | { /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ |
| 1697 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1698 | }, |
| 1699 | { /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ |
| 1700 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1701 | }, |
| 1702 | { /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ |
| 1703 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1704 | }, |
| 1705 | { /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ |
| 1706 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1707 | }, |
| 1708 | { /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ |
| 1709 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1710 | }, |
| 1711 | { /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ |
| 1712 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1713 | }, |
| 1714 | { /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ |
| 1715 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1716 | }, |
| 1717 | { /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ |
| 1718 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1719 | }, |
| 1720 | { /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ |
| 1721 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1722 | }, |
| 1723 | { /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ |
| 1724 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1725 | }, |
| 1726 | { /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ |
| 1727 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1728 | }, |
| 1729 | { /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ |
| 1730 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1731 | }, |
| 1732 | { /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ |
| 1733 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1734 | }, |
| 1735 | { /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ |
| 1736 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1737 | }, |
| 1738 | { /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ |
| 1739 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1740 | }, |
| 1741 | { /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ |
| 1742 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1743 | }, |
| 1744 | { /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ |
| 1745 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1746 | }, |
| 1747 | { /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ |
| 1748 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1749 | }, |
| 1750 | { /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ |
| 1751 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1752 | }, |
| 1753 | { /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ |
| 1754 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1755 | }, |
| 1756 | { /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ |
| 1757 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1758 | }, |
| 1759 | { /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ |
| 1760 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1761 | }, |
| 1762 | { /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ |
| 1763 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1764 | }, |
| 1765 | { /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ |
| 1766 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1767 | }, |
| 1768 | { /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ |
| 1769 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1770 | }, |
| 1771 | { /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ |
| 1772 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1773 | }, |
| 1774 | { /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ |
| 1775 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1776 | }, |
| 1777 | { /* ARM_VCMPD, ARM_INS_VCMP: vcmp${p}.f64 $dd, $dm */ |
| 1778 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1779 | }, |
| 1780 | { /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, $dm */ |
| 1781 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1782 | }, |
| 1783 | { /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, $sm */ |
| 1784 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1785 | }, |
| 1786 | { /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, #0 */ |
| 1787 | { CS_AC_READ, 0 } |
| 1788 | }, |
| 1789 | { /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, #0 */ |
| 1790 | { CS_AC_READ, 0 } |
| 1791 | }, |
| 1792 | { /* ARM_VCMPS, ARM_INS_VCMP: vcmp${p}.f32 $sd, $sm */ |
| 1793 | { CS_AC_READ, CS_AC_READ, 0 } |
| 1794 | }, |
| 1795 | { /* ARM_VCMPZD, ARM_INS_VCMP: vcmp${p}.f64 $dd, #0 */ |
| 1796 | { CS_AC_READ, 0 } |
| 1797 | }, |
| 1798 | { /* ARM_VCMPZS, ARM_INS_VCMP: vcmp${p}.f32 $sd, #0 */ |
| 1799 | { CS_AC_READ, 0 } |
| 1800 | }, |
| 1801 | { /* ARM_VCNTd, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ |
| 1802 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1803 | }, |
| 1804 | { /* ARM_VCNTq, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ |
| 1805 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1806 | }, |
| 1807 | { /* ARM_VCVTANSD, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ |
| 1808 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1809 | }, |
| 1810 | { /* ARM_VCVTANSQ, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ |
| 1811 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1812 | }, |
| 1813 | { /* ARM_VCVTANUD, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ |
| 1814 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1815 | }, |
| 1816 | { /* ARM_VCVTANUQ, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ |
| 1817 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1818 | }, |
| 1819 | { /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta.s32.f64 $sd, $dm */ |
| 1820 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1821 | }, |
| 1822 | { /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta.s32.f32 $sd, $sm */ |
| 1823 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1824 | }, |
| 1825 | { /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta.u32.f64 $sd, $dm */ |
| 1826 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1827 | }, |
| 1828 | { /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta.u32.f32 $sd, $sm */ |
| 1829 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1830 | }, |
| 1831 | { /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb${p}.f16.f64 $sd, $dm */ |
| 1832 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1833 | }, |
| 1834 | { /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb${p}.f64.f16 $dd, $sm */ |
| 1835 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1836 | }, |
| 1837 | { /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb${p}.f32.f16 $sd, $sm */ |
| 1838 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1839 | }, |
| 1840 | { /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb${p}.f16.f32 $sd, $sm */ |
| 1841 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1842 | }, |
| 1843 | { /* ARM_VCVTDS, ARM_INS_VCVT: vcvt${p}.f64.f32 $dd, $sm */ |
| 1844 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1845 | }, |
| 1846 | { /* ARM_VCVTMNSD, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ |
| 1847 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1848 | }, |
| 1849 | { /* ARM_VCVTMNSQ, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ |
| 1850 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1851 | }, |
| 1852 | { /* ARM_VCVTMNUD, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ |
| 1853 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1854 | }, |
| 1855 | { /* ARM_VCVTMNUQ, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ |
| 1856 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1857 | }, |
| 1858 | { /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm.s32.f64 $sd, $dm */ |
| 1859 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1860 | }, |
| 1861 | { /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm.s32.f32 $sd, $sm */ |
| 1862 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1863 | }, |
| 1864 | { /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm.u32.f64 $sd, $dm */ |
| 1865 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1866 | }, |
| 1867 | { /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm.u32.f32 $sd, $sm */ |
| 1868 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1869 | }, |
| 1870 | { /* ARM_VCVTNNSD, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ |
| 1871 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1872 | }, |
| 1873 | { /* ARM_VCVTNNSQ, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ |
| 1874 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1875 | }, |
| 1876 | { /* ARM_VCVTNNUD, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ |
| 1877 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1878 | }, |
| 1879 | { /* ARM_VCVTNNUQ, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ |
| 1880 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1881 | }, |
| 1882 | { /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn.s32.f64 $sd, $dm */ |
| 1883 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1884 | }, |
| 1885 | { /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn.s32.f32 $sd, $sm */ |
| 1886 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1887 | }, |
| 1888 | { /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn.u32.f64 $sd, $dm */ |
| 1889 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1890 | }, |
| 1891 | { /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn.u32.f32 $sd, $sm */ |
| 1892 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1893 | }, |
| 1894 | { /* ARM_VCVTPNSD, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ |
| 1895 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1896 | }, |
| 1897 | { /* ARM_VCVTPNSQ, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ |
| 1898 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1899 | }, |
| 1900 | { /* ARM_VCVTPNUD, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ |
| 1901 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1902 | }, |
| 1903 | { /* ARM_VCVTPNUQ, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ |
| 1904 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1905 | }, |
| 1906 | { /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp.s32.f64 $sd, $dm */ |
| 1907 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1908 | }, |
| 1909 | { /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp.s32.f32 $sd, $sm */ |
| 1910 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1911 | }, |
| 1912 | { /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp.u32.f64 $sd, $dm */ |
| 1913 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1914 | }, |
| 1915 | { /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp.u32.f32 $sd, $sm */ |
| 1916 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1917 | }, |
| 1918 | { /* ARM_VCVTSD, ARM_INS_VCVT: vcvt${p}.f32.f64 $sd, $dm */ |
| 1919 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1920 | }, |
| 1921 | { /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt${p}.f16.f64 $sd, $dm */ |
| 1922 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1923 | }, |
| 1924 | { /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt${p}.f64.f16 $dd, $sm */ |
| 1925 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1926 | }, |
| 1927 | { /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt${p}.f32.f16 $sd, $sm */ |
| 1928 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1929 | }, |
| 1930 | { /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt${p}.f16.f32 $sd, $sm */ |
| 1931 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1932 | }, |
| 1933 | { /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt${p}.f16.f32 $vd, $vm */ |
| 1934 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1935 | }, |
| 1936 | { /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ |
| 1937 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1938 | }, |
| 1939 | { /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ |
| 1940 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1941 | }, |
| 1942 | { /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ |
| 1943 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1944 | }, |
| 1945 | { /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ |
| 1946 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1947 | }, |
| 1948 | { /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ |
| 1949 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1950 | }, |
| 1951 | { /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ |
| 1952 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1953 | }, |
| 1954 | { /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ |
| 1955 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1956 | }, |
| 1957 | { /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ |
| 1958 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1959 | }, |
| 1960 | { /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt${p}.f32.f16 $vd, $vm */ |
| 1961 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1962 | }, |
| 1963 | { /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ |
| 1964 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1965 | }, |
| 1966 | { /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ |
| 1967 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1968 | }, |
| 1969 | { /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ |
| 1970 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1971 | }, |
| 1972 | { /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ |
| 1973 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1974 | }, |
| 1975 | { /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ |
| 1976 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1977 | }, |
| 1978 | { /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ |
| 1979 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1980 | }, |
| 1981 | { /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ |
| 1982 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1983 | }, |
| 1984 | { /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ |
| 1985 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1986 | }, |
| 1987 | { /* ARM_VDIVD, ARM_INS_VDIV: vdiv${p}.f64 $dd, $dn, $dm */ |
| 1988 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1989 | }, |
| 1990 | { /* ARM_VDIVS, ARM_INS_VDIV: vdiv${p}.f32 $sd, $sn, $sm */ |
| 1991 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 1992 | }, |
| 1993 | { /* ARM_VDUP16d, ARM_INS_VDUP: vdup${p}.16 $v, $r */ |
| 1994 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1995 | }, |
| 1996 | { /* ARM_VDUP16q, ARM_INS_VDUP: vdup${p}.16 $v, $r */ |
| 1997 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 1998 | }, |
| 1999 | { /* ARM_VDUP32d, ARM_INS_VDUP: vdup${p}.32 $v, $r */ |
| 2000 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2001 | }, |
| 2002 | { /* ARM_VDUP32q, ARM_INS_VDUP: vdup${p}.32 $v, $r */ |
| 2003 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2004 | }, |
| 2005 | { /* ARM_VDUP8d, ARM_INS_VDUP: vdup${p}.8 $v, $r */ |
| 2006 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2007 | }, |
| 2008 | { /* ARM_VDUP8q, ARM_INS_VDUP: vdup${p}.8 $v, $r */ |
| 2009 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2010 | }, |
| 2011 | { /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ |
| 2012 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2013 | }, |
| 2014 | { /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ |
| 2015 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2016 | }, |
| 2017 | { /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ |
| 2018 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2019 | }, |
| 2020 | { /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ |
| 2021 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2022 | }, |
| 2023 | { /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ |
| 2024 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2025 | }, |
| 2026 | { /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ |
| 2027 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2028 | }, |
| 2029 | { /* ARM_VEORd, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ |
| 2030 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2031 | }, |
| 2032 | { /* ARM_VEORq, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ |
| 2033 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2034 | }, |
| 2035 | { /* ARM_VEXTd16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ |
| 2036 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2037 | }, |
| 2038 | { /* ARM_VEXTd32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ |
| 2039 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2040 | }, |
| 2041 | { /* ARM_VEXTd8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ |
| 2042 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2043 | }, |
| 2044 | { /* ARM_VEXTq16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ |
| 2045 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2046 | }, |
| 2047 | { /* ARM_VEXTq32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ |
| 2048 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2049 | }, |
| 2050 | { /* ARM_VEXTq64, ARM_INS_VEXT: vext${p}.64 $vd, $vn, $vm, $index */ |
| 2051 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2052 | }, |
| 2053 | { /* ARM_VEXTq8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ |
| 2054 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2055 | }, |
| 2056 | { /* ARM_VFMAD, ARM_INS_VFMA: vfma${p}.f64 $dd, $dn, $dm */ |
| 2057 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2058 | }, |
| 2059 | { /* ARM_VFMAS, ARM_INS_VFMA: vfma${p}.f32 $sd, $sn, $sm */ |
| 2060 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2061 | }, |
| 2062 | { /* ARM_VFMAfd, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ |
| 2063 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2064 | }, |
| 2065 | { /* ARM_VFMAfq, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ |
| 2066 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2067 | }, |
| 2068 | { /* ARM_VFMSD, ARM_INS_VFMS: vfms${p}.f64 $dd, $dn, $dm */ |
| 2069 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2070 | }, |
| 2071 | { /* ARM_VFMSS, ARM_INS_VFMS: vfms${p}.f32 $sd, $sn, $sm */ |
| 2072 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2073 | }, |
| 2074 | { /* ARM_VFMSfd, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ |
| 2075 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2076 | }, |
| 2077 | { /* ARM_VFMSfq, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ |
| 2078 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2079 | }, |
| 2080 | { /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma${p}.f64 $dd, $dn, $dm */ |
| 2081 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2082 | }, |
| 2083 | { /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma${p}.f32 $sd, $sn, $sm */ |
| 2084 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2085 | }, |
| 2086 | { /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms${p}.f64 $dd, $dn, $dm */ |
| 2087 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2088 | }, |
| 2089 | { /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms${p}.f32 $sd, $sn, $sm */ |
| 2090 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2091 | }, |
| 2092 | { /* ARM_VGETLNi32, ARM_INS_VMOV: vmov${p}.32 $r, $v$lane */ |
| 2093 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2094 | }, |
| 2095 | { /* ARM_VGETLNs16, ARM_INS_VMOV: vmov${p}.s16 $r, $v$lane */ |
| 2096 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2097 | }, |
| 2098 | { /* ARM_VGETLNs8, ARM_INS_VMOV: vmov${p}.s8 $r, $v$lane */ |
| 2099 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2100 | }, |
| 2101 | { /* ARM_VGETLNu16, ARM_INS_VMOV: vmov${p}.u16 $r, $v$lane */ |
| 2102 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2103 | }, |
| 2104 | { /* ARM_VGETLNu8, ARM_INS_VMOV: vmov${p}.u8 $r, $v$lane */ |
| 2105 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2106 | }, |
| 2107 | { /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ |
| 2108 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2109 | }, |
| 2110 | { /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ |
| 2111 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2112 | }, |
| 2113 | { /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ |
| 2114 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2115 | }, |
| 2116 | { /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ |
| 2117 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2118 | }, |
| 2119 | { /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ |
| 2120 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2121 | }, |
| 2122 | { /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ |
| 2123 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2124 | }, |
| 2125 | { /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ |
| 2126 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2127 | }, |
| 2128 | { /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ |
| 2129 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2130 | }, |
| 2131 | { /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ |
| 2132 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2133 | }, |
| 2134 | { /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ |
| 2135 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2136 | }, |
| 2137 | { /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ |
| 2138 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2139 | }, |
| 2140 | { /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ |
| 2141 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2142 | }, |
| 2143 | { /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ |
| 2144 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2145 | }, |
| 2146 | { /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ |
| 2147 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2148 | }, |
| 2149 | { /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ |
| 2150 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2151 | }, |
| 2152 | { /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ |
| 2153 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2154 | }, |
| 2155 | { /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ |
| 2156 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2157 | }, |
| 2158 | { /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ |
| 2159 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2160 | }, |
| 2161 | { /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ |
| 2162 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2163 | }, |
| 2164 | { /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ |
| 2165 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2166 | }, |
| 2167 | { /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ |
| 2168 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2169 | }, |
| 2170 | { /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ |
| 2171 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2172 | }, |
| 2173 | { /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ |
| 2174 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2175 | }, |
| 2176 | { /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ |
| 2177 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2178 | }, |
| 2179 | { /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| 2180 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2181 | }, |
| 2182 | { /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| 2183 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2184 | }, |
| 2185 | { /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| 2186 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2187 | }, |
| 2188 | { /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| 2189 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2190 | }, |
| 2191 | { /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| 2192 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2193 | }, |
| 2194 | { /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| 2195 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2196 | }, |
| 2197 | { /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| 2198 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2199 | }, |
| 2200 | { /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| 2201 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2202 | }, |
| 2203 | { /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| 2204 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2205 | }, |
| 2206 | { /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| 2207 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2208 | }, |
| 2209 | { /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| 2210 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2211 | }, |
| 2212 | { /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| 2213 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2214 | }, |
| 2215 | { /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| 2216 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2217 | }, |
| 2218 | { /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| 2219 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2220 | }, |
| 2221 | { /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| 2222 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2223 | }, |
| 2224 | { /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| 2225 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2226 | }, |
| 2227 | { /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| 2228 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2229 | }, |
| 2230 | { /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| 2231 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2232 | }, |
| 2233 | { /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn */ |
| 2234 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2235 | }, |
| 2236 | { /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn$rm */ |
| 2237 | { CS_AC_WRITE, 0 } |
| 2238 | }, |
| 2239 | { /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn */ |
| 2240 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 2241 | }, |
| 2242 | { /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn$rm */ |
| 2243 | { CS_AC_WRITE, 0 } |
| 2244 | }, |
| 2245 | { /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn */ |
| 2246 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2247 | }, |
| 2248 | { /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn$rm */ |
| 2249 | { CS_AC_WRITE, 0 } |
| 2250 | }, |
| 2251 | { /* ARM_VLD1d16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| 2252 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2253 | }, |
| 2254 | { /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| 2255 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2256 | }, |
| 2257 | { /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| 2258 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2259 | }, |
| 2260 | { /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| 2261 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2262 | }, |
| 2263 | { /* ARM_VLD1d16T, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| 2264 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2265 | }, |
| 2266 | { /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| 2267 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2268 | }, |
| 2269 | { /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| 2270 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2271 | }, |
| 2272 | { /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| 2273 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2274 | }, |
| 2275 | { /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| 2276 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2277 | }, |
| 2278 | { /* ARM_VLD1d32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| 2279 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2280 | }, |
| 2281 | { /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| 2282 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2283 | }, |
| 2284 | { /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| 2285 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2286 | }, |
| 2287 | { /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| 2288 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2289 | }, |
| 2290 | { /* ARM_VLD1d32T, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| 2291 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2292 | }, |
| 2293 | { /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| 2294 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2295 | }, |
| 2296 | { /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| 2297 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2298 | }, |
| 2299 | { /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| 2300 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2301 | }, |
| 2302 | { /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| 2303 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2304 | }, |
| 2305 | { /* ARM_VLD1d64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ |
| 2306 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2307 | }, |
| 2308 | { /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ |
| 2309 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2310 | }, |
| 2311 | { /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ |
| 2312 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2313 | }, |
| 2314 | { /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ |
| 2315 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2316 | }, |
| 2317 | { /* ARM_VLD1d64T, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ |
| 2318 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2319 | }, |
| 2320 | { /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ |
| 2321 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2322 | }, |
| 2323 | { /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ |
| 2324 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2325 | }, |
| 2326 | { /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ |
| 2327 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2328 | }, |
| 2329 | { /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ |
| 2330 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2331 | }, |
| 2332 | { /* ARM_VLD1d8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| 2333 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2334 | }, |
| 2335 | { /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| 2336 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2337 | }, |
| 2338 | { /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| 2339 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2340 | }, |
| 2341 | { /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| 2342 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2343 | }, |
| 2344 | { /* ARM_VLD1d8T, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| 2345 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2346 | }, |
| 2347 | { /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| 2348 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2349 | }, |
| 2350 | { /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| 2351 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2352 | }, |
| 2353 | { /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| 2354 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2355 | }, |
| 2356 | { /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| 2357 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2358 | }, |
| 2359 | { /* ARM_VLD1q16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ |
| 2360 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2361 | }, |
| 2362 | { /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ |
| 2363 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2364 | }, |
| 2365 | { /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ |
| 2366 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2367 | }, |
| 2368 | { /* ARM_VLD1q32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ |
| 2369 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2370 | }, |
| 2371 | { /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ |
| 2372 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2373 | }, |
| 2374 | { /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ |
| 2375 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2376 | }, |
| 2377 | { /* ARM_VLD1q64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ |
| 2378 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2379 | }, |
| 2380 | { /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ |
| 2381 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2382 | }, |
| 2383 | { /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ |
| 2384 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2385 | }, |
| 2386 | { /* ARM_VLD1q8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ |
| 2387 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2388 | }, |
| 2389 | { /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ |
| 2390 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2391 | }, |
| 2392 | { /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ |
| 2393 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2394 | }, |
| 2395 | { /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| 2396 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2397 | }, |
| 2398 | { /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| 2399 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2400 | }, |
| 2401 | { /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| 2402 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2403 | }, |
| 2404 | { /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| 2405 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2406 | }, |
| 2407 | { /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| 2408 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2409 | }, |
| 2410 | { /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| 2411 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2412 | }, |
| 2413 | { /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| 2414 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2415 | }, |
| 2416 | { /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| 2417 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2418 | }, |
| 2419 | { /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| 2420 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2421 | }, |
| 2422 | { /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| 2423 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2424 | }, |
| 2425 | { /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| 2426 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2427 | }, |
| 2428 | { /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| 2429 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2430 | }, |
| 2431 | { /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| 2432 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2433 | }, |
| 2434 | { /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| 2435 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2436 | }, |
| 2437 | { /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| 2438 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2439 | }, |
| 2440 | { /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| 2441 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2442 | }, |
| 2443 | { /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| 2444 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2445 | }, |
| 2446 | { /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| 2447 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2448 | }, |
| 2449 | { /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| 2450 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2451 | }, |
| 2452 | { /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| 2453 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2454 | }, |
| 2455 | { /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| 2456 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2457 | }, |
| 2458 | { /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| 2459 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2460 | }, |
| 2461 | { /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| 2462 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2463 | }, |
| 2464 | { /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| 2465 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2466 | }, |
| 2467 | { /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| 2468 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2469 | }, |
| 2470 | { /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| 2471 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2472 | }, |
| 2473 | { /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ |
| 2474 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2475 | }, |
| 2476 | { /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ |
| 2477 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2478 | }, |
| 2479 | { /* ARM_VLD2b16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| 2480 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2481 | }, |
| 2482 | { /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| 2483 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2484 | }, |
| 2485 | { /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| 2486 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2487 | }, |
| 2488 | { /* ARM_VLD2b32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| 2489 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2490 | }, |
| 2491 | { /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| 2492 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2493 | }, |
| 2494 | { /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| 2495 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2496 | }, |
| 2497 | { /* ARM_VLD2b8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| 2498 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2499 | }, |
| 2500 | { /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| 2501 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2502 | }, |
| 2503 | { /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| 2504 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2505 | }, |
| 2506 | { /* ARM_VLD2d16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| 2507 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2508 | }, |
| 2509 | { /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| 2510 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2511 | }, |
| 2512 | { /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| 2513 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2514 | }, |
| 2515 | { /* ARM_VLD2d32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| 2516 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2517 | }, |
| 2518 | { /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| 2519 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2520 | }, |
| 2521 | { /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| 2522 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2523 | }, |
| 2524 | { /* ARM_VLD2d8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| 2525 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2526 | }, |
| 2527 | { /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| 2528 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2529 | }, |
| 2530 | { /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| 2531 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2532 | }, |
| 2533 | { /* ARM_VLD2q16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ |
| 2534 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2535 | }, |
| 2536 | { /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ |
| 2537 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2538 | }, |
| 2539 | { /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ |
| 2540 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2541 | }, |
| 2542 | { /* ARM_VLD2q32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ |
| 2543 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2544 | }, |
| 2545 | { /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ |
| 2546 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2547 | }, |
| 2548 | { /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ |
| 2549 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2550 | }, |
| 2551 | { /* ARM_VLD2q8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ |
| 2552 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2553 | }, |
| 2554 | { /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ |
| 2555 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 2556 | }, |
| 2557 | { /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ |
| 2558 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2559 | }, |
| 2560 | { /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| 2561 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2562 | }, |
| 2563 | { /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| 2564 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2565 | }, |
| 2566 | { /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| 2567 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2568 | }, |
| 2569 | { /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| 2570 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2571 | }, |
| 2572 | { /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| 2573 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2574 | }, |
| 2575 | { /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| 2576 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2577 | }, |
| 2578 | { /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| 2579 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2580 | }, |
| 2581 | { /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| 2582 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2583 | }, |
| 2584 | { /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| 2585 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2586 | }, |
| 2587 | { /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| 2588 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2589 | }, |
| 2590 | { /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ |
| 2591 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2592 | }, |
| 2593 | { /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ |
| 2594 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2595 | }, |
| 2596 | { /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| 2597 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2598 | }, |
| 2599 | { /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| 2600 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2601 | }, |
| 2602 | { /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| 2603 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2604 | }, |
| 2605 | { /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| 2606 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2607 | }, |
| 2608 | { /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| 2609 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2610 | }, |
| 2611 | { /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| 2612 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2613 | }, |
| 2614 | { /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| 2615 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2616 | }, |
| 2617 | { /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| 2618 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2619 | }, |
| 2620 | { /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ |
| 2621 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2622 | }, |
| 2623 | { /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ |
| 2624 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2625 | }, |
| 2626 | { /* ARM_VLD3d16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ |
| 2627 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2628 | }, |
| 2629 | { /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| 2630 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2631 | }, |
| 2632 | { /* ARM_VLD3d32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ |
| 2633 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2634 | }, |
| 2635 | { /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| 2636 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2637 | }, |
| 2638 | { /* ARM_VLD3d8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ |
| 2639 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2640 | }, |
| 2641 | { /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| 2642 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2643 | }, |
| 2644 | { /* ARM_VLD3q16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ |
| 2645 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2646 | }, |
| 2647 | { /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| 2648 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2649 | }, |
| 2650 | { /* ARM_VLD3q32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ |
| 2651 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2652 | }, |
| 2653 | { /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| 2654 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2655 | }, |
| 2656 | { /* ARM_VLD3q8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ |
| 2657 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2658 | }, |
| 2659 | { /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ |
| 2660 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2661 | }, |
| 2662 | { /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| 2663 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2664 | }, |
| 2665 | { /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| 2666 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2667 | }, |
| 2668 | { /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| 2669 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2670 | }, |
| 2671 | { /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| 2672 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2673 | }, |
| 2674 | { /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| 2675 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2676 | }, |
| 2677 | { /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| 2678 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2679 | }, |
| 2680 | { /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| 2681 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2682 | }, |
| 2683 | { /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| 2684 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2685 | }, |
| 2686 | { /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| 2687 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2688 | }, |
| 2689 | { /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| 2690 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2691 | }, |
| 2692 | { /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ |
| 2693 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2694 | }, |
| 2695 | { /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ |
| 2696 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2697 | }, |
| 2698 | { /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| 2699 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2700 | }, |
| 2701 | { /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| 2702 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2703 | }, |
| 2704 | { /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| 2705 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2706 | }, |
| 2707 | { /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| 2708 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2709 | }, |
| 2710 | { /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| 2711 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2712 | }, |
| 2713 | { /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| 2714 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2715 | }, |
| 2716 | { /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| 2717 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2718 | }, |
| 2719 | { /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| 2720 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2721 | }, |
| 2722 | { /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ |
| 2723 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2724 | }, |
| 2725 | { /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ |
| 2726 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2727 | }, |
| 2728 | { /* ARM_VLD4d16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| 2729 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2730 | }, |
| 2731 | { /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| 2732 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2733 | }, |
| 2734 | { /* ARM_VLD4d32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| 2735 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2736 | }, |
| 2737 | { /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| 2738 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2739 | }, |
| 2740 | { /* ARM_VLD4d8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| 2741 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2742 | }, |
| 2743 | { /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| 2744 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2745 | }, |
| 2746 | { /* ARM_VLD4q16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| 2747 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2748 | }, |
| 2749 | { /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| 2750 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2751 | }, |
| 2752 | { /* ARM_VLD4q32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| 2753 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2754 | }, |
| 2755 | { /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| 2756 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2757 | }, |
| 2758 | { /* ARM_VLD4q8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ |
| 2759 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 2760 | }, |
| 2761 | { /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ |
| 2762 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 2763 | }, |
| 2764 | { /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ |
| 2765 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 2766 | }, |
| 2767 | { /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ |
| 2768 | { CS_AC_READ, 0 } |
| 2769 | }, |
| 2770 | { /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ |
| 2771 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 2772 | }, |
| 2773 | { /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ |
| 2774 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 2775 | }, |
| 2776 | { /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ |
| 2777 | { CS_AC_READ, 0 } |
| 2778 | }, |
| 2779 | { /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ |
| 2780 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 2781 | }, |
| 2782 | { /* ARM_VLDRD, ARM_INS_VLDR: vldr${p} $dd, $addr */ |
| 2783 | { CS_AC_WRITE, 0 } |
| 2784 | }, |
| 2785 | { /* ARM_VLDRS, ARM_INS_VLDR: vldr${p} $sd, $addr */ |
| 2786 | { CS_AC_WRITE, 0 } |
| 2787 | }, |
| 2788 | { /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm.f64 $dd, $dn, $dm */ |
| 2789 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2790 | }, |
| 2791 | { /* ARM_VMAXNMND, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ |
| 2792 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2793 | }, |
| 2794 | { /* ARM_VMAXNMNQ, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ |
| 2795 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2796 | }, |
| 2797 | { /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm.f32 $sd, $sn, $sm */ |
| 2798 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2799 | }, |
| 2800 | { /* ARM_VMAXfd, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ |
| 2801 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2802 | }, |
| 2803 | { /* ARM_VMAXfq, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ |
| 2804 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2805 | }, |
| 2806 | { /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ |
| 2807 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2808 | }, |
| 2809 | { /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ |
| 2810 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2811 | }, |
| 2812 | { /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ |
| 2813 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2814 | }, |
| 2815 | { /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ |
| 2816 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2817 | }, |
| 2818 | { /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ |
| 2819 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2820 | }, |
| 2821 | { /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ |
| 2822 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2823 | }, |
| 2824 | { /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ |
| 2825 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2826 | }, |
| 2827 | { /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ |
| 2828 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2829 | }, |
| 2830 | { /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ |
| 2831 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2832 | }, |
| 2833 | { /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ |
| 2834 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2835 | }, |
| 2836 | { /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ |
| 2837 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2838 | }, |
| 2839 | { /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ |
| 2840 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2841 | }, |
| 2842 | { /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm.f64 $dd, $dn, $dm */ |
| 2843 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2844 | }, |
| 2845 | { /* ARM_VMINNMND, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ |
| 2846 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2847 | }, |
| 2848 | { /* ARM_VMINNMNQ, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ |
| 2849 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2850 | }, |
| 2851 | { /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm.f32 $sd, $sn, $sm */ |
| 2852 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2853 | }, |
| 2854 | { /* ARM_VMINfd, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ |
| 2855 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2856 | }, |
| 2857 | { /* ARM_VMINfq, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ |
| 2858 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2859 | }, |
| 2860 | { /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ |
| 2861 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2862 | }, |
| 2863 | { /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ |
| 2864 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2865 | }, |
| 2866 | { /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ |
| 2867 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2868 | }, |
| 2869 | { /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ |
| 2870 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2871 | }, |
| 2872 | { /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ |
| 2873 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2874 | }, |
| 2875 | { /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ |
| 2876 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2877 | }, |
| 2878 | { /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ |
| 2879 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2880 | }, |
| 2881 | { /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ |
| 2882 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2883 | }, |
| 2884 | { /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ |
| 2885 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2886 | }, |
| 2887 | { /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ |
| 2888 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2889 | }, |
| 2890 | { /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ |
| 2891 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2892 | }, |
| 2893 | { /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ |
| 2894 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2895 | }, |
| 2896 | { /* ARM_VMLAD, ARM_INS_VMLA: vmla${p}.f64 $dd, $dn, $dm */ |
| 2897 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2898 | }, |
| 2899 | { /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm$lane */ |
| 2900 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2901 | }, |
| 2902 | { /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm$lane */ |
| 2903 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2904 | }, |
| 2905 | { /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm$lane */ |
| 2906 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2907 | }, |
| 2908 | { /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm$lane */ |
| 2909 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2910 | }, |
| 2911 | { /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm */ |
| 2912 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2913 | }, |
| 2914 | { /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm */ |
| 2915 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2916 | }, |
| 2917 | { /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal${p}.s8 $vd, $vn, $vm */ |
| 2918 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2919 | }, |
| 2920 | { /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm */ |
| 2921 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2922 | }, |
| 2923 | { /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm */ |
| 2924 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2925 | }, |
| 2926 | { /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal${p}.u8 $vd, $vn, $vm */ |
| 2927 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2928 | }, |
| 2929 | { /* ARM_VMLAS, ARM_INS_VMLA: vmla${p}.f32 $sd, $sn, $sm */ |
| 2930 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2931 | }, |
| 2932 | { /* ARM_VMLAfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ |
| 2933 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2934 | }, |
| 2935 | { /* ARM_VMLAfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ |
| 2936 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2937 | }, |
| 2938 | { /* ARM_VMLAslfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ |
| 2939 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2940 | }, |
| 2941 | { /* ARM_VMLAslfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ |
| 2942 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2943 | }, |
| 2944 | { /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ |
| 2945 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2946 | }, |
| 2947 | { /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ |
| 2948 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2949 | }, |
| 2950 | { /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ |
| 2951 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2952 | }, |
| 2953 | { /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ |
| 2954 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2955 | }, |
| 2956 | { /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ |
| 2957 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2958 | }, |
| 2959 | { /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ |
| 2960 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2961 | }, |
| 2962 | { /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ |
| 2963 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2964 | }, |
| 2965 | { /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ |
| 2966 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2967 | }, |
| 2968 | { /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ |
| 2969 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2970 | }, |
| 2971 | { /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ |
| 2972 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2973 | }, |
| 2974 | { /* ARM_VMLSD, ARM_INS_VMLS: vmls${p}.f64 $dd, $dn, $dm */ |
| 2975 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2976 | }, |
| 2977 | { /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm$lane */ |
| 2978 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2979 | }, |
| 2980 | { /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm$lane */ |
| 2981 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2982 | }, |
| 2983 | { /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm$lane */ |
| 2984 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2985 | }, |
| 2986 | { /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm$lane */ |
| 2987 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 2988 | }, |
| 2989 | { /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm */ |
| 2990 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2991 | }, |
| 2992 | { /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm */ |
| 2993 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2994 | }, |
| 2995 | { /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl${p}.s8 $vd, $vn, $vm */ |
| 2996 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 2997 | }, |
| 2998 | { /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm */ |
| 2999 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3000 | }, |
| 3001 | { /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm */ |
| 3002 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3003 | }, |
| 3004 | { /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl${p}.u8 $vd, $vn, $vm */ |
| 3005 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3006 | }, |
| 3007 | { /* ARM_VMLSS, ARM_INS_VMLS: vmls${p}.f32 $sd, $sn, $sm */ |
| 3008 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3009 | }, |
| 3010 | { /* ARM_VMLSfd, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm */ |
| 3011 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3012 | }, |
| 3013 | { /* ARM_VMLSfq, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm */ |
| 3014 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3015 | }, |
| 3016 | { /* ARM_VMLSslfd, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm$lane */ |
| 3017 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3018 | }, |
| 3019 | { /* ARM_VMLSslfq, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm$lane */ |
| 3020 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3021 | }, |
| 3022 | { /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm$lane */ |
| 3023 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3024 | }, |
| 3025 | { /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm$lane */ |
| 3026 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3027 | }, |
| 3028 | { /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm$lane */ |
| 3029 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3030 | }, |
| 3031 | { /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm$lane */ |
| 3032 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3033 | }, |
| 3034 | { /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls${p}.i8 $vd, $vn, $vm */ |
| 3035 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3036 | }, |
| 3037 | { /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm */ |
| 3038 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3039 | }, |
| 3040 | { /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm */ |
| 3041 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3042 | }, |
| 3043 | { /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm */ |
| 3044 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3045 | }, |
| 3046 | { /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm */ |
| 3047 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3048 | }, |
| 3049 | { /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls${p}.i8 $vd, $vn, $vm */ |
| 3050 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3051 | }, |
| 3052 | { /* ARM_VMOVD, ARM_INS_VMOV: vmov${p}.f64 $dd, $dm */ |
| 3053 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3054 | }, |
| 3055 | { /* ARM_VMOVDRR, ARM_INS_VMOV: vmov${p} $dm, $rt, $rt2 */ |
| 3056 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3057 | }, |
| 3058 | { /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl${p}.s32 $vd, $vm */ |
| 3059 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3060 | }, |
| 3061 | { /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl${p}.s16 $vd, $vm */ |
| 3062 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3063 | }, |
| 3064 | { /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl${p}.s8 $vd, $vm */ |
| 3065 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3066 | }, |
| 3067 | { /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl${p}.u32 $vd, $vm */ |
| 3068 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3069 | }, |
| 3070 | { /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl${p}.u16 $vd, $vm */ |
| 3071 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3072 | }, |
| 3073 | { /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl${p}.u8 $vd, $vm */ |
| 3074 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3075 | }, |
| 3076 | { /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn${p}.i64 $vd, $vm */ |
| 3077 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3078 | }, |
| 3079 | { /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn${p}.i32 $vd, $vm */ |
| 3080 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3081 | }, |
| 3082 | { /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn${p}.i16 $vd, $vm */ |
| 3083 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3084 | }, |
| 3085 | { /* ARM_VMOVRRD, ARM_INS_VMOV: vmov${p} $rt, $rt2, $dm */ |
| 3086 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 3087 | }, |
| 3088 | { /* ARM_VMOVRRS, ARM_INS_VMOV: vmov${p} $rt, $rt2, $src1, $src2 */ |
| 3089 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3090 | }, |
| 3091 | { /* ARM_VMOVRS, ARM_INS_VMOV: vmov${p} $rt, $sn */ |
| 3092 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3093 | }, |
| 3094 | { /* ARM_VMOVS, ARM_INS_VMOV: vmov${p}.f32 $sd, $sm */ |
| 3095 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3096 | }, |
| 3097 | { /* ARM_VMOVSR, ARM_INS_VMOV: vmov${p} $sn, $rt */ |
| 3098 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3099 | }, |
| 3100 | { /* ARM_VMOVSRR, ARM_INS_VMOV: vmov${p} $dst1, $dst2, $src1, $src2 */ |
| 3101 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3102 | }, |
| 3103 | { /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov${p}.i8 $vd, $simm */ |
| 3104 | { CS_AC_WRITE, 0 } |
| 3105 | }, |
| 3106 | { /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov${p}.i64 $vd, $simm */ |
| 3107 | { CS_AC_WRITE, 0 } |
| 3108 | }, |
| 3109 | { /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov${p}.f32 $vd, $simm */ |
| 3110 | { CS_AC_WRITE, 0 } |
| 3111 | }, |
| 3112 | { /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov${p}.i32 $vd, $simm */ |
| 3113 | { CS_AC_WRITE, 0 } |
| 3114 | }, |
| 3115 | { /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov${p}.i64 $vd, $simm */ |
| 3116 | { CS_AC_WRITE, 0 } |
| 3117 | }, |
| 3118 | { /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov${p}.f32 $vd, $simm */ |
| 3119 | { CS_AC_WRITE, 0 } |
| 3120 | }, |
| 3121 | { /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov${p}.i16 $vd, $simm */ |
| 3122 | { CS_AC_WRITE, 0 } |
| 3123 | }, |
| 3124 | { /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov${p}.i32 $vd, $simm */ |
| 3125 | { CS_AC_WRITE, 0 } |
| 3126 | }, |
| 3127 | { /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov${p}.i16 $vd, $simm */ |
| 3128 | { CS_AC_WRITE, 0 } |
| 3129 | }, |
| 3130 | { /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov${p}.i8 $vd, $simm */ |
| 3131 | { CS_AC_WRITE, 0 } |
| 3132 | }, |
| 3133 | { /* ARM_VMRS, ARM_INS_VMRS: vmrs${p} $rt, fpscr */ |
| 3134 | { CS_AC_WRITE, 0 } |
| 3135 | }, |
| 3136 | { /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs${p} $rt, fpexc */ |
| 3137 | { CS_AC_WRITE, 0 } |
| 3138 | }, |
| 3139 | { /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs${p} $rt, fpinst */ |
| 3140 | { CS_AC_WRITE, 0 } |
| 3141 | }, |
| 3142 | { /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs${p} $rt, fpinst2 */ |
| 3143 | { CS_AC_WRITE, 0 } |
| 3144 | }, |
| 3145 | { /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs${p} $rt, fpsid */ |
| 3146 | { CS_AC_WRITE, 0 } |
| 3147 | }, |
| 3148 | { /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs${p} $rt, mvfr0 */ |
| 3149 | { CS_AC_WRITE, 0 } |
| 3150 | }, |
| 3151 | { /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs${p} $rt, mvfr1 */ |
| 3152 | { CS_AC_WRITE, 0 } |
| 3153 | }, |
| 3154 | { /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs${p} $rt, mvfr2 */ |
| 3155 | { CS_AC_WRITE, 0 } |
| 3156 | }, |
| 3157 | { /* ARM_VMSR, ARM_INS_VMSR: vmsr${p} fpscr, $src */ |
| 3158 | { CS_AC_IGNORE, CS_AC_READ, 0 } |
| 3159 | }, |
| 3160 | { /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr${p} fpexc, $src */ |
| 3161 | { CS_AC_IGNORE, CS_AC_READ, 0 } |
| 3162 | }, |
| 3163 | { /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr${p} fpinst, $src */ |
| 3164 | { CS_AC_IGNORE, CS_AC_READ, 0 } |
| 3165 | }, |
| 3166 | { /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr${p} fpinst2, $src */ |
| 3167 | { CS_AC_IGNORE, CS_AC_READ, 0 } |
| 3168 | }, |
| 3169 | { /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr${p} fpsid, $src */ |
| 3170 | { CS_AC_IGNORE, CS_AC_READ, 0 } |
| 3171 | }, |
| 3172 | { /* ARM_VMULD, ARM_INS_VMUL: vmul${p}.f64 $dd, $dn, $dm */ |
| 3173 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3174 | }, |
| 3175 | { /* ARM_VMULLp64, ARM_INS_VMULL: vmull.p64 $vd, $vn, $vm */ |
| 3176 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3177 | }, |
| 3178 | { /* ARM_VMULLp8, ARM_INS_VMULL: vmull${p}.p8 $vd, $vn, $vm */ |
| 3179 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3180 | }, |
| 3181 | { /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull${p}.s32 $vd, $vn, $vm$lane */ |
| 3182 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3183 | }, |
| 3184 | { /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull${p}.s16 $vd, $vn, $vm$lane */ |
| 3185 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3186 | }, |
| 3187 | { /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull${p}.u32 $vd, $vn, $vm$lane */ |
| 3188 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3189 | }, |
| 3190 | { /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull${p}.u16 $vd, $vn, $vm$lane */ |
| 3191 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3192 | }, |
| 3193 | { /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull${p}.s32 $vd, $vn, $vm */ |
| 3194 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3195 | }, |
| 3196 | { /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull${p}.s16 $vd, $vn, $vm */ |
| 3197 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3198 | }, |
| 3199 | { /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull${p}.s8 $vd, $vn, $vm */ |
| 3200 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3201 | }, |
| 3202 | { /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull${p}.u32 $vd, $vn, $vm */ |
| 3203 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3204 | }, |
| 3205 | { /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull${p}.u16 $vd, $vn, $vm */ |
| 3206 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3207 | }, |
| 3208 | { /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull${p}.u8 $vd, $vn, $vm */ |
| 3209 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3210 | }, |
| 3211 | { /* ARM_VMULS, ARM_INS_VMUL: vmul${p}.f32 $sd, $sn, $sm */ |
| 3212 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3213 | }, |
| 3214 | { /* ARM_VMULfd, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm */ |
| 3215 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3216 | }, |
| 3217 | { /* ARM_VMULfq, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm */ |
| 3218 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3219 | }, |
| 3220 | { /* ARM_VMULpd, ARM_INS_VMUL: vmul${p}.p8 $vd, $vn, $vm */ |
| 3221 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3222 | }, |
| 3223 | { /* ARM_VMULpq, ARM_INS_VMUL: vmul${p}.p8 $vd, $vn, $vm */ |
| 3224 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3225 | }, |
| 3226 | { /* ARM_VMULslfd, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm$lane */ |
| 3227 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3228 | }, |
| 3229 | { /* ARM_VMULslfq, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm$lane */ |
| 3230 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3231 | }, |
| 3232 | { /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm$lane */ |
| 3233 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3234 | }, |
| 3235 | { /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm$lane */ |
| 3236 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3237 | }, |
| 3238 | { /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm$lane */ |
| 3239 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3240 | }, |
| 3241 | { /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm$lane */ |
| 3242 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3243 | }, |
| 3244 | { /* ARM_VMULv16i8, ARM_INS_VMUL: vmul${p}.i8 $vd, $vn, $vm */ |
| 3245 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3246 | }, |
| 3247 | { /* ARM_VMULv2i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm */ |
| 3248 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3249 | }, |
| 3250 | { /* ARM_VMULv4i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm */ |
| 3251 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3252 | }, |
| 3253 | { /* ARM_VMULv4i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm */ |
| 3254 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3255 | }, |
| 3256 | { /* ARM_VMULv8i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm */ |
| 3257 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3258 | }, |
| 3259 | { /* ARM_VMULv8i8, ARM_INS_VMUL: vmul${p}.i8 $vd, $vn, $vm */ |
| 3260 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3261 | }, |
| 3262 | { /* ARM_VMVNd, ARM_INS_VMVN: vmvn${p} $vd, $vm */ |
| 3263 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3264 | }, |
| 3265 | { /* ARM_VMVNq, ARM_INS_VMVN: vmvn${p} $vd, $vm */ |
| 3266 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3267 | }, |
| 3268 | { /* ARM_VMVNv2i32, ARM_INS_VMVN: vmvn${p}.i32 $vd, $simm */ |
| 3269 | { CS_AC_WRITE, 0 } |
| 3270 | }, |
| 3271 | { /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn${p}.i16 $vd, $simm */ |
| 3272 | { CS_AC_WRITE, 0 } |
| 3273 | }, |
| 3274 | { /* ARM_VMVNv4i32, ARM_INS_VMVN: vmvn${p}.i32 $vd, $simm */ |
| 3275 | { CS_AC_WRITE, 0 } |
| 3276 | }, |
| 3277 | { /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn${p}.i16 $vd, $simm */ |
| 3278 | { CS_AC_WRITE, 0 } |
| 3279 | }, |
| 3280 | { /* ARM_VNEGD, ARM_INS_VNEG: vneg${p}.f64 $dd, $dm */ |
| 3281 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3282 | }, |
| 3283 | { /* ARM_VNEGS, ARM_INS_VNEG: vneg${p}.f32 $sd, $sm */ |
| 3284 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3285 | }, |
| 3286 | { /* ARM_VNEGf32q, ARM_INS_VNEG: vneg${p}.f32 $vd, $vm */ |
| 3287 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3288 | }, |
| 3289 | { /* ARM_VNEGfd, ARM_INS_VNEG: vneg${p}.f32 $vd, $vm */ |
| 3290 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3291 | }, |
| 3292 | { /* ARM_VNEGs16d, ARM_INS_VNEG: vneg${p}.s16 $vd, $vm */ |
| 3293 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3294 | }, |
| 3295 | { /* ARM_VNEGs16q, ARM_INS_VNEG: vneg${p}.s16 $vd, $vm */ |
| 3296 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3297 | }, |
| 3298 | { /* ARM_VNEGs32d, ARM_INS_VNEG: vneg${p}.s32 $vd, $vm */ |
| 3299 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3300 | }, |
| 3301 | { /* ARM_VNEGs32q, ARM_INS_VNEG: vneg${p}.s32 $vd, $vm */ |
| 3302 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3303 | }, |
| 3304 | { /* ARM_VNEGs8d, ARM_INS_VNEG: vneg${p}.s8 $vd, $vm */ |
| 3305 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3306 | }, |
| 3307 | { /* ARM_VNEGs8q, ARM_INS_VNEG: vneg${p}.s8 $vd, $vm */ |
| 3308 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3309 | }, |
| 3310 | { /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla${p}.f64 $dd, $dn, $dm */ |
| 3311 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3312 | }, |
| 3313 | { /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla${p}.f32 $sd, $sn, $sm */ |
| 3314 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3315 | }, |
| 3316 | { /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls${p}.f64 $dd, $dn, $dm */ |
| 3317 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3318 | }, |
| 3319 | { /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls${p}.f32 $sd, $sn, $sm */ |
| 3320 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3321 | }, |
| 3322 | { /* ARM_VNMULD, ARM_INS_VNMUL: vnmul${p}.f64 $dd, $dn, $dm */ |
| 3323 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3324 | }, |
| 3325 | { /* ARM_VNMULS, ARM_INS_VNMUL: vnmul${p}.f32 $sd, $sn, $sm */ |
| 3326 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3327 | }, |
| 3328 | { /* ARM_VORNd, ARM_INS_VORN: vorn${p} $vd, $vn, $vm */ |
| 3329 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3330 | }, |
| 3331 | { /* ARM_VORNq, ARM_INS_VORN: vorn${p} $vd, $vn, $vm */ |
| 3332 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3333 | }, |
| 3334 | { /* ARM_VORRd, ARM_INS_VORR: vorr${p} $vd, $vn, $vm */ |
| 3335 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3336 | }, |
| 3337 | { /* ARM_VORRiv2i32, ARM_INS_VORR: vorr${p}.i32 $vd, $simm */ |
| 3338 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 3339 | }, |
| 3340 | { /* ARM_VORRiv4i16, ARM_INS_VORR: vorr${p}.i16 $vd, $simm */ |
| 3341 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 3342 | }, |
| 3343 | { /* ARM_VORRiv4i32, ARM_INS_VORR: vorr${p}.i32 $vd, $simm */ |
| 3344 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 3345 | }, |
| 3346 | { /* ARM_VORRiv8i16, ARM_INS_VORR: vorr${p}.i16 $vd, $simm */ |
| 3347 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 3348 | }, |
| 3349 | { /* ARM_VORRq, ARM_INS_VORR: vorr${p} $vd, $vn, $vm */ |
| 3350 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3351 | }, |
| 3352 | { /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal${p}.s8 $vd, $vm */ |
| 3353 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3354 | }, |
| 3355 | { /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal${p}.s32 $vd, $vm */ |
| 3356 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3357 | }, |
| 3358 | { /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal${p}.s16 $vd, $vm */ |
| 3359 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3360 | }, |
| 3361 | { /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal${p}.s32 $vd, $vm */ |
| 3362 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3363 | }, |
| 3364 | { /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal${p}.s16 $vd, $vm */ |
| 3365 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3366 | }, |
| 3367 | { /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal${p}.s8 $vd, $vm */ |
| 3368 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3369 | }, |
| 3370 | { /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal${p}.u8 $vd, $vm */ |
| 3371 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3372 | }, |
| 3373 | { /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal${p}.u32 $vd, $vm */ |
| 3374 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3375 | }, |
| 3376 | { /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal${p}.u16 $vd, $vm */ |
| 3377 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3378 | }, |
| 3379 | { /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal${p}.u32 $vd, $vm */ |
| 3380 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3381 | }, |
| 3382 | { /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal${p}.u16 $vd, $vm */ |
| 3383 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3384 | }, |
| 3385 | { /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal${p}.u8 $vd, $vm */ |
| 3386 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3387 | }, |
| 3388 | { /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl${p}.s8 $vd, $vm */ |
| 3389 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3390 | }, |
| 3391 | { /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl${p}.s32 $vd, $vm */ |
| 3392 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3393 | }, |
| 3394 | { /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl${p}.s16 $vd, $vm */ |
| 3395 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3396 | }, |
| 3397 | { /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl${p}.s32 $vd, $vm */ |
| 3398 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3399 | }, |
| 3400 | { /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl${p}.s16 $vd, $vm */ |
| 3401 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3402 | }, |
| 3403 | { /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl${p}.s8 $vd, $vm */ |
| 3404 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3405 | }, |
| 3406 | { /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl${p}.u8 $vd, $vm */ |
| 3407 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3408 | }, |
| 3409 | { /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl${p}.u32 $vd, $vm */ |
| 3410 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3411 | }, |
| 3412 | { /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl${p}.u16 $vd, $vm */ |
| 3413 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3414 | }, |
| 3415 | { /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl${p}.u32 $vd, $vm */ |
| 3416 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3417 | }, |
| 3418 | { /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl${p}.u16 $vd, $vm */ |
| 3419 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3420 | }, |
| 3421 | { /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl${p}.u8 $vd, $vm */ |
| 3422 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3423 | }, |
| 3424 | { /* ARM_VPADDf, ARM_INS_VPADD: vpadd${p}.f32 $vd, $vn, $vm */ |
| 3425 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3426 | }, |
| 3427 | { /* ARM_VPADDi16, ARM_INS_VPADD: vpadd${p}.i16 $vd, $vn, $vm */ |
| 3428 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3429 | }, |
| 3430 | { /* ARM_VPADDi32, ARM_INS_VPADD: vpadd${p}.i32 $vd, $vn, $vm */ |
| 3431 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3432 | }, |
| 3433 | { /* ARM_VPADDi8, ARM_INS_VPADD: vpadd${p}.i8 $vd, $vn, $vm */ |
| 3434 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3435 | }, |
| 3436 | { /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax${p}.f32 $vd, $vn, $vm */ |
| 3437 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3438 | }, |
| 3439 | { /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax${p}.s16 $vd, $vn, $vm */ |
| 3440 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3441 | }, |
| 3442 | { /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax${p}.s32 $vd, $vn, $vm */ |
| 3443 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3444 | }, |
| 3445 | { /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax${p}.s8 $vd, $vn, $vm */ |
| 3446 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3447 | }, |
| 3448 | { /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax${p}.u16 $vd, $vn, $vm */ |
| 3449 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3450 | }, |
| 3451 | { /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax${p}.u32 $vd, $vn, $vm */ |
| 3452 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3453 | }, |
| 3454 | { /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax${p}.u8 $vd, $vn, $vm */ |
| 3455 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3456 | }, |
| 3457 | { /* ARM_VPMINf, ARM_INS_VPMIN: vpmin${p}.f32 $vd, $vn, $vm */ |
| 3458 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3459 | }, |
| 3460 | { /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin${p}.s16 $vd, $vn, $vm */ |
| 3461 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3462 | }, |
| 3463 | { /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin${p}.s32 $vd, $vn, $vm */ |
| 3464 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3465 | }, |
| 3466 | { /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin${p}.s8 $vd, $vn, $vm */ |
| 3467 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3468 | }, |
| 3469 | { /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin${p}.u16 $vd, $vn, $vm */ |
| 3470 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3471 | }, |
| 3472 | { /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin${p}.u32 $vd, $vn, $vm */ |
| 3473 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3474 | }, |
| 3475 | { /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin${p}.u8 $vd, $vn, $vm */ |
| 3476 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3477 | }, |
| 3478 | { /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs${p}.s8 $vd, $vm */ |
| 3479 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3480 | }, |
| 3481 | { /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs${p}.s32 $vd, $vm */ |
| 3482 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3483 | }, |
| 3484 | { /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs${p}.s16 $vd, $vm */ |
| 3485 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3486 | }, |
| 3487 | { /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs${p}.s32 $vd, $vm */ |
| 3488 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3489 | }, |
| 3490 | { /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs${p}.s16 $vd, $vm */ |
| 3491 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3492 | }, |
| 3493 | { /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs${p}.s8 $vd, $vm */ |
| 3494 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3495 | }, |
| 3496 | { /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd${p}.s8 $vd, $vn, $vm */ |
| 3497 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3498 | }, |
| 3499 | { /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd${p}.s64 $vd, $vn, $vm */ |
| 3500 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3501 | }, |
| 3502 | { /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd${p}.s32 $vd, $vn, $vm */ |
| 3503 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3504 | }, |
| 3505 | { /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd${p}.s64 $vd, $vn, $vm */ |
| 3506 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3507 | }, |
| 3508 | { /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd${p}.s16 $vd, $vn, $vm */ |
| 3509 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3510 | }, |
| 3511 | { /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd${p}.s32 $vd, $vn, $vm */ |
| 3512 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3513 | }, |
| 3514 | { /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd${p}.s16 $vd, $vn, $vm */ |
| 3515 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3516 | }, |
| 3517 | { /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd${p}.s8 $vd, $vn, $vm */ |
| 3518 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3519 | }, |
| 3520 | { /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd${p}.u8 $vd, $vn, $vm */ |
| 3521 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3522 | }, |
| 3523 | { /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd${p}.u64 $vd, $vn, $vm */ |
| 3524 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3525 | }, |
| 3526 | { /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd${p}.u32 $vd, $vn, $vm */ |
| 3527 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3528 | }, |
| 3529 | { /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd${p}.u64 $vd, $vn, $vm */ |
| 3530 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3531 | }, |
| 3532 | { /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd${p}.u16 $vd, $vn, $vm */ |
| 3533 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3534 | }, |
| 3535 | { /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd${p}.u32 $vd, $vn, $vm */ |
| 3536 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3537 | }, |
| 3538 | { /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd${p}.u16 $vd, $vn, $vm */ |
| 3539 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3540 | }, |
| 3541 | { /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd${p}.u8 $vd, $vn, $vm */ |
| 3542 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3543 | }, |
| 3544 | { /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal${p}.s32 $vd, $vn, $vm$lane */ |
| 3545 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3546 | }, |
| 3547 | { /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal${p}.s16 $vd, $vn, $vm$lane */ |
| 3548 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3549 | }, |
| 3550 | { /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal${p}.s32 $vd, $vn, $vm */ |
| 3551 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3552 | }, |
| 3553 | { /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal${p}.s16 $vd, $vn, $vm */ |
| 3554 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3555 | }, |
| 3556 | { /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s32 $vd, $vn, $vm$lane */ |
| 3557 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3558 | }, |
| 3559 | { /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl${p}.s16 $vd, $vn, $vm$lane */ |
| 3560 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 3561 | }, |
| 3562 | { /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl${p}.s32 $vd, $vn, $vm */ |
| 3563 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3564 | }, |
| 3565 | { /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s16 $vd, $vn, $vm */ |
| 3566 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3567 | }, |
| 3568 | { /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm$lane */ |
| 3569 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3570 | }, |
| 3571 | { /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm$lane */ |
| 3572 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3573 | }, |
| 3574 | { /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm$lane */ |
| 3575 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3576 | }, |
| 3577 | { /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm$lane */ |
| 3578 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3579 | }, |
| 3580 | { /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm */ |
| 3581 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3582 | }, |
| 3583 | { /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm */ |
| 3584 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3585 | }, |
| 3586 | { /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm */ |
| 3587 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3588 | }, |
| 3589 | { /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm */ |
| 3590 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3591 | }, |
| 3592 | { /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull${p}.s32 $vd, $vn, $vm$lane */ |
| 3593 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3594 | }, |
| 3595 | { /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull${p}.s16 $vd, $vn, $vm$lane */ |
| 3596 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3597 | }, |
| 3598 | { /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull${p}.s32 $vd, $vn, $vm */ |
| 3599 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3600 | }, |
| 3601 | { /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull${p}.s16 $vd, $vn, $vm */ |
| 3602 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3603 | }, |
| 3604 | { /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun${p}.s64 $vd, $vm */ |
| 3605 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3606 | }, |
| 3607 | { /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun${p}.s32 $vd, $vm */ |
| 3608 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3609 | }, |
| 3610 | { /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun${p}.s16 $vd, $vm */ |
| 3611 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3612 | }, |
| 3613 | { /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn${p}.s64 $vd, $vm */ |
| 3614 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3615 | }, |
| 3616 | { /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn${p}.s32 $vd, $vm */ |
| 3617 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3618 | }, |
| 3619 | { /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn${p}.s16 $vd, $vm */ |
| 3620 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3621 | }, |
| 3622 | { /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn${p}.u64 $vd, $vm */ |
| 3623 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3624 | }, |
| 3625 | { /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn${p}.u32 $vd, $vm */ |
| 3626 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3627 | }, |
| 3628 | { /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn${p}.u16 $vd, $vm */ |
| 3629 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3630 | }, |
| 3631 | { /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg${p}.s8 $vd, $vm */ |
| 3632 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3633 | }, |
| 3634 | { /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg${p}.s32 $vd, $vm */ |
| 3635 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3636 | }, |
| 3637 | { /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg${p}.s16 $vd, $vm */ |
| 3638 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3639 | }, |
| 3640 | { /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg${p}.s32 $vd, $vm */ |
| 3641 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3642 | }, |
| 3643 | { /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg${p}.s16 $vd, $vm */ |
| 3644 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3645 | }, |
| 3646 | { /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg${p}.s8 $vd, $vm */ |
| 3647 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3648 | }, |
| 3649 | { /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm$lane */ |
| 3650 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3651 | }, |
| 3652 | { /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm$lane */ |
| 3653 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3654 | }, |
| 3655 | { /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm$lane */ |
| 3656 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3657 | }, |
| 3658 | { /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm$lane */ |
| 3659 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3660 | }, |
| 3661 | { /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm */ |
| 3662 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3663 | }, |
| 3664 | { /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm */ |
| 3665 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3666 | }, |
| 3667 | { /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm */ |
| 3668 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3669 | }, |
| 3670 | { /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm */ |
| 3671 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3672 | }, |
| 3673 | { /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl${p}.s8 $vd, $vm, $vn */ |
| 3674 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3675 | }, |
| 3676 | { /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl${p}.s64 $vd, $vm, $vn */ |
| 3677 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3678 | }, |
| 3679 | { /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl${p}.s32 $vd, $vm, $vn */ |
| 3680 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3681 | }, |
| 3682 | { /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl${p}.s64 $vd, $vm, $vn */ |
| 3683 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3684 | }, |
| 3685 | { /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl${p}.s16 $vd, $vm, $vn */ |
| 3686 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3687 | }, |
| 3688 | { /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl${p}.s32 $vd, $vm, $vn */ |
| 3689 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3690 | }, |
| 3691 | { /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl${p}.s16 $vd, $vm, $vn */ |
| 3692 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3693 | }, |
| 3694 | { /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl${p}.s8 $vd, $vm, $vn */ |
| 3695 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3696 | }, |
| 3697 | { /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl${p}.u8 $vd, $vm, $vn */ |
| 3698 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3699 | }, |
| 3700 | { /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl${p}.u64 $vd, $vm, $vn */ |
| 3701 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3702 | }, |
| 3703 | { /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl${p}.u32 $vd, $vm, $vn */ |
| 3704 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3705 | }, |
| 3706 | { /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl${p}.u64 $vd, $vm, $vn */ |
| 3707 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3708 | }, |
| 3709 | { /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl${p}.u16 $vd, $vm, $vn */ |
| 3710 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3711 | }, |
| 3712 | { /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl${p}.u32 $vd, $vm, $vn */ |
| 3713 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3714 | }, |
| 3715 | { /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl${p}.u16 $vd, $vm, $vn */ |
| 3716 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3717 | }, |
| 3718 | { /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl${p}.u8 $vd, $vm, $vn */ |
| 3719 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3720 | }, |
| 3721 | { /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.s64 $vd, $vm, $simm */ |
| 3722 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3723 | }, |
| 3724 | { /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.s32 $vd, $vm, $simm */ |
| 3725 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3726 | }, |
| 3727 | { /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.s16 $vd, $vm, $simm */ |
| 3728 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3729 | }, |
| 3730 | { /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.u64 $vd, $vm, $simm */ |
| 3731 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3732 | }, |
| 3733 | { /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.u32 $vd, $vm, $simm */ |
| 3734 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3735 | }, |
| 3736 | { /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.u16 $vd, $vm, $simm */ |
| 3737 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3738 | }, |
| 3739 | { /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun${p}.s64 $vd, $vm, $simm */ |
| 3740 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3741 | }, |
| 3742 | { /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun${p}.s32 $vd, $vm, $simm */ |
| 3743 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3744 | }, |
| 3745 | { /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun${p}.s16 $vd, $vm, $simm */ |
| 3746 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3747 | }, |
| 3748 | { /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */ |
| 3749 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3750 | }, |
| 3751 | { /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */ |
| 3752 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3753 | }, |
| 3754 | { /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */ |
| 3755 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3756 | }, |
| 3757 | { /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */ |
| 3758 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3759 | }, |
| 3760 | { /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */ |
| 3761 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3762 | }, |
| 3763 | { /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */ |
| 3764 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3765 | }, |
| 3766 | { /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */ |
| 3767 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3768 | }, |
| 3769 | { /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */ |
| 3770 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3771 | }, |
| 3772 | { /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu${p}.s8 $vd, $vm, $simm */ |
| 3773 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3774 | }, |
| 3775 | { /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu${p}.s64 $vd, $vm, $simm */ |
| 3776 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3777 | }, |
| 3778 | { /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu${p}.s32 $vd, $vm, $simm */ |
| 3779 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3780 | }, |
| 3781 | { /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu${p}.s64 $vd, $vm, $simm */ |
| 3782 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3783 | }, |
| 3784 | { /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu${p}.s16 $vd, $vm, $simm */ |
| 3785 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3786 | }, |
| 3787 | { /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu${p}.s32 $vd, $vm, $simm */ |
| 3788 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3789 | }, |
| 3790 | { /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu${p}.s16 $vd, $vm, $simm */ |
| 3791 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3792 | }, |
| 3793 | { /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu${p}.s8 $vd, $vm, $simm */ |
| 3794 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3795 | }, |
| 3796 | { /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */ |
| 3797 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3798 | }, |
| 3799 | { /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */ |
| 3800 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3801 | }, |
| 3802 | { /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $vn */ |
| 3803 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3804 | }, |
| 3805 | { /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */ |
| 3806 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3807 | }, |
| 3808 | { /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $vn */ |
| 3809 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3810 | }, |
| 3811 | { /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $vn */ |
| 3812 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3813 | }, |
| 3814 | { /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $vn */ |
| 3815 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3816 | }, |
| 3817 | { /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */ |
| 3818 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3819 | }, |
| 3820 | { /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $simm */ |
| 3821 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3822 | }, |
| 3823 | { /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $simm */ |
| 3824 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3825 | }, |
| 3826 | { /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $simm */ |
| 3827 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3828 | }, |
| 3829 | { /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $simm */ |
| 3830 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3831 | }, |
| 3832 | { /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $simm */ |
| 3833 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3834 | }, |
| 3835 | { /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $simm */ |
| 3836 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3837 | }, |
| 3838 | { /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $simm */ |
| 3839 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3840 | }, |
| 3841 | { /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $simm */ |
| 3842 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3843 | }, |
| 3844 | { /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $vn */ |
| 3845 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3846 | }, |
| 3847 | { /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $vn */ |
| 3848 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3849 | }, |
| 3850 | { /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $vn */ |
| 3851 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3852 | }, |
| 3853 | { /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $vn */ |
| 3854 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3855 | }, |
| 3856 | { /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $vn */ |
| 3857 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3858 | }, |
| 3859 | { /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $vn */ |
| 3860 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3861 | }, |
| 3862 | { /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $vn */ |
| 3863 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3864 | }, |
| 3865 | { /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $vn */ |
| 3866 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3867 | }, |
| 3868 | { /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn${p}.s64 $vd, $vm, $simm */ |
| 3869 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3870 | }, |
| 3871 | { /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn${p}.s32 $vd, $vm, $simm */ |
| 3872 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3873 | }, |
| 3874 | { /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn${p}.s16 $vd, $vm, $simm */ |
| 3875 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3876 | }, |
| 3877 | { /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn${p}.u64 $vd, $vm, $simm */ |
| 3878 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3879 | }, |
| 3880 | { /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn${p}.u32 $vd, $vm, $simm */ |
| 3881 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3882 | }, |
| 3883 | { /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn${p}.u16 $vd, $vm, $simm */ |
| 3884 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3885 | }, |
| 3886 | { /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun${p}.s64 $vd, $vm, $simm */ |
| 3887 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3888 | }, |
| 3889 | { /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun${p}.s32 $vd, $vm, $simm */ |
| 3890 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3891 | }, |
| 3892 | { /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun${p}.s16 $vd, $vm, $simm */ |
| 3893 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3894 | }, |
| 3895 | { /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub${p}.s8 $vd, $vn, $vm */ |
| 3896 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3897 | }, |
| 3898 | { /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub${p}.s64 $vd, $vn, $vm */ |
| 3899 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3900 | }, |
| 3901 | { /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub${p}.s32 $vd, $vn, $vm */ |
| 3902 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3903 | }, |
| 3904 | { /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub${p}.s64 $vd, $vn, $vm */ |
| 3905 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3906 | }, |
| 3907 | { /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub${p}.s16 $vd, $vn, $vm */ |
| 3908 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3909 | }, |
| 3910 | { /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub${p}.s32 $vd, $vn, $vm */ |
| 3911 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3912 | }, |
| 3913 | { /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub${p}.s16 $vd, $vn, $vm */ |
| 3914 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3915 | }, |
| 3916 | { /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub${p}.s8 $vd, $vn, $vm */ |
| 3917 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3918 | }, |
| 3919 | { /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub${p}.u8 $vd, $vn, $vm */ |
| 3920 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3921 | }, |
| 3922 | { /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub${p}.u64 $vd, $vn, $vm */ |
| 3923 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3924 | }, |
| 3925 | { /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub${p}.u32 $vd, $vn, $vm */ |
| 3926 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3927 | }, |
| 3928 | { /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub${p}.u64 $vd, $vn, $vm */ |
| 3929 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3930 | }, |
| 3931 | { /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub${p}.u16 $vd, $vn, $vm */ |
| 3932 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3933 | }, |
| 3934 | { /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub${p}.u32 $vd, $vn, $vm */ |
| 3935 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3936 | }, |
| 3937 | { /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub${p}.u16 $vd, $vn, $vm */ |
| 3938 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3939 | }, |
| 3940 | { /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub${p}.u8 $vd, $vn, $vm */ |
| 3941 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3942 | }, |
| 3943 | { /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn${p}.i64 $vd, $vn, $vm */ |
| 3944 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3945 | }, |
| 3946 | { /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn${p}.i32 $vd, $vn, $vm */ |
| 3947 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3948 | }, |
| 3949 | { /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn${p}.i16 $vd, $vn, $vm */ |
| 3950 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3951 | }, |
| 3952 | { /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */ |
| 3953 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3954 | }, |
| 3955 | { /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */ |
| 3956 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3957 | }, |
| 3958 | { /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */ |
| 3959 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3960 | }, |
| 3961 | { /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */ |
| 3962 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3963 | }, |
| 3964 | { /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps${p}.f32 $vd, $vn, $vm */ |
| 3965 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3966 | }, |
| 3967 | { /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps${p}.f32 $vd, $vn, $vm */ |
| 3968 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 3969 | }, |
| 3970 | { /* ARM_VREV16d8, ARM_INS_VREV16: vrev16${p}.8 $vd, $vm */ |
| 3971 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3972 | }, |
| 3973 | { /* ARM_VREV16q8, ARM_INS_VREV16: vrev16${p}.8 $vd, $vm */ |
| 3974 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3975 | }, |
| 3976 | { /* ARM_VREV32d16, ARM_INS_VREV32: vrev32${p}.16 $vd, $vm */ |
| 3977 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3978 | }, |
| 3979 | { /* ARM_VREV32d8, ARM_INS_VREV32: vrev32${p}.8 $vd, $vm */ |
| 3980 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3981 | }, |
| 3982 | { /* ARM_VREV32q16, ARM_INS_VREV32: vrev32${p}.16 $vd, $vm */ |
| 3983 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3984 | }, |
| 3985 | { /* ARM_VREV32q8, ARM_INS_VREV32: vrev32${p}.8 $vd, $vm */ |
| 3986 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3987 | }, |
| 3988 | { /* ARM_VREV64d16, ARM_INS_VREV64: vrev64${p}.16 $vd, $vm */ |
| 3989 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3990 | }, |
| 3991 | { /* ARM_VREV64d32, ARM_INS_VREV64: vrev64${p}.32 $vd, $vm */ |
| 3992 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3993 | }, |
| 3994 | { /* ARM_VREV64d8, ARM_INS_VREV64: vrev64${p}.8 $vd, $vm */ |
| 3995 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3996 | }, |
| 3997 | { /* ARM_VREV64q16, ARM_INS_VREV64: vrev64${p}.16 $vd, $vm */ |
| 3998 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 3999 | }, |
| 4000 | { /* ARM_VREV64q32, ARM_INS_VREV64: vrev64${p}.32 $vd, $vm */ |
| 4001 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4002 | }, |
| 4003 | { /* ARM_VREV64q8, ARM_INS_VREV64: vrev64${p}.8 $vd, $vm */ |
| 4004 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4005 | }, |
| 4006 | { /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd${p}.s8 $vd, $vn, $vm */ |
| 4007 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4008 | }, |
| 4009 | { /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd${p}.s32 $vd, $vn, $vm */ |
| 4010 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4011 | }, |
| 4012 | { /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd${p}.s16 $vd, $vn, $vm */ |
| 4013 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4014 | }, |
| 4015 | { /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd${p}.s32 $vd, $vn, $vm */ |
| 4016 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4017 | }, |
| 4018 | { /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd${p}.s16 $vd, $vn, $vm */ |
| 4019 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4020 | }, |
| 4021 | { /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd${p}.s8 $vd, $vn, $vm */ |
| 4022 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4023 | }, |
| 4024 | { /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd${p}.u8 $vd, $vn, $vm */ |
| 4025 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4026 | }, |
| 4027 | { /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd${p}.u32 $vd, $vn, $vm */ |
| 4028 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4029 | }, |
| 4030 | { /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd${p}.u16 $vd, $vn, $vm */ |
| 4031 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4032 | }, |
| 4033 | { /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd${p}.u32 $vd, $vn, $vm */ |
| 4034 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4035 | }, |
| 4036 | { /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd${p}.u16 $vd, $vn, $vm */ |
| 4037 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4038 | }, |
| 4039 | { /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd${p}.u8 $vd, $vn, $vm */ |
| 4040 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4041 | }, |
| 4042 | { /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta.f64 $dd, $dm */ |
| 4043 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4044 | }, |
| 4045 | { /* ARM_VRINTAND, ARM_INS_VRINTA: vrinta.f32 $vd, $vm */ |
| 4046 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4047 | }, |
| 4048 | { /* ARM_VRINTANQ, ARM_INS_VRINTA: vrinta.f32 $vd, $vm */ |
| 4049 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4050 | }, |
| 4051 | { /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta.f32 $sd, $sm */ |
| 4052 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4053 | }, |
| 4054 | { /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm.f64 $dd, $dm */ |
| 4055 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4056 | }, |
| 4057 | { /* ARM_VRINTMND, ARM_INS_VRINTM: vrintm.f32 $vd, $vm */ |
| 4058 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4059 | }, |
| 4060 | { /* ARM_VRINTMNQ, ARM_INS_VRINTM: vrintm.f32 $vd, $vm */ |
| 4061 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4062 | }, |
| 4063 | { /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm.f32 $sd, $sm */ |
| 4064 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4065 | }, |
| 4066 | { /* ARM_VRINTND, ARM_INS_VRINTN: vrintn.f64 $dd, $dm */ |
| 4067 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4068 | }, |
| 4069 | { /* ARM_VRINTNND, ARM_INS_VRINTN: vrintn.f32 $vd, $vm */ |
| 4070 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4071 | }, |
| 4072 | { /* ARM_VRINTNNQ, ARM_INS_VRINTN: vrintn.f32 $vd, $vm */ |
| 4073 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4074 | }, |
| 4075 | { /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn.f32 $sd, $sm */ |
| 4076 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4077 | }, |
| 4078 | { /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp.f64 $dd, $dm */ |
| 4079 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4080 | }, |
| 4081 | { /* ARM_VRINTPND, ARM_INS_VRINTP: vrintp.f32 $vd, $vm */ |
| 4082 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4083 | }, |
| 4084 | { /* ARM_VRINTPNQ, ARM_INS_VRINTP: vrintp.f32 $vd, $vm */ |
| 4085 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4086 | }, |
| 4087 | { /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp.f32 $sd, $sm */ |
| 4088 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4089 | }, |
| 4090 | { /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr${p}.f64 $dd, $dm */ |
| 4091 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4092 | }, |
| 4093 | { /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr${p}.f32 $sd, $sm */ |
| 4094 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4095 | }, |
| 4096 | { /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx${p}.f64 $dd, $dm */ |
| 4097 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4098 | }, |
| 4099 | { /* ARM_VRINTXND, ARM_INS_VRINTX: vrintx.f32 $vd, $vm */ |
| 4100 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4101 | }, |
| 4102 | { /* ARM_VRINTXNQ, ARM_INS_VRINTX: vrintx.f32 $vd, $vm */ |
| 4103 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4104 | }, |
| 4105 | { /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx${p}.f32 $sd, $sm */ |
| 4106 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4107 | }, |
| 4108 | { /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz${p}.f64 $dd, $dm */ |
| 4109 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4110 | }, |
| 4111 | { /* ARM_VRINTZND, ARM_INS_VRINTZ: vrintz.f32 $vd, $vm */ |
| 4112 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4113 | }, |
| 4114 | { /* ARM_VRINTZNQ, ARM_INS_VRINTZ: vrintz.f32 $vd, $vm */ |
| 4115 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4116 | }, |
| 4117 | { /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz${p}.f32 $sd, $sm */ |
| 4118 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4119 | }, |
| 4120 | { /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */ |
| 4121 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4122 | }, |
| 4123 | { /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */ |
| 4124 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4125 | }, |
| 4126 | { /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */ |
| 4127 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4128 | }, |
| 4129 | { /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */ |
| 4130 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4131 | }, |
| 4132 | { /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */ |
| 4133 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4134 | }, |
| 4135 | { /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */ |
| 4136 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4137 | }, |
| 4138 | { /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */ |
| 4139 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4140 | }, |
| 4141 | { /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */ |
| 4142 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4143 | }, |
| 4144 | { /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */ |
| 4145 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4146 | }, |
| 4147 | { /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */ |
| 4148 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4149 | }, |
| 4150 | { /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl${p}.u32 $vd, $vm, $vn */ |
| 4151 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4152 | }, |
| 4153 | { /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */ |
| 4154 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4155 | }, |
| 4156 | { /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl${p}.u16 $vd, $vm, $vn */ |
| 4157 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4158 | }, |
| 4159 | { /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl${p}.u32 $vd, $vm, $vn */ |
| 4160 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4161 | }, |
| 4162 | { /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl${p}.u16 $vd, $vm, $vn */ |
| 4163 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4164 | }, |
| 4165 | { /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */ |
| 4166 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4167 | }, |
| 4168 | { /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn${p}.i64 $vd, $vm, $simm */ |
| 4169 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4170 | }, |
| 4171 | { /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn${p}.i32 $vd, $vm, $simm */ |
| 4172 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4173 | }, |
| 4174 | { /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn${p}.i16 $vd, $vm, $simm */ |
| 4175 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4176 | }, |
| 4177 | { /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr${p}.s8 $vd, $vm, $simm */ |
| 4178 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4179 | }, |
| 4180 | { /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr${p}.s64 $vd, $vm, $simm */ |
| 4181 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4182 | }, |
| 4183 | { /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr${p}.s32 $vd, $vm, $simm */ |
| 4184 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4185 | }, |
| 4186 | { /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr${p}.s64 $vd, $vm, $simm */ |
| 4187 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4188 | }, |
| 4189 | { /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr${p}.s16 $vd, $vm, $simm */ |
| 4190 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4191 | }, |
| 4192 | { /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr${p}.s32 $vd, $vm, $simm */ |
| 4193 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4194 | }, |
| 4195 | { /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr${p}.s16 $vd, $vm, $simm */ |
| 4196 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4197 | }, |
| 4198 | { /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr${p}.s8 $vd, $vm, $simm */ |
| 4199 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4200 | }, |
| 4201 | { /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr${p}.u8 $vd, $vm, $simm */ |
| 4202 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4203 | }, |
| 4204 | { /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr${p}.u64 $vd, $vm, $simm */ |
| 4205 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4206 | }, |
| 4207 | { /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr${p}.u32 $vd, $vm, $simm */ |
| 4208 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4209 | }, |
| 4210 | { /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr${p}.u64 $vd, $vm, $simm */ |
| 4211 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4212 | }, |
| 4213 | { /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr${p}.u16 $vd, $vm, $simm */ |
| 4214 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4215 | }, |
| 4216 | { /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr${p}.u32 $vd, $vm, $simm */ |
| 4217 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4218 | }, |
| 4219 | { /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr${p}.u16 $vd, $vm, $simm */ |
| 4220 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4221 | }, |
| 4222 | { /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr${p}.u8 $vd, $vm, $simm */ |
| 4223 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4224 | }, |
| 4225 | { /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte${p}.u32 $vd, $vm */ |
| 4226 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4227 | }, |
| 4228 | { /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte${p}.f32 $vd, $vm */ |
| 4229 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4230 | }, |
| 4231 | { /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte${p}.f32 $vd, $vm */ |
| 4232 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4233 | }, |
| 4234 | { /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte${p}.u32 $vd, $vm */ |
| 4235 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4236 | }, |
| 4237 | { /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts${p}.f32 $vd, $vn, $vm */ |
| 4238 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4239 | }, |
| 4240 | { /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts${p}.f32 $vd, $vn, $vm */ |
| 4241 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4242 | }, |
| 4243 | { /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra${p}.s8 $vd, $vm, $simm */ |
| 4244 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4245 | }, |
| 4246 | { /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra${p}.s64 $vd, $vm, $simm */ |
| 4247 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4248 | }, |
| 4249 | { /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra${p}.s32 $vd, $vm, $simm */ |
| 4250 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4251 | }, |
| 4252 | { /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra${p}.s64 $vd, $vm, $simm */ |
| 4253 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4254 | }, |
| 4255 | { /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra${p}.s16 $vd, $vm, $simm */ |
| 4256 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4257 | }, |
| 4258 | { /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra${p}.s32 $vd, $vm, $simm */ |
| 4259 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4260 | }, |
| 4261 | { /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra${p}.s16 $vd, $vm, $simm */ |
| 4262 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4263 | }, |
| 4264 | { /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra${p}.s8 $vd, $vm, $simm */ |
| 4265 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4266 | }, |
| 4267 | { /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra${p}.u8 $vd, $vm, $simm */ |
| 4268 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4269 | }, |
| 4270 | { /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra${p}.u64 $vd, $vm, $simm */ |
| 4271 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4272 | }, |
| 4273 | { /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra${p}.u32 $vd, $vm, $simm */ |
| 4274 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4275 | }, |
| 4276 | { /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra${p}.u64 $vd, $vm, $simm */ |
| 4277 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4278 | }, |
| 4279 | { /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra${p}.u16 $vd, $vm, $simm */ |
| 4280 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4281 | }, |
| 4282 | { /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra${p}.u32 $vd, $vm, $simm */ |
| 4283 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4284 | }, |
| 4285 | { /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra${p}.u16 $vd, $vm, $simm */ |
| 4286 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4287 | }, |
| 4288 | { /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra${p}.u8 $vd, $vm, $simm */ |
| 4289 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4290 | }, |
| 4291 | { /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn${p}.i64 $vd, $vn, $vm */ |
| 4292 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4293 | }, |
| 4294 | { /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn${p}.i32 $vd, $vn, $vm */ |
| 4295 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4296 | }, |
| 4297 | { /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn${p}.i16 $vd, $vn, $vm */ |
| 4298 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4299 | }, |
| 4300 | { /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq.f64 $dd, $dn, $dm */ |
| 4301 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4302 | }, |
| 4303 | { /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq.f32 $sd, $sn, $sm */ |
| 4304 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4305 | }, |
| 4306 | { /* ARM_VSELGED, ARM_INS_VSELGE: vselge.f64 $dd, $dn, $dm */ |
| 4307 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4308 | }, |
| 4309 | { /* ARM_VSELGES, ARM_INS_VSELGE: vselge.f32 $sd, $sn, $sm */ |
| 4310 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4311 | }, |
| 4312 | { /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt.f64 $dd, $dn, $dm */ |
| 4313 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4314 | }, |
| 4315 | { /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt.f32 $sd, $sn, $sm */ |
| 4316 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4317 | }, |
| 4318 | { /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs.f64 $dd, $dn, $dm */ |
| 4319 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4320 | }, |
| 4321 | { /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs.f32 $sd, $sn, $sm */ |
| 4322 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4323 | }, |
| 4324 | { /* ARM_VSETLNi16, ARM_INS_VMOV: vmov${p}.16 $v$lane, $r */ |
| 4325 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4326 | }, |
| 4327 | { /* ARM_VSETLNi32, ARM_INS_VMOV: vmov${p}.32 $v$lane, $r */ |
| 4328 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4329 | }, |
| 4330 | { /* ARM_VSETLNi8, ARM_INS_VMOV: vmov${p}.8 $v$lane, $r */ |
| 4331 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4332 | }, |
| 4333 | { /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll${p}.i16 $vd, $vm, $simm */ |
| 4334 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4335 | }, |
| 4336 | { /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll${p}.i32 $vd, $vm, $simm */ |
| 4337 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4338 | }, |
| 4339 | { /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll${p}.i8 $vd, $vm, $simm */ |
| 4340 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4341 | }, |
| 4342 | { /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll${p}.s32 $vd, $vm, $simm */ |
| 4343 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4344 | }, |
| 4345 | { /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll${p}.s16 $vd, $vm, $simm */ |
| 4346 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4347 | }, |
| 4348 | { /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll${p}.s8 $vd, $vm, $simm */ |
| 4349 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4350 | }, |
| 4351 | { /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll${p}.u32 $vd, $vm, $simm */ |
| 4352 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4353 | }, |
| 4354 | { /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll${p}.u16 $vd, $vm, $simm */ |
| 4355 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4356 | }, |
| 4357 | { /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll${p}.u8 $vd, $vm, $simm */ |
| 4358 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4359 | }, |
| 4360 | { /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl${p}.i8 $vd, $vm, $simm */ |
| 4361 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4362 | }, |
| 4363 | { /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl${p}.i64 $vd, $vm, $simm */ |
| 4364 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4365 | }, |
| 4366 | { /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl${p}.i32 $vd, $vm, $simm */ |
| 4367 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4368 | }, |
| 4369 | { /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl${p}.i64 $vd, $vm, $simm */ |
| 4370 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4371 | }, |
| 4372 | { /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl${p}.i16 $vd, $vm, $simm */ |
| 4373 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4374 | }, |
| 4375 | { /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl${p}.i32 $vd, $vm, $simm */ |
| 4376 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4377 | }, |
| 4378 | { /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl${p}.i16 $vd, $vm, $simm */ |
| 4379 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4380 | }, |
| 4381 | { /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl${p}.i8 $vd, $vm, $simm */ |
| 4382 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4383 | }, |
| 4384 | { /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl${p}.s8 $vd, $vm, $vn */ |
| 4385 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4386 | }, |
| 4387 | { /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl${p}.s64 $vd, $vm, $vn */ |
| 4388 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4389 | }, |
| 4390 | { /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl${p}.s32 $vd, $vm, $vn */ |
| 4391 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4392 | }, |
| 4393 | { /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl${p}.s64 $vd, $vm, $vn */ |
| 4394 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4395 | }, |
| 4396 | { /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl${p}.s16 $vd, $vm, $vn */ |
| 4397 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4398 | }, |
| 4399 | { /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl${p}.s32 $vd, $vm, $vn */ |
| 4400 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4401 | }, |
| 4402 | { /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl${p}.s16 $vd, $vm, $vn */ |
| 4403 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4404 | }, |
| 4405 | { /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl${p}.s8 $vd, $vm, $vn */ |
| 4406 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4407 | }, |
| 4408 | { /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl${p}.u8 $vd, $vm, $vn */ |
| 4409 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4410 | }, |
| 4411 | { /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl${p}.u64 $vd, $vm, $vn */ |
| 4412 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4413 | }, |
| 4414 | { /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl${p}.u32 $vd, $vm, $vn */ |
| 4415 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4416 | }, |
| 4417 | { /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl${p}.u64 $vd, $vm, $vn */ |
| 4418 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4419 | }, |
| 4420 | { /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl${p}.u16 $vd, $vm, $vn */ |
| 4421 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4422 | }, |
| 4423 | { /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl${p}.u32 $vd, $vm, $vn */ |
| 4424 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4425 | }, |
| 4426 | { /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl${p}.u16 $vd, $vm, $vn */ |
| 4427 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4428 | }, |
| 4429 | { /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl${p}.u8 $vd, $vm, $vn */ |
| 4430 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 4431 | }, |
| 4432 | { /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn${p}.i64 $vd, $vm, $simm */ |
| 4433 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4434 | }, |
| 4435 | { /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn${p}.i32 $vd, $vm, $simm */ |
| 4436 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4437 | }, |
| 4438 | { /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn${p}.i16 $vd, $vm, $simm */ |
| 4439 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4440 | }, |
| 4441 | { /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */ |
| 4442 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4443 | }, |
| 4444 | { /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */ |
| 4445 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4446 | }, |
| 4447 | { /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */ |
| 4448 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4449 | }, |
| 4450 | { /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */ |
| 4451 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4452 | }, |
| 4453 | { /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */ |
| 4454 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4455 | }, |
| 4456 | { /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */ |
| 4457 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4458 | }, |
| 4459 | { /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */ |
| 4460 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4461 | }, |
| 4462 | { /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */ |
| 4463 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4464 | }, |
| 4465 | { /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */ |
| 4466 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4467 | }, |
| 4468 | { /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */ |
| 4469 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4470 | }, |
| 4471 | { /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr${p}.u32 $vd, $vm, $simm */ |
| 4472 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4473 | }, |
| 4474 | { /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */ |
| 4475 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4476 | }, |
| 4477 | { /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr${p}.u16 $vd, $vm, $simm */ |
| 4478 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4479 | }, |
| 4480 | { /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr${p}.u32 $vd, $vm, $simm */ |
| 4481 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4482 | }, |
| 4483 | { /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr${p}.u16 $vd, $vm, $simm */ |
| 4484 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4485 | }, |
| 4486 | { /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */ |
| 4487 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4488 | }, |
| 4489 | { /* ARM_VSHTOD, ARM_INS_VCVT: vcvt${p}.f64.s16 $dst, $a, $fbits */ |
| 4490 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 4491 | }, |
| 4492 | { /* ARM_VSHTOS, ARM_INS_VCVT: vcvt${p}.f32.s16 $dst, $a, $fbits */ |
| 4493 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 4494 | }, |
| 4495 | { /* ARM_VSITOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dd, $sm */ |
| 4496 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4497 | }, |
| 4498 | { /* ARM_VSITOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $sd, $sm */ |
| 4499 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4500 | }, |
| 4501 | { /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli${p}.8 $vd, $vm, $simm */ |
| 4502 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4503 | }, |
| 4504 | { /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli${p}.64 $vd, $vm, $simm */ |
| 4505 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4506 | }, |
| 4507 | { /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli${p}.32 $vd, $vm, $simm */ |
| 4508 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4509 | }, |
| 4510 | { /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli${p}.64 $vd, $vm, $simm */ |
| 4511 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4512 | }, |
| 4513 | { /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli${p}.16 $vd, $vm, $simm */ |
| 4514 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4515 | }, |
| 4516 | { /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli${p}.32 $vd, $vm, $simm */ |
| 4517 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4518 | }, |
| 4519 | { /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli${p}.16 $vd, $vm, $simm */ |
| 4520 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4521 | }, |
| 4522 | { /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli${p}.8 $vd, $vm, $simm */ |
| 4523 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4524 | }, |
| 4525 | { /* ARM_VSLTOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dst, $a, $fbits */ |
| 4526 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 4527 | }, |
| 4528 | { /* ARM_VSLTOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $dst, $a, $fbits */ |
| 4529 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 4530 | }, |
| 4531 | { /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt${p}.f64 $dd, $dm */ |
| 4532 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4533 | }, |
| 4534 | { /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt${p}.f32 $sd, $sm */ |
| 4535 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 4536 | }, |
| 4537 | { /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra${p}.s8 $vd, $vm, $simm */ |
| 4538 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4539 | }, |
| 4540 | { /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra${p}.s64 $vd, $vm, $simm */ |
| 4541 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4542 | }, |
| 4543 | { /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra${p}.s32 $vd, $vm, $simm */ |
| 4544 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4545 | }, |
| 4546 | { /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra${p}.s64 $vd, $vm, $simm */ |
| 4547 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4548 | }, |
| 4549 | { /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra${p}.s16 $vd, $vm, $simm */ |
| 4550 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4551 | }, |
| 4552 | { /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra${p}.s32 $vd, $vm, $simm */ |
| 4553 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4554 | }, |
| 4555 | { /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra${p}.s16 $vd, $vm, $simm */ |
| 4556 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4557 | }, |
| 4558 | { /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra${p}.s8 $vd, $vm, $simm */ |
| 4559 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4560 | }, |
| 4561 | { /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra${p}.u8 $vd, $vm, $simm */ |
| 4562 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4563 | }, |
| 4564 | { /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra${p}.u64 $vd, $vm, $simm */ |
| 4565 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4566 | }, |
| 4567 | { /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra${p}.u32 $vd, $vm, $simm */ |
| 4568 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4569 | }, |
| 4570 | { /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra${p}.u64 $vd, $vm, $simm */ |
| 4571 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4572 | }, |
| 4573 | { /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra${p}.u16 $vd, $vm, $simm */ |
| 4574 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4575 | }, |
| 4576 | { /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra${p}.u32 $vd, $vm, $simm */ |
| 4577 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4578 | }, |
| 4579 | { /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra${p}.u16 $vd, $vm, $simm */ |
| 4580 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4581 | }, |
| 4582 | { /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra${p}.u8 $vd, $vm, $simm */ |
| 4583 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4584 | }, |
| 4585 | { /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri${p}.8 $vd, $vm, $simm */ |
| 4586 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4587 | }, |
| 4588 | { /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri${p}.64 $vd, $vm, $simm */ |
| 4589 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4590 | }, |
| 4591 | { /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri${p}.32 $vd, $vm, $simm */ |
| 4592 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4593 | }, |
| 4594 | { /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri${p}.64 $vd, $vm, $simm */ |
| 4595 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4596 | }, |
| 4597 | { /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri${p}.16 $vd, $vm, $simm */ |
| 4598 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4599 | }, |
| 4600 | { /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri${p}.32 $vd, $vm, $simm */ |
| 4601 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4602 | }, |
| 4603 | { /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri${p}.16 $vd, $vm, $simm */ |
| 4604 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4605 | }, |
| 4606 | { /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri${p}.8 $vd, $vm, $simm */ |
| 4607 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 4608 | }, |
| 4609 | { /* ARM_VST1LNd16, ARM_INS_VST1: vst1${p}.16 \{$vd[$lane]\}, $rn */ |
| 4610 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4611 | }, |
| 4612 | { /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1${p}.16 \{$vd[$lane]\}, $rn$rm */ |
| 4613 | { CS_AC_READ, 0 } |
| 4614 | }, |
| 4615 | { /* ARM_VST1LNd32, ARM_INS_VST1: vst1${p}.32 \{$vd[$lane]\}, $rn */ |
| 4616 | { CS_AC_READ, 0 } |
| 4617 | }, |
| 4618 | { /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1${p}.32 \{$vd[$lane]\}, $rn$rm */ |
| 4619 | { CS_AC_READ, 0 } |
| 4620 | }, |
| 4621 | { /* ARM_VST1LNd8, ARM_INS_VST1: vst1${p}.8 \{$vd[$lane]\}, $rn */ |
| 4622 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4623 | }, |
| 4624 | { /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1${p}.8 \{$vd[$lane]\}, $rn$rm */ |
| 4625 | { CS_AC_READ, 0 } |
| 4626 | }, |
| 4627 | { /* ARM_VST1d16, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ |
| 4628 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4629 | }, |
| 4630 | { /* ARM_VST1d16Q, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ |
| 4631 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4632 | }, |
| 4633 | { /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ |
| 4634 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4635 | }, |
| 4636 | { /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ |
| 4637 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4638 | }, |
| 4639 | { /* ARM_VST1d16T, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ |
| 4640 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4641 | }, |
| 4642 | { /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ |
| 4643 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4644 | }, |
| 4645 | { /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ |
| 4646 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4647 | }, |
| 4648 | { /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ |
| 4649 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4650 | }, |
| 4651 | { /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ |
| 4652 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4653 | }, |
| 4654 | { /* ARM_VST1d32, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ |
| 4655 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4656 | }, |
| 4657 | { /* ARM_VST1d32Q, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ |
| 4658 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4659 | }, |
| 4660 | { /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ |
| 4661 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4662 | }, |
| 4663 | { /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ |
| 4664 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4665 | }, |
| 4666 | { /* ARM_VST1d32T, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ |
| 4667 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4668 | }, |
| 4669 | { /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ |
| 4670 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4671 | }, |
| 4672 | { /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ |
| 4673 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4674 | }, |
| 4675 | { /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ |
| 4676 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4677 | }, |
| 4678 | { /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ |
| 4679 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4680 | }, |
| 4681 | { /* ARM_VST1d64, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ |
| 4682 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4683 | }, |
| 4684 | { /* ARM_VST1d64Q, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ |
| 4685 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4686 | }, |
| 4687 | { /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ |
| 4688 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4689 | }, |
| 4690 | { /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ |
| 4691 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4692 | }, |
| 4693 | { /* ARM_VST1d64T, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ |
| 4694 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4695 | }, |
| 4696 | { /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ |
| 4697 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4698 | }, |
| 4699 | { /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ |
| 4700 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4701 | }, |
| 4702 | { /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ |
| 4703 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4704 | }, |
| 4705 | { /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ |
| 4706 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4707 | }, |
| 4708 | { /* ARM_VST1d8, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ |
| 4709 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4710 | }, |
| 4711 | { /* ARM_VST1d8Q, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ |
| 4712 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4713 | }, |
| 4714 | { /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ |
| 4715 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4716 | }, |
| 4717 | { /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ |
| 4718 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4719 | }, |
| 4720 | { /* ARM_VST1d8T, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ |
| 4721 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4722 | }, |
| 4723 | { /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ |
| 4724 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4725 | }, |
| 4726 | { /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ |
| 4727 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4728 | }, |
| 4729 | { /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ |
| 4730 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4731 | }, |
| 4732 | { /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ |
| 4733 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4734 | }, |
| 4735 | { /* ARM_VST1q16, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ |
| 4736 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4737 | }, |
| 4738 | { /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ |
| 4739 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4740 | }, |
| 4741 | { /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ |
| 4742 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4743 | }, |
| 4744 | { /* ARM_VST1q32, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ |
| 4745 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4746 | }, |
| 4747 | { /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ |
| 4748 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4749 | }, |
| 4750 | { /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ |
| 4751 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4752 | }, |
| 4753 | { /* ARM_VST1q64, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ |
| 4754 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4755 | }, |
| 4756 | { /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ |
| 4757 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4758 | }, |
| 4759 | { /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ |
| 4760 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4761 | }, |
| 4762 | { /* ARM_VST1q8, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ |
| 4763 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4764 | }, |
| 4765 | { /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ |
| 4766 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4767 | }, |
| 4768 | { /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ |
| 4769 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4770 | }, |
| 4771 | { /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn */ |
| 4772 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4773 | }, |
| 4774 | { /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ |
| 4775 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4776 | }, |
| 4777 | { /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn */ |
| 4778 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4779 | }, |
| 4780 | { /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ |
| 4781 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4782 | }, |
| 4783 | { /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane], $src2[$lane]\}, $rn */ |
| 4784 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4785 | }, |
| 4786 | { /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ |
| 4787 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4788 | }, |
| 4789 | { /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn */ |
| 4790 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4791 | }, |
| 4792 | { /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ |
| 4793 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4794 | }, |
| 4795 | { /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn */ |
| 4796 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4797 | }, |
| 4798 | { /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ |
| 4799 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4800 | }, |
| 4801 | { /* ARM_VST2b16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ |
| 4802 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4803 | }, |
| 4804 | { /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ |
| 4805 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4806 | }, |
| 4807 | { /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ |
| 4808 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4809 | }, |
| 4810 | { /* ARM_VST2b32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ |
| 4811 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4812 | }, |
| 4813 | { /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ |
| 4814 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4815 | }, |
| 4816 | { /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ |
| 4817 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4818 | }, |
| 4819 | { /* ARM_VST2b8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ |
| 4820 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4821 | }, |
| 4822 | { /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ |
| 4823 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4824 | }, |
| 4825 | { /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ |
| 4826 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4827 | }, |
| 4828 | { /* ARM_VST2d16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ |
| 4829 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4830 | }, |
| 4831 | { /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ |
| 4832 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4833 | }, |
| 4834 | { /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ |
| 4835 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4836 | }, |
| 4837 | { /* ARM_VST2d32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ |
| 4838 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4839 | }, |
| 4840 | { /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ |
| 4841 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4842 | }, |
| 4843 | { /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ |
| 4844 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4845 | }, |
| 4846 | { /* ARM_VST2d8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ |
| 4847 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4848 | }, |
| 4849 | { /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ |
| 4850 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4851 | }, |
| 4852 | { /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ |
| 4853 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4854 | }, |
| 4855 | { /* ARM_VST2q16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ |
| 4856 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4857 | }, |
| 4858 | { /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ |
| 4859 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4860 | }, |
| 4861 | { /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ |
| 4862 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4863 | }, |
| 4864 | { /* ARM_VST2q32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ |
| 4865 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4866 | }, |
| 4867 | { /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ |
| 4868 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4869 | }, |
| 4870 | { /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ |
| 4871 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4872 | }, |
| 4873 | { /* ARM_VST2q8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ |
| 4874 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4875 | }, |
| 4876 | { /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ |
| 4877 | { CS_AC_READ, CS_AC_READ, 0 } |
| 4878 | }, |
| 4879 | { /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ |
| 4880 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4881 | }, |
| 4882 | { /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ |
| 4883 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4884 | }, |
| 4885 | { /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ |
| 4886 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4887 | }, |
| 4888 | { /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ |
| 4889 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4890 | }, |
| 4891 | { /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ |
| 4892 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4893 | }, |
| 4894 | { /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ |
| 4895 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4896 | }, |
| 4897 | { /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ |
| 4898 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4899 | }, |
| 4900 | { /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ |
| 4901 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4902 | }, |
| 4903 | { /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ |
| 4904 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4905 | }, |
| 4906 | { /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ |
| 4907 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4908 | }, |
| 4909 | { /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ |
| 4910 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4911 | }, |
| 4912 | { /* ARM_VST3d16, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn */ |
| 4913 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4914 | }, |
| 4915 | { /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn$rm */ |
| 4916 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4917 | }, |
| 4918 | { /* ARM_VST3d32, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn */ |
| 4919 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4920 | }, |
| 4921 | { /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn$rm */ |
| 4922 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4923 | }, |
| 4924 | { /* ARM_VST3d8, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn */ |
| 4925 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4926 | }, |
| 4927 | { /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn$rm */ |
| 4928 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4929 | }, |
| 4930 | { /* ARM_VST3q16, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn */ |
| 4931 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4932 | }, |
| 4933 | { /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn$rm */ |
| 4934 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4935 | }, |
| 4936 | { /* ARM_VST3q32, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn */ |
| 4937 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4938 | }, |
| 4939 | { /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn$rm */ |
| 4940 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4941 | }, |
| 4942 | { /* ARM_VST3q8, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn */ |
| 4943 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4944 | }, |
| 4945 | { /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn$rm */ |
| 4946 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4947 | }, |
| 4948 | { /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ |
| 4949 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4950 | }, |
| 4951 | { /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ |
| 4952 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4953 | }, |
| 4954 | { /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ |
| 4955 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4956 | }, |
| 4957 | { /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ |
| 4958 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4959 | }, |
| 4960 | { /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ |
| 4961 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4962 | }, |
| 4963 | { /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ |
| 4964 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4965 | }, |
| 4966 | { /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ |
| 4967 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4968 | }, |
| 4969 | { /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ |
| 4970 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4971 | }, |
| 4972 | { /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ |
| 4973 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4974 | }, |
| 4975 | { /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ |
| 4976 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4977 | }, |
| 4978 | { /* ARM_VST4d16, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn */ |
| 4979 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4980 | }, |
| 4981 | { /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn$rm */ |
| 4982 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4983 | }, |
| 4984 | { /* ARM_VST4d32, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn */ |
| 4985 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4986 | }, |
| 4987 | { /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn$rm */ |
| 4988 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4989 | }, |
| 4990 | { /* ARM_VST4d8, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn */ |
| 4991 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4992 | }, |
| 4993 | { /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn$rm */ |
| 4994 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4995 | }, |
| 4996 | { /* ARM_VST4q16, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn */ |
| 4997 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 4998 | }, |
| 4999 | { /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn$rm */ |
| 5000 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5001 | }, |
| 5002 | { /* ARM_VST4q32, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn */ |
| 5003 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5004 | }, |
| 5005 | { /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn$rm */ |
| 5006 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5007 | }, |
| 5008 | { /* ARM_VST4q8, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn */ |
| 5009 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5010 | }, |
| 5011 | { /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn$rm */ |
| 5012 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5013 | }, |
| 5014 | { /* ARM_VSTMDDB_UPD, ARM_INS_VSTMDB: vstmdb${p} $rn!, $regs */ |
| 5015 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 5016 | }, |
| 5017 | { /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia${p} $rn, $regs */ |
| 5018 | { CS_AC_READ, 0 } |
| 5019 | }, |
| 5020 | { /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia${p} $rn!, $regs */ |
| 5021 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 5022 | }, |
| 5023 | { /* ARM_VSTMSDB_UPD, ARM_INS_VSTMDB: vstmdb${p} $rn!, $regs */ |
| 5024 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 5025 | }, |
| 5026 | { /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia${p} $rn, $regs */ |
| 5027 | { CS_AC_READ, 0 } |
| 5028 | }, |
| 5029 | { /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia${p} $rn!, $regs */ |
| 5030 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 5031 | }, |
| 5032 | { /* ARM_VSTRD, ARM_INS_VSTR: vstr${p} $dd, $addr */ |
| 5033 | { CS_AC_READ, 0 } |
| 5034 | }, |
| 5035 | { /* ARM_VSTRS, ARM_INS_VSTR: vstr${p} $sd, $addr */ |
| 5036 | { CS_AC_READ, 0 } |
| 5037 | }, |
| 5038 | { /* ARM_VSUBD, ARM_INS_VSUB: vsub${p}.f64 $dd, $dn, $dm */ |
| 5039 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5040 | }, |
| 5041 | { /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn${p}.i64 $vd, $vn, $vm */ |
| 5042 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5043 | }, |
| 5044 | { /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn${p}.i32 $vd, $vn, $vm */ |
| 5045 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5046 | }, |
| 5047 | { /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn${p}.i16 $vd, $vn, $vm */ |
| 5048 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5049 | }, |
| 5050 | { /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl${p}.s32 $vd, $vn, $vm */ |
| 5051 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5052 | }, |
| 5053 | { /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl${p}.s16 $vd, $vn, $vm */ |
| 5054 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5055 | }, |
| 5056 | { /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl${p}.s8 $vd, $vn, $vm */ |
| 5057 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5058 | }, |
| 5059 | { /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl${p}.u32 $vd, $vn, $vm */ |
| 5060 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5061 | }, |
| 5062 | { /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl${p}.u16 $vd, $vn, $vm */ |
| 5063 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5064 | }, |
| 5065 | { /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl${p}.u8 $vd, $vn, $vm */ |
| 5066 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5067 | }, |
| 5068 | { /* ARM_VSUBS, ARM_INS_VSUB: vsub${p}.f32 $sd, $sn, $sm */ |
| 5069 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5070 | }, |
| 5071 | { /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw${p}.s32 $vd, $vn, $vm */ |
| 5072 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5073 | }, |
| 5074 | { /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw${p}.s16 $vd, $vn, $vm */ |
| 5075 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5076 | }, |
| 5077 | { /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw${p}.s8 $vd, $vn, $vm */ |
| 5078 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5079 | }, |
| 5080 | { /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw${p}.u32 $vd, $vn, $vm */ |
| 5081 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5082 | }, |
| 5083 | { /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw${p}.u16 $vd, $vn, $vm */ |
| 5084 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5085 | }, |
| 5086 | { /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw${p}.u8 $vd, $vn, $vm */ |
| 5087 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5088 | }, |
| 5089 | { /* ARM_VSUBfd, ARM_INS_VSUB: vsub${p}.f32 $vd, $vn, $vm */ |
| 5090 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5091 | }, |
| 5092 | { /* ARM_VSUBfq, ARM_INS_VSUB: vsub${p}.f32 $vd, $vn, $vm */ |
| 5093 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5094 | }, |
| 5095 | { /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub${p}.i8 $vd, $vn, $vm */ |
| 5096 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5097 | }, |
| 5098 | { /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub${p}.i64 $vd, $vn, $vm */ |
| 5099 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5100 | }, |
| 5101 | { /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub${p}.i32 $vd, $vn, $vm */ |
| 5102 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5103 | }, |
| 5104 | { /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub${p}.i64 $vd, $vn, $vm */ |
| 5105 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5106 | }, |
| 5107 | { /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub${p}.i16 $vd, $vn, $vm */ |
| 5108 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5109 | }, |
| 5110 | { /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub${p}.i32 $vd, $vn, $vm */ |
| 5111 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5112 | }, |
| 5113 | { /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub${p}.i16 $vd, $vn, $vm */ |
| 5114 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5115 | }, |
| 5116 | { /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub${p}.i8 $vd, $vn, $vm */ |
| 5117 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5118 | }, |
| 5119 | { /* ARM_VSWPd, ARM_INS_VSWP: vswp${p} $vd, $vm */ |
| 5120 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5121 | }, |
| 5122 | { /* ARM_VSWPq, ARM_INS_VSWP: vswp${p} $vd, $vm */ |
| 5123 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5124 | }, |
| 5125 | { /* ARM_VTBL1, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ |
| 5126 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5127 | }, |
| 5128 | { /* ARM_VTBL2, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ |
| 5129 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5130 | }, |
| 5131 | { /* ARM_VTBL3, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ |
| 5132 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5133 | }, |
| 5134 | { /* ARM_VTBL4, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ |
| 5135 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5136 | }, |
| 5137 | { /* ARM_VTBX1, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ |
| 5138 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5139 | }, |
| 5140 | { /* ARM_VTBX2, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ |
| 5141 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5142 | }, |
| 5143 | { /* ARM_VTBX3, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ |
| 5144 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5145 | }, |
| 5146 | { /* ARM_VTBX4, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ |
| 5147 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5148 | }, |
| 5149 | { /* ARM_VTOSHD, ARM_INS_VCVT: vcvt${p}.s16.f64 $dst, $a, $fbits */ |
| 5150 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5151 | }, |
| 5152 | { /* ARM_VTOSHS, ARM_INS_VCVT: vcvt${p}.s16.f32 $dst, $a, $fbits */ |
| 5153 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5154 | }, |
| 5155 | { /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr${p}.s32.f64 $sd, $dm */ |
| 5156 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5157 | }, |
| 5158 | { /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr${p}.s32.f32 $sd, $sm */ |
| 5159 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5160 | }, |
| 5161 | { /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt${p}.s32.f64 $sd, $dm */ |
| 5162 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5163 | }, |
| 5164 | { /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt${p}.s32.f32 $sd, $sm */ |
| 5165 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5166 | }, |
| 5167 | { /* ARM_VTOSLD, ARM_INS_VCVT: vcvt${p}.s32.f64 $dst, $a, $fbits */ |
| 5168 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5169 | }, |
| 5170 | { /* ARM_VTOSLS, ARM_INS_VCVT: vcvt${p}.s32.f32 $dst, $a, $fbits */ |
| 5171 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5172 | }, |
| 5173 | { /* ARM_VTOUHD, ARM_INS_VCVT: vcvt${p}.u16.f64 $dst, $a, $fbits */ |
| 5174 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5175 | }, |
| 5176 | { /* ARM_VTOUHS, ARM_INS_VCVT: vcvt${p}.u16.f32 $dst, $a, $fbits */ |
| 5177 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5178 | }, |
| 5179 | { /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr${p}.u32.f64 $sd, $dm */ |
| 5180 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5181 | }, |
| 5182 | { /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr${p}.u32.f32 $sd, $sm */ |
| 5183 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5184 | }, |
| 5185 | { /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt${p}.u32.f64 $sd, $dm */ |
| 5186 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5187 | }, |
| 5188 | { /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt${p}.u32.f32 $sd, $sm */ |
| 5189 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5190 | }, |
| 5191 | { /* ARM_VTOULD, ARM_INS_VCVT: vcvt${p}.u32.f64 $dst, $a, $fbits */ |
| 5192 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5193 | }, |
| 5194 | { /* ARM_VTOULS, ARM_INS_VCVT: vcvt${p}.u32.f32 $dst, $a, $fbits */ |
| 5195 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5196 | }, |
| 5197 | { /* ARM_VTRNd16, ARM_INS_VTRN: vtrn${p}.16 $vd, $vm */ |
| 5198 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5199 | }, |
| 5200 | { /* ARM_VTRNd32, ARM_INS_VTRN: vtrn${p}.32 $vd, $vm */ |
| 5201 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5202 | }, |
| 5203 | { /* ARM_VTRNd8, ARM_INS_VTRN: vtrn${p}.8 $vd, $vm */ |
| 5204 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5205 | }, |
| 5206 | { /* ARM_VTRNq16, ARM_INS_VTRN: vtrn${p}.16 $vd, $vm */ |
| 5207 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5208 | }, |
| 5209 | { /* ARM_VTRNq32, ARM_INS_VTRN: vtrn${p}.32 $vd, $vm */ |
| 5210 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5211 | }, |
| 5212 | { /* ARM_VTRNq8, ARM_INS_VTRN: vtrn${p}.8 $vd, $vm */ |
| 5213 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5214 | }, |
| 5215 | { /* ARM_VTSTv16i8, ARM_INS_VTST: vtst${p}.8 $vd, $vn, $vm */ |
| 5216 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5217 | }, |
| 5218 | { /* ARM_VTSTv2i32, ARM_INS_VTST: vtst${p}.32 $vd, $vn, $vm */ |
| 5219 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5220 | }, |
| 5221 | { /* ARM_VTSTv4i16, ARM_INS_VTST: vtst${p}.16 $vd, $vn, $vm */ |
| 5222 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5223 | }, |
| 5224 | { /* ARM_VTSTv4i32, ARM_INS_VTST: vtst${p}.32 $vd, $vn, $vm */ |
| 5225 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5226 | }, |
| 5227 | { /* ARM_VTSTv8i16, ARM_INS_VTST: vtst${p}.16 $vd, $vn, $vm */ |
| 5228 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5229 | }, |
| 5230 | { /* ARM_VTSTv8i8, ARM_INS_VTST: vtst${p}.8 $vd, $vn, $vm */ |
| 5231 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5232 | }, |
| 5233 | { /* ARM_VUHTOD, ARM_INS_VCVT: vcvt${p}.f64.u16 $dst, $a, $fbits */ |
| 5234 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5235 | }, |
| 5236 | { /* ARM_VUHTOS, ARM_INS_VCVT: vcvt${p}.f32.u16 $dst, $a, $fbits */ |
| 5237 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5238 | }, |
| 5239 | { /* ARM_VUITOD, ARM_INS_VCVT: vcvt${p}.f64.u32 $dd, $sm */ |
| 5240 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5241 | }, |
| 5242 | { /* ARM_VUITOS, ARM_INS_VCVT: vcvt${p}.f32.u32 $sd, $sm */ |
| 5243 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5244 | }, |
| 5245 | { /* ARM_VULTOD, ARM_INS_VCVT: vcvt${p}.f64.u32 $dst, $a, $fbits */ |
| 5246 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5247 | }, |
| 5248 | { /* ARM_VULTOS, ARM_INS_VCVT: vcvt${p}.f32.u32 $dst, $a, $fbits */ |
| 5249 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } |
| 5250 | }, |
| 5251 | { /* ARM_VUZPd16, ARM_INS_VUZP: vuzp${p}.16 $vd, $vm */ |
| 5252 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5253 | }, |
| 5254 | { /* ARM_VUZPd8, ARM_INS_VUZP: vuzp${p}.8 $vd, $vm */ |
| 5255 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5256 | }, |
| 5257 | { /* ARM_VUZPq16, ARM_INS_VUZP: vuzp${p}.16 $vd, $vm */ |
| 5258 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5259 | }, |
| 5260 | { /* ARM_VUZPq32, ARM_INS_VUZP: vuzp${p}.32 $vd, $vm */ |
| 5261 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5262 | }, |
| 5263 | { /* ARM_VUZPq8, ARM_INS_VUZP: vuzp${p}.8 $vd, $vm */ |
| 5264 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5265 | }, |
| 5266 | { /* ARM_VZIPd16, ARM_INS_VZIP: vzip${p}.16 $vd, $vm */ |
| 5267 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5268 | }, |
| 5269 | { /* ARM_VZIPd8, ARM_INS_VZIP: vzip${p}.8 $vd, $vm */ |
| 5270 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5271 | }, |
| 5272 | { /* ARM_VZIPq16, ARM_INS_VZIP: vzip${p}.16 $vd, $vm */ |
| 5273 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5274 | }, |
| 5275 | { /* ARM_VZIPq32, ARM_INS_VZIP: vzip${p}.32 $vd, $vm */ |
| 5276 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5277 | }, |
| 5278 | { /* ARM_VZIPq8, ARM_INS_VZIP: vzip${p}.8 $vd, $vm */ |
| 5279 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5280 | }, |
| 5281 | { /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs ^ */ |
| 5282 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 5283 | }, |
| 5284 | { /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs ^ */ |
| 5285 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5286 | }, |
| 5287 | { /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs ^ */ |
| 5288 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 5289 | }, |
| 5290 | { /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs ^ */ |
| 5291 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5292 | }, |
| 5293 | { /* ARM_sysLDMIA, ARM_INS_LDM: ldm${p} $rn, $regs ^ */ |
| 5294 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 5295 | }, |
| 5296 | { /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs ^ */ |
| 5297 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5298 | }, |
| 5299 | { /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs ^ */ |
| 5300 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 5301 | }, |
| 5302 | { /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs ^ */ |
| 5303 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5304 | }, |
| 5305 | { /* ARM_sysSTMDA, ARM_INS_STMDA: stmda${p} $rn, $regs ^ */ |
| 5306 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5307 | }, |
| 5308 | { /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs ^ */ |
| 5309 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 5310 | }, |
| 5311 | { /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs ^ */ |
| 5312 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5313 | }, |
| 5314 | { /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs ^ */ |
| 5315 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 5316 | }, |
| 5317 | { /* ARM_sysSTMIA, ARM_INS_STM: stm${p} $rn, $regs ^ */ |
| 5318 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5319 | }, |
| 5320 | { /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs ^ */ |
| 5321 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 5322 | }, |
| 5323 | { /* ARM_sysSTMIB, ARM_INS_STMIB: stmib${p} $rn, $regs ^ */ |
| 5324 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5325 | }, |
| 5326 | { /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs ^ */ |
| 5327 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 5328 | }, |
| 5329 | { /* ARM_t2ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ |
| 5330 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5331 | }, |
| 5332 | { /* ARM_t2ADCrr, ARM_INS_ADC: adc${s}${p}.w $rd, $rn, $rm */ |
| 5333 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5334 | }, |
| 5335 | { /* ARM_t2ADCrs, ARM_INS_ADC: adc${s}${p}.w $rd, $rn, $shiftedrm */ |
| 5336 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5337 | }, |
| 5338 | { /* ARM_t2ADDri, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $imm */ |
| 5339 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5340 | }, |
| 5341 | { /* ARM_t2ADDri12, ARM_INS_ADDW: addw${p} $rd, $rn, $imm */ |
| 5342 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5343 | }, |
| 5344 | { /* ARM_t2ADDrr, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $rm */ |
| 5345 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5346 | }, |
| 5347 | { /* ARM_t2ADDrs, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $shiftedrm */ |
| 5348 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5349 | }, |
| 5350 | { /* ARM_t2ADR, ARM_INS_ADR: adr{$p}.w $rd, $addr */ |
| 5351 | { CS_AC_WRITE, 0 } |
| 5352 | }, |
| 5353 | { /* ARM_t2ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ |
| 5354 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5355 | }, |
| 5356 | { /* ARM_t2ANDrr, ARM_INS_AND: and${s}${p}.w $rd, $rn, $rm */ |
| 5357 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5358 | }, |
| 5359 | { /* ARM_t2ANDrs, ARM_INS_AND: and${s}${p}.w $rd, $rn, $shiftedrm */ |
| 5360 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5361 | }, |
| 5362 | { /* ARM_t2ASRri, ARM_INS_ASR: asr${s}${p}.w $rd, $rm, $imm */ |
| 5363 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5364 | }, |
| 5365 | { /* ARM_t2ASRrr, ARM_INS_ASR: asr${s}${p}.w $rd, $rn, $rm */ |
| 5366 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5367 | }, |
| 5368 | { /* ARM_t2B, ARM_INS_B: b${p}.w $target */ |
| 5369 | { 0 } |
| 5370 | }, |
| 5371 | { /* ARM_t2BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ |
| 5372 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 5373 | }, |
| 5374 | { /* ARM_t2BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ |
| 5375 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 5376 | }, |
| 5377 | { /* ARM_t2BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ |
| 5378 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5379 | }, |
| 5380 | { /* ARM_t2BICrr, ARM_INS_BIC: bic${s}${p}.w $rd, $rn, $rm */ |
| 5381 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5382 | }, |
| 5383 | { /* ARM_t2BICrs, ARM_INS_BIC: bic${s}${p}.w $rd, $rn, $shiftedrm */ |
| 5384 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5385 | }, |
| 5386 | { /* ARM_t2BXJ, ARM_INS_BXJ: bxj${p} $func */ |
| 5387 | { CS_AC_READ, 0 } |
| 5388 | }, |
| 5389 | { /* ARM_t2Bcc, ARM_INS_B: b${p}.w $target */ |
| 5390 | { 0 } |
| 5391 | }, |
| 5392 | { /* ARM_t2CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ |
| 5393 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 5394 | }, |
| 5395 | { /* ARM_t2CDP2, ARM_INS_CDP2: cdp2${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ |
| 5396 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 5397 | }, |
| 5398 | { /* ARM_t2CLREX, ARM_INS_CLREX: clrex${p} */ |
| 5399 | { 0 } |
| 5400 | }, |
| 5401 | { /* ARM_t2CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ |
| 5402 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5403 | }, |
| 5404 | { /* ARM_t2CMNri, ARM_INS_CMN: cmn${p}.w $rn, $imm */ |
| 5405 | { CS_AC_READ, 0 } |
| 5406 | }, |
| 5407 | { /* ARM_t2CMNzrr, ARM_INS_CMN: cmn${p}.w $rn, $rm */ |
| 5408 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5409 | }, |
| 5410 | { /* ARM_t2CMNzrs, ARM_INS_CMN: cmn${p}.w $rn, $shiftedrm */ |
| 5411 | { CS_AC_READ, 0 } |
| 5412 | }, |
| 5413 | { /* ARM_t2CMPri, ARM_INS_CMP: cmp${p}.w $rn, $imm */ |
| 5414 | { CS_AC_READ, 0 } |
| 5415 | }, |
| 5416 | { /* ARM_t2CMPrr, ARM_INS_CMP: cmp${p}.w $rn, $rm */ |
| 5417 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5418 | }, |
| 5419 | { /* ARM_t2CMPrs, ARM_INS_CMP: cmp${p}.w $rn, $shiftedrm */ |
| 5420 | { CS_AC_READ, 0 } |
| 5421 | }, |
| 5422 | { /* ARM_t2CPS1p, ARM_INS_CPS: cps $mode */ |
| 5423 | { 0 } |
| 5424 | }, |
| 5425 | { /* ARM_t2CPS2p, ARM_INS_CPS: cps$imod.w $iflags */ |
| 5426 | { 0 } |
| 5427 | }, |
| 5428 | { /* ARM_t2CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ |
| 5429 | { 0 } |
| 5430 | }, |
| 5431 | { /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ |
| 5432 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5433 | }, |
| 5434 | { /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ |
| 5435 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5436 | }, |
| 5437 | { /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ |
| 5438 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5439 | }, |
| 5440 | { /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ |
| 5441 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5442 | }, |
| 5443 | { /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ |
| 5444 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5445 | }, |
| 5446 | { /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ |
| 5447 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5448 | }, |
| 5449 | { /* ARM_t2DBG, ARM_INS_DBG: dbg${p} $opt */ |
| 5450 | { 0 } |
| 5451 | }, |
| 5452 | { /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1${p} */ |
| 5453 | { 0 } |
| 5454 | }, |
| 5455 | { /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2${p} */ |
| 5456 | { 0 } |
| 5457 | }, |
| 5458 | { /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3${p} */ |
| 5459 | { 0 } |
| 5460 | }, |
| 5461 | { /* ARM_t2DMB, ARM_INS_DMB: dmb${p} $opt */ |
| 5462 | { 0 } |
| 5463 | }, |
| 5464 | { /* ARM_t2DSB, ARM_INS_DSB: dsb${p} $opt */ |
| 5465 | { 0 } |
| 5466 | }, |
| 5467 | { /* ARM_t2EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ |
| 5468 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5469 | }, |
| 5470 | { /* ARM_t2EORrr, ARM_INS_EOR: eor${s}${p}.w $rd, $rn, $rm */ |
| 5471 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5472 | }, |
| 5473 | { /* ARM_t2EORrs, ARM_INS_EOR: eor${s}${p}.w $rd, $rn, $shiftedrm */ |
| 5474 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5475 | }, |
| 5476 | { /* ARM_t2HINT, ARM_INS_HINT: hint${p}.w $imm */ |
| 5477 | { 0 } |
| 5478 | }, |
| 5479 | { /* ARM_t2HVC, ARM_INS_HVC: hvc.w $imm16 */ |
| 5480 | { 0 } |
| 5481 | }, |
| 5482 | { /* ARM_t2ISB, ARM_INS_ISB: isb${p} $opt */ |
| 5483 | { 0 } |
| 5484 | }, |
| 5485 | { /* ARM_t2IT, ARM_INS_IT: it$mask $cc */ |
| 5486 | { 0 } |
| 5487 | }, |
| 5488 | { /* ARM_t2LDA, ARM_INS_LDA: lda${p} $rt, $addr */ |
| 5489 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5490 | }, |
| 5491 | { /* ARM_t2LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ |
| 5492 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5493 | }, |
| 5494 | { /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ |
| 5495 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5496 | }, |
| 5497 | { /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ |
| 5498 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5499 | }, |
| 5500 | { /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $rt2, $addr */ |
| 5501 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 5502 | }, |
| 5503 | { /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ |
| 5504 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5505 | }, |
| 5506 | { /* ARM_t2LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ |
| 5507 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5508 | }, |
| 5509 | { /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr */ |
| 5510 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5511 | }, |
| 5512 | { /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $option */ |
| 5513 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5514 | }, |
| 5515 | { /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $offset */ |
| 5516 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5517 | }, |
| 5518 | { /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr! */ |
| 5519 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5520 | }, |
| 5521 | { /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr */ |
| 5522 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5523 | }, |
| 5524 | { /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $option */ |
| 5525 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5526 | }, |
| 5527 | { /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $offset */ |
| 5528 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5529 | }, |
| 5530 | { /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr! */ |
| 5531 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5532 | }, |
| 5533 | { /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ |
| 5534 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5535 | }, |
| 5536 | { /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ |
| 5537 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5538 | }, |
| 5539 | { /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ |
| 5540 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5541 | }, |
| 5542 | { /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ |
| 5543 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5544 | }, |
| 5545 | { /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ |
| 5546 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5547 | }, |
| 5548 | { /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ |
| 5549 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5550 | }, |
| 5551 | { /* ARM_t2LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ |
| 5552 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5553 | }, |
| 5554 | { /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ |
| 5555 | { CS_AC_READ, CS_AC_READ, 0 } |
| 5556 | }, |
| 5557 | { /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ |
| 5558 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 5559 | }, |
| 5560 | { /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ |
| 5561 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5562 | }, |
| 5563 | { /* ARM_t2LDMIA, ARM_INS_LDM: ldm${p}.w $rn, $regs */ |
| 5564 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 5565 | }, |
| 5566 | { /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm${p}.w $rn!, $regs */ |
| 5567 | { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5568 | }, |
| 5569 | { /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt${p} $rt, $addr */ |
| 5570 | { CS_AC_WRITE, 0 } |
| 5571 | }, |
| 5572 | { /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb${p} $rt, $rn$offset */ |
| 5573 | { CS_AC_WRITE, 0 } |
| 5574 | }, |
| 5575 | { /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ |
| 5576 | { CS_AC_WRITE, 0 } |
| 5577 | }, |
| 5578 | { /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ |
| 5579 | { CS_AC_WRITE, 0 } |
| 5580 | }, |
| 5581 | { /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb${p} $rt, $addr */ |
| 5582 | { CS_AC_WRITE, 0 } |
| 5583 | }, |
| 5584 | { /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ |
| 5585 | { CS_AC_WRITE, 0 } |
| 5586 | }, |
| 5587 | { /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ |
| 5588 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5589 | }, |
| 5590 | { /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr$imm */ |
| 5591 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5592 | }, |
| 5593 | { /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ |
| 5594 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5595 | }, |
| 5596 | { /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ |
| 5597 | { CS_AC_WRITE, CS_AC_WRITE, 0 } |
| 5598 | }, |
| 5599 | { /* ARM_t2LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ |
| 5600 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5601 | }, |
| 5602 | { /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ |
| 5603 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5604 | }, |
| 5605 | { /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $rt2, $addr */ |
| 5606 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } |
| 5607 | }, |
| 5608 | { /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ |
| 5609 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5610 | }, |
| 5611 | { /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht${p} $rt, $addr */ |
| 5612 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5613 | }, |
| 5614 | { /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $rn$offset */ |
| 5615 | { CS_AC_WRITE, 0 } |
| 5616 | }, |
| 5617 | { /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ |
| 5618 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5619 | }, |
| 5620 | { /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ |
| 5621 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5622 | }, |
| 5623 | { /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh${p} $rt, $addr */ |
| 5624 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5625 | }, |
| 5626 | { /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ |
| 5627 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5628 | }, |
| 5629 | { /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ |
| 5630 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5631 | }, |
| 5632 | { /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr */ |
| 5633 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5634 | }, |
| 5635 | { /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $rn$offset */ |
| 5636 | { CS_AC_WRITE, 0 } |
| 5637 | }, |
| 5638 | { /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ |
| 5639 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5640 | }, |
| 5641 | { /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ |
| 5642 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5643 | }, |
| 5644 | { /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ |
| 5645 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5646 | }, |
| 5647 | { /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ |
| 5648 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5649 | }, |
| 5650 | { /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ |
| 5651 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5652 | }, |
| 5653 | { /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr */ |
| 5654 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5655 | }, |
| 5656 | { /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $rn$offset */ |
| 5657 | { CS_AC_WRITE, 0 } |
| 5658 | }, |
| 5659 | { /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ |
| 5660 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5661 | }, |
| 5662 | { /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ |
| 5663 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5664 | }, |
| 5665 | { /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ |
| 5666 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5667 | }, |
| 5668 | { /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ |
| 5669 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5670 | }, |
| 5671 | { /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ |
| 5672 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5673 | }, |
| 5674 | { /* ARM_t2LDRT, ARM_INS_LDRT: ldrt${p} $rt, $addr */ |
| 5675 | { CS_AC_WRITE, 0 } |
| 5676 | }, |
| 5677 | { /* ARM_t2LDR_POST, ARM_INS_LDR: ldr${p} $rt, $rn$offset */ |
| 5678 | { CS_AC_WRITE, 0 } |
| 5679 | }, |
| 5680 | { /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr${p} $rt, $addr! */ |
| 5681 | { CS_AC_WRITE, 0 } |
| 5682 | }, |
| 5683 | { /* ARM_t2LDRi12, ARM_INS_LDR: ldr${p}.w $rt, $addr */ |
| 5684 | { CS_AC_WRITE, 0 } |
| 5685 | }, |
| 5686 | { /* ARM_t2LDRi8, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| 5687 | { CS_AC_WRITE, 0 } |
| 5688 | }, |
| 5689 | { /* ARM_t2LDRpci, ARM_INS_LDR: ldr${p}.w $rt, $addr */ |
| 5690 | { CS_AC_WRITE, 0 } |
| 5691 | }, |
| 5692 | { /* ARM_t2LDRs, ARM_INS_LDR: ldr${p}.w $rt, $addr */ |
| 5693 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5694 | }, |
| 5695 | { /* ARM_t2LSLri, ARM_INS_LSL: lsl${s}${p}.w $rd, $rm, $imm */ |
| 5696 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5697 | }, |
| 5698 | { /* ARM_t2LSLrr, ARM_INS_LSL: lsl${s}${p}.w $rd, $rn, $rm */ |
| 5699 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5700 | }, |
| 5701 | { /* ARM_t2LSRri, ARM_INS_LSR: lsr${s}${p}.w $rd, $rm, $imm */ |
| 5702 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5703 | }, |
| 5704 | { /* ARM_t2LSRrr, ARM_INS_LSR: lsr${s}${p}.w $rd, $rn, $rm */ |
| 5705 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5706 | }, |
| 5707 | { /* ARM_t2MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| 5708 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 5709 | }, |
| 5710 | { /* ARM_t2MCR2, ARM_INS_MCR2: mcr2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| 5711 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 5712 | }, |
| 5713 | { /* ARM_t2MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ |
| 5714 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5715 | }, |
| 5716 | { /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2${p} $cop, $opc1, $rt, $rt2, $crm */ |
| 5717 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5718 | }, |
| 5719 | { /* ARM_t2MLA, ARM_INS_MLA: mla${p} $rd, $rn, $rm, $ra */ |
| 5720 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5721 | }, |
| 5722 | { /* ARM_t2MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ |
| 5723 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5724 | }, |
| 5725 | { /* ARM_t2MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ |
| 5726 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 5727 | }, |
| 5728 | { /* ARM_t2MOVi, ARM_INS_MOV: mov${s}${p}.w $rd, $imm */ |
| 5729 | { CS_AC_WRITE, 0 } |
| 5730 | }, |
| 5731 | { /* ARM_t2MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ |
| 5732 | { CS_AC_WRITE, 0 } |
| 5733 | }, |
| 5734 | { /* ARM_t2MOVr, ARM_INS_MOV: mov${s}${p}.w $rd, $rm */ |
| 5735 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5736 | }, |
| 5737 | { /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd, $rm, #1 */ |
| 5738 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5739 | }, |
| 5740 | { /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd, $rm, #1 */ |
| 5741 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5742 | }, |
| 5743 | { /* ARM_t2MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| 5744 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 5745 | }, |
| 5746 | { /* ARM_t2MRC2, ARM_INS_MRC2: mrc2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ |
| 5747 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } |
| 5748 | }, |
| 5749 | { /* ARM_t2MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ |
| 5750 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5751 | }, |
| 5752 | { /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2${p} $cop, $opc1, $rt, $rt2, $crm */ |
| 5753 | { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5754 | }, |
| 5755 | { /* ARM_t2MRS_AR, ARM_INS_MRS: mrs${p} $rd, apsr */ |
| 5756 | { CS_AC_WRITE, 0 } |
| 5757 | }, |
| 5758 | { /* ARM_t2MRS_M, ARM_INS_MRS: mrs${p} $rd, $sysm */ |
| 5759 | { CS_AC_WRITE, 0 } |
| 5760 | }, |
| 5761 | { /* ARM_t2MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ |
| 5762 | { CS_AC_WRITE, 0 } |
| 5763 | }, |
| 5764 | { /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs${p} $rd, spsr */ |
| 5765 | { CS_AC_WRITE, 0 } |
| 5766 | }, |
| 5767 | { /* ARM_t2MSR_AR, ARM_INS_MSR: msr${p} $mask, $rn */ |
| 5768 | { CS_AC_READ, 0 } |
| 5769 | }, |
| 5770 | { /* ARM_t2MSR_M, ARM_INS_MSR: msr${p} $sysm, $rn */ |
| 5771 | { CS_AC_READ, 0 } |
| 5772 | }, |
| 5773 | { /* ARM_t2MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ |
| 5774 | { CS_AC_READ, 0 } |
| 5775 | }, |
| 5776 | { /* ARM_t2MUL, ARM_INS_MUL: mul${p} $rd, $rn, $rm */ |
| 5777 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5778 | }, |
| 5779 | { /* ARM_t2MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ |
| 5780 | { CS_AC_WRITE, 0 } |
| 5781 | }, |
| 5782 | { /* ARM_t2MVNr, ARM_INS_MVN: mvn${s}${p}.w $rd, $rm */ |
| 5783 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5784 | }, |
| 5785 | { /* ARM_t2MVNs, ARM_INS_MVN: mvn${s}${p}.w $rd, $shiftedrm */ |
| 5786 | { CS_AC_WRITE, 0 } |
| 5787 | }, |
| 5788 | { /* ARM_t2ORNri, ARM_INS_ORN: orn${s}${p} $rd, $rn, $imm */ |
| 5789 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5790 | }, |
| 5791 | { /* ARM_t2ORNrr, ARM_INS_ORN: orn${s}${p} $rd, $rn, $rm */ |
| 5792 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5793 | }, |
| 5794 | { /* ARM_t2ORNrs, ARM_INS_ORN: orn${s}${p} $rd, $rn, $shiftedrm */ |
| 5795 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5796 | }, |
| 5797 | { /* ARM_t2ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ |
| 5798 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5799 | }, |
| 5800 | { /* ARM_t2ORRrr, ARM_INS_ORR: orr${s}${p}.w $rd, $rn, $rm */ |
| 5801 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5802 | }, |
| 5803 | { /* ARM_t2ORRrs, ARM_INS_ORR: orr${s}${p}.w $rd, $rn, $shiftedrm */ |
| 5804 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5805 | }, |
| 5806 | { /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ |
| 5807 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5808 | }, |
| 5809 | { /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ |
| 5810 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5811 | }, |
| 5812 | { /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw${p} $addr */ |
| 5813 | { CS_AC_READ, 0 } |
| 5814 | }, |
| 5815 | { /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw${p} $addr */ |
| 5816 | { CS_AC_READ, 0 } |
| 5817 | }, |
| 5818 | { /* ARM_t2PLDWs, ARM_INS_PLDW: pldw${p} $addr */ |
| 5819 | { CS_AC_READ, 0 } |
| 5820 | }, |
| 5821 | { /* ARM_t2PLDi12, ARM_INS_PLD: pld${p} $addr */ |
| 5822 | { CS_AC_READ, 0 } |
| 5823 | }, |
| 5824 | { /* ARM_t2PLDi8, ARM_INS_PLD: pld${p} $addr */ |
| 5825 | { CS_AC_READ, 0 } |
| 5826 | }, |
| 5827 | { /* ARM_t2PLDpci, ARM_INS_PLD: pld${p} $addr */ |
| 5828 | { CS_AC_READ, 0 } |
| 5829 | }, |
| 5830 | { /* ARM_t2PLDs, ARM_INS_PLD: pld${p} $addr */ |
| 5831 | { CS_AC_READ, 0 } |
| 5832 | }, |
| 5833 | { /* ARM_t2PLIi12, ARM_INS_PLI: pli${p} $addr */ |
| 5834 | { CS_AC_READ, 0 } |
| 5835 | }, |
| 5836 | { /* ARM_t2PLIi8, ARM_INS_PLI: pli${p} $addr */ |
| 5837 | { CS_AC_READ, 0 } |
| 5838 | }, |
| 5839 | { /* ARM_t2PLIpci, ARM_INS_PLI: pli${p} $addr */ |
| 5840 | { CS_AC_READ, 0 } |
| 5841 | }, |
| 5842 | { /* ARM_t2PLIs, ARM_INS_PLI: pli${p} $addr */ |
| 5843 | { CS_AC_READ, 0 } |
| 5844 | }, |
| 5845 | { /* ARM_t2QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ |
| 5846 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5847 | }, |
| 5848 | { /* ARM_t2QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ |
| 5849 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5850 | }, |
| 5851 | { /* ARM_t2QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ |
| 5852 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5853 | }, |
| 5854 | { /* ARM_t2QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ |
| 5855 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5856 | }, |
| 5857 | { /* ARM_t2QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ |
| 5858 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5859 | }, |
| 5860 | { /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ |
| 5861 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5862 | }, |
| 5863 | { /* ARM_t2QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ |
| 5864 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5865 | }, |
| 5866 | { /* ARM_t2QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ |
| 5867 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5868 | }, |
| 5869 | { /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ |
| 5870 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5871 | }, |
| 5872 | { /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ |
| 5873 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5874 | }, |
| 5875 | { /* ARM_t2RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ |
| 5876 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5877 | }, |
| 5878 | { /* ARM_t2REV, ARM_INS_REV: rev${p}.w $rd, $rm */ |
| 5879 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5880 | }, |
| 5881 | { /* ARM_t2REV16, ARM_INS_REV16: rev16${p}.w $rd, $rm */ |
| 5882 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5883 | }, |
| 5884 | { /* ARM_t2REVSH, ARM_INS_REVSH: revsh${p}.w $rd, $rm */ |
| 5885 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5886 | }, |
| 5887 | { /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb${p} $rn */ |
| 5888 | { CS_AC_READ, 0 } |
| 5889 | }, |
| 5890 | { /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb${p} $rn! */ |
| 5891 | { CS_AC_READ, 0 } |
| 5892 | }, |
| 5893 | { /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia${p} $rn */ |
| 5894 | { CS_AC_READ, 0 } |
| 5895 | }, |
| 5896 | { /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia${p} $rn! */ |
| 5897 | { CS_AC_READ, 0 } |
| 5898 | }, |
| 5899 | { /* ARM_t2RORri, ARM_INS_ROR: ror${s}${p}.w $rd, $rm, $imm */ |
| 5900 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5901 | }, |
| 5902 | { /* ARM_t2RORrr, ARM_INS_ROR: ror${s}${p}.w $rd, $rn, $rm */ |
| 5903 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5904 | }, |
| 5905 | { /* ARM_t2RRX, ARM_INS_RRX: rrx${s}${p} $rd, $rm */ |
| 5906 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5907 | }, |
| 5908 | { /* ARM_t2RSBri, ARM_INS_RSB: rsb${s}${p}.w $rd, $rn, $imm */ |
| 5909 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5910 | }, |
| 5911 | { /* ARM_t2RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ |
| 5912 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5913 | }, |
| 5914 | { /* ARM_t2RSBrs, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shiftedrm */ |
| 5915 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5916 | }, |
| 5917 | { /* ARM_t2SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ |
| 5918 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5919 | }, |
| 5920 | { /* ARM_t2SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ |
| 5921 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5922 | }, |
| 5923 | { /* ARM_t2SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ |
| 5924 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5925 | }, |
| 5926 | { /* ARM_t2SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ |
| 5927 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5928 | }, |
| 5929 | { /* ARM_t2SBCrr, ARM_INS_SBC: sbc${s}${p}.w $rd, $rn, $rm */ |
| 5930 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5931 | }, |
| 5932 | { /* ARM_t2SBCrs, ARM_INS_SBC: sbc${s}${p}.w $rd, $rn, $shiftedrm */ |
| 5933 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5934 | }, |
| 5935 | { /* ARM_t2SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $msb */ |
| 5936 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 5937 | }, |
| 5938 | { /* ARM_t2SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ |
| 5939 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5940 | }, |
| 5941 | { /* ARM_t2SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ |
| 5942 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5943 | }, |
| 5944 | { /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ |
| 5945 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5946 | }, |
| 5947 | { /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ |
| 5948 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5949 | }, |
| 5950 | { /* ARM_t2SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ |
| 5951 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5952 | }, |
| 5953 | { /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ |
| 5954 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5955 | }, |
| 5956 | { /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ |
| 5957 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5958 | }, |
| 5959 | { /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ |
| 5960 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5961 | }, |
| 5962 | { /* ARM_t2SMC, ARM_INS_SMC: smc${p} $opt */ |
| 5963 | { 0 } |
| 5964 | }, |
| 5965 | { /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ |
| 5966 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5967 | }, |
| 5968 | { /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ |
| 5969 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5970 | }, |
| 5971 | { /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ |
| 5972 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5973 | }, |
| 5974 | { /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ |
| 5975 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 5976 | }, |
| 5977 | { /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal${p} $rdlo, $rdhi, $rn, $rm */ |
| 5978 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5979 | }, |
| 5980 | { /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $ra, $rd, $rn, $rm */ |
| 5981 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5982 | }, |
| 5983 | { /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $ra, $rd, $rn, $rm */ |
| 5984 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5985 | }, |
| 5986 | { /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald${p} $ra, $rd, $rn, $rm */ |
| 5987 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5988 | }, |
| 5989 | { /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $ra, $rd, $rn, $rm */ |
| 5990 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5991 | }, |
| 5992 | { /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $ra, $rd, $rn, $rm */ |
| 5993 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5994 | }, |
| 5995 | { /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $ra, $rd, $rn, $rm */ |
| 5996 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 5997 | }, |
| 5998 | { /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ |
| 5999 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6000 | }, |
| 6001 | { /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ |
| 6002 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6003 | }, |
| 6004 | { /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ |
| 6005 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6006 | }, |
| 6007 | { /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ |
| 6008 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6009 | }, |
| 6010 | { /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ |
| 6011 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6012 | }, |
| 6013 | { /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ |
| 6014 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6015 | }, |
| 6016 | { /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld${p} $ra, $rd, $rn, $rm */ |
| 6017 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6018 | }, |
| 6019 | { /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $ra, $rd, $rn, $rm */ |
| 6020 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6021 | }, |
| 6022 | { /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ |
| 6023 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6024 | }, |
| 6025 | { /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ |
| 6026 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6027 | }, |
| 6028 | { /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ |
| 6029 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6030 | }, |
| 6031 | { /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ |
| 6032 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6033 | }, |
| 6034 | { /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ |
| 6035 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6036 | }, |
| 6037 | { /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ |
| 6038 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6039 | }, |
| 6040 | { /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ |
| 6041 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6042 | }, |
| 6043 | { /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ |
| 6044 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6045 | }, |
| 6046 | { /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ |
| 6047 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6048 | }, |
| 6049 | { /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ |
| 6050 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6051 | }, |
| 6052 | { /* ARM_t2SMULL, ARM_INS_SMULL: smull${p} $rdlo, $rdhi, $rn, $rm */ |
| 6053 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6054 | }, |
| 6055 | { /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ |
| 6056 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6057 | }, |
| 6058 | { /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ |
| 6059 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6060 | }, |
| 6061 | { /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ |
| 6062 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6063 | }, |
| 6064 | { /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ |
| 6065 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6066 | }, |
| 6067 | { /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ |
| 6068 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6069 | }, |
| 6070 | { /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ |
| 6071 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6072 | }, |
| 6073 | { /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb${p} sp, $mode */ |
| 6074 | { 0 } |
| 6075 | }, |
| 6076 | { /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb${p} sp!, $mode */ |
| 6077 | { 0 } |
| 6078 | }, |
| 6079 | { /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia${p} sp, $mode */ |
| 6080 | { 0 } |
| 6081 | }, |
| 6082 | { /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia${p} sp!, $mode */ |
| 6083 | { 0 } |
| 6084 | }, |
| 6085 | { /* ARM_t2SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ |
| 6086 | { CS_AC_WRITE, 0 } |
| 6087 | }, |
| 6088 | { /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ |
| 6089 | { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } |
| 6090 | }, |
| 6091 | { /* ARM_t2SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ |
| 6092 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6093 | }, |
| 6094 | { /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ |
| 6095 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6096 | }, |
| 6097 | { /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ |
| 6098 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6099 | }, |
| 6100 | { /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr */ |
| 6101 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6102 | }, |
| 6103 | { /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $option */ |
| 6104 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6105 | }, |
| 6106 | { /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $offset */ |
| 6107 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6108 | }, |
| 6109 | { /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr! */ |
| 6110 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6111 | }, |
| 6112 | { /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2${p} $cop, $crd, $addr */ |
| 6113 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6114 | }, |
| 6115 | { /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $option */ |
| 6116 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6117 | }, |
| 6118 | { /* ARM_t2STC2_POST, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $offset */ |
| 6119 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6120 | }, |
| 6121 | { /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2${p} $cop, $crd, $addr! */ |
| 6122 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6123 | }, |
| 6124 | { /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ |
| 6125 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6126 | }, |
| 6127 | { /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ |
| 6128 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6129 | }, |
| 6130 | { /* ARM_t2STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ |
| 6131 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6132 | }, |
| 6133 | { /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ |
| 6134 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6135 | }, |
| 6136 | { /* ARM_t2STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ |
| 6137 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6138 | }, |
| 6139 | { /* ARM_t2STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ |
| 6140 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6141 | }, |
| 6142 | { /* ARM_t2STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ |
| 6143 | { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6144 | }, |
| 6145 | { /* ARM_t2STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ |
| 6146 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6147 | }, |
| 6148 | { /* ARM_t2STL, ARM_INS_STL: stl${p} $rt, $addr */ |
| 6149 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6150 | }, |
| 6151 | { /* ARM_t2STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ |
| 6152 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6153 | }, |
| 6154 | { /* ARM_t2STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ |
| 6155 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6156 | }, |
| 6157 | { /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ |
| 6158 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6159 | }, |
| 6160 | { /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $rt2, $addr */ |
| 6161 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6162 | }, |
| 6163 | { /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ |
| 6164 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6165 | }, |
| 6166 | { /* ARM_t2STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ |
| 6167 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6168 | }, |
| 6169 | { /* ARM_t2STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ |
| 6170 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6171 | }, |
| 6172 | { /* ARM_t2STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ |
| 6173 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6174 | }, |
| 6175 | { /* ARM_t2STMIA, ARM_INS_STM: stm${p}.w $rn, $regs */ |
| 6176 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6177 | }, |
| 6178 | { /* ARM_t2STMIA_UPD, ARM_INS_STM: stm${p}.w $rn!, $regs */ |
| 6179 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6180 | }, |
| 6181 | { /* ARM_t2STRBT, ARM_INS_STRBT: strbt${p} $rt, $addr */ |
| 6182 | { CS_AC_WRITE, 0 } |
| 6183 | }, |
| 6184 | { /* ARM_t2STRB_POST, ARM_INS_STRB: strb${p} $rt, $rn$offset */ |
| 6185 | { CS_AC_READ, 0 } |
| 6186 | }, |
| 6187 | { /* ARM_t2STRB_PRE, ARM_INS_STRB: strb${p} $rt, $addr! */ |
| 6188 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6189 | }, |
| 6190 | { /* ARM_t2STRBi12, ARM_INS_STRB: strb${p}.w $rt, $addr */ |
| 6191 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6192 | }, |
| 6193 | { /* ARM_t2STRBi8, ARM_INS_STRB: strb${p} $rt, $addr */ |
| 6194 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6195 | }, |
| 6196 | { /* ARM_t2STRBs, ARM_INS_STRB: strb${p}.w $rt, $addr */ |
| 6197 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6198 | }, |
| 6199 | { /* ARM_t2STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr$imm */ |
| 6200 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6201 | }, |
| 6202 | { /* ARM_t2STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ |
| 6203 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6204 | }, |
| 6205 | { /* ARM_t2STRDi8, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ |
| 6206 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6207 | }, |
| 6208 | { /* ARM_t2STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ |
| 6209 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6210 | }, |
| 6211 | { /* ARM_t2STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ |
| 6212 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6213 | }, |
| 6214 | { /* ARM_t2STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $rt2, $addr */ |
| 6215 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6216 | }, |
| 6217 | { /* ARM_t2STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ |
| 6218 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6219 | }, |
| 6220 | { /* ARM_t2STRHT, ARM_INS_STRHT: strht${p} $rt, $addr */ |
| 6221 | { CS_AC_WRITE, 0 } |
| 6222 | }, |
| 6223 | { /* ARM_t2STRH_POST, ARM_INS_STRH: strh${p} $rt, $rn$offset */ |
| 6224 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6225 | }, |
| 6226 | { /* ARM_t2STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ |
| 6227 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6228 | }, |
| 6229 | { /* ARM_t2STRHi12, ARM_INS_STRH: strh${p}.w $rt, $addr */ |
| 6230 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6231 | }, |
| 6232 | { /* ARM_t2STRHi8, ARM_INS_STRH: strh${p} $rt, $addr */ |
| 6233 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6234 | }, |
| 6235 | { /* ARM_t2STRHs, ARM_INS_STRH: strh${p}.w $rt, $addr */ |
| 6236 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6237 | }, |
| 6238 | { /* ARM_t2STRT, ARM_INS_STRT: strt${p} $rt, $addr */ |
| 6239 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6240 | }, |
| 6241 | { /* ARM_t2STR_POST, ARM_INS_STR: str${p} $rt, $rn$offset */ |
| 6242 | { CS_AC_READ, 0 } |
| 6243 | }, |
| 6244 | { /* ARM_t2STR_PRE, ARM_INS_STR: str${p} $rt, $addr! */ |
| 6245 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6246 | }, |
| 6247 | { /* ARM_t2STRi12, ARM_INS_STR: str${p}.w $rt, $addr */ |
| 6248 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6249 | }, |
| 6250 | { /* ARM_t2STRi8, ARM_INS_STR: str${p} $rt, $addr */ |
| 6251 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6252 | }, |
| 6253 | { /* ARM_t2STRs, ARM_INS_STR: str${p}.w $rt, $addr */ |
| 6254 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6255 | }, |
| 6256 | { /* ARM_t2SUBS_PC_LR, ARM_INS_SUB: subs${p} pc, lr, $imm */ |
| 6257 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6258 | }, |
| 6259 | { /* ARM_t2SUBri, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $imm */ |
| 6260 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6261 | }, |
| 6262 | { /* ARM_t2SUBri12, ARM_INS_SUBW: subw${p} $rd, $rn, $imm */ |
| 6263 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6264 | }, |
| 6265 | { /* ARM_t2SUBrr, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $rm */ |
| 6266 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6267 | }, |
| 6268 | { /* ARM_t2SUBrs, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $shiftedrm */ |
| 6269 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6270 | }, |
| 6271 | { /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ |
| 6272 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6273 | }, |
| 6274 | { /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ |
| 6275 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6276 | }, |
| 6277 | { /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ |
| 6278 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6279 | }, |
| 6280 | { /* ARM_t2SXTB, ARM_INS_SXTB: sxtb${p}.w $rd, $rm$rot */ |
| 6281 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6282 | }, |
| 6283 | { /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ |
| 6284 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6285 | }, |
| 6286 | { /* ARM_t2SXTH, ARM_INS_SXTH: sxth${p}.w $rd, $rm$rot */ |
| 6287 | { CS_AC_WRITE, 0 } |
| 6288 | }, |
| 6289 | { /* ARM_t2TBB, ARM_INS_TBB: tbb${p} $addr */ |
| 6290 | { CS_AC_READ, 0 } |
| 6291 | }, |
| 6292 | { /* ARM_t2TBH, ARM_INS_TBH: tbh${p} $addr */ |
| 6293 | { CS_AC_READ, 0 } |
| 6294 | }, |
| 6295 | { /* ARM_t2TEQri, ARM_INS_TEQ: teq${p}.w $rn, $imm */ |
| 6296 | { CS_AC_READ, 0 } |
| 6297 | }, |
| 6298 | { /* ARM_t2TEQrr, ARM_INS_TEQ: teq${p}.w $rn, $rm */ |
| 6299 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6300 | }, |
| 6301 | { /* ARM_t2TEQrs, ARM_INS_TEQ: teq${p}.w $rn, $shiftedrm */ |
| 6302 | { CS_AC_READ, 0 } |
| 6303 | }, |
| 6304 | { /* ARM_t2TSTri, ARM_INS_TST: tst${p}.w $rn, $imm */ |
| 6305 | { CS_AC_READ, 0 } |
| 6306 | }, |
| 6307 | { /* ARM_t2TSTrr, ARM_INS_TST: tst${p}.w $rn, $rm */ |
| 6308 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6309 | }, |
| 6310 | { /* ARM_t2TSTrs, ARM_INS_TST: tst${p}.w $rn, $shiftedrm */ |
| 6311 | { CS_AC_READ, 0 } |
| 6312 | }, |
| 6313 | { /* ARM_t2UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ |
| 6314 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6315 | }, |
| 6316 | { /* ARM_t2UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ |
| 6317 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6318 | }, |
| 6319 | { /* ARM_t2UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ |
| 6320 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6321 | }, |
| 6322 | { /* ARM_t2UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $msb */ |
| 6323 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6324 | }, |
| 6325 | { /* ARM_t2UDF, ARM_INS_UDF: udf.w $imm16 */ |
| 6326 | { 0 } |
| 6327 | }, |
| 6328 | { /* ARM_t2UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ |
| 6329 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6330 | }, |
| 6331 | { /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ |
| 6332 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6333 | }, |
| 6334 | { /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ |
| 6335 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6336 | }, |
| 6337 | { /* ARM_t2UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ |
| 6338 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6339 | }, |
| 6340 | { /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ |
| 6341 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6342 | }, |
| 6343 | { /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ |
| 6344 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6345 | }, |
| 6346 | { /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ |
| 6347 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6348 | }, |
| 6349 | { /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ |
| 6350 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6351 | }, |
| 6352 | { /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal${p} $rdlo, $rdhi, $rn, $rm */ |
| 6353 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6354 | }, |
| 6355 | { /* ARM_t2UMULL, ARM_INS_UMULL: umull${p} $rdlo, $rdhi, $rn, $rm */ |
| 6356 | { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6357 | }, |
| 6358 | { /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ |
| 6359 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6360 | }, |
| 6361 | { /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ |
| 6362 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6363 | }, |
| 6364 | { /* ARM_t2UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ |
| 6365 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6366 | }, |
| 6367 | { /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ |
| 6368 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6369 | }, |
| 6370 | { /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ |
| 6371 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6372 | }, |
| 6373 | { /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ |
| 6374 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6375 | }, |
| 6376 | { /* ARM_t2USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ |
| 6377 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6378 | }, |
| 6379 | { /* ARM_t2USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ |
| 6380 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } |
| 6381 | }, |
| 6382 | { /* ARM_t2USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ |
| 6383 | { CS_AC_WRITE, 0 } |
| 6384 | }, |
| 6385 | { /* ARM_t2USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ |
| 6386 | { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } |
| 6387 | }, |
| 6388 | { /* ARM_t2USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ |
| 6389 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6390 | }, |
| 6391 | { /* ARM_t2USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ |
| 6392 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6393 | }, |
| 6394 | { /* ARM_t2USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ |
| 6395 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6396 | }, |
| 6397 | { /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ |
| 6398 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6399 | }, |
| 6400 | { /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ |
| 6401 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6402 | }, |
| 6403 | { /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ |
| 6404 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6405 | }, |
| 6406 | { /* ARM_t2UXTB, ARM_INS_UXTB: uxtb${p}.w $rd, $rm$rot */ |
| 6407 | { CS_AC_WRITE, 0 } |
| 6408 | }, |
| 6409 | { /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ |
| 6410 | { CS_AC_WRITE, 0 } |
| 6411 | }, |
| 6412 | { /* ARM_t2UXTH, ARM_INS_UXTH: uxth${p}.w $rd, $rm$rot */ |
| 6413 | { CS_AC_WRITE, 0 } |
| 6414 | }, |
| 6415 | { /* ARM_tADC, ARM_INS_ADC: adc${s}${p} $rdn, $rm */ |
| 6416 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6417 | }, |
| 6418 | { /* ARM_tADDhirr, ARM_INS_ADD: add${p} $rdn, $rm */ |
| 6419 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6420 | }, |
| 6421 | { /* ARM_tADDi3, ARM_INS_ADD: add${s}${p} $rd, $rm, $imm3 */ |
| 6422 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6423 | }, |
| 6424 | { /* ARM_tADDi8, ARM_INS_ADD: add${s}${p} $rdn, $imm8 */ |
| 6425 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 6426 | }, |
| 6427 | { /* ARM_tADDrSP, ARM_INS_ADD: add${p} $rdn, $sp, $rn */ |
| 6428 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6429 | }, |
| 6430 | { /* ARM_tADDrSPi, ARM_INS_ADD: add${p} $dst, $sp, $imm */ |
| 6431 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6432 | }, |
| 6433 | { /* ARM_tADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ |
| 6434 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6435 | }, |
| 6436 | { /* ARM_tADDspi, ARM_INS_ADD: add${p} $rdn, $imm */ |
| 6437 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 6438 | }, |
| 6439 | { /* ARM_tADDspr, ARM_INS_ADD: add${p} $rdn, $rm */ |
| 6440 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6441 | }, |
| 6442 | { /* ARM_tADR, ARM_INS_ADR: adr{$p} $rd, $addr */ |
| 6443 | { CS_AC_WRITE, 0 } |
| 6444 | }, |
| 6445 | { /* ARM_tAND, ARM_INS_AND: and${s}${p} $rdn, $rm */ |
| 6446 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6447 | }, |
| 6448 | { /* ARM_tASRri, ARM_INS_ASR: asr${s}${p} $rd, $rm, $imm5 */ |
| 6449 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6450 | }, |
| 6451 | { /* ARM_tASRrr, ARM_INS_ASR: asr${s}${p} $rdn, $rm */ |
| 6452 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6453 | }, |
| 6454 | { /* ARM_tB, ARM_INS_B: b${p} $target */ |
| 6455 | { 0 } |
| 6456 | }, |
| 6457 | { /* ARM_tBIC, ARM_INS_BIC: bic${s}${p} $rdn, $rm */ |
| 6458 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6459 | }, |
| 6460 | { /* ARM_tBKPT, ARM_INS_BKPT: bkpt $val */ |
| 6461 | { 0 } |
| 6462 | }, |
| 6463 | { /* ARM_tBL, ARM_INS_BL: bl${p} $func */ |
| 6464 | { 0 } |
| 6465 | }, |
| 6466 | { /* ARM_tBLXi, ARM_INS_BLX: blx${p} $func */ |
| 6467 | { 0 } |
| 6468 | }, |
| 6469 | { /* ARM_tBLXr, ARM_INS_BLX: blx${p} $func */ |
| 6470 | { CS_AC_READ, 0 } |
| 6471 | }, |
| 6472 | { /* ARM_tBX, ARM_INS_BX: bx${p} $rm */ |
| 6473 | { CS_AC_READ, 0 } |
| 6474 | }, |
| 6475 | { /* ARM_tBcc, ARM_INS_B: b${p} $target */ |
| 6476 | { 0 } |
| 6477 | }, |
| 6478 | { /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz $rn, $target */ |
| 6479 | { CS_AC_READ, 0 } |
| 6480 | }, |
| 6481 | { /* ARM_tCBZ, ARM_INS_CBZ: cbz $rn, $target */ |
| 6482 | { CS_AC_READ, 0 } |
| 6483 | }, |
| 6484 | { /* ARM_tCMNz, ARM_INS_CMN: cmn${p} $rn, $rm */ |
| 6485 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6486 | }, |
| 6487 | { /* ARM_tCMPhir, ARM_INS_CMP: cmp${p} $rn, $rm */ |
| 6488 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6489 | }, |
| 6490 | { /* ARM_tCMPi8, ARM_INS_CMP: cmp${p} $rn, $imm8 */ |
| 6491 | { CS_AC_READ, 0 } |
| 6492 | }, |
| 6493 | { /* ARM_tCMPr, ARM_INS_CMP: cmp${p} $rn, $rm */ |
| 6494 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6495 | }, |
| 6496 | { /* ARM_tCPS, ARM_INS_CPS: cps$imod $iflags */ |
| 6497 | { 0 } |
| 6498 | }, |
| 6499 | { /* ARM_tEOR, ARM_INS_EOR: eor${s}${p} $rdn, $rm */ |
| 6500 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6501 | }, |
| 6502 | { /* ARM_tHINT, ARM_INS_HINT: hint${p} $imm */ |
| 6503 | { 0 } |
| 6504 | }, |
| 6505 | { /* ARM_tHLT, ARM_INS_HLT: hlt $val */ |
| 6506 | { 0 } |
| 6507 | }, |
| 6508 | { /* ARM_tLDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ |
| 6509 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6510 | }, |
| 6511 | { /* ARM_tLDRBi, ARM_INS_LDRB: ldrb${p} $rt, $addr */ |
| 6512 | { CS_AC_WRITE, 0 } |
| 6513 | }, |
| 6514 | { /* ARM_tLDRBr, ARM_INS_LDRB: ldrb${p} $rt, $addr */ |
| 6515 | { CS_AC_WRITE, 0 } |
| 6516 | }, |
| 6517 | { /* ARM_tLDRHi, ARM_INS_LDRH: ldrh${p} $rt, $addr */ |
| 6518 | { CS_AC_WRITE, 0 } |
| 6519 | }, |
| 6520 | { /* ARM_tLDRHr, ARM_INS_LDRH: ldrh${p} $rt, $addr */ |
| 6521 | { CS_AC_WRITE, 0 } |
| 6522 | }, |
| 6523 | { /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ |
| 6524 | { CS_AC_WRITE, 0 } |
| 6525 | }, |
| 6526 | { /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ |
| 6527 | { CS_AC_WRITE, 0 } |
| 6528 | }, |
| 6529 | { /* ARM_tLDRi, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| 6530 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6531 | }, |
| 6532 | { /* ARM_tLDRpci, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| 6533 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6534 | }, |
| 6535 | { /* ARM_tLDRr, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| 6536 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6537 | }, |
| 6538 | { /* ARM_tLDRspi, ARM_INS_LDR: ldr${p} $rt, $addr */ |
| 6539 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6540 | }, |
| 6541 | { /* ARM_tLSLri, ARM_INS_LSL: lsl${s}${p} $rd, $rm, $imm5 */ |
| 6542 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6543 | }, |
| 6544 | { /* ARM_tLSLrr, ARM_INS_LSL: lsl${s}${p} $rdn, $rm */ |
| 6545 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6546 | }, |
| 6547 | { /* ARM_tLSRri, ARM_INS_LSR: lsr${s}${p} $rd, $rm, $imm5 */ |
| 6548 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6549 | }, |
| 6550 | { /* ARM_tLSRrr, ARM_INS_LSR: lsr${s}${p} $rdn, $rm */ |
| 6551 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6552 | }, |
| 6553 | { /* ARM_tMOVSr, ARM_INS_MOV: movs $rd, $rm */ |
| 6554 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6555 | }, |
| 6556 | { /* ARM_tMOVi8, ARM_INS_MOV: mov${s}${p} $rd, $imm8 */ |
| 6557 | { CS_AC_WRITE, 0 } |
| 6558 | }, |
| 6559 | { /* ARM_tMOVr, ARM_INS_MOV: mov${p} $rd, $rm */ |
| 6560 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6561 | }, |
| 6562 | { /* ARM_tMUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ |
| 6563 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } |
| 6564 | }, |
| 6565 | { /* ARM_tMVN, ARM_INS_MVN: mvn${s}${p} $rd, $rn */ |
| 6566 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6567 | }, |
| 6568 | { /* ARM_tORR, ARM_INS_ORR: orr${s}${p} $rdn, $rm */ |
| 6569 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6570 | }, |
| 6571 | { /* ARM_tPOP, ARM_INS_POP: pop${p} $regs */ |
| 6572 | { 0 } |
| 6573 | }, |
| 6574 | { /* ARM_tPUSH, ARM_INS_PUSH: push${p} $regs */ |
| 6575 | { 0 } |
| 6576 | }, |
| 6577 | { /* ARM_tREV, ARM_INS_REV: rev${p} $rd, $rm */ |
| 6578 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6579 | }, |
| 6580 | { /* ARM_tREV16, ARM_INS_REV16: rev16${p} $rd, $rm */ |
| 6581 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6582 | }, |
| 6583 | { /* ARM_tREVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ |
| 6584 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6585 | }, |
| 6586 | { /* ARM_tROR, ARM_INS_ROR: ror${s}${p} $rdn, $rm */ |
| 6587 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6588 | }, |
| 6589 | { /* ARM_tRSB, ARM_INS_RSB: rsb${s}${p} $rd, $rn, #0 */ |
| 6590 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6591 | }, |
| 6592 | { /* ARM_tSBC, ARM_INS_SBC: sbc${s}${p} $rdn, $rm */ |
| 6593 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6594 | }, |
| 6595 | { /* ARM_tSETEND, ARM_INS_SETEND: setend $end */ |
| 6596 | { 0 } |
| 6597 | }, |
| 6598 | { /* ARM_tSTMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ |
| 6599 | { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } |
| 6600 | }, |
| 6601 | { /* ARM_tSTRBi, ARM_INS_STRB: strb${p} $rt, $addr */ |
| 6602 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6603 | }, |
| 6604 | { /* ARM_tSTRBr, ARM_INS_STRB: strb${p} $rt, $addr */ |
| 6605 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6606 | }, |
| 6607 | { /* ARM_tSTRHi, ARM_INS_STRH: strh${p} $rt, $addr */ |
| 6608 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6609 | }, |
| 6610 | { /* ARM_tSTRHr, ARM_INS_STRH: strh${p} $rt, $addr */ |
| 6611 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6612 | }, |
| 6613 | { /* ARM_tSTRi, ARM_INS_STR: str${p} $rt, $addr */ |
| 6614 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6615 | }, |
| 6616 | { /* ARM_tSTRr, ARM_INS_STR: str${p} $rt, $addr */ |
| 6617 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6618 | }, |
| 6619 | { /* ARM_tSTRspi, ARM_INS_STR: str${p} $rt, $addr */ |
| 6620 | { CS_AC_READ, CS_AC_WRITE, 0 } |
| 6621 | }, |
| 6622 | { /* ARM_tSUBi3, ARM_INS_SUB: sub${s}${p} $rd, $rm, $imm3 */ |
| 6623 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6624 | }, |
| 6625 | { /* ARM_tSUBi8, ARM_INS_SUB: sub${s}${p} $rdn, $imm8 */ |
| 6626 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 6627 | }, |
| 6628 | { /* ARM_tSUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ |
| 6629 | { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } |
| 6630 | }, |
| 6631 | { /* ARM_tSUBspi, ARM_INS_SUB: sub${p} $rdn, $imm */ |
| 6632 | { CS_AC_READ | CS_AC_WRITE, 0 } |
| 6633 | }, |
| 6634 | { /* ARM_tSVC, ARM_INS_SVC: svc${p} $imm */ |
| 6635 | { 0 } |
| 6636 | }, |
| 6637 | { /* ARM_tSXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm */ |
| 6638 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6639 | }, |
| 6640 | { /* ARM_tSXTH, ARM_INS_SXTH: sxth${p} $rd, $rm */ |
| 6641 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6642 | }, |
| 6643 | { /* ARM_tTRAP, ARM_INS_TRAP: trap */ |
| 6644 | { 0 } |
| 6645 | }, |
| 6646 | { /* ARM_tTST, ARM_INS_TST: tst${p} $rn, $rm */ |
| 6647 | { CS_AC_READ, CS_AC_READ, 0 } |
| 6648 | }, |
| 6649 | { /* ARM_tUDF, ARM_INS_UDF: udf $imm8 */ |
| 6650 | { 0 } |
| 6651 | }, |
| 6652 | { /* ARM_tUXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm */ |
| 6653 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6654 | }, |
| 6655 | { /* ARM_tUXTH, ARM_INS_UXTH: uxth${p} $rd, $rm */ |
| 6656 | { CS_AC_WRITE, CS_AC_READ, 0 } |
| 6657 | }, |