Nguyen Anh Quynh | dd40750 | 2014-01-19 23:51:34 +0800 | [diff] [blame] | 1 | #ifndef CAPSTONE_ARM64_H |
| 2 | #define CAPSTONE_ARM64_H |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 3 | |
| 4 | /* Capstone Disassembler Engine */ |
| 5 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */ |
| 6 | |
| 7 | #ifdef __cplusplus |
| 8 | extern "C" { |
| 9 | #endif |
| 10 | |
| 11 | #include <stdint.h> |
| 12 | #include <stdbool.h> |
| 13 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame^] | 14 | #ifdef _MSC_VER |
| 15 | #pragma warning(disable:4201) |
| 16 | #endif |
| 17 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 18 | //> ARM64 shift type |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 19 | typedef enum arm64_shifter { |
| 20 | ARM64_SFT_INVALID = 0, |
| 21 | ARM64_SFT_LSL = 1, |
| 22 | ARM64_SFT_MSL = 2, |
| 23 | ARM64_SFT_LSR = 3, |
| 24 | ARM64_SFT_ASR = 4, |
Nguyen Anh Quynh | f8db76a | 2013-12-04 12:37:55 +0800 | [diff] [blame] | 25 | ARM64_SFT_ROR = 5, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 26 | } arm64_shifter; |
| 27 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 28 | //> ARM64 extender type |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 29 | typedef enum arm64_extender { |
| 30 | ARM64_EXT_INVALID = 0, |
| 31 | ARM64_EXT_UXTB = 1, |
| 32 | ARM64_EXT_UXTH = 2, |
| 33 | ARM64_EXT_UXTW = 3, |
| 34 | ARM64_EXT_UXTX = 4, |
| 35 | ARM64_EXT_SXTB = 5, |
| 36 | ARM64_EXT_SXTH = 6, |
| 37 | ARM64_EXT_SXTW = 7, |
| 38 | ARM64_EXT_SXTX = 8, |
| 39 | } arm64_extender; |
| 40 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 41 | //> ARM64 condition code |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 42 | typedef enum arm64_cc { |
| 43 | ARM64_CC_INVALID = 0, |
| 44 | ARM64_CC_EQ = 1, // Equal |
| 45 | ARM64_CC_NE = 2, // Not equal: Not equal, or unordered |
| 46 | ARM64_CC_HS = 3, // Unsigned higher or same: >, ==, or unordered |
| 47 | ARM64_CC_LO = 4, // Unsigned lower or same: Less than |
| 48 | ARM64_CC_MI = 5, // Minus, negative: Less than |
| 49 | ARM64_CC_PL = 6, // Plus, positive or zero: >, ==, or unordered |
| 50 | ARM64_CC_VS = 7, // Overflow: Unordered |
| 51 | ARM64_CC_VC = 8, // No overflow: Ordered |
| 52 | ARM64_CC_HI = 9, // Unsigned higher: Greater than, or unordered |
| 53 | ARM64_CC_LS = 10, // Unsigned lower or same: Less than or equal |
| 54 | ARM64_CC_GE = 11, // Greater than or equal: Greater than or equal |
| 55 | ARM64_CC_LT = 12, // Less than: Less than, or unordered |
| 56 | ARM64_CC_GT = 13, // Signed greater than: Greater than |
| 57 | ARM64_CC_LE = 14, // Signed less than or equal: <, ==, or unordered |
| 58 | ARM64_CC_AL = 15, // Always (unconditional): Always (unconditional) |
| 59 | ARM64_CC_NV = 16, // Always (unconditional): Always (unconditional) |
| 60 | // Note the NV exists purely to disassemble 0b1111. Execution |
| 61 | // is "always". |
| 62 | } arm64_cc; |
| 63 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 64 | //> Operand type for instruction's operands |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 65 | typedef enum arm64_op_type { |
| 66 | ARM64_OP_INVALID = 0, // Uninitialized. |
| 67 | ARM64_OP_REG, // Register operand. |
| 68 | ARM64_OP_CIMM, // C-Immediate |
| 69 | ARM64_OP_IMM, // Immediate operand. |
| 70 | ARM64_OP_FP, // Floating-Point immediate operand. |
| 71 | ARM64_OP_MEM, // Memory operand |
| 72 | } arm64_op_type; |
| 73 | |
| 74 | // Instruction's operand referring to memory |
| 75 | // This is associated with ARM64_OP_MEM operand type above |
| 76 | typedef struct arm64_op_mem { |
| 77 | unsigned int base; // base register |
| 78 | unsigned int index; // index register |
Nguyen Anh Quynh | 90acea3 | 2013-11-29 17:54:17 +0800 | [diff] [blame] | 79 | int32_t disp; // displacement/offset value |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 80 | } arm64_op_mem; |
| 81 | |
| 82 | // Instruction operand |
| 83 | typedef struct cs_arm64_op { |
| 84 | struct { |
| 85 | arm64_shifter type; // shifter type of this operand |
| 86 | unsigned int value; // shifter value of this operand |
| 87 | } shift; |
| 88 | arm64_extender ext; // extender type of this operand |
| 89 | arm64_op_type type; // operand type |
| 90 | union { |
| 91 | unsigned int reg; // register value for REG operand |
Nguyen Anh Quynh | 90acea3 | 2013-11-29 17:54:17 +0800 | [diff] [blame] | 92 | int32_t imm; // immediate value, or index for C-IMM or IMM operand |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 93 | double fp; // floating point value for FP operand |
| 94 | arm64_op_mem mem; // base/index/scale/disp value for MEM operand |
| 95 | }; |
| 96 | } cs_arm64_op; |
| 97 | |
| 98 | // Instruction structure |
| 99 | typedef struct cs_arm64 { |
| 100 | arm64_cc cc; // conditional code for this insn |
| 101 | bool update_flags; // does this insn update flags? |
| 102 | bool writeback; // does this insn request writeback? 'True' means 'yes' |
| 103 | |
| 104 | // Number of operands of this instruction, |
| 105 | // or 0 when instruction has no operand. |
| 106 | uint8_t op_count; |
| 107 | |
Nguyen Anh Quynh | f1656de | 2013-11-29 20:26:34 +0800 | [diff] [blame] | 108 | cs_arm64_op operands[8]; // operands for this instruction. |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 109 | } cs_arm64; |
| 110 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 111 | //> ARM64 registers |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 112 | typedef enum arm64_reg { |
| 113 | ARM64_REG_INVALID = 0, |
Nguyen Anh Quynh | ea5b79d | 2013-12-04 12:10:47 +0800 | [diff] [blame] | 114 | |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 115 | ARM64_REG_NZCV, |
| 116 | ARM64_REG_WSP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 117 | ARM64_REG_SP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 118 | ARM64_REG_B0, |
| 119 | ARM64_REG_B1, |
| 120 | ARM64_REG_B2, |
| 121 | ARM64_REG_B3, |
| 122 | ARM64_REG_B4, |
| 123 | ARM64_REG_B5, |
| 124 | ARM64_REG_B6, |
| 125 | ARM64_REG_B7, |
| 126 | ARM64_REG_B8, |
| 127 | ARM64_REG_B9, |
| 128 | ARM64_REG_B10, |
| 129 | ARM64_REG_B11, |
| 130 | ARM64_REG_B12, |
| 131 | ARM64_REG_B13, |
| 132 | ARM64_REG_B14, |
| 133 | ARM64_REG_B15, |
| 134 | ARM64_REG_B16, |
| 135 | ARM64_REG_B17, |
| 136 | ARM64_REG_B18, |
| 137 | ARM64_REG_B19, |
| 138 | ARM64_REG_B20, |
| 139 | ARM64_REG_B21, |
| 140 | ARM64_REG_B22, |
| 141 | ARM64_REG_B23, |
| 142 | ARM64_REG_B24, |
| 143 | ARM64_REG_B25, |
| 144 | ARM64_REG_B26, |
| 145 | ARM64_REG_B27, |
| 146 | ARM64_REG_B28, |
| 147 | ARM64_REG_B29, |
| 148 | ARM64_REG_B30, |
| 149 | ARM64_REG_B31, |
| 150 | ARM64_REG_D0, |
| 151 | ARM64_REG_D1, |
| 152 | ARM64_REG_D2, |
| 153 | ARM64_REG_D3, |
| 154 | ARM64_REG_D4, |
| 155 | ARM64_REG_D5, |
| 156 | ARM64_REG_D6, |
| 157 | ARM64_REG_D7, |
| 158 | ARM64_REG_D8, |
| 159 | ARM64_REG_D9, |
| 160 | ARM64_REG_D10, |
| 161 | ARM64_REG_D11, |
| 162 | ARM64_REG_D12, |
| 163 | ARM64_REG_D13, |
| 164 | ARM64_REG_D14, |
| 165 | ARM64_REG_D15, |
| 166 | ARM64_REG_D16, |
| 167 | ARM64_REG_D17, |
| 168 | ARM64_REG_D18, |
| 169 | ARM64_REG_D19, |
| 170 | ARM64_REG_D20, |
| 171 | ARM64_REG_D21, |
| 172 | ARM64_REG_D22, |
| 173 | ARM64_REG_D23, |
| 174 | ARM64_REG_D24, |
| 175 | ARM64_REG_D25, |
| 176 | ARM64_REG_D26, |
| 177 | ARM64_REG_D27, |
| 178 | ARM64_REG_D28, |
| 179 | ARM64_REG_D29, |
| 180 | ARM64_REG_D30, |
| 181 | ARM64_REG_D31, |
| 182 | ARM64_REG_H0, |
| 183 | ARM64_REG_H1, |
| 184 | ARM64_REG_H2, |
| 185 | ARM64_REG_H3, |
| 186 | ARM64_REG_H4, |
| 187 | ARM64_REG_H5, |
| 188 | ARM64_REG_H6, |
| 189 | ARM64_REG_H7, |
| 190 | ARM64_REG_H8, |
| 191 | ARM64_REG_H9, |
| 192 | ARM64_REG_H10, |
| 193 | ARM64_REG_H11, |
| 194 | ARM64_REG_H12, |
| 195 | ARM64_REG_H13, |
| 196 | ARM64_REG_H14, |
| 197 | ARM64_REG_H15, |
| 198 | ARM64_REG_H16, |
| 199 | ARM64_REG_H17, |
| 200 | ARM64_REG_H18, |
| 201 | ARM64_REG_H19, |
| 202 | ARM64_REG_H20, |
| 203 | ARM64_REG_H21, |
| 204 | ARM64_REG_H22, |
| 205 | ARM64_REG_H23, |
| 206 | ARM64_REG_H24, |
| 207 | ARM64_REG_H25, |
| 208 | ARM64_REG_H26, |
| 209 | ARM64_REG_H27, |
| 210 | ARM64_REG_H28, |
| 211 | ARM64_REG_H29, |
| 212 | ARM64_REG_H30, |
| 213 | ARM64_REG_H31, |
| 214 | ARM64_REG_Q0, |
| 215 | ARM64_REG_Q1, |
| 216 | ARM64_REG_Q2, |
| 217 | ARM64_REG_Q3, |
| 218 | ARM64_REG_Q4, |
| 219 | ARM64_REG_Q5, |
| 220 | ARM64_REG_Q6, |
| 221 | ARM64_REG_Q7, |
| 222 | ARM64_REG_Q8, |
| 223 | ARM64_REG_Q9, |
| 224 | ARM64_REG_Q10, |
| 225 | ARM64_REG_Q11, |
| 226 | ARM64_REG_Q12, |
| 227 | ARM64_REG_Q13, |
| 228 | ARM64_REG_Q14, |
| 229 | ARM64_REG_Q15, |
| 230 | ARM64_REG_Q16, |
| 231 | ARM64_REG_Q17, |
| 232 | ARM64_REG_Q18, |
| 233 | ARM64_REG_Q19, |
| 234 | ARM64_REG_Q20, |
| 235 | ARM64_REG_Q21, |
| 236 | ARM64_REG_Q22, |
| 237 | ARM64_REG_Q23, |
| 238 | ARM64_REG_Q24, |
| 239 | ARM64_REG_Q25, |
| 240 | ARM64_REG_Q26, |
| 241 | ARM64_REG_Q27, |
| 242 | ARM64_REG_Q28, |
| 243 | ARM64_REG_Q29, |
| 244 | ARM64_REG_Q30, |
| 245 | ARM64_REG_Q31, |
| 246 | ARM64_REG_S0, |
| 247 | ARM64_REG_S1, |
| 248 | ARM64_REG_S2, |
| 249 | ARM64_REG_S3, |
| 250 | ARM64_REG_S4, |
| 251 | ARM64_REG_S5, |
| 252 | ARM64_REG_S6, |
| 253 | ARM64_REG_S7, |
| 254 | ARM64_REG_S8, |
| 255 | ARM64_REG_S9, |
| 256 | ARM64_REG_S10, |
| 257 | ARM64_REG_S11, |
| 258 | ARM64_REG_S12, |
| 259 | ARM64_REG_S13, |
| 260 | ARM64_REG_S14, |
| 261 | ARM64_REG_S15, |
| 262 | ARM64_REG_S16, |
| 263 | ARM64_REG_S17, |
| 264 | ARM64_REG_S18, |
| 265 | ARM64_REG_S19, |
| 266 | ARM64_REG_S20, |
| 267 | ARM64_REG_S21, |
| 268 | ARM64_REG_S22, |
| 269 | ARM64_REG_S23, |
| 270 | ARM64_REG_S24, |
| 271 | ARM64_REG_S25, |
| 272 | ARM64_REG_S26, |
| 273 | ARM64_REG_S27, |
| 274 | ARM64_REG_S28, |
| 275 | ARM64_REG_S29, |
| 276 | ARM64_REG_S30, |
| 277 | ARM64_REG_S31, |
| 278 | ARM64_REG_W0, |
| 279 | ARM64_REG_W1, |
| 280 | ARM64_REG_W2, |
| 281 | ARM64_REG_W3, |
| 282 | ARM64_REG_W4, |
| 283 | ARM64_REG_W5, |
| 284 | ARM64_REG_W6, |
| 285 | ARM64_REG_W7, |
| 286 | ARM64_REG_W8, |
| 287 | ARM64_REG_W9, |
| 288 | ARM64_REG_W10, |
| 289 | ARM64_REG_W11, |
| 290 | ARM64_REG_W12, |
| 291 | ARM64_REG_W13, |
| 292 | ARM64_REG_W14, |
| 293 | ARM64_REG_W15, |
| 294 | ARM64_REG_W16, |
| 295 | ARM64_REG_W17, |
| 296 | ARM64_REG_W18, |
| 297 | ARM64_REG_W19, |
| 298 | ARM64_REG_W20, |
| 299 | ARM64_REG_W21, |
| 300 | ARM64_REG_W22, |
| 301 | ARM64_REG_W23, |
| 302 | ARM64_REG_W24, |
| 303 | ARM64_REG_W25, |
| 304 | ARM64_REG_W26, |
| 305 | ARM64_REG_W27, |
| 306 | ARM64_REG_W28, |
| 307 | ARM64_REG_W29, |
| 308 | ARM64_REG_W30, |
| 309 | ARM64_REG_X0, |
| 310 | ARM64_REG_X1, |
| 311 | ARM64_REG_X2, |
| 312 | ARM64_REG_X3, |
| 313 | ARM64_REG_X4, |
| 314 | ARM64_REG_X5, |
| 315 | ARM64_REG_X6, |
| 316 | ARM64_REG_X7, |
| 317 | ARM64_REG_X8, |
| 318 | ARM64_REG_X9, |
| 319 | ARM64_REG_X10, |
| 320 | ARM64_REG_X11, |
| 321 | ARM64_REG_X12, |
| 322 | ARM64_REG_X13, |
| 323 | ARM64_REG_X14, |
| 324 | ARM64_REG_X15, |
| 325 | ARM64_REG_X16, |
| 326 | ARM64_REG_X17, |
| 327 | ARM64_REG_X18, |
| 328 | ARM64_REG_X19, |
| 329 | ARM64_REG_X20, |
| 330 | ARM64_REG_X21, |
| 331 | ARM64_REG_X22, |
| 332 | ARM64_REG_X23, |
| 333 | ARM64_REG_X24, |
| 334 | ARM64_REG_X25, |
| 335 | ARM64_REG_X26, |
| 336 | ARM64_REG_X27, |
| 337 | ARM64_REG_X28, |
| 338 | ARM64_REG_X29, |
| 339 | ARM64_REG_X30, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 340 | |
| 341 | ARM64_REG_MAX, // <-- mark the end of the list of registers |
Nguyen Anh Quynh | 7957ed1 | 2013-12-15 00:32:20 +0800 | [diff] [blame] | 342 | |
| 343 | //> alias registers |
| 344 | |
| 345 | ARM64_REG_IP1 = ARM64_REG_X16, |
| 346 | ARM64_REG_IP0 = ARM64_REG_X17, |
| 347 | ARM64_REG_FP = ARM64_REG_X29, |
| 348 | ARM64_REG_LR = ARM64_REG_X30, |
| 349 | ARM64_REG_XZR = ARM64_REG_SP, |
| 350 | ARM64_REG_WZR = ARM64_REG_WSP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 351 | } arm64_reg; |
| 352 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 353 | //> ARM64 instruction |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 354 | typedef enum arm64_insn { |
| 355 | ARM64_INS_INVALID = 0, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 356 | |
| 357 | ARM64_INS_ABS, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 358 | ARM64_INS_ADC, |
| 359 | ARM64_INS_ADDHN2, |
| 360 | ARM64_INS_ADDHN, |
| 361 | ARM64_INS_ADDP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 362 | ARM64_INS_ADDV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 363 | ARM64_INS_ADD, |
| 364 | ARM64_INS_CMN, |
| 365 | ARM64_INS_ADRP, |
| 366 | ARM64_INS_ADR, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 367 | ARM64_INS_AESD, |
| 368 | ARM64_INS_AESE, |
| 369 | ARM64_INS_AESIMC, |
| 370 | ARM64_INS_AESMC, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 371 | ARM64_INS_AND, |
| 372 | ARM64_INS_ASR, |
| 373 | ARM64_INS_AT, |
| 374 | ARM64_INS_BFI, |
| 375 | ARM64_INS_BFM, |
| 376 | ARM64_INS_BFXIL, |
| 377 | ARM64_INS_BIC, |
| 378 | ARM64_INS_BIF, |
| 379 | ARM64_INS_BIT, |
| 380 | ARM64_INS_BLR, |
| 381 | ARM64_INS_BL, |
| 382 | ARM64_INS_BRK, |
| 383 | ARM64_INS_BR, |
| 384 | ARM64_INS_BSL, |
| 385 | ARM64_INS_B, |
| 386 | ARM64_INS_CBNZ, |
| 387 | ARM64_INS_CBZ, |
| 388 | ARM64_INS_CCMN, |
| 389 | ARM64_INS_CCMP, |
| 390 | ARM64_INS_CLREX, |
| 391 | ARM64_INS_CLS, |
| 392 | ARM64_INS_CLZ, |
| 393 | ARM64_INS_CMEQ, |
| 394 | ARM64_INS_CMGE, |
| 395 | ARM64_INS_CMGT, |
| 396 | ARM64_INS_CMHI, |
| 397 | ARM64_INS_CMHS, |
| 398 | ARM64_INS_CMLE, |
| 399 | ARM64_INS_CMLT, |
| 400 | ARM64_INS_CMP, |
| 401 | ARM64_INS_CMTST, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 402 | ARM64_INS_CNT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 403 | ARM64_INS_CRC32B, |
| 404 | ARM64_INS_CRC32CB, |
| 405 | ARM64_INS_CRC32CH, |
| 406 | ARM64_INS_CRC32CW, |
| 407 | ARM64_INS_CRC32CX, |
| 408 | ARM64_INS_CRC32H, |
| 409 | ARM64_INS_CRC32W, |
| 410 | ARM64_INS_CRC32X, |
| 411 | ARM64_INS_CSEL, |
| 412 | ARM64_INS_CSINC, |
| 413 | ARM64_INS_CSINV, |
| 414 | ARM64_INS_CSNEG, |
| 415 | ARM64_INS_DCPS1, |
| 416 | ARM64_INS_DCPS2, |
| 417 | ARM64_INS_DCPS3, |
| 418 | ARM64_INS_DC, |
| 419 | ARM64_INS_DMB, |
| 420 | ARM64_INS_DRPS, |
| 421 | ARM64_INS_DSB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 422 | ARM64_INS_DUP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 423 | ARM64_INS_EON, |
| 424 | ARM64_INS_EOR, |
| 425 | ARM64_INS_ERET, |
| 426 | ARM64_INS_EXTR, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 427 | ARM64_INS_EXT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 428 | ARM64_INS_FABD, |
| 429 | ARM64_INS_FABS, |
| 430 | ARM64_INS_FACGE, |
| 431 | ARM64_INS_FACGT, |
| 432 | ARM64_INS_FADDP, |
| 433 | ARM64_INS_FADD, |
| 434 | ARM64_INS_FCCMPE, |
| 435 | ARM64_INS_FCCMP, |
| 436 | ARM64_INS_FCMEQ, |
| 437 | ARM64_INS_FCMGE, |
| 438 | ARM64_INS_FCMGT, |
| 439 | ARM64_INS_FCMLE, |
| 440 | ARM64_INS_FCMLT, |
| 441 | ARM64_INS_FCMP, |
| 442 | ARM64_INS_FCMPE, |
| 443 | ARM64_INS_FCSEL, |
| 444 | ARM64_INS_FCVTAS, |
| 445 | ARM64_INS_FCVTAU, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 446 | ARM64_INS_FCVTL, |
| 447 | ARM64_INS_FCVTL2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 448 | ARM64_INS_FCVTMS, |
| 449 | ARM64_INS_FCVTMU, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 450 | ARM64_INS_FCVTN, |
| 451 | ARM64_INS_FCVTN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 452 | ARM64_INS_FCVTNS, |
| 453 | ARM64_INS_FCVTNU, |
| 454 | ARM64_INS_FCVTPS, |
| 455 | ARM64_INS_FCVTPU, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 456 | ARM64_INS_FCVTXN, |
| 457 | ARM64_INS_FCVTXN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 458 | ARM64_INS_FCVTZS, |
| 459 | ARM64_INS_FCVTZU, |
| 460 | ARM64_INS_FCVT, |
| 461 | ARM64_INS_FDIV, |
| 462 | ARM64_INS_FMADD, |
| 463 | ARM64_INS_FMAXNMP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 464 | ARM64_INS_FMAXNMV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 465 | ARM64_INS_FMAXNM, |
| 466 | ARM64_INS_FMAXP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 467 | ARM64_INS_FMAXV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 468 | ARM64_INS_FMAX, |
| 469 | ARM64_INS_FMINNMP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 470 | ARM64_INS_FMINNMV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 471 | ARM64_INS_FMINNM, |
| 472 | ARM64_INS_FMINP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 473 | ARM64_INS_FMINV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 474 | ARM64_INS_FMIN, |
| 475 | ARM64_INS_FMLA, |
| 476 | ARM64_INS_FMLS, |
| 477 | ARM64_INS_FMOV, |
| 478 | ARM64_INS_FMSUB, |
| 479 | ARM64_INS_FMULX, |
| 480 | ARM64_INS_FMUL, |
| 481 | ARM64_INS_FNEG, |
| 482 | ARM64_INS_FNMADD, |
| 483 | ARM64_INS_FNMSUB, |
| 484 | ARM64_INS_FNMUL, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 485 | ARM64_INS_FRECPE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 486 | ARM64_INS_FRECPS, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 487 | ARM64_INS_FRECPX, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 488 | ARM64_INS_FRINTA, |
| 489 | ARM64_INS_FRINTI, |
| 490 | ARM64_INS_FRINTM, |
| 491 | ARM64_INS_FRINTN, |
| 492 | ARM64_INS_FRINTP, |
| 493 | ARM64_INS_FRINTX, |
| 494 | ARM64_INS_FRINTZ, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 495 | ARM64_INS_FRSQRTE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 496 | ARM64_INS_FRSQRTS, |
| 497 | ARM64_INS_FSQRT, |
| 498 | ARM64_INS_FSUB, |
| 499 | ARM64_INS_HINT, |
| 500 | ARM64_INS_HLT, |
| 501 | ARM64_INS_HVC, |
| 502 | ARM64_INS_IC, |
| 503 | ARM64_INS_INS, |
| 504 | ARM64_INS_ISB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 505 | ARM64_INS_LD1, |
| 506 | ARM64_INS_LD1R, |
| 507 | ARM64_INS_LD2, |
| 508 | ARM64_INS_LD2R, |
| 509 | ARM64_INS_LD3, |
| 510 | ARM64_INS_LD3R, |
| 511 | ARM64_INS_LD4, |
| 512 | ARM64_INS_LD4R, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 513 | ARM64_INS_LDARB, |
| 514 | ARM64_INS_LDAR, |
| 515 | ARM64_INS_LDARH, |
| 516 | ARM64_INS_LDAXP, |
| 517 | ARM64_INS_LDAXRB, |
| 518 | ARM64_INS_LDAXR, |
| 519 | ARM64_INS_LDAXRH, |
| 520 | ARM64_INS_LDPSW, |
| 521 | ARM64_INS_LDRSB, |
| 522 | ARM64_INS_LDURSB, |
| 523 | ARM64_INS_LDRSH, |
| 524 | ARM64_INS_LDURSH, |
| 525 | ARM64_INS_LDRSW, |
| 526 | ARM64_INS_LDR, |
| 527 | ARM64_INS_LDTRSB, |
| 528 | ARM64_INS_LDTRSH, |
| 529 | ARM64_INS_LDTRSW, |
| 530 | ARM64_INS_LDURSW, |
| 531 | ARM64_INS_LDXP, |
| 532 | ARM64_INS_LDXRB, |
| 533 | ARM64_INS_LDXR, |
| 534 | ARM64_INS_LDXRH, |
| 535 | ARM64_INS_LDRH, |
| 536 | ARM64_INS_LDURH, |
| 537 | ARM64_INS_STRH, |
| 538 | ARM64_INS_STURH, |
| 539 | ARM64_INS_LDTRH, |
| 540 | ARM64_INS_STTRH, |
| 541 | ARM64_INS_LDUR, |
| 542 | ARM64_INS_STR, |
| 543 | ARM64_INS_STUR, |
| 544 | ARM64_INS_LDTR, |
| 545 | ARM64_INS_STTR, |
| 546 | ARM64_INS_LDRB, |
| 547 | ARM64_INS_LDURB, |
| 548 | ARM64_INS_STRB, |
| 549 | ARM64_INS_STURB, |
| 550 | ARM64_INS_LDTRB, |
| 551 | ARM64_INS_STTRB, |
| 552 | ARM64_INS_LDP, |
| 553 | ARM64_INS_LDNP, |
| 554 | ARM64_INS_STNP, |
| 555 | ARM64_INS_STP, |
| 556 | ARM64_INS_LSL, |
| 557 | ARM64_INS_LSR, |
| 558 | ARM64_INS_MADD, |
| 559 | ARM64_INS_MLA, |
| 560 | ARM64_INS_MLS, |
| 561 | ARM64_INS_MOVI, |
| 562 | ARM64_INS_MOVK, |
| 563 | ARM64_INS_MOVN, |
| 564 | ARM64_INS_MOVZ, |
| 565 | ARM64_INS_MRS, |
| 566 | ARM64_INS_MSR, |
| 567 | ARM64_INS_MSUB, |
| 568 | ARM64_INS_MUL, |
| 569 | ARM64_INS_MVNI, |
| 570 | ARM64_INS_MVN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 571 | ARM64_INS_NEG, |
| 572 | ARM64_INS_NOT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 573 | ARM64_INS_ORN, |
| 574 | ARM64_INS_ORR, |
| 575 | ARM64_INS_PMULL2, |
| 576 | ARM64_INS_PMULL, |
| 577 | ARM64_INS_PMUL, |
| 578 | ARM64_INS_PRFM, |
| 579 | ARM64_INS_PRFUM, |
| 580 | ARM64_INS_SQRSHRUN2, |
| 581 | ARM64_INS_SQRSHRUN, |
| 582 | ARM64_INS_SQSHRUN2, |
| 583 | ARM64_INS_SQSHRUN, |
| 584 | ARM64_INS_RADDHN2, |
| 585 | ARM64_INS_RADDHN, |
| 586 | ARM64_INS_RBIT, |
| 587 | ARM64_INS_RET, |
| 588 | ARM64_INS_REV16, |
| 589 | ARM64_INS_REV32, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 590 | ARM64_INS_REV64, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 591 | ARM64_INS_REV, |
| 592 | ARM64_INS_ROR, |
| 593 | ARM64_INS_RSHRN2, |
| 594 | ARM64_INS_RSHRN, |
| 595 | ARM64_INS_RSUBHN2, |
| 596 | ARM64_INS_RSUBHN, |
| 597 | ARM64_INS_SABAL2, |
| 598 | ARM64_INS_SABAL, |
| 599 | ARM64_INS_SABA, |
| 600 | ARM64_INS_SABDL2, |
| 601 | ARM64_INS_SABDL, |
| 602 | ARM64_INS_SABD, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 603 | ARM64_INS_SADALP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 604 | ARM64_INS_SADDL2, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 605 | ARM64_INS_SADDLP, |
| 606 | ARM64_INS_SADDLV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 607 | ARM64_INS_SADDL, |
| 608 | ARM64_INS_SADDW2, |
| 609 | ARM64_INS_SADDW, |
| 610 | ARM64_INS_SBC, |
| 611 | ARM64_INS_SBFIZ, |
| 612 | ARM64_INS_SBFM, |
| 613 | ARM64_INS_SBFX, |
| 614 | ARM64_INS_SCVTF, |
| 615 | ARM64_INS_SDIV, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 616 | ARM64_INS_SHA1C, |
| 617 | ARM64_INS_SHA1H, |
| 618 | ARM64_INS_SHA1M, |
| 619 | ARM64_INS_SHA1P, |
| 620 | ARM64_INS_SHA1SU0, |
| 621 | ARM64_INS_SHA1SU1, |
| 622 | ARM64_INS_SHA256H, |
| 623 | ARM64_INS_SHA256H2, |
| 624 | ARM64_INS_SHA256SU0, |
| 625 | ARM64_INS_SHA256SU1, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 626 | ARM64_INS_SHADD, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 627 | ARM64_INS_SHLL2, |
| 628 | ARM64_INS_SHLL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 629 | ARM64_INS_SHL, |
| 630 | ARM64_INS_SHRN2, |
| 631 | ARM64_INS_SHRN, |
| 632 | ARM64_INS_SHSUB, |
| 633 | ARM64_INS_SLI, |
| 634 | ARM64_INS_SMADDL, |
| 635 | ARM64_INS_SMAXP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 636 | ARM64_INS_SMAXV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 637 | ARM64_INS_SMAX, |
| 638 | ARM64_INS_SMC, |
| 639 | ARM64_INS_SMINP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 640 | ARM64_INS_SMINV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 641 | ARM64_INS_SMIN, |
| 642 | ARM64_INS_SMLAL2, |
| 643 | ARM64_INS_SMLAL, |
| 644 | ARM64_INS_SMLSL2, |
| 645 | ARM64_INS_SMLSL, |
| 646 | ARM64_INS_SMOV, |
| 647 | ARM64_INS_SMSUBL, |
| 648 | ARM64_INS_SMULH, |
| 649 | ARM64_INS_SMULL2, |
| 650 | ARM64_INS_SMULL, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 651 | ARM64_INS_SQABS, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 652 | ARM64_INS_SQADD, |
| 653 | ARM64_INS_SQDMLAL2, |
| 654 | ARM64_INS_SQDMLAL, |
| 655 | ARM64_INS_SQDMLSL2, |
| 656 | ARM64_INS_SQDMLSL, |
| 657 | ARM64_INS_SQDMULH, |
| 658 | ARM64_INS_SQDMULL2, |
| 659 | ARM64_INS_SQDMULL, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 660 | ARM64_INS_SQNEG, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 661 | ARM64_INS_SQRDMULH, |
| 662 | ARM64_INS_SQRSHL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 663 | ARM64_INS_SQRSHRN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 664 | ARM64_INS_SQRSHRN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 665 | ARM64_INS_SQSHLU, |
| 666 | ARM64_INS_SQSHL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 667 | ARM64_INS_SQSHRN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 668 | ARM64_INS_SQSHRN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 669 | ARM64_INS_SQSUB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 670 | ARM64_INS_SQXTN, |
| 671 | ARM64_INS_SQXTN2, |
| 672 | ARM64_INS_SQXTUN, |
| 673 | ARM64_INS_SQXTUN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 674 | ARM64_INS_SRHADD, |
| 675 | ARM64_INS_SRI, |
| 676 | ARM64_INS_SRSHL, |
| 677 | ARM64_INS_SRSHR, |
| 678 | ARM64_INS_SRSRA, |
| 679 | ARM64_INS_SSHLL2, |
| 680 | ARM64_INS_SSHLL, |
| 681 | ARM64_INS_SSHL, |
| 682 | ARM64_INS_SSHR, |
| 683 | ARM64_INS_SSRA, |
| 684 | ARM64_INS_SSUBL2, |
| 685 | ARM64_INS_SSUBL, |
| 686 | ARM64_INS_SSUBW2, |
| 687 | ARM64_INS_SSUBW, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 688 | ARM64_INS_ST1, |
| 689 | ARM64_INS_ST2, |
| 690 | ARM64_INS_ST3, |
| 691 | ARM64_INS_ST4, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 692 | ARM64_INS_STLRB, |
| 693 | ARM64_INS_STLR, |
| 694 | ARM64_INS_STLRH, |
| 695 | ARM64_INS_STLXP, |
| 696 | ARM64_INS_STLXRB, |
| 697 | ARM64_INS_STLXR, |
| 698 | ARM64_INS_STLXRH, |
| 699 | ARM64_INS_STXP, |
| 700 | ARM64_INS_STXRB, |
| 701 | ARM64_INS_STXR, |
| 702 | ARM64_INS_STXRH, |
| 703 | ARM64_INS_SUBHN2, |
| 704 | ARM64_INS_SUBHN, |
| 705 | ARM64_INS_SUB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 706 | ARM64_INS_SUQADD, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 707 | ARM64_INS_SVC, |
| 708 | ARM64_INS_SXTB, |
| 709 | ARM64_INS_SXTH, |
| 710 | ARM64_INS_SXTW, |
| 711 | ARM64_INS_SYSL, |
| 712 | ARM64_INS_SYS, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 713 | ARM64_INS_TBL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 714 | ARM64_INS_TBNZ, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 715 | ARM64_INS_TBX, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 716 | ARM64_INS_TBZ, |
| 717 | ARM64_INS_TLBI, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 718 | ARM64_INS_TRN1, |
| 719 | ARM64_INS_TRN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 720 | ARM64_INS_TST, |
| 721 | ARM64_INS_UABAL2, |
| 722 | ARM64_INS_UABAL, |
| 723 | ARM64_INS_UABA, |
| 724 | ARM64_INS_UABDL2, |
| 725 | ARM64_INS_UABDL, |
| 726 | ARM64_INS_UABD, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 727 | ARM64_INS_UADALP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 728 | ARM64_INS_UADDL2, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 729 | ARM64_INS_UADDLP, |
| 730 | ARM64_INS_UADDLV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 731 | ARM64_INS_UADDL, |
| 732 | ARM64_INS_UADDW2, |
| 733 | ARM64_INS_UADDW, |
| 734 | ARM64_INS_UBFIZ, |
| 735 | ARM64_INS_UBFM, |
| 736 | ARM64_INS_UBFX, |
| 737 | ARM64_INS_UCVTF, |
| 738 | ARM64_INS_UDIV, |
| 739 | ARM64_INS_UHADD, |
| 740 | ARM64_INS_UHSUB, |
| 741 | ARM64_INS_UMADDL, |
| 742 | ARM64_INS_UMAXP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 743 | ARM64_INS_UMAXV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 744 | ARM64_INS_UMAX, |
| 745 | ARM64_INS_UMINP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 746 | ARM64_INS_UMINV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 747 | ARM64_INS_UMIN, |
| 748 | ARM64_INS_UMLAL2, |
| 749 | ARM64_INS_UMLAL, |
| 750 | ARM64_INS_UMLSL2, |
| 751 | ARM64_INS_UMLSL, |
| 752 | ARM64_INS_UMOV, |
| 753 | ARM64_INS_UMSUBL, |
| 754 | ARM64_INS_UMULH, |
| 755 | ARM64_INS_UMULL2, |
| 756 | ARM64_INS_UMULL, |
| 757 | ARM64_INS_UQADD, |
| 758 | ARM64_INS_UQRSHL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 759 | ARM64_INS_UQRSHRN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 760 | ARM64_INS_UQRSHRN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 761 | ARM64_INS_UQSHL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 762 | ARM64_INS_UQSHRN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 763 | ARM64_INS_UQSHRN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 764 | ARM64_INS_UQSUB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 765 | ARM64_INS_UQXTN, |
| 766 | ARM64_INS_UQXTN2, |
| 767 | ARM64_INS_URECPE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 768 | ARM64_INS_URHADD, |
| 769 | ARM64_INS_URSHL, |
| 770 | ARM64_INS_URSHR, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 771 | ARM64_INS_URSQRTE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 772 | ARM64_INS_URSRA, |
| 773 | ARM64_INS_USHLL2, |
| 774 | ARM64_INS_USHLL, |
| 775 | ARM64_INS_USHL, |
| 776 | ARM64_INS_USHR, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 777 | ARM64_INS_USQADD, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 778 | ARM64_INS_USRA, |
| 779 | ARM64_INS_USUBL2, |
| 780 | ARM64_INS_USUBL, |
| 781 | ARM64_INS_USUBW2, |
| 782 | ARM64_INS_USUBW, |
| 783 | ARM64_INS_UXTB, |
| 784 | ARM64_INS_UXTH, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 785 | ARM64_INS_UZP1, |
| 786 | ARM64_INS_UZP2, |
| 787 | ARM64_INS_XTN, |
| 788 | ARM64_INS_XTN2, |
| 789 | ARM64_INS_ZIP1, |
| 790 | ARM64_INS_ZIP2, |
Nguyen Anh Quynh | 6b7abe3 | 2013-11-30 00:54:24 +0800 | [diff] [blame] | 791 | |
| 792 | // alias insn |
| 793 | ARM64_INS_MNEG, |
Nguyen Anh Quynh | 6b9b664 | 2013-11-30 12:28:56 +0800 | [diff] [blame] | 794 | ARM64_INS_UMNEGL, |
| 795 | ARM64_INS_SMNEGL, |
| 796 | ARM64_INS_MOV, |
| 797 | ARM64_INS_NOP, |
| 798 | ARM64_INS_YIELD, |
| 799 | ARM64_INS_WFE, |
| 800 | ARM64_INS_WFI, |
| 801 | ARM64_INS_SEV, |
| 802 | ARM64_INS_SEVL, |
| 803 | ARM64_INS_NGC, |
Nguyen Anh Quynh | 6b7abe3 | 2013-11-30 00:54:24 +0800 | [diff] [blame] | 804 | |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 805 | ARM64_INS_MAX, // <-- mark the end of the list of insn |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 806 | } arm64_insn; |
| 807 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 808 | //> Group of ARM64 instructions |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 809 | typedef enum arm64_insn_group { |
| 810 | ARM64_GRP_INVALID = 0, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 811 | |
| 812 | ARM64_GRP_CRYPTO, |
| 813 | ARM64_GRP_FPARMV8, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 814 | ARM64_GRP_NEON, |
Nguyen Anh Quynh | 3582bc1 | 2013-12-03 09:43:27 +0800 | [diff] [blame] | 815 | |
| 816 | ARM64_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) |
| 817 | |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 818 | ARM64_GRP_MAX, // <-- mark the end of the list of groups |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 819 | } arm64_insn_group; |
| 820 | |
| 821 | #ifdef __cplusplus |
| 822 | } |
| 823 | #endif |
| 824 | |
| 825 | #endif |