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Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +08001/* Capstone Disassembler Engine */
2/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
3
4#include <stdio.h>
5#include <stdlib.h>
6#include <inttypes.h>
7
8#include <capstone.h>
9
10static csh handle;
11
12struct platform {
13 cs_arch arch;
14 cs_mode mode;
Nguyen Anh Quynhb42a6572013-11-29 17:40:07 +080015 unsigned char *code;
16 size_t size;
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080017 char *comment;
18};
19
Nguyen Anh Quynhb42a6572013-11-29 17:40:07 +080020static void print_string_hex(char *comment, unsigned char *str, int len)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080021{
Nguyen Anh Quynhb42a6572013-11-29 17:40:07 +080022 unsigned char *c;
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080023
24 printf("%s", comment);
25 for (c = str; c < str + len; c++) {
26 printf("0x%02x ", *c & 0xff);
27 }
28
29 printf("\n");
30}
31
32static void print_insn_detail(cs_arch mode, cs_insn *ins)
33{
34 cs_arm64 *arm64 = &(ins->arm64);
35 int i;
36
37 if (arm64->op_count)
38 printf("\top_count: %u\n", arm64->op_count);
39
40 for (i = 0; i < arm64->op_count; i++) {
41 cs_arm64_op *op = &(arm64->operands[i]);
42 switch(op->type) {
43 default:
44 break;
45 case ARM64_OP_REG:
46 printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
47 break;
48 case ARM64_OP_IMM:
Nguyen Anh Quynh90acea32013-11-29 17:54:17 +080049 printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080050 break;
51 case ARM64_OP_FP:
52 printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
53 break;
54 case ARM64_OP_MEM:
55 printf("\t\toperands[%u].type: MEM\n", i);
56 if (op->mem.base != ARM64_REG_INVALID)
57 printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
58 if (op->mem.index != ARM64_REG_INVALID)
59 printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
60 if (op->mem.disp != 0)
Nguyen Anh Quynh90acea32013-11-29 17:54:17 +080061 printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080062
63 break;
64 case ARM64_OP_CIMM:
Nguyen Anh Quynh90acea32013-11-29 17:54:17 +080065 printf("\t\toperands[%u].type: C-IMM = %u\n", i, op->imm);
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080066 break;
67 }
68
69 if (op->shift.type != ARM64_SFT_INVALID &&
70 op->shift.value)
71 printf("\t\t\tShift: type = %u, value = %u\n",
72 op->shift.type, op->shift.value);
73
74 if (op->ext != ARM64_EXT_INVALID)
75 printf("\t\t\tExt: %u\n", op->ext);
76 }
77
78 if (arm64->cc != ARM64_CC_INVALID)
79 printf("\tCode condition: %u\n", arm64->cc);
80
81 if (arm64->update_flags)
82 printf("\tUpdate-flags: True\n");
83
84 if (arm64->writeback)
85 printf("\tWrite-back: True\n");
86
87 printf("\n");
88}
89
90static void test()
91{
92//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
93//#define ARM64_CODE "\x21\x7c\x00\x53" // lsr w1, w1, #0x0
94//#define ARM64_CODE "\x21\x7c\x02\x9b"
95//#define ARM64_CODE "\x20\x04\x81\xda" // csneg x0, x1, x1, eq | cneg x0, x1, ne
96//#define ARM64_CODE "\x20\x08\x02\x8b" // add x0, x1, x2, lsl #2
97
98//#define ARM64_CODE "\x20\xcc\x20\x8b"
99//#define ARM64_CODE "\xe2\x8f\x40\xa9" // ldp x2, x3, [sp, #8]
100//#define ARM64_CODE "\x20\x40\x60\x1e" // fmov d0, d1
101//#define ARM64_CODE "\x20\x7c\x7d\x93" // sbfiz x0, x1, #3, #32
102
103//#define ARM64_CODE "\x20\x88\x43\xb3" // bfxil x0, x1, #3, #32
104//#define ARM64_CODE "\x01\x71\x08\xd5" // sys #0, c7, c1, #0, x1
105//#define ARM64_CODE "\x00\x71\x28\xd5" // sysl x0, #0, c7, c1, #0
106
107//#define ARM64_CODE "\x20\xf4\x18\x9e" // fcvtzs x0, s1, #3
108//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0: FIXME: handle as "sys" insn
109//#define ARM64_CODE "\x00\x90\x24\x1e" // fmov s0, ##10.00000000
110//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
111//#define ARM64_CODE "\x20\x78\x62\xf8" // ldr x0, [x1, x2, lsl #3]
112//#define ARM64_CODE "\x41\x14\x44\xb3" // bfm x1, x2, #4, #5
113//#define ARM64_CODE "\x80\x23\x29\xd5" // sysl x0, #1, c2, c3, #4
114//#define ARM64_CODE "\x20\x00\x24\x1e" // fcvtas w0, s1
115//#define ARM64_CODE "\x41\x04\x40\xd2" // eor x1, x2, #0x3
116//#define ARM64_CODE "\x9f\x33\x03\xd5" // dsb osh
117//#define ARM64_CODE "\x41\x10\x23\x8a" // bic x1, x2, x3, lsl #4
118//#define ARM64_CODE "\x16\x41\x3c\xd5" // mrs x22, sp_el1
119//#define ARM64_CODE "\x41\x1c\x63\x0e" // bic v1.8b, v2.8b, v3.8b
120//#define ARM64_CODE "\x41\xd4\xe3\x6e" // fabd v1.2d, v2.2d, v3.2d
121//#define ARM64_CODE "\x20\x8c\x62\x2e" // cmeq v0.4h, v1.4h, v2.4h
122//#define ARM64_CODE "\x20\x98\x20\x4e" // cmeq v0.16b, v1.16b, #0
123//#define ARM64_CODE "\x20\x2c\x05\x4e" // smov x0, v1.b[2]
124//#define ARM64_CODE "\x21\xe4\x00\x2f" // movi d1, #0xff
125//#define ARM64_CODE "\x60\x78\x08\xd5" // at s1e0w, x0 // FIXME: same problem with dc ZVA
126//#define ARM64_CODE "\x20\x00\xa0\xf2" // movk x0, #1, lsl #16
127//#define ARM64_CODE "\x20\x08\x00\xb1" // adds x0, x1, #0x2
128//#define ARM64_CODE "\x41\x04\x00\x0f" // movi v1.2s, #0x2
129//#define ARM64_CODE "\x06\x00\x00\x14" // b 0x44
130//#define ARM64_CODE "\x00\x90\x24\x1e" // fmov s0, ##10.00000000
131//#define ARM64_CODE "\x5f\x3f\x03\xd5" // clrex
132//#define ARM64_CODE "\x5f\x3e\x03\xd5" // clrex #14
133//#define ARM64_CODE "\x20\x00\x02\xab" // adds x0, x1, x2 (alias of adds x0, x1, x2, lsl #0)
Nguyen Anh Quynh6b7abe32013-11-30 00:54:24 +0800134//#define ARM64_CODE "\x20\xf4\x18\x9e" // fcvtzs x0, s1, #3
135//#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2
Nguyen Anh Quynh0e3defb2013-12-02 10:30:01 +0800136//#define ARM64_CODE "\xd0\xb6\x1e\xd5" // msr s3_6_c11_c6_6, x16
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800137#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b"
138
139 struct platform platforms[] = {
140 {
141 .arch = CS_ARCH_ARM64,
142 .mode = CS_MODE_ARM,
Nguyen Anh Quynhb42a6572013-11-29 17:40:07 +0800143 .code = (unsigned char *)ARM64_CODE,
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800144 .size = sizeof(ARM64_CODE) - 1,
145 .comment = "ARM-64"
146 },
147 };
148
Nguyen Anh Quynh5df9e4b2013-12-03 15:02:12 +0800149 uint64_t address = 0x2c;
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800150 //cs_insn insn[16];
151 cs_insn *insn;
152 int i;
153
154 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
155 if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
156 return;
157
Nguyen Anh Quynhb42a6572013-11-29 17:40:07 +0800158 //size_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, insn);
159 size_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800160 if (count) {
161 printf("****************\n");
162 printf("Platform: %s\n", platforms[i].comment);
163 print_string_hex("Code:", platforms[i].code, platforms[i].size);
164 printf("Disasm:\n");
165
Nguyen Anh Quynhb42a6572013-11-29 17:40:07 +0800166 size_t j;
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800167 for (j = 0; j < count; j++) {
Nguyen Anh Quynh7b7b40c2013-12-03 12:24:06 +0800168 printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800169 print_insn_detail(platforms[i].mode, &insn[j]);
170 }
Nguyen Anh Quynh7b7b40c2013-12-03 12:24:06 +0800171 printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +0800172
173 // free memory allocated by cs_disasm_dyn()
174 cs_free(insn);
175 } else {
176 printf("****************\n");
177 printf("Platform: %s\n", platforms[i].comment);
178 print_string_hex("Code:", platforms[i].code, platforms[i].size);
179 printf("ERROR: Failed to disasm given code!\n");
180 }
181
182 printf("\n");
183
184 cs_close(handle);
185 }
186}
187
188int main()
189{
190 test();
191
192 return 0;
193}
194