Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1 | (* Capstone Disassembler Engine |
| 2 | * By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> *) |
| 3 | |
Nguyen Anh Quynh | 586be76 | 2014-09-21 23:23:38 +0800 | [diff] [blame] | 4 | open Arm64_const |
| 5 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 6 | (* architecture specific info of instruction *) |
| 7 | type arm64_op_shift = { |
Nguyen Anh Quynh | 77d93e9 | 2014-09-25 23:03:36 +0800 | [diff] [blame^] | 8 | shift_type: int; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 9 | shift_value: int; |
| 10 | } |
| 11 | |
| 12 | type arm64_op_mem = { |
| 13 | base: int; |
| 14 | index: int; |
Nguyen Anh Quynh | 77d93e9 | 2014-09-25 23:03:36 +0800 | [diff] [blame^] | 15 | disp: int |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 16 | } |
| 17 | |
| 18 | type arm64_op_value = |
| 19 | | ARM64_OP_INVALID of int |
| 20 | | ARM64_OP_REG of int |
| 21 | | ARM64_OP_CIMM of int |
| 22 | | ARM64_OP_IMM of int |
| 23 | | ARM64_OP_FP of float |
| 24 | | ARM64_OP_MEM of arm64_op_mem |
Nguyen Anh Quynh | 77d93e9 | 2014-09-25 23:03:36 +0800 | [diff] [blame^] | 25 | | ARM64_OP_REG_MRS of int |
| 26 | | ARM64_OP_REG_MSR of int |
| 27 | | ARM64_OP_PSTATE of int |
| 28 | | ARM64_OP_SYS of int |
| 29 | | ARM64_OP_PREFETCH of int |
| 30 | | ARM64_OP_BARRIER of int |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 31 | |
| 32 | type arm64_op = { |
Nguyen Anh Quynh | 77d93e9 | 2014-09-25 23:03:36 +0800 | [diff] [blame^] | 33 | vector_index: int; |
| 34 | vas: int; |
| 35 | vess: int; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 36 | shift: arm64_op_shift; |
| 37 | ext: int; |
| 38 | value: arm64_op_value; |
| 39 | } |
| 40 | |
| 41 | type cs_arm64 = { |
| 42 | cc: int; |
| 43 | update_flags: bool; |
| 44 | writeback: bool; |
| 45 | op_count: int; |
| 46 | operands: arm64_op array; |
| 47 | } |