Blame - arch/ARM/ARMInstPrinter.c - platform/external/capstone

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Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1	//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
				9	//
				10	// This class prints an ARM MCInst to a .s file.
				11	//
				12	//===----------------------------------------------------------------------===//
				13
Nguyen Anh Quynh	8598a21	2014-05-14 11:26:41 +0800	[diff] [blame]	14	/* Capstone Disassembly Engine */
				15	/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
				16
				17	#ifdef CAPSTONE_HAS_ARM
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	18
				19	#include <stdio.h> // DEBUG
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	20	#include <stdlib.h>
				21	#include <string.h>
Cr4sh	9d60607	2015-03-29 18:29:06 +0800	[diff] [blame]	22	#include "../../myinttypes.h"
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	23
				24	#include "ARMInstPrinter.h"
				25	#include "ARMAddressingModes.h"
				26	#include "ARMBaseInfo.h"
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	27	#include "ARMDisassembler.h"
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	28	#include "../../MCInst.h"
				29	#include "../../SStream.h"
				30	#include "../../MCRegisterInfo.h"
				31	#include "../../utils.h"
Nguyen Anh Quynh	3732725	2014-01-20 09:47:21 +0800	[diff] [blame]	32	#include "ARMMapping.h"
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	33
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	34	#define GET_SUBTARGETINFO_ENUM
				35	#include "ARMGenSubtargetInfo.inc"
				36
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	37	static void printRegName(cs_struct h, SStream OS, unsigned RegNo);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	38
				39	// Autogenerated by tblgen.
				40	static void printInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI);
				41	static void printOperand(MCInst MI, unsigned OpNo, SStream O);
				42	static void printSORegRegOperand(MCInst MI, unsigned OpNum, SStream O);
				43	static void printSORegImmOperand(MCInst MI, unsigned OpNum, SStream O);
				44
				45	static void printAddrModeTBB(MCInst MI, unsigned OpNum, SStream O);
				46	static void printAddrModeTBH(MCInst MI, unsigned OpNum, SStream O);
				47	static void printAddrMode2Operand(MCInst MI, unsigned OpNum, SStream O);
				48	static void printAM2PreOrOffsetIndexOp(MCInst MI, unsigned OpNum, SStream O);
				49	static void printAddrMode2OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
				50	static void printAddrMode3Operand(MCInst MI, unsigned OpNum, SStream O, bool AlwaysPrintImm0);
				51	static void printAddrMode3OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	52	static void printAM3PreOrOffsetIndexOp(MCInst MI, unsigned Op, SStream O, bool AlwaysPrintImm0);
				53	static void printPostIdxImm8Operand(MCInst MI, unsigned OpNum, SStream O);
				54	static void printPostIdxRegOperand(MCInst MI, unsigned OpNum, SStream O);
				55	static void printPostIdxImm8s4Operand(MCInst MI, unsigned OpNum, SStream O);
				56	static void printAddrMode5Operand(MCInst MI, unsigned OpNum, SStream O, bool AlwaysPrintImm0);
				57	static void printAddrMode6Operand(MCInst MI, unsigned OpNum, SStream O);
				58	static void printAddrMode7Operand(MCInst MI, unsigned OpNum, SStream O);
				59	static void printAddrMode6OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
				60
				61	static void printBitfieldInvMaskImmOperand(MCInst MI, unsigned OpNum, SStream O);
				62	static void printMemBOption(MCInst MI, unsigned OpNum, SStream O);
				63	static void printShiftImmOperand(MCInst MI, unsigned OpNum, SStream O);
				64	static void printPKHLSLShiftImm(MCInst MI, unsigned OpNum, SStream O);
				65	static void printPKHASRShiftImm(MCInst MI, unsigned OpNum, SStream O);
				66	static void printAdrLabelOperand(MCInst MI, unsigned OpNum, SStream O, unsigned);
				67	static void printThumbS4ImmOperand(MCInst MI, unsigned OpNum, SStream O);
				68	static void printThumbSRImm(MCInst MI, unsigned OpNum, SStream O);
				69	static void printThumbITMask(MCInst MI, unsigned OpNum, SStream O);
				70	static void printThumbAddrModeRROperand(MCInst MI, unsigned OpNum, SStream O);
				71	static void printThumbAddrModeImm5SOperand(MCInst MI, unsigned OpNum, SStream O, unsigned Scale);
				72	static void printThumbAddrModeImm5S1Operand(MCInst MI, unsigned OpNum, SStream O);
				73	static void printThumbAddrModeImm5S2Operand(MCInst MI, unsigned OpNum, SStream O);
				74	static void printThumbAddrModeImm5S4Operand(MCInst MI, unsigned OpNum, SStream O);
				75	static void printThumbAddrModeSPOperand(MCInst MI, unsigned OpNum, SStream O);
				76	static void printT2SOOperand(MCInst MI, unsigned OpNum, SStream O);
				77	static void printAddrModeImm12Operand(MCInst MI, unsigned OpNum, SStream O, bool AlwaysPrintImm0);
				78	static void printT2AddrModeImm8Operand(MCInst MI, unsigned OpNum, SStream O, bool);
				79	static void printT2AddrModeImm8s4Operand(MCInst MI, unsigned OpNum, SStream O, bool);
				80	static void printT2AddrModeImm0_1020s4Operand(MCInst MI, unsigned OpNum, SStream O);
				81	static void printT2AddrModeImm8OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
				82	static void printT2AddrModeImm8s4OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
				83	static void printT2AddrModeSoRegOperand(MCInst MI, unsigned OpNum, SStream O);
				84	static void printSetendOperand(MCInst MI, unsigned OpNum, SStream O);
				85	static void printCPSIMod(MCInst MI, unsigned OpNum, SStream O);
				86	static void printCPSIFlag(MCInst MI, unsigned OpNum, SStream O);
				87	static void printMSRMaskOperand(MCInst MI, unsigned OpNum, SStream O);
				88	static void printPredicateOperand(MCInst MI, unsigned OpNum, SStream O);
				89	static void printMandatoryPredicateOperand(MCInst MI, unsigned OpNum, SStream O);
				90	static void printSBitModifierOperand(MCInst MI, unsigned OpNum, SStream O);
				91	static void printRegisterList(MCInst MI, unsigned OpNum, SStream O);
				92	static void printNoHashImmediate(MCInst MI, unsigned OpNum, SStream O);
				93	static void printPImmediate(MCInst MI, unsigned OpNum, SStream O);
				94	static void printCImmediate(MCInst MI, unsigned OpNum, SStream O);
				95	static void printCoprocOptionImm(MCInst MI, unsigned OpNum, SStream O);
				96	static void printFPImmOperand(MCInst MI, unsigned OpNum, SStream O);
				97	static void printNEONModImmOperand(MCInst MI, unsigned OpNum, SStream O);
				98	static void printImmPlusOneOperand(MCInst MI, unsigned OpNum, SStream O);
				99	static void printRotImmOperand(MCInst MI, unsigned OpNum, SStream O);
				100	static void printGPRPairOperand(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *MRI);
				101	static void printThumbLdrLabelOperand(MCInst MI, unsigned OpNum, SStream O);
				102	static void printFBits16(MCInst MI, unsigned OpNum, SStream O);
				103	static void printFBits32(MCInst MI, unsigned OpNum, SStream O);
				104	static void printVectorIndex(MCInst MI, unsigned OpNum, SStream O);
				105	static void printVectorListOne(MCInst MI, unsigned OpNum, SStream O);
				106	static void printVectorListTwo(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *MRI);
				107	static void printVectorListTwoSpaced(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *RI);
				108	static void printVectorListThree(MCInst MI, unsigned OpNum, SStream O);
				109	static void printVectorListFour(MCInst MI, unsigned OpNum, SStream O);
				110	static void printVectorListOneAllLanes(MCInst MI, unsigned OpNum, SStream O);
				111	static void printVectorListTwoAllLanes(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *RI);
				112	static void printVectorListThreeAllLanes(MCInst MI, unsigned OpNum, SStream O);
				113	static void printVectorListFourAllLanes(MCInst MI, unsigned OpNum, SStream O);
				114	static void printVectorListTwoSpacedAllLanes(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *MRI);
				115	static void printVectorListThreeSpacedAllLanes(MCInst MI, unsigned OpNum, SStream O);
				116	static void printVectorListFourSpacedAllLanes(MCInst MI, unsigned OpNum, SStream O);
				117	static void printVectorListThreeSpaced(MCInst MI, unsigned OpNum, SStream O);
				118	static void printVectorListFourSpaced(MCInst MI, unsigned OpNum, SStream O);
				119
				120	static void printInstSyncBOption(MCInst MI, unsigned OpNum, SStream O);
				121
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	122	static void set_mem_access(MCInst *MI, bool status)
				123	{
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	124	if (MI->csh->detail != CS_OPT_ON)
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	125	return;
				126
Nguyen Anh Quynh	19b0de3	2013-12-31 22:40:04 +0800	[diff] [blame]	127	MI->csh->doing_mem = status;
				128	if (status) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	129	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
				130	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
				131	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
				132	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
				133	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	134	} else {
				135	// done, create the next operand slot
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	136	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	137	}
				138	}
				139
Nguyen Anh Quynh	ebe2443	2014-06-17 13:56:01 +0800	[diff] [blame]	140	static void op_addImm(MCInst *MI, int v)
				141	{
Nguyen Anh Quynh	73eb5d5	2014-06-17 18:08:29 +0800	[diff] [blame]	142	if (MI->csh->detail) {
				143	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				144	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
				145	MI->flat_insn->detail->arm.op_count++;
				146	}
Nguyen Anh Quynh	ebe2443	2014-06-17 13:56:01 +0800	[diff] [blame]	147	}
				148
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	149	#define GET_INSTRINFO_ENUM
				150	#include "ARMGenInstrInfo.inc"
				151
				152	//#define PRINT_ALIAS_INSTR
				153	#include "ARMGenAsmWriter.inc"
				154
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	155	void ARM_getRegName(cs_struct *handle, int value)
				156	{
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	157	if (value == CS_OPT_SYNTAX_NOREGNAME) {
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	158	handle->get_regname = getRegisterName2;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	159	handle->reg_name = ARM_reg_name2;;
				160	} else {
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	161	handle->get_regname = getRegisterName;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	162	handle->reg_name = ARM_reg_name;;
				163	}
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	164	}
				165
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	166	/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
				167	///
				168	/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
				169	static unsigned translateShiftImm(unsigned imm)
				170	{
				171	// lsr #32 and asr #32 exist, but should be encoded as a 0.
				172	//assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
				173	if (imm == 0)
				174	return 32;
				175	return imm;
				176	}
				177
				178	/// Prints the shift value with an immediate value.
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	179	static void printRegImmShift(MCInst MI, SStream O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm)
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	180	{
				181	if (ShOpc == ARM_AM_no_shift \|\| (ShOpc == ARM_AM_lsl && !ShImm))
				182	return;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	183	SStream_concat0(O, ", ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	184
				185	//assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	186	SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	187	if (MI->csh->detail) {
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	188	if (MI->csh->doing_mem)
				189	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc;
				190	else
				191	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	192	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	193
				194	if (ShOpc != ARM_AM_rrx) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	195	SStream_concat0(O, " ");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	196	SStream_concat(O, "#%u", translateShiftImm(ShImm));
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	197	if (MI->csh->detail) {
				198	if (MI->csh->doing_mem)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	199	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm);
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	200	else
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	201	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm);
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	202	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	203	}
				204	}
				205
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	206	static void printRegName(cs_struct h, SStream OS, unsigned RegNo)
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	207	{
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	208	#ifndef CAPSTONE_DIET
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	209	SStream_concat0(OS, h->get_regname(RegNo));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	210	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	211	}
				212
				213	static name_map insn_update_flgs[] = {
				214	{ ARM_INS_CMN, "cmn" },
				215	{ ARM_INS_CMP, "cmp" },
				216	{ ARM_INS_TEQ, "teq" },
				217	{ ARM_INS_TST, "tst" },
				218
				219	{ ARM_INS_ADC, "adcs" },
				220	{ ARM_INS_ADD, "adds" },
				221	{ ARM_INS_AND, "ands" },
				222	{ ARM_INS_ASR, "asrs" },
				223	{ ARM_INS_BIC, "bics" },
				224	{ ARM_INS_EOR, "eors" },
				225	{ ARM_INS_LSL, "lsls" },
				226	{ ARM_INS_LSR, "lsrs" },
				227	{ ARM_INS_MLA, "mlas" },
				228	{ ARM_INS_MOV, "movs" },
				229	{ ARM_INS_MUL, "muls" },
				230	{ ARM_INS_MVN, "mvns" },
				231	{ ARM_INS_ORN, "orns" },
				232	{ ARM_INS_ORR, "orrs" },
				233	{ ARM_INS_ROR, "rors" },
				234	{ ARM_INS_RRX, "rrxs" },
				235	{ ARM_INS_RSB, "rsbs" },
				236	{ ARM_INS_RSC, "rscs" },
				237	{ ARM_INS_SBC, "sbcs" },
				238	{ ARM_INS_SMLAL, "smlals" },
				239	{ ARM_INS_SMULL, "smulls" },
				240	{ ARM_INS_SUB, "subs" },
				241	{ ARM_INS_UMLAL, "umlals" },
				242	{ ARM_INS_UMULL, "umulls" },
				243	};
				244
Nguyen Anh Quynh	6456481	2014-05-19 16:46:31 +0800	[diff] [blame]	245	void ARM_post_printer(csh ud, cs_insn insn, char insn_asm, MCInst *mci)
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	246	{
Nguyen Anh Quynh	5ef633c	2014-01-04 10:41:17 +0800	[diff] [blame]	247	if (((cs_struct *)ud)->detail != CS_OPT_ON)
				248	return;
				249
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	250	// check if this insn requests write-back
Nguyen Anh Quynh	e19490e	2015-01-21 12:15:14 +0800	[diff] [blame]	251	if (mci->writeback \|\| (strrchr(insn_asm, '!')) != NULL) {
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	252	insn->detail->arm.writeback = true;
Nguyen Anh Quynh	7bbb433	2015-01-21 12:16:15 +0800	[diff] [blame]	253	} else if (mci->csh->mode & CS_MODE_THUMB) {
Nguyen Anh Quynh	e19490e	2015-01-21 12:15:14 +0800	[diff] [blame]	254	// handle some special instructions with writeback
				255	switch(mci->Opcode) {
				256	default:
				257	break;
				258	case ARM_t2LDC2L_PRE:
				259	case ARM_t2LDC2_PRE:
				260	case ARM_t2LDCL_PRE:
				261	case ARM_t2LDC_PRE:
				262
				263	case ARM_t2LDRB_PRE:
				264	case ARM_t2LDRD_PRE:
				265	case ARM_t2LDRH_PRE:
				266	case ARM_t2LDRSB_PRE:
				267	case ARM_t2LDRSH_PRE:
				268	case ARM_t2LDR_PRE:
				269
				270	case ARM_t2STC2L_PRE:
				271	case ARM_t2STC2_PRE:
				272	case ARM_t2STCL_PRE:
				273	case ARM_t2STC_PRE:
				274
				275	case ARM_t2STRB_PRE:
				276	case ARM_t2STRD_PRE:
				277	case ARM_t2STRH_PRE:
				278	case ARM_t2STR_PRE:
				279
				280	case ARM_t2LDC2L_POST:
				281	case ARM_t2LDC2_POST:
				282	case ARM_t2LDCL_POST:
				283	case ARM_t2LDC_POST:
				284
				285	case ARM_t2LDRB_POST:
				286	case ARM_t2LDRD_POST:
				287	case ARM_t2LDRH_POST:
				288	case ARM_t2LDRSB_POST:
				289	case ARM_t2LDRSH_POST:
				290	case ARM_t2LDR_POST:
				291
				292	case ARM_t2STC2L_POST:
				293	case ARM_t2STC2_POST:
				294	case ARM_t2STCL_POST:
				295	case ARM_t2STC_POST:
				296
				297	case ARM_t2STRB_POST:
				298	case ARM_t2STRD_POST:
				299	case ARM_t2STRH_POST:
				300	case ARM_t2STR_POST:
				301	insn->detail->arm.writeback = true;
				302	break;
				303	}
				304	} else { // ARM mode
				305	// handle some special instructions with writeback
				306	switch(mci->Opcode) {
				307	default:
				308	break;
				309	case ARM_LDC2L_PRE:
				310	case ARM_LDC2_PRE:
				311	case ARM_LDCL_PRE:
				312	case ARM_LDC_PRE:
				313
				314	case ARM_LDRD_PRE:
				315	case ARM_LDRH_PRE:
				316	case ARM_LDRSB_PRE:
				317	case ARM_LDRSH_PRE:
				318
				319	case ARM_STC2L_PRE:
				320	case ARM_STC2_PRE:
				321	case ARM_STCL_PRE:
				322	case ARM_STC_PRE:
				323
				324	case ARM_STRD_PRE:
				325	case ARM_STRH_PRE:
				326
				327	case ARM_LDC2L_POST:
				328	case ARM_LDC2_POST:
				329	case ARM_LDCL_POST:
				330	case ARM_LDC_POST:
				331
				332	case ARM_LDRBT_POST:
				333	case ARM_LDRD_POST:
				334	case ARM_LDRH_POST:
				335	case ARM_LDRSB_POST:
				336	case ARM_LDRSH_POST:
				337
				338	case ARM_STC2L_POST:
				339	case ARM_STC2_POST:
				340	case ARM_STCL_POST:
				341	case ARM_STC_POST:
				342
				343	case ARM_STRBT_POST:
				344	case ARM_STRD_POST:
				345	case ARM_STRH_POST:
Nguyen Anh Quynh	9426ad5	2015-01-21 12:25:36 +0800	[diff] [blame]	346
				347	case ARM_LDRB_POST_IMM:
				348	case ARM_LDR_POST_IMM:
				349	case ARM_STRB_POST_IMM:
				350	case ARM_STR_POST_IMM:
				351
Nguyen Anh Quynh	e19490e	2015-01-21 12:15:14 +0800	[diff] [blame]	352	insn->detail->arm.writeback = true;
				353	break;
				354	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	355	}
				356
				357	// check if this insn requests update flags
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	358	if (insn->detail->arm.update_flags == false) {
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	359	// some insn still update flags, regardless of tabgen info
Nguyen Anh Quynh	f6c7cbc	2014-03-12 12:50:54 +0800	[diff] [blame]	360	unsigned int i, j;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	361
				362	for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) {
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	363	if (insn->id == insn_update_flgs[i].id &&
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	364	!strncmp(insn_asm, insn_update_flgs[i].name,
				365	strlen(insn_update_flgs[i].name))) {
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	366	insn->detail->arm.update_flags = true;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	367	// we have to update regs_write array as well
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	368	for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) {
				369	if (insn->detail->regs_write[j] == 0) {
				370	insn->detail->regs_write[j] = ARM_REG_CPSR;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	371	break;
				372	}
				373	}
				374	break;
				375	}
				376	}
				377	}
Nguyen Anh Quynh	48b6cb4	2014-06-01 09:45:19 +0700	[diff] [blame]	378
				379	// instruction should not have invalid CC
				380	if (insn->detail->arm.cc == ARM_CC_INVALID) {
				381	insn->detail->arm.cc = ARM_CC_AL;
				382	}
				383
Nguyen Anh Quynh	6eb55cf	2014-06-01 10:03:14 +0700	[diff] [blame]	384	// manual fix for some special instructions
				385	// printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode);
				386	switch(mci->Opcode) {
				387	default:
				388	break;
				389	case ARM_MOVPCLR:
				390	insn->detail->arm.operands[0].type = ARM_OP_REG;
				391	insn->detail->arm.operands[0].reg = ARM_REG_PC;
				392	insn->detail->arm.operands[1].type = ARM_OP_REG;
				393	insn->detail->arm.operands[1].reg = ARM_REG_LR;
				394	insn->detail->arm.op_count = 2;
				395	break;
				396	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	397	}
				398
				399	void ARM_printInst(MCInst MI, SStream O, void *Info)
				400	{
				401	MCRegisterInfo MRI = (MCRegisterInfo )Info;
				402
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	403	unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	404
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	405	switch(Opcode) {
				406	// Check for HINT instructions w/ canonical names.
				407	case ARM_HINT:
				408	case ARM_tHINT:
				409	case ARM_t2HINT:
				410	switch (MCOperand_getImm(MCInst_getOperand(MI, 0))) {
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	411	case 0: SStream_concat0(O, "nop"); pubOpcode = ARM_INS_NOP; break;
				412	case 1: SStream_concat0(O, "yield"); pubOpcode = ARM_INS_YIELD; break;
				413	case 2: SStream_concat0(O, "wfe"); pubOpcode = ARM_INS_WFE; break;
				414	case 3: SStream_concat0(O, "wfi"); pubOpcode = ARM_INS_WFI; break;
				415	case 4: SStream_concat0(O, "sev"); pubOpcode = ARM_INS_SEV; break;
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	416	case 5:
Nguyen Anh Quynh	2593e22	2014-11-10 16:35:38 +0800	[diff] [blame]	417	if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) {
				418	SStream_concat0(O, "sevl");
				419	pubOpcode = ARM_INS_SEVL;
				420	break;
				421	}
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	422	// Fallthrough for non-v8
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	423	default:
				424	// Anything else should just print normally.
				425	printInstruction(MI, O, MRI);
				426	return;
				427	}
				428	printPredicateOperand(MI, 1, O);
				429	if (Opcode == ARM_t2HINT)
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	430	SStream_concat0(O, ".w");
				431
				432	MCInst_setOpcodePub(MI, pubOpcode);
				433
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	434	return;
				435
				436	// Check for MOVs and print canonical forms, instead.
				437	case ARM_MOVsr: {
				438	// FIXME: Thumb variants?
				439	MCOperand *Dst = MCInst_getOperand(MI, 0);
				440	MCOperand *MO1 = MCInst_getOperand(MI, 1);
				441	MCOperand *MO2 = MCInst_getOperand(MI, 2);
				442	MCOperand *MO3 = MCInst_getOperand(MI, 3);
				443
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	444	SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3))));
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	445	printSBitModifierOperand(MI, 6, O);
				446	printPredicateOperand(MI, 4, O);
				447
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	448	SStream_concat0(O, "\t");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	449	printRegName(MI->csh, O, MCOperand_getReg(Dst));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	450	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	451	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				452	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
				453	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	454	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	455
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	456	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	457	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	458
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	459	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	460	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				461	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
				462	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	463	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	464
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	465	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	466	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	467	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	468	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				469	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
				470	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	471	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	472	//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
				473	return;
				474	}
				475
				476	case ARM_MOVsi: {
				477	// FIXME: Thumb variants?
				478	MCOperand *Dst = MCInst_getOperand(MI, 0);
				479	MCOperand *MO1 = MCInst_getOperand(MI, 1);
				480	MCOperand *MO2 = MCInst_getOperand(MI, 2);
				481
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	482	SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2))));
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	483	printSBitModifierOperand(MI, 5, O);
				484	printPredicateOperand(MI, 3, O);
				485
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	486	SStream_concat0(O, "\t");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	487	printRegName(MI->csh, O, MCOperand_getReg(Dst));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	488	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	489	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				490	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
				491	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	492	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	493
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	494	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	495	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	496	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	497	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				498	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
				499	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	500	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	501
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	502	if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) {
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	503	//printAnnotation(O, Annot);
				504	return;
				505	}
				506
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	507	SStream_concat0(O, ", ");
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	508	tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	509	if (tmp > HEX_THRESHOLD)
				510	SStream_concat(O, "#0x%x", tmp);
				511	else
				512	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	513	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	514	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type =
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	515	(arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	516	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	517	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	518	return;
				519	}
				520
				521	// A8.6.123 PUSH
				522	case ARM_STMDB_UPD:
				523	case ARM_t2STMDB_UPD:
				524	if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
				525	MCInst_getNumOperands(MI) > 5) {
				526	// Should only print PUSH if there are at least two registers in the list.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	527	SStream_concat0(O, "push");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	528	MCInst_setOpcodePub(MI, ARM_INS_PUSH);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	529	printPredicateOperand(MI, 2, O);
				530	if (Opcode == ARM_t2STMDB_UPD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	531	SStream_concat0(O, ".w");
				532	SStream_concat0(O, "\t");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	533	printRegisterList(MI, 4, O);
				534	return;
				535	}
				536	break;
				537
				538	case ARM_STR_PRE_IMM:
				539	if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP &&
				540	MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	541	SStream_concat0(O, "push");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	542	MCInst_setOpcodePub(MI, ARM_INS_PUSH);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	543	printPredicateOperand(MI, 4, O);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	544	SStream_concat0(O, "\t{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	545	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	546	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	547	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				548	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
				549	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	550	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	551	SStream_concat0(O, "}");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	552	return;
				553	}
				554	break;
				555
				556	// A8.6.122 POP
				557	case ARM_LDMIA_UPD:
				558	case ARM_t2LDMIA_UPD:
				559	if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
				560	MCInst_getNumOperands(MI) > 5) {
				561	// Should only print POP if there are at least two registers in the list.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	562	SStream_concat0(O, "pop");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	563	MCInst_setOpcodePub(MI, ARM_INS_POP);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	564	printPredicateOperand(MI, 2, O);
				565	if (Opcode == ARM_t2LDMIA_UPD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	566	SStream_concat0(O, ".w");
				567	SStream_concat0(O, "\t");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	568	printRegisterList(MI, 4, O);
				569	return;
				570	}
				571	break;
				572
				573	case ARM_LDR_POST_IMM:
Nguyen Anh Quynh	3caf837	2014-11-27 14:34:40 +0800	[diff] [blame]	574	if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) {
				575	MCOperand *MO2 = MCInst_getOperand(MI, 4);
				576	if ((getAM2Op((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_add &&
				577	getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) \|\|
				578	MCOperand_getImm(MO2) == 4) {
				579	SStream_concat0(O, "pop");
				580	MCInst_setOpcodePub(MI, ARM_INS_POP);
				581	printPredicateOperand(MI, 5, O);
				582	SStream_concat0(O, "\t{");
				583	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
				584	if (MI->csh->detail) {
				585	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				586	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
				587	MI->flat_insn->detail->arm.op_count++;
				588	}
				589	SStream_concat0(O, "}");
				590	return;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	591	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	592	}
				593	break;
				594
				595	// A8.6.355 VPUSH
				596	case ARM_VSTMSDB_UPD:
				597	case ARM_VSTMDDB_UPD:
				598	if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	599	SStream_concat0(O, "vpush");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	600	MCInst_setOpcodePub(MI, ARM_INS_VPUSH);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	601	printPredicateOperand(MI, 2, O);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	602	SStream_concat0(O, "\t");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	603	printRegisterList(MI, 4, O);
				604	return;
				605	}
				606	break;
				607
				608	// A8.6.354 VPOP
				609	case ARM_VLDMSIA_UPD:
				610	case ARM_VLDMDIA_UPD:
				611	if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	612	SStream_concat0(O, "vpop");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	613	MCInst_setOpcodePub(MI, ARM_INS_VPOP);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	614	printPredicateOperand(MI, 2, O);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	615	SStream_concat0(O, "\t");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	616	printRegisterList(MI, 4, O);
				617	return;
				618	}
				619	break;
				620
				621	case ARM_tLDMIA: {
Nguyen Anh Quynh	8cdafda	2014-11-11 22:30:30 +0800	[diff] [blame]	622	bool Writeback = true;
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	623	unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0));
				624	unsigned i;
				625	for (i = 3; i < MCInst_getNumOperands(MI); ++i) {
				626	if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg)
				627	Writeback = false;
				628	}
				629
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	630	SStream_concat0(O, "ldm");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	631	MCInst_setOpcodePub(MI, ARM_INS_LDM);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	632
				633	printPredicateOperand(MI, 1, O);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	634	SStream_concat0(O, "\t");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	635	printRegName(MI->csh, O, BaseReg);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	636	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	637	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				638	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg;
				639	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	640	}
Nguyen Anh Quynh	e19490e	2015-01-21 12:15:14 +0800	[diff] [blame]	641	if (Writeback) {
				642	MI->writeback = true;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	643	SStream_concat0(O, "!");
Nguyen Anh Quynh	e19490e	2015-01-21 12:15:14 +0800	[diff] [blame]	644	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	645	SStream_concat0(O, ", ");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	646	printRegisterList(MI, 3, O);
				647	return;
				648	}
				649
				650	// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
				651	// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
				652	// a single GPRPair reg operand is used in the .td file to replace the two
				653	// GPRs. However, when decoding them, the two GRPs cannot be automatically
				654	// expressed as a GPRPair, so we have to manually merge them.
				655	// FIXME: We would really like to be able to tablegen'erate this.
				656	case ARM_LDREXD:
				657	case ARM_STREXD:
				658	case ARM_LDAEXD:
				659	case ARM_STLEXD: {
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	660	MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
				661	bool isStore = Opcode == ARM_STREXD \|\| Opcode == ARM_STLEXD;
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	662
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	663	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
				664	if (MCRegisterClass_contains(MRC, Reg)) {
				665	MCInst NewMI;
Nguyen Anh Quynh	5e2e660	2014-05-30 17:43:36 +0800	[diff] [blame]	666
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	667	MCInst_Init(&NewMI);
				668	MCInst_setOpcode(&NewMI, Opcode);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	669
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	670	if (isStore)
				671	MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	672
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	673	MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
				674	MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
Nguyen Anh Quynh	9678705	2014-06-10 13:59:55 +0700	[diff] [blame]	675
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	676	// Copy the rest operands into NewMI.
				677	for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
				678	MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
Nguyen Anh Quynh	9678705	2014-06-10 13:59:55 +0700	[diff] [blame]	679
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	680	printInstruction(&NewMI, O, MRI);
				681	return;
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	682	}
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	683	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	684	}
				685
				686	//if (printAliasInstr(MI, O, MRI))
				687	// printInstruction(MI, O, MRI);
				688	printInstruction(MI, O, MRI);
				689	}
				690
				691	static void printOperand(MCInst MI, unsigned OpNo, SStream O)
				692	{
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	693	int32_t imm;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	694	MCOperand *Op = MCInst_getOperand(MI, OpNo);
				695	if (MCOperand_isReg(Op)) {
				696	unsigned Reg = MCOperand_getReg(Op);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	697	printRegName(MI->csh, O, Reg);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	698	if (MI->csh->detail) {
Nguyen Anh Quynh	19b0de3	2013-12-31 22:40:04 +0800	[diff] [blame]	699	if (MI->csh->doing_mem) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	700	if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID)
				701	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	702	else
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	703	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	704	} else {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	705	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				706	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
				707	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	708	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	709	}
				710	} else if (MCOperand_isImm(Op)) {
Nguyen Anh Quynh	0c235e1	2014-07-31 21:16:54 +0800	[diff] [blame]	711	unsigned int opc = MCInst_getOpcode(MI);
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	712
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	713	imm = (int32_t)MCOperand_getImm(Op);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	714
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	715	// relative branch only has relative offset, so we have to update it
				716	// to reflect absolute address.
				717	// Note: in ARM, PC is always 2 instructions ahead, so we have to
				718	// add 8 in ARM mode, or 4 in Thumb mode
Nguyen Anh Quynh	bc80b3d	2014-05-09 17:31:41 +0800	[diff] [blame]	719	// printf(">> opcode: %u\n", MCInst_getOpcode(MI));
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	720	if (ARM_rel_branch(MI->csh, opc)) {
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	721	// only do this for relative branch
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	722	if (MI->csh->mode & CS_MODE_THUMB) {
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	723	imm += (int32_t)MI->address + 4;
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	724	if (ARM_blx_to_arm_mode(MI->csh, opc)) {
Nguyen Anh Quynh	0c235e1	2014-07-31 21:16:54 +0800	[diff] [blame]	725	// here need to align down to the nearest 4-byte address
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	726	#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width)
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	727	imm = _ALIGN_DOWN(imm, 4);
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	728	#undef _ALIGN_DOWN
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	729	}
				730	} else {
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	731	imm += (int32_t)MI->address + 8;
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	732	}
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	733
				734	if (imm >= 0) {
				735	if (imm > HEX_THRESHOLD)
				736	SStream_concat(O, "#0x%x", imm);
				737	else
				738	SStream_concat(O, "#%u", imm);
				739	} else {
Nguyen Anh Quynh	4e87675	2014-09-23 16:49:12 +0800	[diff] [blame]	740	SStream_concat(O, "#0x%x", imm);
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	741	}
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	742	} else {
Nguyen Anh Quynh	278e727	2014-11-11 12:50:43 +0800	[diff] [blame]	743	switch(MI->flat_insn->id) {
				744	default:
				745	if (imm >= 0) {
				746	if (imm > HEX_THRESHOLD)
				747	SStream_concat(O, "#0x%x", imm);
				748	else
				749	SStream_concat(O, "#%u", imm);
				750	} else {
				751	if (imm < -HEX_THRESHOLD)
				752	SStream_concat(O, "#-0x%x", -imm);
				753	else
				754	SStream_concat(O, "#-%u", -imm);
				755	}
				756	break;
				757	case ARM_INS_AND:
				758	case ARM_INS_ORR:
				759	case ARM_INS_EOR:
				760	case ARM_INS_BIC:
Nguyen Anh Quynh	a2934a7	2014-11-25 21:02:18 +0800	[diff] [blame]	761	case ARM_INS_MVN:
Nguyen Anh Quynh	278e727	2014-11-11 12:50:43 +0800	[diff] [blame]	762	// do not print number in negative form
				763	if (imm >= 0 && imm <= HEX_THRESHOLD)
				764	SStream_concat(O, "#%u", imm);
				765	else
				766	SStream_concat(O, "#0x%x", imm);
				767	break;
				768	}
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	769	}
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	770
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	771	if (MI->csh->detail) {
Nguyen Anh Quynh	19b0de3	2013-12-31 22:40:04 +0800	[diff] [blame]	772	if (MI->csh->doing_mem)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	773	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	774	else {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	775	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				776	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
				777	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	778	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	779	}
				780	}
				781	}
				782
				783	static void printThumbLdrLabelOperand(MCInst MI, unsigned OpNum, SStream O)
				784	{
				785	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	786	int32_t OffImm;
Nguyen Anh Quynh	42706a3	2014-05-09 07:33:35 +0800	[diff] [blame]	787	bool isSub;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	788	SStream_concat0(O, "[pc, ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	789
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	790	OffImm = (int32_t)MCOperand_getImm(MO1);
				791	isSub = OffImm < 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	792
				793	// Special value for #-0. All others are normal.
				794	if (OffImm == INT32_MIN)
				795	OffImm = 0;
				796	if (isSub) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	797	SStream_concat(O, "#-0x%x", -OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	798	} else {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	799	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	800	SStream_concat(O, "#0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	801	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	802	SStream_concat(O, "#%u", OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	803	}
				804
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	805	SStream_concat0(O, "]");
Nguyen Anh Quynh	bb71c13	2014-06-01 10:14:31 +0700	[diff] [blame]	806
				807	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	808	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
				809	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC;
				810	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
				811	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
				812	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
				813	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	bb71c13	2014-06-01 10:14:31 +0700	[diff] [blame]	814	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	815	}
				816
				817	// so_reg is a 4-operand unit corresponding to register forms of the A5.1
				818	// "Addressing Mode 1 - Data-processing operands" forms. This includes:
				819	// REG 0 0 - e.g. R5
				820	// REG REG 0,SH_OPC - e.g. R5, ROR R3
				821	// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
				822	static void printSORegRegOperand(MCInst MI, unsigned OpNum, SStream O)
				823	{
				824	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				825	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				826	MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
Nguyen Anh Quynh	42706a3	2014-05-09 07:33:35 +0800	[diff] [blame]	827	ARM_AM_ShiftOpc ShOpc;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	828
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	829	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	830
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	831	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	832	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				833	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	834
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	835	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
				836	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	837	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	838
				839	// Print the shift opc.
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	840	ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	841	SStream_concat0(O, ", ");
				842	SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	843	if (ShOpc == ARM_AM_rrx)
				844	return;
				845
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	846	SStream_concat0(O, " ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	847	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	848	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	849	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	850	//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
				851	}
				852
				853	static void printSORegImmOperand(MCInst MI, unsigned OpNum, SStream O)
				854	{
				855	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				856	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				857
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	858	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	859	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	860	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				861	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
				862	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
				863	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
				864	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	865	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	866
				867	// Print the shift opc.
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	868	printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	869	getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	870	}
				871
				872	//===--------------------------------------------------------------------===//
				873	// Addressing Mode #2
				874	//===--------------------------------------------------------------------===//
				875
				876	static void printAM2PreOrOffsetIndexOp(MCInst MI, unsigned Op, SStream O)
				877	{
				878	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				879	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
				880	MCOperand *MO3 = MCInst_getOperand(MI, Op + 2);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	881	ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	882
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	883	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	884	set_mem_access(MI, true);
				885
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	886	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	887	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	888	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	889	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	890
				891	if (!MCOperand_getReg(MO2)) {
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	892	unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	893	if (tmp) { // Don't print +0.
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	894	subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3));
				895
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	896	SStream_concat0(O, ", ");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	897	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	898	SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	899	else
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	900	SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	901	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	902	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3));
				903	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	904	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	905	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	906	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	907	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	908	set_mem_access(MI, false);
				909	return;
				910	}
				911
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	912	SStream_concat0(O, ", ");
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	913	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	914	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	915	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	916	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	917	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	918	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	919
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	920	printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)),
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	921	getAM2Offset((unsigned int)MCOperand_getImm(MO3)));
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	922	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	923	set_mem_access(MI, false);
				924	}
				925
				926	static void printAddrModeTBB(MCInst MI, unsigned Op, SStream O)
				927	{
				928	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				929	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	930	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	931	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	932	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	933	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	934	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	935	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	936	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	937	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	938	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	939	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	940	set_mem_access(MI, false);
				941	}
				942
				943	static void printAddrModeTBH(MCInst MI, unsigned Op, SStream O)
				944	{
				945	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				946	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	947	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	948	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	949	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	950	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	951	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	952	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	953	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	954	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	955	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	956	SStream_concat0(O, ", lsl #1]");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	957	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	958	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
				959	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	960	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	961	set_mem_access(MI, false);
				962	}
				963
				964	static void printAddrMode2Operand(MCInst MI, unsigned Op, SStream O)
				965	{
				966	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				967
				968	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				969	printOperand(MI, Op, O);
				970	return;
				971	}
				972
				973	printAM2PreOrOffsetIndexOp(MI, Op, O);
				974	}
				975
				976	static void printAddrMode2OffsetOperand(MCInst MI, unsigned OpNum, SStream O)
				977	{
				978	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				979	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	980	ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	981
				982	if (!MCOperand_getReg(MO1)) {
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	983	unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	984	if (ImmOffs > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	985	SStream_concat(O, "#%s0x%x",
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	986	ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	987	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	988	SStream_concat(O, "#%s%u",
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	989	ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	990	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	991	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				992	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	993	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	994	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	995	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	996	return;
				997	}
				998
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	999	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1000	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1001	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1002	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1003	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1004	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1005	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1006	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1007
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1008	printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	1009	getAM2Offset((unsigned int)MCOperand_getImm(MO2)));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1010	}
				1011
				1012	//===--------------------------------------------------------------------===//
				1013	// Addressing Mode #3
				1014	//===--------------------------------------------------------------------===//
				1015
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1016	static void printAM3PreOrOffsetIndexOp(MCInst MI, unsigned Op, SStream O,
				1017	bool AlwaysPrintImm0)
				1018	{
				1019	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1020	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
				1021	MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
Nguyen Anh Quynh	8b012d5	2015-08-15 14:16:39 +0800	[diff] [blame^]	1022	ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1023	unsigned ImmOffs;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1024
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1025	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1026	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1027	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1028	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1029	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1030
				1031	if (MCOperand_getReg(MO2)) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1032	SStream_concat0(O, ", ");
Nguyen Anh Quynh	8b012d5	2015-08-15 14:16:39 +0800	[diff] [blame^]	1033	SStream_concat0(O, ARM_AM_getAddrOpcStr(sign));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1034	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1035	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1036	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	8b012d5	2015-08-15 14:16:39 +0800	[diff] [blame^]	1037	if (!sign) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1038	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1039	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
				1040	}
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1041	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1042	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1043	set_mem_access(MI, false);
				1044	return;
				1045	}
				1046
				1047	//If the op is sub we have to print the immediate even if it is 0
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1048	ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1049
Nguyen Anh Quynh	8b012d5	2015-08-15 14:16:39 +0800	[diff] [blame^]	1050	if (AlwaysPrintImm0 \|\| ImmOffs \|\| (sign == ARM_AM_sub)) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1051	if (ImmOffs > HEX_THRESHOLD)
Nguyen Anh Quynh	8b012d5	2015-08-15 14:16:39 +0800	[diff] [blame^]	1052	SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1053	else
Nguyen Anh Quynh	8b012d5	2015-08-15 14:16:39 +0800	[diff] [blame^]	1054	SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1055	}
Nguyen Anh Quynh	6677b99	2013-12-08 22:20:35 +0800	[diff] [blame]	1056
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1057	if (MI->csh->detail) {
Nguyen Anh Quynh	8b012d5	2015-08-15 14:16:39 +0800	[diff] [blame^]	1058	if (!sign) {
pzread	5598301	2015-02-15 18:22:51 +0900	[diff] [blame]	1059	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1060	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
				1061	} else
Nguyen Anh Quynh	b756aed	2015-02-25 18:01:02 +0800	[diff] [blame]	1062	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1063	}
Nguyen Anh Quynh	6677b99	2013-12-08 22:20:35 +0800	[diff] [blame]	1064
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1065	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1066	set_mem_access(MI, false);
				1067	}
				1068
				1069	static void printAddrMode3Operand(MCInst MI, unsigned Op, SStream O,
				1070	bool AlwaysPrintImm0)
				1071	{
				1072	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1073	if (!MCOperand_isReg(MO1)) { // For label symbolic references.
				1074	printOperand(MI, Op, O);
				1075	return;
				1076	}
				1077
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1078	printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
				1079	}
				1080
				1081	static void printAddrMode3OffsetOperand(MCInst MI, unsigned OpNum, SStream O)
				1082	{
				1083	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1084	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1085	ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1086	unsigned ImmOffs;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1087
				1088	if (MCOperand_getReg(MO1)) {
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1089	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1090	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1091	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1092	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
Nguyen Anh Quynh	8693fcd	2014-06-17 13:28:33 +0800	[diff] [blame]	1093	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1094	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1095	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1096	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1097	return;
				1098	}
				1099
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1100	ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1101	if (ImmOffs > HEX_THRESHOLD)
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1102	SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1103	else
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1104	SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1105	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1106	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
Nguyen Anh Quynh	6677b99	2013-12-08 22:20:35 +0800	[diff] [blame]	1107
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1108	if (subtracted) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1109	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1110	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
				1111	} else
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1112	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
Nguyen Anh Quynh	6677b99	2013-12-08 22:20:35 +0800	[diff] [blame]	1113
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1114	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1115	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1116	}
				1117
				1118	static void printPostIdxImm8Operand(MCInst MI, unsigned OpNum, SStream O)
				1119	{
				1120	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1121	unsigned Imm = (unsigned int)MCOperand_getImm(MO);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1122	if ((Imm & 0xff) > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1123	SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1124	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1125	SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1126	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1127	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1128	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff;
				1129	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1130	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1131	}
				1132
				1133	static void printPostIdxRegOperand(MCInst MI, unsigned OpNum, SStream O)
				1134	{
				1135	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1136	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				1137
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1138	SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-"));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1139	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1140	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1141	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1142	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
				1143	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1144	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1145	}
				1146
				1147	static void printPostIdxImm8s4Operand(MCInst MI, unsigned OpNum, SStream O)
				1148	{
				1149	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1150	unsigned Imm = (unsigned int)MCOperand_getImm(MO);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1151	if (((Imm & 0xff) << 2) > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1152	SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1153	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1154	SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1155	}
				1156
				1157	static void printAddrMode5Operand(MCInst MI, unsigned OpNum, SStream O,
				1158	bool AlwaysPrintImm0)
				1159	{
Nguyen Anh Quynh	6acaaa5	2014-11-10 17:41:05 +0800	[diff] [blame]	1160	unsigned ImmOffs;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1161	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1162	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	6acaaa5	2014-11-10 17:41:05 +0800	[diff] [blame]	1163	ARM_AM_AddrOpc subtracted = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1164
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1165	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				1166	printOperand(MI, OpNum, O);
				1167	return;
				1168	}
				1169
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1170	SStream_concat0(O, "[");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1171	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1172
Nguyen Anh Quynh	b79d915	2014-06-01 10:48:55 +0700	[diff] [blame]	1173	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1174	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
				1175	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
				1176	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
				1177	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
				1178	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
Nguyen Anh Quynh	b79d915	2014-06-01 10:48:55 +0700	[diff] [blame]	1179	}
				1180
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1181	ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	6acaaa5	2014-11-10 17:41:05 +0800	[diff] [blame]	1182	if (AlwaysPrintImm0 \|\| ImmOffs \|\| subtracted == ARM_AM_sub) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1183	if (ImmOffs * 4 > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1184	SStream_concat(O, ", #%s0x%x",
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1185	ARM_AM_getAddrOpcStr(subtracted),
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1186	ImmOffs * 4);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1187	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1188	SStream_concat(O, ", #%s%u",
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1189	ARM_AM_getAddrOpcStr(subtracted),
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1190	ImmOffs * 4);
Nguyen Anh Quynh	a04ee4f	2014-06-01 10:52:01 +0700	[diff] [blame]	1191	if (MI->csh->detail) {
Nguyen Anh Quynh	6acaaa5	2014-11-10 17:41:05 +0800	[diff] [blame]	1192	if (subtracted)
				1193	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4;
				1194	else
Nguyen Anh Quynh	51888c3	2014-11-11 23:59:23 +0800	[diff] [blame]	1195	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4;
Nguyen Anh Quynh	a04ee4f	2014-06-01 10:52:01 +0700	[diff] [blame]	1196	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1197	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1198	SStream_concat0(O, "]");
Nguyen Anh Quynh	b79d915	2014-06-01 10:48:55 +0700	[diff] [blame]	1199
				1200	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1201	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	b79d915	2014-06-01 10:48:55 +0700	[diff] [blame]	1202	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1203	}
				1204
				1205	static void printAddrMode6Operand(MCInst MI, unsigned OpNum, SStream O)
				1206	{
				1207	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1208	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1209	unsigned tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1210
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1211	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1212	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1213	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1214	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1215	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1216	tmp = (unsigned int)MCOperand_getImm(MO2);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1217	if (tmp) {
				1218	if (tmp << 3 > HEX_THRESHOLD)
				1219	SStream_concat(O, ":0x%x", (tmp << 3));
				1220	else
				1221	SStream_concat(O, ":%u", (tmp << 3));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1222	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1223	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1224	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1225	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1226	set_mem_access(MI, false);
				1227	}
				1228
				1229	static void printAddrMode7Operand(MCInst MI, unsigned OpNum, SStream O)
				1230	{
				1231	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1232	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1233	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1234	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1235	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1236	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1237	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1238	set_mem_access(MI, false);
				1239	}
				1240
				1241	static void printAddrMode6OffsetOperand(MCInst MI, unsigned OpNum, SStream O)
				1242	{
				1243	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	e19490e	2015-01-21 12:15:14 +0800	[diff] [blame]	1244	if (MCOperand_getReg(MO) == 0) {
				1245	MI->writeback = true;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1246	SStream_concat0(O, "!");
Nguyen Anh Quynh	e19490e	2015-01-21 12:15:14 +0800	[diff] [blame]	1247	} else {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1248	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1249	printRegName(MI->csh, O, MCOperand_getReg(MO));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1250	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1251	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1252	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO);
				1253	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1254	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1255	}
				1256	}
				1257
				1258	static void printBitfieldInvMaskImmOperand(MCInst MI, unsigned OpNum, SStream O)
				1259	{
				1260	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1261	uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1262	int32_t lsb = CountTrailingZeros_32(v);
				1263	int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1264
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1265	//assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1266	if (lsb > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1267	SStream_concat(O, "#0x%x", lsb);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1268	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1269	SStream_concat(O, "#%u", lsb);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1270
				1271	if (width > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1272	SStream_concat(O, ", #0x%x", width);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1273	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1274	SStream_concat(O, ", #%u", width);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1275
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1276	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1277	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1278	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
				1279	MI->flat_insn->detail->arm.op_count++;
				1280	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1281	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
				1282	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1283	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1284	}
				1285
				1286	static void printMemBOption(MCInst MI, unsigned OpNum, SStream O)
				1287	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1288	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	8cdafda	2014-11-11 22:30:30 +0800	[diff] [blame]	1289	SStream_concat0(O, ARM_MB_MemBOptToString(val + 1,
Nguyen Anh Quynh	ded1577	2015-05-24 21:33:17 +0800	[diff] [blame]	1290	(ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops) != 0));
Nguyen Anh Quynh	8cdafda	2014-11-11 22:30:30 +0800	[diff] [blame]	1291
				1292	if (MI->csh->detail) {
Nguyen Anh Quynh	51888c3	2014-11-11 23:59:23 +0800	[diff] [blame]	1293	MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1);
Nguyen Anh Quynh	8cdafda	2014-11-11 22:30:30 +0800	[diff] [blame]	1294	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1295	}
				1296
				1297	void printInstSyncBOption(MCInst MI, unsigned OpNum, SStream O)
				1298	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1299	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1300	SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1301	}
				1302
				1303	static void printShiftImmOperand(MCInst MI, unsigned OpNum, SStream O)
				1304	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1305	unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1306	bool isASR = (ShiftOp & (1 << 5)) != 0;
				1307	unsigned Amt = ShiftOp & 0x1f;
				1308	if (isASR) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1309	unsigned tmp = Amt == 0 ? 32 : Amt;
				1310	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1311	SStream_concat(O, ", asr #0x%x", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1312	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1313	SStream_concat(O, ", asr #%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1314	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1315	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
				1316	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1317	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1318	} else if (Amt) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1319	if (Amt > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1320	SStream_concat(O, ", lsl #0x%x", Amt);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1321	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1322	SStream_concat(O, ", lsl #%u", Amt);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1323	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1324	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
				1325	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1326	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1327	}
				1328	}
				1329
				1330	static void printPKHLSLShiftImm(MCInst MI, unsigned OpNum, SStream O)
				1331	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1332	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1333	if (Imm == 0)
				1334	return;
				1335	//assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1336	if (Imm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1337	SStream_concat(O, ", lsl #0x%x", Imm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1338	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1339	SStream_concat(O, ", lsl #%u", Imm);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1340	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1341	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
				1342	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1343	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1344	}
				1345
				1346	static void printPKHASRShiftImm(MCInst MI, unsigned OpNum, SStream O)
				1347	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1348	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1349	// A shift amount of 32 is encoded as 0.
				1350	if (Imm == 0)
				1351	Imm = 32;
				1352	//assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1353	if (Imm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1354	SStream_concat(O, ", asr #0x%x", Imm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1355	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1356	SStream_concat(O, ", asr #%u", Imm);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1357	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1358	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
				1359	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1360	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1361	}
				1362
				1363	// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct
				1364	static void printRegisterList(MCInst MI, unsigned OpNum, SStream O)
				1365	{
Nguyen Anh Quynh	42706a3	2014-05-09 07:33:35 +0800	[diff] [blame]	1366	unsigned i, e;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1367	SStream_concat0(O, "{");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1368	for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1369	if (i != OpNum) SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1370	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1371	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1372	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1373	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
				1374	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1375	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1376	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1377	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1378	}
				1379
				1380	static void printGPRPairOperand(MCInst MI, unsigned OpNum, SStream O,
				1381	MCRegisterInfo *MRI)
				1382	{
				1383	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1384	printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1385	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1386	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1387	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0);
				1388	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1389	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1390	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1391	printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1392	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1393	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1394	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1);
				1395	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1396	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1397	}
				1398
				1399	// SETEND BE/LE
				1400	static void printSetendOperand(MCInst MI, unsigned OpNum, SStream O)
				1401	{
				1402	MCOperand *Op = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1403	if (MCOperand_getImm(Op)) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1404	SStream_concat0(O, "be");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1405	if (MI->csh->detail) {
				1406	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
				1407	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE;
				1408	MI->flat_insn->detail->arm.op_count++;
				1409	}
				1410	} else {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1411	SStream_concat0(O, "le");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1412	if (MI->csh->detail) {
				1413	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
				1414	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE;
				1415	MI->flat_insn->detail->arm.op_count++;
				1416	}
				1417	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1418	}
				1419
				1420	static void printCPSIMod(MCInst MI, unsigned OpNum, SStream O)
				1421	{
				1422	MCOperand *Op = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1423	unsigned int mode = (unsigned int)MCOperand_getImm(Op);
				1424
				1425	SStream_concat0(O, ARM_PROC_IModToString(mode));
				1426
				1427	if (MI->csh->detail) {
				1428	MI->flat_insn->detail->arm.cps_mode = mode;
				1429	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1430	}
				1431
				1432	static void printCPSIFlag(MCInst MI, unsigned OpNum, SStream O)
				1433	{
				1434	MCOperand *Op = MCInst_getOperand(MI, OpNum);
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1435	unsigned IFlags = (unsigned int)MCOperand_getImm(Op);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1436	int i;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1437
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1438	for (i = 2; i >= 0; --i)
				1439	if (IFlags & (1 << i)) {
				1440	SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i));
				1441	}
				1442
				1443	if (IFlags == 0) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1444	SStream_concat0(O, "none");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1445	IFlags = ARM_CPSFLAG_NONE;
				1446	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1447
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1448	if (MI->csh->detail) {
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1449	MI->flat_insn->detail->arm.cps_flag = IFlags;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1450	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1451	}
				1452
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1453	static void printMSRMaskOperand(MCInst MI, unsigned OpNum, SStream O)
				1454	{
				1455	MCOperand *Op = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	07c92ec	2014-08-26 15:35:11 +0800	[diff] [blame]	1456	unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4;
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1457	unsigned Mask = MCOperand_getImm(Op) & 0xf;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1458	unsigned reg;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1459
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1460	if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
Nguyen Anh Quynh	07c92ec	2014-08-26 15:35:11 +0800	[diff] [blame]	1461	unsigned SYSm = (unsigned)MCOperand_getImm(Op);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1462	unsigned Opcode = MCInst_getOpcode(MI);
				1463	// For reads of the special registers ignore the "mask encoding" bits
				1464	// which are only for writes.
				1465	if (Opcode == ARM_t2MRS_M)
				1466	SYSm &= 0xff;
				1467	switch (SYSm) {
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1468	default: //llvm_unreachable("Unexpected mask value!");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1469	case 0:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1470	case 0x800: SStream_concat0(O, "apsr"); ARM_addSysReg(MI, ARM_SYSREG_APSR); return; // with _nzcvq bits is an alias for aspr
				1471	case 0x400: SStream_concat0(O, "apsr_g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
				1472	case 0xc00: SStream_concat0(O, "apsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1473	case 1:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1474	case 0x801: SStream_concat0(O, "iapsr"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR); return; // with _nzcvq bits is an alias for iapsr
				1475	case 0x401: SStream_concat0(O, "iapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_G); return;
				1476	case 0xc01: SStream_concat0(O, "iapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQG); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1477	case 2:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1478	case 0x802: SStream_concat0(O, "eapsr"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR); return; // with _nzcvq bits is an alias for eapsr
				1479	case 0x402: SStream_concat0(O, "eapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_G); return;
				1480	case 0xc02: SStream_concat0(O, "eapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQG); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1481	case 3:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1482	case 0x803: SStream_concat0(O, "xpsr"); ARM_addSysReg(MI, ARM_SYSREG_XPSR); return; // with _nzcvq bits is an alias for xpsr
				1483	case 0x403: SStream_concat0(O, "xpsr_g"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_G); return;
				1484	case 0xc03: SStream_concat0(O, "xpsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQG); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1485	case 5:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1486	case 0x805: SStream_concat0(O, "ipsr"); ARM_addSysReg(MI, ARM_SYSREG_IPSR); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1487	case 6:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1488	case 0x806: SStream_concat0(O, "epsr"); ARM_addSysReg(MI, ARM_SYSREG_EPSR); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1489	case 7:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1490	case 0x807: SStream_concat0(O, "iepsr"); ARM_addSysReg(MI, ARM_SYSREG_IEPSR); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1491	case 8:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1492	case 0x808: SStream_concat0(O, "msp"); ARM_addSysReg(MI, ARM_SYSREG_MSP); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1493	case 9:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1494	case 0x809: SStream_concat0(O, "psp"); ARM_addSysReg(MI, ARM_SYSREG_PSP); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1495	case 0x10:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1496	case 0x810: SStream_concat0(O, "primask"); ARM_addSysReg(MI, ARM_SYSREG_PRIMASK); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1497	case 0x11:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1498	case 0x811: SStream_concat0(O, "basepri"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1499	case 0x12:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1500	case 0x812: SStream_concat0(O, "basepri_max"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI_MAX); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1501	case 0x13:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1502	case 0x813: SStream_concat0(O, "faultmask"); ARM_addSysReg(MI, ARM_SYSREG_FAULTMASK); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1503	case 0x14:
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1504	case 0x814: SStream_concat0(O, "control"); ARM_addSysReg(MI, ARM_SYSREG_CONTROL); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1505	}
				1506	}
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1507
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1508	// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
				1509	// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
				1510	if (!SpecRegRBit && (Mask == 8 \|\| Mask == 4 \|\| Mask == 12)) {
Nguyen Anh Quynh	d865f39	2014-11-10 16:38:17 +0800	[diff] [blame]	1511	SStream_concat0(O, "apsr_");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1512	switch (Mask) {
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1513	default: // llvm_unreachable("Unexpected mask value!");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1514	case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
				1515	case 8: SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return;
				1516	case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1517	}
				1518	}
				1519
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1520	reg = 0;
				1521	if (SpecRegRBit) {
Nguyen Anh Quynh	d865f39	2014-11-10 16:38:17 +0800	[diff] [blame]	1522	SStream_concat0(O, "spsr");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1523	if (Mask) {
				1524	SStream_concat0(O, "_");
				1525	if (Mask & 8) {
				1526	SStream_concat0(O, "f");
				1527	reg += ARM_SYSREG_SPSR_F;
				1528	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1529
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1530	if (Mask & 4) {
				1531	SStream_concat0(O, "s");
				1532	reg += ARM_SYSREG_SPSR_S;
				1533	}
				1534
				1535	if (Mask & 2) {
				1536	SStream_concat0(O, "x");
				1537	reg += ARM_SYSREG_SPSR_X;
				1538	}
				1539
				1540	if (Mask & 1) {
				1541	SStream_concat0(O, "c");
				1542	reg += ARM_SYSREG_SPSR_C;
				1543	}
				1544	ARM_addSysReg(MI, reg);
				1545	}
				1546	} else {
Nguyen Anh Quynh	d865f39	2014-11-10 16:38:17 +0800	[diff] [blame]	1547	SStream_concat0(O, "cpsr");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1548	if (Mask) {
				1549	SStream_concat0(O, "_");
				1550	if (Mask & 8) {
				1551	SStream_concat0(O, "f");
				1552	reg += ARM_SYSREG_CPSR_F;
				1553	}
				1554
				1555	if (Mask & 4) {
				1556	SStream_concat0(O, "s");
				1557	reg += ARM_SYSREG_CPSR_S;
				1558	}
				1559
				1560	if (Mask & 2) {
				1561	SStream_concat0(O, "x");
				1562	reg += ARM_SYSREG_CPSR_X;
				1563	}
				1564
				1565	if (Mask & 1) {
				1566	SStream_concat0(O, "c");
				1567	reg += ARM_SYSREG_CPSR_C;
				1568	}
				1569	ARM_addSysReg(MI, reg);
				1570	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1571	}
				1572	}
				1573
				1574	static void printPredicateOperand(MCInst MI, unsigned OpNum, SStream O)
				1575	{
				1576	ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1577	// Handle the undefined 15 CC value here for printing so we don't abort().
				1578	if ((unsigned)CC == 15) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1579	SStream_concat0(O, "<und>");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1580	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1581	MI->flat_insn->detail->arm.cc = ARM_CC_INVALID;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1582	} else {
				1583	if (CC != ARMCC_AL) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1584	SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1585	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1586	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1587	MI->flat_insn->detail->arm.cc = CC + 1;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1588	}
				1589	}
				1590
				1591	// TODO: test this
				1592	static void printMandatoryPredicateOperand(MCInst MI, unsigned OpNum, SStream O)
				1593	{
				1594	ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1595	SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1596	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1597	MI->flat_insn->detail->arm.cc = CC + 1;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1598	}
				1599
				1600	static void printSBitModifierOperand(MCInst MI, unsigned OpNum, SStream O)
				1601	{
				1602	if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) {
				1603	//assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR &&
				1604	// "Expect ARM CPSR register!");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1605	SStream_concat0(O, "s");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1606	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1607	MI->flat_insn->detail->arm.update_flags = true;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1608	}
				1609	}
				1610
				1611	static void printNoHashImmediate(MCInst MI, unsigned OpNum, SStream O)
				1612	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1613	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1614	if (tmp > HEX_THRESHOLD)
				1615	SStream_concat(O, "0x%x", tmp);
				1616	else
				1617	SStream_concat(O, "%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1618	if (MI->csh->detail) {
Nguyen Anh Quynh	19b0de3	2013-12-31 22:40:04 +0800	[diff] [blame]	1619	if (MI->csh->doing_mem) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1620	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1621	} else {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1622	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1623	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				1624	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1625	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1626	}
				1627	}
				1628
				1629	static void printPImmediate(MCInst MI, unsigned OpNum, SStream O)
				1630	{
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1631	unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1632
				1633	SStream_concat(O, "p%u", imm);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1634	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1635	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1636	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1637	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1638	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1639	}
				1640
				1641	static void printCImmediate(MCInst MI, unsigned OpNum, SStream O)
				1642	{
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1643	unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1644
				1645	SStream_concat(O, "c%u", imm);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1646	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1647	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1648	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1649	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1650	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1651	}
				1652
				1653	static void printCoprocOptionImm(MCInst MI, unsigned OpNum, SStream O)
				1654	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1655	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1656	if (tmp > HEX_THRESHOLD)
				1657	SStream_concat(O, "{0x%x}", tmp);
				1658	else
				1659	SStream_concat(O, "{%u}", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1660	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1661	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1662	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				1663	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1664	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1665	}
				1666
				1667	static void printAdrLabelOperand(MCInst MI, unsigned OpNum, SStream O, unsigned scale)
				1668	{
				1669	MCOperand *MO = MCInst_getOperand(MI, OpNum);
				1670
				1671	int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale;
				1672
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1673	if (OffImm == INT32_MIN) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1674	SStream_concat0(O, "#-0");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1675	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1676	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1677	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
				1678	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1679	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1680	} else {
				1681	if (OffImm < 0)
Nguyen Anh Quynh	741a9de	2013-11-28 16:02:08 +0800	[diff] [blame]	1682	SStream_concat(O, "#-0x%x", -OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1683	else {
				1684	if (OffImm > HEX_THRESHOLD)
				1685	SStream_concat(O, "#0x%x", OffImm);
				1686	else
				1687	SStream_concat(O, "#%u", OffImm);
				1688	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1689	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1690	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1691	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
				1692	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1693	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1694	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1695	}
				1696
				1697	static void printThumbS4ImmOperand(MCInst MI, unsigned OpNum, SStream O)
				1698	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1699	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1700	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1701	SStream_concat(O, "#0x%x", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1702	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1703	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	1704	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1705	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1706	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				1707	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	1708	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1709	}
				1710
				1711	static void printThumbSRImm(MCInst MI, unsigned OpNum, SStream O)
				1712	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1713	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1714	unsigned tmp = Imm == 0 ? 32 : Imm;
				1715	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1716	SStream_concat(O, "#0x%x", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1717	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1718	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1719
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1720	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1721	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1722	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				1723	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1724	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1725	}
				1726
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1727	static void printThumbITMask(MCInst MI, unsigned OpNum, SStream O)
				1728	{
				1729	// (3 - the number of trailing zeros) is the number of then / else.
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1730	unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1731	unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1732	unsigned CondBit0 = Firstcond & 1;
				1733	unsigned NumTZ = CountTrailingZeros_32(Mask);
				1734	//assert(NumTZ <= 3 && "Invalid IT mask!");
				1735	unsigned Pos, e;
				1736	for (Pos = 3, e = NumTZ; Pos > e; --Pos) {
				1737	bool T = ((Mask >> Pos) & 1) == CondBit0;
				1738	if (T)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1739	SStream_concat0(O, "t");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1740	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1741	SStream_concat0(O, "e");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1742	}
				1743	}
				1744
				1745	static void printThumbAddrModeRROperand(MCInst MI, unsigned Op, SStream O)
				1746	{
				1747	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1748	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1749	unsigned RegNum;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1750
				1751	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				1752	printOperand(MI, Op, O);
				1753	return;
				1754	}
				1755
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1756	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1757	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1758	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1759	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1760	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1761	RegNum = MCOperand_getReg(MO2);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1762	if (RegNum) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1763	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1764	printRegName(MI->csh, O, RegNum);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1765	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1766	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1767	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1768	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1769	set_mem_access(MI, false);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1770	}
				1771
				1772	static void printThumbAddrModeImm5SOperand(MCInst MI, unsigned Op, SStream O,
				1773	unsigned Scale)
				1774	{
				1775	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1776	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1777	unsigned ImmOffs, tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1778
				1779	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				1780	printOperand(MI, Op, O);
				1781	return;
				1782	}
				1783
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1784	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1785	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1786	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1787	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1788	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1789	ImmOffs = (unsigned int)MCOperand_getImm(MO2);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1790	if (ImmOffs) {
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1791	tmp = ImmOffs * Scale;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1792	SStream_concat0(O, ", ");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1793	if (tmp > HEX_THRESHOLD)
				1794	SStream_concat(O, "#0x%x", tmp);
				1795	else
				1796	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1797	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1798	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1799	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1800	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1801	set_mem_access(MI, false);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1802	}
				1803
				1804	static void printThumbAddrModeImm5S1Operand(MCInst MI, unsigned Op, SStream O)
				1805	{
				1806	printThumbAddrModeImm5SOperand(MI, Op, O, 1);
				1807	}
				1808
				1809	static void printThumbAddrModeImm5S2Operand(MCInst MI, unsigned Op, SStream O)
				1810	{
				1811	printThumbAddrModeImm5SOperand(MI, Op, O, 2);
				1812	}
				1813
				1814	static void printThumbAddrModeImm5S4Operand(MCInst MI, unsigned Op, SStream O)
				1815	{
				1816	printThumbAddrModeImm5SOperand(MI, Op, O, 4);
				1817	}
				1818
				1819	static void printThumbAddrModeSPOperand(MCInst MI, unsigned Op, SStream O)
				1820	{
				1821	printThumbAddrModeImm5SOperand(MI, Op, O, 4);
				1822	}
				1823
				1824	// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
				1825	// register with shift forms.
				1826	// REG 0 0 - e.g. R5
				1827	// REG IMM, SH_OPC - e.g. R5, LSL #3
				1828	static void printT2SOOperand(MCInst MI, unsigned OpNum, SStream O)
				1829	{
				1830	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1831	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				1832
				1833	unsigned Reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1834	printRegName(MI->csh, O, Reg);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1835	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1836	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1837	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
				1838	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1839	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1840
				1841	// Print the shift opc.
				1842	//assert(MO2.isImm() && "Not a valid t2_so_reg value!");
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1843	printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	1844	getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1845	}
				1846
				1847	static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
				1848	SStream *O, bool AlwaysPrintImm0)
				1849	{
				1850	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1851	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	1852	int32_t OffImm;
				1853	bool isSub;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1854
				1855	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				1856	printOperand(MI, OpNum, O);
				1857	return;
				1858	}
				1859
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1860	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1861	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1862	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1863
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1864	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1865	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1866
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1867	OffImm = (int32_t)MCOperand_getImm(MO2);
				1868	isSub = OffImm < 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1869	// Special value for #-0. All others are normal.
				1870	if (OffImm == INT32_MIN)
				1871	OffImm = 0;
				1872	if (isSub) {
Nguyen Anh Quynh	a247dc1	2014-04-12 00:19:42 +0800	[diff] [blame]	1873	if (OffImm < -HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1874	SStream_concat(O, ", #-0x%x", -OffImm);
Nguyen Anh Quynh	a247dc1	2014-04-12 00:19:42 +0800	[diff] [blame]	1875	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1876	SStream_concat(O, ", #-%u", -OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1877	} else if (AlwaysPrintImm0 \|\| OffImm > 0) {
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	1878	if (OffImm >= 0) {
				1879	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1880	SStream_concat(O, ", #0x%x", OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	1881	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1882	SStream_concat(O, ", #%u", OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	1883	} else {
				1884	if (OffImm < -HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1885	SStream_concat(O, ", #-0x%x", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	1886	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1887	SStream_concat(O, ", #-%u", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	1888	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1889	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1890	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1891	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1892	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1893	set_mem_access(MI, false);
				1894	}
				1895
				1896	static void printT2AddrModeImm8Operand(MCInst MI, unsigned OpNum, SStream O,
				1897	bool AlwaysPrintImm0)
				1898	{
				1899	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1900	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	1901	int32_t OffImm;
				1902	bool isSub;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1903
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1904	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1905	set_mem_access(MI, true);
				1906
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1907	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1908	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1909	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1910
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1911	OffImm = (int32_t)MCOperand_getImm(MO2);
				1912	isSub = OffImm < 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1913	// Don't print +0.
				1914	if (OffImm == INT32_MIN)
				1915	OffImm = 0;
				1916
				1917	if (isSub)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1918	SStream_concat(O, ", #-0x%x", -OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1919	else if (AlwaysPrintImm0 \|\| OffImm > 0) {
				1920	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1921	SStream_concat(O, ", #0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1922	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1923	SStream_concat(O, ", #%u", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1924	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1925
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1926	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1927	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1928	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1929	set_mem_access(MI, false);
				1930	}
				1931
				1932	static void printT2AddrModeImm8s4Operand(MCInst *MI,
				1933	unsigned OpNum, SStream *O, bool AlwaysPrintImm0)
				1934	{
				1935	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1936	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	1937	int32_t OffImm;
				1938	bool isSub;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1939
				1940	if (!MCOperand_isReg(MO1)) { // For label symbolic references.
				1941	printOperand(MI, OpNum, O);
				1942	return;
				1943	}
				1944
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1945	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1946	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1947	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1948	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1949	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1950
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1951	OffImm = (int32_t)MCOperand_getImm(MO2);
				1952	isSub = OffImm < 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1953
				1954	//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
				1955
				1956	// Don't print +0.
				1957	if (OffImm == INT32_MIN)
				1958	OffImm = 0;
				1959	if (isSub) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1960	SStream_concat(O, ", #-0x%x", -OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1961	} else if (AlwaysPrintImm0 \|\| OffImm > 0) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1962	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1963	SStream_concat(O, ", #0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1964	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1965	SStream_concat(O, ", #%u", OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1966	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1967	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1968	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1969
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1970	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1971	set_mem_access(MI, false);
				1972	}
				1973
				1974	static void printT2AddrModeImm0_1020s4Operand(MCInst MI, unsigned OpNum, SStream O)
				1975	{
				1976	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1977	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1978	unsigned tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1979
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1980	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1981	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1982	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1983	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1984	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1985	if (MCOperand_getImm(MO2)) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1986	SStream_concat0(O, ", ");
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1987	tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1988	if (tmp > HEX_THRESHOLD)
				1989	SStream_concat(O, "#0x%x", tmp);
				1990	else
				1991	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1992	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1993	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1994	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1995	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1996	set_mem_access(MI, false);
				1997	}
				1998
				1999	static void printT2AddrModeImm8OffsetOperand(MCInst *MI,
				2000	unsigned OpNum, SStream *O)
				2001	{
				2002	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2003	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2004	SStream_concat0(O, ", ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2005	if (OffImm == INT32_MIN) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2006	SStream_concat0(O, "#-0");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2007	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2008	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2009	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
				2010	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2011	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2012	} else {
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2013	if (OffImm < 0) {
				2014	if (OffImm < -HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2015	SStream_concat(O, "#-0x%x", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2016	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2017	SStream_concat(O, "#-%u", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2018	} else {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2019	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2020	SStream_concat(O, "#0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2021	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2022	SStream_concat(O, "#%u", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2023	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2024	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2025	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2026	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
				2027	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2028	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2029	}
				2030	}
				2031
				2032	static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI,
				2033	unsigned OpNum, SStream *O)
				2034	{
				2035	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2036	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
				2037
				2038	//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
				2039
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2040	SStream_concat0(O, ", ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2041	if (OffImm == INT32_MIN) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2042	SStream_concat0(O, "#-0");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2043	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2044	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2045	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
				2046	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2047	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2048	} else {
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2049	if (OffImm < 0) {
				2050	if (OffImm < -HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2051	SStream_concat(O, "#-0x%x", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2052	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2053	SStream_concat(O, "#-%u", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2054	} else {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2055	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2056	SStream_concat(O, "#0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2057	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2058	SStream_concat(O, "#%u", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2059	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2060	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2061	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2062	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
				2063	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2064	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2065	}
				2066	}
				2067
				2068	static void printT2AddrModeSoRegOperand(MCInst *MI,
				2069	unsigned OpNum, SStream *O)
				2070	{
				2071	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2072	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				2073	MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	2074	unsigned ShAmt;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2075
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2076	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2077	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2078	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2079	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2080	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2081
				2082	//assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2083	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2084	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2085	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2086	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2087
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	2088	ShAmt = (unsigned int)MCOperand_getImm(MO3);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2089	if (ShAmt) {
				2090	//assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2091	SStream_concat0(O, ", lsl ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2092	SStream_concat(O, "#%d", ShAmt);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2093	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2094	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
				2095	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2096	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2097	}
				2098
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2099	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2100	set_mem_access(MI, false);
				2101	}
				2102
				2103	static void printFPImmOperand(MCInst MI, unsigned OpNum, SStream O)
				2104	{
				2105	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	2ac5d79	2014-11-10 21:46:34 +0800	[diff] [blame]	2106	SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2107	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2108	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP;
				2109	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
				2110	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2111	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2112	}
				2113
				2114	static void printNEONModImmOperand(MCInst MI, unsigned OpNum, SStream O)
				2115	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2116	unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2117	unsigned EltBits;
				2118	uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2119	if (Val > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2120	SStream_concat(O, "#0x%"PRIx64, Val);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2121	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2122	SStream_concat(O, "#%"PRIu64, Val);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2123	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2124	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2125	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val;
				2126	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2127	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2128	}
				2129
				2130	static void printImmPlusOneOperand(MCInst MI, unsigned OpNum, SStream O)
				2131	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2132	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2133	if (Imm + 1 > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2134	SStream_concat(O, "#0x%x", Imm + 1);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2135	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2136	SStream_concat(O, "#%u", Imm + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2137	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2138	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2139	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
				2140	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2141	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2142	}
				2143
				2144	static void printRotImmOperand(MCInst MI, unsigned OpNum, SStream O)
				2145	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2146	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2147	if (Imm == 0)
				2148	return;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2149	SStream_concat0(O, ", ror #");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2150	switch (Imm) {
				2151	default: //assert (0 && "illegal ror immediate!");
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2152	case 1: SStream_concat0(O, "8"); break;
				2153	case 2: SStream_concat0(O, "16"); break;
				2154	case 3: SStream_concat0(O, "24"); break;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2155	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2156	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2157	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR;
				2158	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2159	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2160	}
				2161
				2162	static void printFBits16(MCInst MI, unsigned OpNum, SStream O)
				2163	{
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	2164	unsigned tmp;
				2165
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	2166	tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2167	if (tmp > HEX_THRESHOLD)
				2168	SStream_concat(O, "#0x%x", tmp);
				2169	else
				2170	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2171	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2172	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2173	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				2174	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2175	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2176	}
				2177
				2178	static void printFBits32(MCInst MI, unsigned OpNum, SStream O)
				2179	{
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	2180	unsigned tmp;
				2181
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	2182	tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2183	if (tmp > HEX_THRESHOLD)
				2184	SStream_concat(O, "#0x%x", tmp);
				2185	else
				2186	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2187	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2188	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2189	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				2190	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2191	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2192	}
				2193
				2194	static void printVectorIndex(MCInst MI, unsigned OpNum, SStream O)
				2195	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2196	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2197	if (tmp > HEX_THRESHOLD)
				2198	SStream_concat(O, "[0x%x]",tmp);
				2199	else
				2200	SStream_concat(O, "[%u]",tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2201	if (MI->csh->detail) {
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	2202	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2203	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2204	}
				2205
				2206	static void printVectorListOne(MCInst MI, unsigned OpNum, SStream O)
				2207	{
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2208	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2209	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2210	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2211	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2212	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2213	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2214	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2215	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2216	}
				2217
				2218	static void printVectorListTwo(MCInst *MI, unsigned OpNum,
				2219	SStream O, MCRegisterInfo MRI)
				2220	{
				2221	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2222	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
				2223	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2224	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2225	printRegName(MI->csh, O, Reg0);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2226	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2227	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2228	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
				2229	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2230	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2231	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2232	printRegName(MI->csh, O, Reg1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2233	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2234	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2235	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
				2236	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2237	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2238	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2239	}
				2240
				2241	static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum,
				2242	SStream O, MCRegisterInfo MRI)
				2243	{
				2244	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2245	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
				2246	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2247	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2248	printRegName(MI->csh, O, Reg0);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2249	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2250	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2251	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
				2252	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2253	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2254	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2255	printRegName(MI->csh, O, Reg1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2256	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2257	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2258	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
				2259	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2260	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2261	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2262	}
				2263
				2264	static void printVectorListThree(MCInst MI, unsigned OpNum, SStream O)
				2265	{
				2266	// Normally, it's not safe to use register enum values directly with
				2267	// addition to get the next register, but for VFP registers, the
				2268	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2269	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2270	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2271	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2272	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2273	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2274	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2275	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2276	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2277	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2278	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2279	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2280	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
				2281	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2282	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2283	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2284	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2285	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2286	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2287	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
				2288	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2289	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2290	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2291	}
				2292
				2293	static void printVectorListFour(MCInst MI, unsigned OpNum, SStream O)
				2294	{
				2295	// Normally, it's not safe to use register enum values directly with
				2296	// addition to get the next register, but for VFP registers, the
				2297	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2298	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2299	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2300	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2301	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2302	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2303	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2304	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2305	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2306	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2307	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2308	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2309	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
				2310	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2311	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2312	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2313	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2314	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2315	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2316	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
				2317	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2318	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2319	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2320	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2321	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2322	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2323	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
				2324	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2325	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2326	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2327	}
				2328
				2329	static void printVectorListOneAllLanes(MCInst MI, unsigned OpNum, SStream O)
				2330	{
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2331	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2332	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2333	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2334	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2335	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2336	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2337	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2338	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2339	}
				2340
				2341	static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum,
				2342	SStream O, MCRegisterInfo MRI)
				2343	{
				2344	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2345	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
				2346	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2347	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2348	printRegName(MI->csh, O, Reg0);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2349	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2350	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2351	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
				2352	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2353	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2354	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2355	printRegName(MI->csh, O, Reg1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2356	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2357	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2358	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
				2359	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2360	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2361	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2362	}
				2363
				2364	static void printVectorListThreeAllLanes(MCInst MI, unsigned OpNum, SStream O)
				2365	{
				2366	// Normally, it's not safe to use register enum values directly with
				2367	// addition to get the next register, but for VFP registers, the
				2368	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2369	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2370	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2371	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2372	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2373	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2374	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2375	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2376	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2377	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2378	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2379	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2380	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
				2381	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2382	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2383	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2384	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2385	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2386	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2387	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
				2388	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2389	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2390	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2391	}
				2392
				2393	static void printVectorListFourAllLanes(MCInst MI, unsigned OpNum, SStream O)
				2394	{
				2395	// Normally, it's not safe to use register enum values directly with
				2396	// addition to get the next register, but for VFP registers, the
				2397	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2398	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2399	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2400	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2401	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2402	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2403	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2404	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2405	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2406	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2407	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2408	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2409	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
				2410	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2411	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2412	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2413	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2414	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2415	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2416	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
				2417	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2418	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2419	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2420	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2421	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2422	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2423	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
				2424	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2425	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2426	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2427	}
				2428
				2429	static void printVectorListTwoSpacedAllLanes(MCInst *MI,
				2430	unsigned OpNum, SStream O, MCRegisterInfo MRI)
				2431	{
				2432	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2433	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
				2434	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2435	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2436	printRegName(MI->csh, O, Reg0);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2437	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2438	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2439	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
				2440	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2441	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2442	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2443	printRegName(MI->csh, O, Reg1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2444	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2445	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2446	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
				2447	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2448	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2449	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2450	}
				2451
				2452	static void printVectorListThreeSpacedAllLanes(MCInst *MI,
				2453	unsigned OpNum, SStream *O)
				2454	{
				2455	// Normally, it's not safe to use register enum values directly with
				2456	// addition to get the next register, but for VFP registers, the
				2457	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2458	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2459	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2460	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2461	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2462	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2463	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2464	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2465	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2466	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2467	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2468	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2469	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
				2470	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2471	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2472	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2473	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2474	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2475	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2476	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
				2477	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2478	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2479	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2480	}
				2481
				2482	static void printVectorListFourSpacedAllLanes(MCInst *MI,
				2483	unsigned OpNum, SStream *O)
				2484	{
				2485	// Normally, it's not safe to use register enum values directly with
				2486	// addition to get the next register, but for VFP registers, the
				2487	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2488	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2489	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2490	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2491	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2492	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2493	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2494	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2495	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2496	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2497	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2498	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2499	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
				2500	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2501	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2502	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2503	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2504	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2505	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2506	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
				2507	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2508	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2509	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2510	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2511	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2512	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2513	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
				2514	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2515	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2516	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2517	}
				2518
				2519	static void printVectorListThreeSpaced(MCInst MI, unsigned OpNum, SStream O)
				2520	{
				2521	// Normally, it's not safe to use register enum values directly with
				2522	// addition to get the next register, but for VFP registers, the
				2523	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2524	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2525	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2526	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2527	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2528	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2529	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2530	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2531	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2532	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2533	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2534	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2535	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
				2536	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2537	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2538	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2539	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2540	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2541	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2542	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
				2543	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2544	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2545	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2546	}
				2547
				2548	static void printVectorListFourSpaced(MCInst MI, unsigned OpNum, SStream O)
				2549	{
				2550	// Normally, it's not safe to use register enum values directly with
				2551	// addition to get the next register, but for VFP registers, the
				2552	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2553	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2554	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2555	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2556	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2557	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2558	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2559	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2560	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2561	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2562	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2563	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2564	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
				2565	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2566	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2567	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2568	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2569	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2570	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2571	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
				2572	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2573	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2574	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2575	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2576	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2577	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2578	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
				2579	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2580	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2581	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2582	}
Nguyen Anh Quynh	8598a21	2014-05-14 11:26:41 +0800	[diff] [blame]	2583
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	2584	void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd)
				2585	{
				2586	if (MI->csh->detail) {
				2587	MI->flat_insn->detail->arm.vector_data = vd;
				2588	}
				2589	}
				2590
				2591	void ARM_addVectorDataSize(MCInst *MI, int size)
				2592	{
				2593	if (MI->csh->detail) {
				2594	MI->flat_insn->detail->arm.vector_size = size;
				2595	}
				2596	}
				2597
				2598	void ARM_addReg(MCInst *MI, int reg)
				2599	{
				2600	if (MI->csh->detail) {
				2601	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2602	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
				2603	MI->flat_insn->detail->arm.op_count++;
				2604	}
				2605	}
				2606
				2607	void ARM_addUserMode(MCInst *MI)
				2608	{
				2609	if (MI->csh->detail) {
				2610	MI->flat_insn->detail->arm.usermode = true;
				2611	}
				2612	}
				2613
				2614	void ARM_addSysReg(MCInst *MI, arm_sysreg reg)
				2615	{
				2616	if (MI->csh->detail) {
				2617	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG;
				2618	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
				2619	MI->flat_insn->detail->arm.op_count++;
				2620	}
				2621	}
				2622
Nguyen Anh Quynh	8598a21	2014-05-14 11:26:41 +0800	[diff] [blame]	2623	#endif