Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / capstone / a6609fede895063c62b2ef5710dbc4e473924347 / . / arch / Sparc / SparcGenAsmWriter.inc
blob: b8f34959d7ff35021775a60ee50d8cd82c95179d [file] [log] [blame]
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|*Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9/* Capstone Disassembly Engine */
10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
11
12#include <stdio.h> // debug
Nguyen Anh Quynhb158b932016-04-26 09:47:30 +0800[diff] [blame]13#include <platform.h>
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]14
15
16/// printInstruction - This method is automatically generated by tablegen
17/// from the instruction set description.
18static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
19{
20 static const uint32_t OpInfo[] = {
21 0U, // PHI
22 0U, // INLINEASM
23 0U, // CFI_INSTRUCTION
24 0U, // EH_LABEL
25 0U, // GC_LABEL
26 0U, // KILL
27 0U, // EXTRACT_SUBREG
28 0U, // INSERT_SUBREG
29 0U, // IMPLICIT_DEF
30 0U, // SUBREG_TO_REG
31 0U, // COPY_TO_REGCLASS
32 2452U, // DBG_VALUE
33 0U, // REG_SEQUENCE
34 0U, // COPY
35 2445U, // BUNDLE
36 2462U, // LIFETIME_START
37 2432U, // LIFETIME_END
38 0U, // STACKMAP
39 0U, // PATCHPOINT
Nguyen Anh Quynh159ddbd2014-08-15 16:35:12 +0800[diff] [blame]40 0U, // LOAD_STACK_GUARD
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]41 4688U, // ADDCCri
42 4688U, // ADDCCrr
43 5925U, // ADDCri
44 5925U, // ADDCrr
45 4772U, // ADDEri
46 4772U, // ADDErr
47 4786U, // ADDXC
48 4678U, // ADDXCCC
49 4808U, // ADDXri
50 4808U, // ADDXrr
51 4808U, // ADDri
52 4808U, // ADDrr
53 74166U, // ADJCALLSTACKDOWN
54 74185U, // ADJCALLSTACKUP
55 5497U, // ALIGNADDR
56 5127U, // ALIGNADDRL
57 4695U, // ANDCCri
58 4695U, // ANDCCrr
59 4718U, // ANDNCCri
60 4718U, // ANDNCCrr
61 5182U, // ANDNri
62 5182U, // ANDNrr
63 5182U, // ANDXNrr
64 4876U, // ANDXri
65 4876U, // ANDXrr
66 4876U, // ANDri
67 4876U, // ANDrr
68 4502U, // ARRAY16
69 4255U, // ARRAY32
70 4526U, // ARRAY8
71 0U, // ATOMIC_LOAD_ADD_32
72 0U, // ATOMIC_LOAD_ADD_64
73 0U, // ATOMIC_LOAD_AND_32
74 0U, // ATOMIC_LOAD_AND_64
75 0U, // ATOMIC_LOAD_MAX_32
76 0U, // ATOMIC_LOAD_MAX_64
77 0U, // ATOMIC_LOAD_MIN_32
78 0U, // ATOMIC_LOAD_MIN_64
79 0U, // ATOMIC_LOAD_NAND_32
80 0U, // ATOMIC_LOAD_NAND_64
81 0U, // ATOMIC_LOAD_OR_32
82 0U, // ATOMIC_LOAD_OR_64
83 0U, // ATOMIC_LOAD_SUB_32
84 0U, // ATOMIC_LOAD_SUB_64
85 0U, // ATOMIC_LOAD_UMAX_32
86 0U, // ATOMIC_LOAD_UMAX_64
87 0U, // ATOMIC_LOAD_UMIN_32
88 0U, // ATOMIC_LOAD_UMIN_64
89 0U, // ATOMIC_LOAD_XOR_32
90 0U, // ATOMIC_LOAD_XOR_64
91 0U, // ATOMIC_SWAP_64
92 74271U, // BA
93 1194492U, // BCOND
94 1260028U, // BCONDA
95 17659U, // BINDri
96 17659U, // BINDrr
97 5065U, // BMASK
98 145915U, // BPFCC
99 211451U, // BPFCCA
100 276987U, // BPFCCANT
101 342523U, // BPFCCNT
102 2106465U, // BPGEZapn
103 2105838U, // BPGEZapt
104 2106532U, // BPGEZnapn
105 2107288U, // BPGEZnapt
106 2106489U, // BPGZapn
107 2105856U, // BPGZapt
108 2106552U, // BPGZnapn
109 2107384U, // BPGZnapt
110 1456636U, // BPICC
111 473596U, // BPICCA
112 539132U, // BPICCANT
113 604668U, // BPICCNT
114 2106477U, // BPLEZapn
115 2105847U, // BPLEZapt
116 2106542U, // BPLEZnapn
117 2107337U, // BPLEZnapt
118 2106500U, // BPLZapn
119 2105864U, // BPLZapt
120 2106561U, // BPLZnapn
121 2107428U, // BPLZnapt
122 2106511U, // BPNZapn
123 2105872U, // BPNZapt
124 2106570U, // BPNZnapn
125 2107472U, // BPNZnapt
126 1718780U, // BPXCC
127 735740U, // BPXCCA
128 801276U, // BPXCCANT
129 866812U, // BPXCCNT
130 2106522U, // BPZapn
131 2105880U, // BPZapt
132 2106579U, // BPZnapn
133 2107505U, // BPZnapt
134 4983U, // BSHUFFLE
135 74742U, // CALL
136 17398U, // CALLri
137 17398U, // CALLrr
138 924148U, // CASXrr
139 924129U, // CASrr
140 74001U, // CMASK16
141 73833U, // CMASK32
142 74150U, // CMASK8
143 2106607U, // CMPri
144 2106607U, // CMPrr
145 4332U, // EDGE16
146 5081U, // EDGE16L
147 5198U, // EDGE16LN
148 5165U, // EDGE16N
149 4164U, // EDGE32
150 5072U, // EDGE32L
151 5188U, // EDGE32LN
152 5156U, // EDGE32N
153 4511U, // EDGE8
154 5090U, // EDGE8L
155 5208U, // EDGE8LN
156 5174U, // EDGE8N
157 1053516U, // FABSD
158 1054031U, // FABSQ
159 1054376U, // FABSS
160 4813U, // FADDD
161 5383U, // FADDQ
162 5645U, // FADDS
163 4648U, // FALIGNADATA
164 4875U, // FAND
165 4112U, // FANDNOT1
166 5544U, // FANDNOT1S
167 4271U, // FANDNOT2
168 5591U, // FANDNOT2S
169 5677U, // FANDS
170 1194491U, // FBCOND
171 1260027U, // FBCONDA
172 4394U, // FCHKSM16
173 2106173U, // FCMPD
174 4413U, // FCMPEQ16
175 4226U, // FCMPEQ32
176 4432U, // FCMPGT16
177 4245U, // FCMPGT32
178 4340U, // FCMPLE16
179 4172U, // FCMPLE32
180 4350U, // FCMPNE16
181 4182U, // FCMPNE32
182 2106696U, // FCMPQ
183 2107005U, // FCMPS
184 4960U, // FDIVD
185 5475U, // FDIVQ
186 5815U, // FDIVS
187 5405U, // FDMULQ
188 1053620U, // FDTOI
189 1053996U, // FDTOQ
190 1054305U, // FDTOS
191 1054536U, // FDTOX
192 1053464U, // FEXPAND
193 4820U, // FHADDD
194 5652U, // FHADDS
195 4800U, // FHSUBD
196 5637U, // FHSUBS
197 1053473U, // FITOD
198 1054003U, // FITOQ
199 1054312U, // FITOS
200 6300484U, // FLCMPD
201 6301316U, // FLCMPS
202 2606U, // FLUSHW
203 4404U, // FMEAN16
204 1053543U, // FMOVD
205 1006078U, // FMOVD_FCC
206 23484926U, // FMOVD_ICC
207 23747070U, // FMOVD_XCC
208 1054058U, // FMOVQ
209 1006102U, // FMOVQ_FCC
210 23484950U, // FMOVQ_ICC
211 23747094U, // FMOVQ_XCC
212 6018U, // FMOVRGEZD
213 6029U, // FMOVRGEZQ
214 6056U, // FMOVRGEZS
215 6116U, // FMOVRGZD
216 6126U, // FMOVRGZQ
217 6150U, // FMOVRGZS
218 6067U, // FMOVRLEZD
219 6078U, // FMOVRLEZQ
220 6105U, // FMOVRLEZS
221 6160U, // FMOVRLZD
222 6170U, // FMOVRLZQ
223 6194U, // FMOVRLZS
224 6204U, // FMOVRNZD
225 6214U, // FMOVRNZQ
226 6238U, // FMOVRNZS
227 6009U, // FMOVRZD
228 6248U, // FMOVRZQ
229 6269U, // FMOVRZS
230 1054398U, // FMOVS
231 1006114U, // FMOVS_FCC
232 23484962U, // FMOVS_ICC
233 23747106U, // FMOVS_XCC
234 4490U, // FMUL8SUX16
235 4465U, // FMUL8ULX16
236 4442U, // FMUL8X16
237 5098U, // FMUL8X16AL
238 5849U, // FMUL8X16AU
239 4860U, // FMULD
240 4477U, // FMULD8SUX16
241 4452U, // FMULD8ULX16
242 5413U, // FMULQ
243 5714U, // FMULS
244 4837U, // FNADDD
245 5669U, // FNADDS
246 4881U, // FNAND
247 5684U, // FNANDS
248 1053429U, // FNEGD
249 1053974U, // FNEGQ
250 1054283U, // FNEGS
251 4828U, // FNHADDD
252 5660U, // FNHADDS
253 4828U, // FNMULD
254 5660U, // FNMULS
255 5513U, // FNOR
256 5778U, // FNORS
257 1052698U, // FNOT1
258 1054131U, // FNOT1S
259 1052857U, // FNOT2
260 1054178U, // FNOT2S
261 5660U, // FNSMULD
262 74625U, // FONE
263 75324U, // FONES
264 5508U, // FOR
265 4129U, // FORNOT1
266 5563U, // FORNOT1S
267 4288U, // FORNOT2
268 5610U, // FORNOT2S
269 5772U, // FORS
270 1052936U, // FPACK16
271 4192U, // FPACK32
272 1054507U, // FPACKFIX
273 4323U, // FPADD16
274 5620U, // FPADD16S
275 4155U, // FPADD32
276 5573U, // FPADD32S
277 4297U, // FPADD64
278 4974U, // FPMERGE
279 4314U, // FPSUB16
280 4580U, // FPSUB16S
281 4146U, // FPSUB32
282 4570U, // FPSUB32S
283 1053480U, // FQTOD
284 1053627U, // FQTOI
285 1054319U, // FQTOS
286 1054552U, // FQTOX
287 4423U, // FSLAS16
288 4236U, // FSLAS32
289 4378U, // FSLL16
290 4210U, // FSLL32
291 4867U, // FSMULD
292 1053523U, // FSQRTD
293 1054038U, // FSQRTQ
294 1054383U, // FSQRTS
295 4306U, // FSRA16
296 4138U, // FSRA32
297 1052681U, // FSRC1
298 1054112U, // FSRC1S
299 1052840U, // FSRC2
300 1054159U, // FSRC2S
301 4386U, // FSRL16
302 4218U, // FSRL32
303 1053487U, // FSTOD
304 1053634U, // FSTOI
305 1054010U, // FSTOQ
306 1054559U, // FSTOX
307 4793U, // FSUBD
308 5376U, // FSUBQ
309 5630U, // FSUBS
310 5519U, // FXNOR
311 5785U, // FXNORS
312 5526U, // FXOR
313 5793U, // FXORS
314 1053494U, // FXTOD
315 1054017U, // FXTOQ
316 1054326U, // FXTOS
317 74984U, // FZERO
318 75353U, // FZEROS
319 24584U, // GETPCX
320 1078273U, // JMPLri
321 1078273U, // JMPLrr
322 1997243U, // LDDFri
323 1997243U, // LDDFrr
324 1997249U, // LDFri
325 1997249U, // LDFrr
326 1997275U, // LDQFri
327 1997275U, // LDQFrr
328 1997229U, // LDSBri
329 1997229U, // LDSBrr
330 1997254U, // LDSHri
331 1997254U, // LDSHrr
332 1997287U, // LDSWri
333 1997287U, // LDSWrr
334 1997236U, // LDUBri
335 1997236U, // LDUBrr
336 1997261U, // LDUHri
337 1997261U, // LDUHrr
338 1997294U, // LDXri
339 1997294U, // LDXrr
340 1997249U, // LDri
341 1997249U, // LDrr
342 33480U, // LEAX_ADDri
343 33480U, // LEA_ADDri
344 1054405U, // LZCNT
345 75121U, // MEMBARi
346 1054543U, // MOVDTOX
347 1006122U, // MOVFCCri
348 1006122U, // MOVFCCrr
349 23484970U, // MOVICCri
350 23484970U, // MOVICCrr
351 6047U, // MOVRGEZri
352 6047U, // MOVRGEZrr
353 6142U, // MOVRGZri
354 6142U, // MOVRGZrr
355 6096U, // MOVRLEZri
356 6096U, // MOVRLEZrr
357 6186U, // MOVRLZri
358 6186U, // MOVRLZrr
359 6230U, // MOVRNZri
360 6230U, // MOVRNZrr
361 6262U, // MOVRRZri
362 6262U, // MOVRRZrr
363 1054469U, // MOVSTOSW
364 1054479U, // MOVSTOUW
365 1054543U, // MOVWTOS
366 23747114U, // MOVXCCri
367 23747114U, // MOVXCCrr
368 1054543U, // MOVXTOD
369 5954U, // MULXri
370 5954U, // MULXrr
371 2578U, // NOP
372 4735U, // ORCCri
373 4735U, // ORCCrr
374 4726U, // ORNCCri
375 4726U, // ORNCCrr
376 5339U, // ORNri
377 5339U, // ORNrr
378 5339U, // ORXNrr
379 5509U, // ORXri
380 5509U, // ORXrr
381 5509U, // ORri
382 5509U, // ORrr
383 5836U, // PDIST
384 5344U, // PDISTN
385 1053356U, // POPCrr
386 73729U, // RDY
387 4999U, // RESTOREri
388 4999U, // RESTORErr
389 76132U, // RET
390 76141U, // RETL
391 18131U, // RETTri
392 18131U, // RETTrr
393 5008U, // SAVEri
394 5008U, // SAVErr
395 4748U, // SDIVCCri
396 4748U, // SDIVCCrr
397 5995U, // SDIVXri
398 5995U, // SDIVXrr
399 5861U, // SDIVri
400 5861U, // SDIVrr
401 2182U, // SELECT_CC_DFP_FCC
402 2293U, // SELECT_CC_DFP_ICC
403 2238U, // SELECT_CC_FP_FCC
404 2349U, // SELECT_CC_FP_ICC
405 2265U, // SELECT_CC_Int_FCC
406 2376U, // SELECT_CC_Int_ICC
407 2210U, // SELECT_CC_QFP_FCC
408 2321U, // SELECT_CC_QFP_ICC
409 1053595U, // SETHIXi
410 1053595U, // SETHIi
411 2569U, // SHUTDOWN
412 2564U, // SIAM
413 5941U, // SLLXri
414 5941U, // SLLXrr
415 5116U, // SLLri
416 5116U, // SLLrr
417 4702U, // SMULCCri
418 4702U, // SMULCCrr
419 5144U, // SMULri
420 5144U, // SMULrr
421 5913U, // SRAXri
422 5913U, // SRAXrr
423 4643U, // SRAri
424 4643U, // SRArr
425 5947U, // SRLXri
426 5947U, // SRLXrr
427 5139U, // SRLri
428 5139U, // SRLrr
429 2588U, // STBAR
430 37428U, // STBri
431 37428U, // STBrr
432 37723U, // STDFri
433 37723U, // STDFrr
434 38607U, // STFri
435 38607U, // STFrr
436 37782U, // STHri
437 37782U, // STHrr
438 38238U, // STQFri
439 38238U, // STQFrr
440 38758U, // STXri
441 38758U, // STXrr
442 38607U, // STri
443 38607U, // STrr
444 4671U, // SUBCCri
445 4671U, // SUBCCrr
446 5919U, // SUBCri
447 5919U, // SUBCrr
448 4764U, // SUBEri
449 4764U, // SUBErr
450 4665U, // SUBXri
451 4665U, // SUBXrr
452 4665U, // SUBri
453 4665U, // SUBrr
454 1997268U, // SWAPri
455 1997268U, // SWAPrr
456 2422U, // TA3
457 2427U, // TA5
458 5883U, // TADDCCTVri
459 5883U, // TADDCCTVrr
460 4687U, // TADDCCri
461 4687U, // TADDCCrr
462 9873960U, // TICCri
463 9873960U, // TICCrr
464 37753544U, // TLS_ADDXrr
465 37753544U, // TLS_ADDrr
466 2106358U, // TLS_CALL
467 39746030U, // TLS_LDXrr
468 39745985U, // TLS_LDrr
469 5873U, // TSUBCCTVri
470 5873U, // TSUBCCTVrr
471 4670U, // TSUBCCri
472 4670U, // TSUBCCrr
473 10136104U, // TXCCri
474 10136104U, // TXCCrr
475 4756U, // UDIVCCri
476 4756U, // UDIVCCrr
477 6002U, // UDIVXri
478 6002U, // UDIVXrr
479 5867U, // UDIVri
480 5867U, // UDIVrr
481 4710U, // UMULCCri
482 4710U, // UMULCCrr
483 5026U, // UMULXHI
484 5150U, // UMULri
485 5150U, // UMULrr
486 74996U, // UNIMP
487 6300477U, // V9FCMPD
488 6300397U, // V9FCMPED
489 6300942U, // V9FCMPEQ
490 6301251U, // V9FCMPES
491 6301000U, // V9FCMPQ
492 6301309U, // V9FCMPS
493 47614U, // V9FMOVD_FCC
494 47638U, // V9FMOVQ_FCC
495 47650U, // V9FMOVS_FCC
496 47658U, // V9MOVFCCri
497 47658U, // V9MOVFCCrr
498 14689692U, // WRYri
499 14689692U, // WRYrr
500 5953U, // XMULX
501 5035U, // XMULXHI
502 4733U, // XNORCCri
503 4733U, // XNORCCrr
504 5520U, // XNORXrr
505 5520U, // XNORri
506 5520U, // XNORrr
507 4741U, // XORCCri
508 4741U, // XORCCrr
509 5527U, // XORXri
510 5527U, // XORXrr
511 5527U, // XORri
512 5527U, // XORrr
513 0U
514 };
515
516#ifndef CAPSTONE_DIET
517 static char AsmStrs[] = {
518 /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
519 /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
520 /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
521 /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
522 /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
523 /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
524 /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
525 /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
526 /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
527 /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
528 /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
529 /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
530 /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
531 /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
532 /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
533 /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
534 /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
535 /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
536 /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
537 /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
538 /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
539 /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
540 /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
541 /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
542 /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
543 /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
544 /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
545 /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
546 /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
547 /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
548 /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
549 /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
550 /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
551 /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
552 /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
553 /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
554 /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
555 /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
556 /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
557 /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
558 /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
559 /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
560 /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
561 /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
562 /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
563 /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
564 /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
565 /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
566 /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
567 /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
568 /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
569 /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
570 /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
571 /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
572 /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
573 /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
574 /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
575 /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
576 /* 542 */ 'b', 'a', 32, 0,
577 /* 546 */ 's', 'r', 'a', 32, 0,
578 /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
579 /* 563 */ 's', 't', 'b', 32, 0,
580 /* 568 */ 's', 'u', 'b', 32, 0,
581 /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
582 /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
583 /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
584 /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
585 /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
586 /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
587 /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
588 /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
589 /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
590 /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
591 /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
592 /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
593 /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
594 /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
595 /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
596 /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
597 /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
598 /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
599 /* 711 */ 'a', 'd', 'd', 32, 0,
600 /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
601 /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
602 /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
603 /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
604 /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
605 /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
606 /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
607 /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
608 /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
609 /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
610 /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
611 /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
612 /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
613 /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
614 /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
615 /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
616 /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
617 /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
618 /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
619 /* 858 */ 's', 't', 'd', 32, 0,
620 /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
621 /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
622 /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
623 /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
624 /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
625 /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
626 /* 911 */ 's', 'a', 'v', 'e', 32, 0,
627 /* 917 */ 's', 't', 'h', 32, 0,
628 /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
629 /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
630 /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
631 /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
632 /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
633 /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
634 /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
635 /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
636 /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
637 /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
638 /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
639 /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
640 /* 1019 */ 's', 'l', 'l', 32, 0,
641 /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
642 /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
643 /* 1042 */ 's', 'r', 'l', 32, 0,
644 /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
645 /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
646 /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
647 /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
648 /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
649 /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
650 /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
651 /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
652 /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
653 /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
654 /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
655 /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656 /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657 /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658 /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659 /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
660 /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
661 /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
662 /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
663 /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
664 /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
665 /* 1242 */ 'o', 'r', 'n', 32, 0,
666 /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
667 /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
668 /* 1262 */ 'c', 'm', 'p', 32, 0,
669 /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
670 /* 1274 */ 'j', 'm', 'p', 32, 0,
671 /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
672 /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
673 /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
674 /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
675 /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
676 /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
677 /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
678 /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
679 /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
680 /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
681 /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
682 /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
683 /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
684 /* 1373 */ 's', 't', 'q', 32, 0,
685 /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
686 /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
687 /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
688 /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
689 /* 1411 */ 'f', 'o', 'r', 32, 0,
690 /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
691 /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
692 /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
693 /* 1435 */ 'w', 'r', 32, 0,
694 /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
695 /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
696 /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
697 /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
698 /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
699 /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
700 /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
701 /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
702 /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
703 /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
704 /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
705 /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
706 /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
707 /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
708 /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
709 /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
710 /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
711 /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
712 /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
713 /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
714 /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
715 /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
716 /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
717 /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
718 /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
719 /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
720 /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
721 /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
722 /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
723 /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
724 /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
725 /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
726 /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
727 /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
728 /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
729 /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
730 /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
731 /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
732 /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
733 /* 1746 */ 'r', 'e', 't', 't', 32, 0,
734 /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
735 /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
736 /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
737 /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
738 /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
739 /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
740 /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
741 /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
742 /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
743 /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
744 /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
745 /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
746 /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
747 /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
748 /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
749 /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
750 /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
751 /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
752 /* 1893 */ 's', 't', 'x', 32, 0,
753 /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
754 /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
755 /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
756 /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
757 /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
758 /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
759 /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
760 /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
761 /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
762 /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
763 /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
764 /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
765 /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
766 /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
767 /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
768 /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
769 /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
770 /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
771 /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
772 /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
773 /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
774 /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
775 /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
776 /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
777 /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
778 /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
779 /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
780 /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
781 /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
782 /* 2160 */ 'b', 'r', 'z', 32, 0,
783 /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
784 /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
785 /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
786 /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
787 /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788 /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789 /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790 /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791 /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792 /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793 /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
794 /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
795 /* 2421 */ 't', 'a', 32, '3', 0,
796 /* 2426 */ 't', 'a', 32, '5', 0,
797 /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
798 /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
799 /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
800 /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
801 /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
802 /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
803 /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
804 /* 2496 */ 'l', 'd', 32, '[', 0,
805 /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
806 /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
807 /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
808 /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
809 /* 2528 */ 'c', 'a', 's', 32, '[', 0,
810 /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
811 /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
812 /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
813 /* 2554 */ 'f', 'b', 0,
814 /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
815 /* 2563 */ 's', 'i', 'a', 'm', 0,
816 /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
817 /* 2577 */ 'n', 'o', 'p', 0,
818 /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
819 /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
820 /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
821 /* 2599 */ 't', 0,
822 /* 2601 */ 'm', 'o', 'v', 0,
823 /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
824 };
825#endif
826
827 // Emit the opcode for the instruction.
828 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
829#ifndef CAPSTONE_DIET
830 // assert(Bits != 0 && "Cannot print this instruction.");
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]831 SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]832#endif
833
834
835 // Fragment 0 encoded into 4 bits for 12 unique commands.
Nguyen Anh Quynh1055a2e2014-03-10 14:37:08 +0800[diff] [blame]836 // printf("Frag-0: %u\n", (Bits >> 12) & 15);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]837 switch ((Bits >> 12) & 15) {
838 default: // unreachable.
839 case 0:
840 // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
841 return;
842 break;
843 case 1:
844 // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
845 printOperand(MI, 1, O);
846 break;
847 case 2:
848 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
849 printOperand(MI, 0, O);
850 break;
851 case 3:
852 // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
853 printCCOperand(MI, 1, O);
854 break;
855 case 4:
856 // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
857 printMemOperand(MI, 0, O, NULL);
858 return;
859 break;
860 case 5:
861 // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
862 printCCOperand(MI, 3, O);
863 break;
864 case 6:
865 // GETPCX
866 printGetPCX(MI, 0, O);
867 return;
868 break;
869 case 7:
870 // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
871 printMemOperand(MI, 1, O, NULL);
872 break;
873 case 8:
874 // LEAX_ADDri, LEA_ADDri
875 printMemOperand(MI, 1, O, "arith");
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]876 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]877 printOperand(MI, 0, O);
878 return;
879 break;
880 case 9:
881 // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
882 printOperand(MI, 2, O);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]883 SStream_concat0(O, ", [");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]884 printMemOperand(MI, 0, O, NULL);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]885 SStream_concat0(O, "]");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]886 return;
887 break;
888 case 10:
889 // TICCri, TICCrr, TXCCri, TXCCrr
890 printCCOperand(MI, 2, O);
891 break;
892 case 11:
893 // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
894 printCCOperand(MI, 4, O);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]895 SStream_concat0(O, " ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]896 printOperand(MI, 1, O);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]897 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]898 printOperand(MI, 2, O);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]899 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]900 printOperand(MI, 0, O);
901 return;
902 break;
903 }
904
905
906 // Fragment 1 encoded into 4 bits for 16 unique commands.
Nguyen Anh Quynh1055a2e2014-03-10 14:37:08 +0800[diff] [blame]907 // printf("Frag-1: %u\n", (Bits >> 16) & 15);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]908 switch ((Bits >> 16) & 15) {
909 default: // unreachable.
910 case 0:
911 // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]912 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]913 break;
914 case 1:
915 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
916 return;
917 break;
918 case 2:
919 // BCOND, BPFCC, FBCOND
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]920 SStream_concat0(O, " ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]921 break;
922 case 3:
923 // BCONDA, BPFCCA, FBCONDA
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]924 SStream_concat0(O, ",a ");
925 Sparc_add_hint(MI, SPARC_HINT_A);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]926 break;
927 case 4:
928 // BPFCCANT
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]929 SStream_concat0(O, ",a,pn ");
930 Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]931 printOperand(MI, 2, O);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]932 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]933 printOperand(MI, 0, O);
934 return;
935 break;
936 case 5:
937 // BPFCCNT
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]938 SStream_concat0(O, ",pn ");
939 Sparc_add_hint(MI, SPARC_HINT_PN);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]940 printOperand(MI, 2, O);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]941 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]942 printOperand(MI, 0, O);
943 return;
944 break;
945 case 6:
946 // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]947 SStream_concat0(O, " %icc, ");
948 Sparc_add_reg(MI, SPARC_REG_ICC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]949 break;
950 case 7:
951 // BPICCA
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]952 SStream_concat0(O, ",a %icc, ");
953 Sparc_add_hint(MI, SPARC_HINT_A);
954 Sparc_add_reg(MI, SPARC_REG_ICC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]955 printOperand(MI, 0, O);
956 return;
957 break;
958 case 8:
959 // BPICCANT
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]960 SStream_concat0(O, ",a,pn %icc, ");
961 Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
962 Sparc_add_reg(MI, SPARC_REG_ICC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]963 printOperand(MI, 0, O);
964 return;
965 break;
966 case 9:
967 // BPICCNT
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]968 SStream_concat0(O, ",pn %icc, ");
969 Sparc_add_hint(MI, SPARC_HINT_PN);
970 Sparc_add_reg(MI, SPARC_REG_ICC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]971 printOperand(MI, 0, O);
972 return;
973 break;
974 case 10:
975 // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]976 SStream_concat0(O, " %xcc, ");
977 Sparc_add_reg(MI, SPARC_REG_XCC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]978 break;
979 case 11:
980 // BPXCCA
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]981 SStream_concat0(O, ",a %xcc, ");
982 Sparc_add_hint(MI, SPARC_HINT_A);
983 Sparc_add_reg(MI, SPARC_REG_XCC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]984 printOperand(MI, 0, O);
985 return;
986 break;
987 case 12:
988 // BPXCCANT
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]989 SStream_concat0(O, ",a,pn %xcc, ");
990 Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
991 Sparc_add_reg(MI, SPARC_REG_XCC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]992 printOperand(MI, 0, O);
993 return;
994 break;
995 case 13:
996 // BPXCCNT
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]997 SStream_concat0(O, ",pn %xcc, ");
998 Sparc_add_hint(MI, SPARC_HINT_PN);
999 Sparc_add_reg(MI, SPARC_REG_XCC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1000 printOperand(MI, 0, O);
1001 return;
1002 break;
1003 case 14:
1004 // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]1005 SStream_concat0(O, "], ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1006 break;
1007 case 15:
1008 // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]1009 SStream_concat0(O, " %fcc0, ");
1010 Sparc_add_reg(MI, SPARC_REG_FCC0);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1011 printOperand(MI, 1, O);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]1012 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1013 printOperand(MI, 0, O);
1014 return;
1015 break;
1016 }
1017
1018
1019 // Fragment 2 encoded into 2 bits for 3 unique commands.
Nguyen Anh Quynh1055a2e2014-03-10 14:37:08 +0800[diff] [blame]1020 // printf("Frag-2: %u\n", (Bits >> 20) & 3);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1021 switch ((Bits >> 20) & 3) {
1022 default: // unreachable.
1023 case 0:
1024 // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1025 printOperand(MI, 2, O);
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]1026 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1027 printOperand(MI, 0, O);
1028 break;
1029 case 1:
1030 // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1031 printOperand(MI, 0, O);
1032 break;
1033 case 2:
1034 // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1035 printOperand(MI, 1, O);
1036 break;
1037 }
1038
1039
1040 // Fragment 3 encoded into 2 bits for 4 unique commands.
Nguyen Anh Quynh1055a2e2014-03-10 14:37:08 +0800[diff] [blame]1041 // printf("Frag-3: %u\n", (Bits >> 22) & 3);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1042 switch ((Bits >> 22) & 3) {
1043 default: // unreachable.
1044 case 0:
1045 // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1046 return;
1047 break;
1048 case 1:
1049 // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]1050 SStream_concat0(O, ", ");
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1051 break;
1052 case 2:
1053 // TICCri, TICCrr, TXCCri, TXCCrr
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]1054 SStream_concat0(O, " + "); // qq
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1055 printOperand(MI, 1, O);
1056 return;
1057 break;
1058 case 3:
1059 // WRYri, WRYrr
Nguyen Anh Quynh1738a3e2014-09-17 00:01:04 +0800[diff] [blame]1060 SStream_concat0(O, ", %y");
1061 Sparc_add_reg(MI, SPARC_REG_Y);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1062 return;
1063 break;
1064 }
1065
1066
1067 // Fragment 4 encoded into 2 bits for 3 unique commands.
Nguyen Anh Quynh1055a2e2014-03-10 14:37:08 +0800[diff] [blame]1068 // printf("Frag-4: %u\n", (Bits >> 24) & 3);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1069 switch ((Bits >> 24) & 3) {
1070 default: // unreachable.
1071 case 0:
1072 // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1073 printOperand(MI, 2, O);
1074 return;
1075 break;
1076 case 1:
1077 // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1078 printOperand(MI, 0, O);
1079 return;
1080 break;
1081 case 2:
1082 // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1083 printOperand(MI, 3, O);
1084 return;
1085 break;
1086 }
1087}
1088
1089
1090/// getRegisterName - This method is automatically generated by tblgen
1091/// from the register set description. This returns the assembler name
1092/// for the specified register.
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]1093static char *getRegisterName(unsigned RegNo)
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1094{
1095 // assert(RegNo && RegNo < 119 && "Invalid register number!");
1096
1097#ifndef CAPSTONE_DIET
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]1098 static char AsmStrs[] = {
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1099 /* 0 */ 'f', '1', '0', 0,
1100 /* 4 */ 'f', '2', '0', 0,
1101 /* 8 */ 'f', '3', '0', 0,
1102 /* 12 */ 'f', '4', '0', 0,
1103 /* 16 */ 'f', '5', '0', 0,
1104 /* 20 */ 'f', '6', '0', 0,
1105 /* 24 */ 'f', 'c', 'c', '0', 0,
1106 /* 29 */ 'f', '0', 0,
1107 /* 32 */ 'g', '0', 0,
1108 /* 35 */ 'i', '0', 0,
1109 /* 38 */ 'l', '0', 0,
1110 /* 41 */ 'o', '0', 0,
1111 /* 44 */ 'f', '1', '1', 0,
1112 /* 48 */ 'f', '2', '1', 0,
1113 /* 52 */ 'f', '3', '1', 0,
1114 /* 56 */ 'f', 'c', 'c', '1', 0,
1115 /* 61 */ 'f', '1', 0,
1116 /* 64 */ 'g', '1', 0,
1117 /* 67 */ 'i', '1', 0,
1118 /* 70 */ 'l', '1', 0,
1119 /* 73 */ 'o', '1', 0,
1120 /* 76 */ 'f', '1', '2', 0,
1121 /* 80 */ 'f', '2', '2', 0,
1122 /* 84 */ 'f', '3', '2', 0,
1123 /* 88 */ 'f', '4', '2', 0,
1124 /* 92 */ 'f', '5', '2', 0,
1125 /* 96 */ 'f', '6', '2', 0,
1126 /* 100 */ 'f', 'c', 'c', '2', 0,
1127 /* 105 */ 'f', '2', 0,
1128 /* 108 */ 'g', '2', 0,
1129 /* 111 */ 'i', '2', 0,
1130 /* 114 */ 'l', '2', 0,
1131 /* 117 */ 'o', '2', 0,
1132 /* 120 */ 'f', '1', '3', 0,
1133 /* 124 */ 'f', '2', '3', 0,
1134 /* 128 */ 'f', 'c', 'c', '3', 0,
1135 /* 133 */ 'f', '3', 0,
1136 /* 136 */ 'g', '3', 0,
1137 /* 139 */ 'i', '3', 0,
1138 /* 142 */ 'l', '3', 0,
1139 /* 145 */ 'o', '3', 0,
1140 /* 148 */ 'f', '1', '4', 0,
1141 /* 152 */ 'f', '2', '4', 0,
1142 /* 156 */ 'f', '3', '4', 0,
1143 /* 160 */ 'f', '4', '4', 0,
1144 /* 164 */ 'f', '5', '4', 0,
1145 /* 168 */ 'f', '4', 0,
1146 /* 171 */ 'g', '4', 0,
1147 /* 174 */ 'i', '4', 0,
1148 /* 177 */ 'l', '4', 0,
1149 /* 180 */ 'o', '4', 0,
1150 /* 183 */ 'f', '1', '5', 0,
1151 /* 187 */ 'f', '2', '5', 0,
1152 /* 191 */ 'f', '5', 0,
1153 /* 194 */ 'g', '5', 0,
1154 /* 197 */ 'i', '5', 0,
1155 /* 200 */ 'l', '5', 0,
1156 /* 203 */ 'o', '5', 0,
1157 /* 206 */ 'f', '1', '6', 0,
1158 /* 210 */ 'f', '2', '6', 0,
1159 /* 214 */ 'f', '3', '6', 0,
1160 /* 218 */ 'f', '4', '6', 0,
1161 /* 222 */ 'f', '5', '6', 0,
1162 /* 226 */ 'f', '6', 0,
1163 /* 229 */ 'g', '6', 0,
1164 /* 232 */ 'l', '6', 0,
1165 /* 235 */ 'f', '1', '7', 0,
1166 /* 239 */ 'f', '2', '7', 0,
1167 /* 243 */ 'f', '7', 0,
1168 /* 246 */ 'g', '7', 0,
1169 /* 249 */ 'i', '7', 0,
1170 /* 252 */ 'l', '7', 0,
1171 /* 255 */ 'o', '7', 0,
1172 /* 258 */ 'f', '1', '8', 0,
1173 /* 262 */ 'f', '2', '8', 0,
1174 /* 266 */ 'f', '3', '8', 0,
1175 /* 270 */ 'f', '4', '8', 0,
1176 /* 274 */ 'f', '5', '8', 0,
1177 /* 278 */ 'f', '8', 0,
1178 /* 281 */ 'f', '1', '9', 0,
1179 /* 285 */ 'f', '2', '9', 0,
1180 /* 289 */ 'f', '9', 0,
1181 /* 292 */ 'i', 'c', 'c', 0,
1182 /* 296 */ 'f', 'p', 0,
1183 /* 299 */ 's', 'p', 0,
1184 /* 302 */ 'y', 0,
1185 };
1186
1187 static const uint32_t RegAsmOffset[] = {
1188 292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80,
1189 152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16,
1190 92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243,
1191 278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48,
1192 80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128,
1193 32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197,
1194 296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145,
1195 180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214,
1196 12, 160, 270, 92, 222, 20,
1197 };
1198
1199 //int i;
1200 //for (i = 0; i < sizeof(RegAsmOffset)/4; i++)
1201 // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1202 //printf("*************************\n");
1203 return AsmStrs+RegAsmOffset[RegNo-1];
1204#else
1205 return NULL;
1206#endif
1207}
1208
1209#ifdef PRINT_ALIAS_INSTR
1210#undef PRINT_ALIAS_INSTR
1211
Nguyen Anh Quynh159ddbd2014-08-15 16:35:12 +0800[diff] [blame]1212static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1213 unsigned PrintMethodIdx, SStream *OS)
1214{
1215}
1216
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1217static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1218{
Nguyen Anh Quynh159ddbd2014-08-15 16:35:12 +0800[diff] [blame]1219 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1220 const char *AsmString;
1221 char *tmp, *AsmMnem, *AsmOps, *c;
Nguyen Anh Quynh159ddbd2014-08-15 16:35:12 +0800[diff] [blame]1222 int OpIdx, PrintMethodIdx;
1223 MCRegisterInfo *MRI = (MCRegisterInfo *)info;
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]1224 switch (MCInst_getOpcode(MI)) {
1225 default: return NULL;
Nguyen Anh Quynh159ddbd2014-08-15 16:35:12 +0800[diff] [blame]1226 case SP_BCOND:
1227 if (MCInst_getNumOperands(MI) == 2 &&
1228 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1229 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1230 // (BCOND brtarget:$imm, 8)
1231 AsmString = "ba $\x01";
1232 break;
1233 }
1234 if (MCInst_getNumOperands(MI) == 2 &&
1235 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1236 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1237 // (BCOND brtarget:$imm, 0)
1238 AsmString = "bn $\x01";
1239 break;
1240 }
1241 if (MCInst_getNumOperands(MI) == 2 &&
1242 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1243 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1244 // (BCOND brtarget:$imm, 9)
1245 AsmString = "bne $\x01";
1246 break;
1247 }
1248 if (MCInst_getNumOperands(MI) == 2 &&
1249 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1250 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1251 // (BCOND brtarget:$imm, 1)
1252 AsmString = "be $\x01";
1253 break;
1254 }
1255 if (MCInst_getNumOperands(MI) == 2 &&
1256 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1257 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1258 // (BCOND brtarget:$imm, 10)
1259 AsmString = "bg $\x01";
1260 break;
1261 }
1262 if (MCInst_getNumOperands(MI) == 2 &&
1263 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1264 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1265 // (BCOND brtarget:$imm, 2)
1266 AsmString = "ble $\x01";
1267 break;
1268 }
1269 if (MCInst_getNumOperands(MI) == 2 &&
1270 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1271 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1272 // (BCOND brtarget:$imm, 11)
1273 AsmString = "bge $\x01";
1274 break;
1275 }
1276 if (MCInst_getNumOperands(MI) == 2 &&
1277 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1278 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1279 // (BCOND brtarget:$imm, 3)
1280 AsmString = "bl $\x01";
1281 break;
1282 }
1283 if (MCInst_getNumOperands(MI) == 2 &&
1284 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1285 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1286 // (BCOND brtarget:$imm, 12)
1287 AsmString = "bgu $\x01";
1288 break;
1289 }
1290 if (MCInst_getNumOperands(MI) == 2 &&
1291 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1292 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1293 // (BCOND brtarget:$imm, 4)
1294 AsmString = "bleu $\x01";
1295 break;
1296 }
1297 if (MCInst_getNumOperands(MI) == 2 &&
1298 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1299 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1300 // (BCOND brtarget:$imm, 13)
1301 AsmString = "bcc $\x01";
1302 break;
1303 }
1304 if (MCInst_getNumOperands(MI) == 2 &&
1305 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1306 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1307 // (BCOND brtarget:$imm, 5)
1308 AsmString = "bcs $\x01";
1309 break;
1310 }
1311 if (MCInst_getNumOperands(MI) == 2 &&
1312 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1313 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1314 // (BCOND brtarget:$imm, 14)
1315 AsmString = "bpos $\x01";
1316 break;
1317 }
1318 if (MCInst_getNumOperands(MI) == 2 &&
1319 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1320 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1321 // (BCOND brtarget:$imm, 6)
1322 AsmString = "bneg $\x01";
1323 break;
1324 }
1325 if (MCInst_getNumOperands(MI) == 2 &&
1326 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1327 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1328 // (BCOND brtarget:$imm, 15)
1329 AsmString = "bvc $\x01";
1330 break;
1331 }
1332 if (MCInst_getNumOperands(MI) == 2 &&
1333 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1334 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1335 // (BCOND brtarget:$imm, 7)
1336 AsmString = "bvs $\x01";
1337 break;
1338 }
1339 return NULL;
1340 case SP_BCONDA:
1341 if (MCInst_getNumOperands(MI) == 2 &&
1342 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1343 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1344 // (BCONDA brtarget:$imm, 8)
1345 AsmString = "ba,a $\x01";
1346 break;
1347 }
1348 if (MCInst_getNumOperands(MI) == 2 &&
1349 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1350 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1351 // (BCONDA brtarget:$imm, 0)
1352 AsmString = "bn,a $\x01";
1353 break;
1354 }
1355 if (MCInst_getNumOperands(MI) == 2 &&
1356 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1357 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1358 // (BCONDA brtarget:$imm, 9)
1359 AsmString = "bne,a $\x01";
1360 break;
1361 }
1362 if (MCInst_getNumOperands(MI) == 2 &&
1363 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1364 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1365 // (BCONDA brtarget:$imm, 1)
1366 AsmString = "be,a $\x01";
1367 break;
1368 }
1369 if (MCInst_getNumOperands(MI) == 2 &&
1370 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1371 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1372 // (BCONDA brtarget:$imm, 10)
1373 AsmString = "bg,a $\x01";
1374 break;
1375 }
1376 if (MCInst_getNumOperands(MI) == 2 &&
1377 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1378 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1379 // (BCONDA brtarget:$imm, 2)
1380 AsmString = "ble,a $\x01";
1381 break;
1382 }
1383 if (MCInst_getNumOperands(MI) == 2 &&
1384 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1385 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1386 // (BCONDA brtarget:$imm, 11)
1387 AsmString = "bge,a $\x01";
1388 break;
1389 }
1390 if (MCInst_getNumOperands(MI) == 2 &&
1391 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1392 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1393 // (BCONDA brtarget:$imm, 3)
1394 AsmString = "bl,a $\x01";
1395 break;
1396 }
1397 if (MCInst_getNumOperands(MI) == 2 &&
1398 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1399 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1400 // (BCONDA brtarget:$imm, 12)
1401 AsmString = "bgu,a $\x01";
1402 break;
1403 }
1404 if (MCInst_getNumOperands(MI) == 2 &&
1405 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1406 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1407 // (BCONDA brtarget:$imm, 4)
1408 AsmString = "bleu,a $\x01";
1409 break;
1410 }
1411 if (MCInst_getNumOperands(MI) == 2 &&
1412 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1413 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1414 // (BCONDA brtarget:$imm, 13)
1415 AsmString = "bcc,a $\x01";
1416 break;
1417 }
1418 if (MCInst_getNumOperands(MI) == 2 &&
1419 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1420 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1421 // (BCONDA brtarget:$imm, 5)
1422 AsmString = "bcs,a $\x01";
1423 break;
1424 }
1425 if (MCInst_getNumOperands(MI) == 2 &&
1426 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1427 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1428 // (BCONDA brtarget:$imm, 14)
1429 AsmString = "bpos,a $\x01";
1430 break;
1431 }
1432 if (MCInst_getNumOperands(MI) == 2 &&
1433 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1434 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1435 // (BCONDA brtarget:$imm, 6)
1436 AsmString = "bneg,a $\x01";
1437 break;
1438 }
1439 if (MCInst_getNumOperands(MI) == 2 &&
1440 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1441 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1442 // (BCONDA brtarget:$imm, 15)
1443 AsmString = "bvc,a $\x01";
1444 break;
1445 }
1446 if (MCInst_getNumOperands(MI) == 2 &&
1447 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1448 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1449 // (BCONDA brtarget:$imm, 7)
1450 AsmString = "bvs,a $\x01";
1451 break;
1452 }
1453 return NULL;
1454 case SP_BPFCCANT:
1455 if (MCInst_getNumOperands(MI) == 3 &&
1456 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1457 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1458 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1459 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1460 // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1461 AsmString = "fba,a,pn $\x03, $\x01";
1462 break;
1463 }
1464 if (MCInst_getNumOperands(MI) == 3 &&
1465 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1466 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1467 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1468 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1469 // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1470 AsmString = "fbn,a,pn $\x03, $\x01";
1471 break;
1472 }
1473 if (MCInst_getNumOperands(MI) == 3 &&
1474 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1475 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1476 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1477 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1478 // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1479 AsmString = "fbu,a,pn $\x03, $\x01";
1480 break;
1481 }
1482 if (MCInst_getNumOperands(MI) == 3 &&
1483 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1484 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1485 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1486 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1487 // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1488 AsmString = "fbg,a,pn $\x03, $\x01";
1489 break;
1490 }
1491 if (MCInst_getNumOperands(MI) == 3 &&
1492 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1493 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1494 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1495 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1496 // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1497 AsmString = "fbug,a,pn $\x03, $\x01";
1498 break;
1499 }
1500 if (MCInst_getNumOperands(MI) == 3 &&
1501 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1502 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1503 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1504 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1505 // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1506 AsmString = "fbl,a,pn $\x03, $\x01";
1507 break;
1508 }
1509 if (MCInst_getNumOperands(MI) == 3 &&
1510 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1511 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1512 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1513 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1514 // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1515 AsmString = "fbul,a,pn $\x03, $\x01";
1516 break;
1517 }
1518 if (MCInst_getNumOperands(MI) == 3 &&
1519 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1520 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1521 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1522 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1523 // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1524 AsmString = "fblg,a,pn $\x03, $\x01";
1525 break;
1526 }
1527 if (MCInst_getNumOperands(MI) == 3 &&
1528 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1529 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1530 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1531 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1532 // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1533 AsmString = "fbne,a,pn $\x03, $\x01";
1534 break;
1535 }
1536 if (MCInst_getNumOperands(MI) == 3 &&
1537 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1538 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1539 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1540 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1541 // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1542 AsmString = "fbe,a,pn $\x03, $\x01";
1543 break;
1544 }
1545 if (MCInst_getNumOperands(MI) == 3 &&
1546 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1547 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1548 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1549 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1550 // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1551 AsmString = "fbue,a,pn $\x03, $\x01";
1552 break;
1553 }
1554 if (MCInst_getNumOperands(MI) == 3 &&
1555 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1556 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1557 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1558 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1559 // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1560 AsmString = "fbge,a,pn $\x03, $\x01";
1561 break;
1562 }
1563 if (MCInst_getNumOperands(MI) == 3 &&
1564 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1565 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1566 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1567 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1568 // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1569 AsmString = "fbuge,a,pn $\x03, $\x01";
1570 break;
1571 }
1572 if (MCInst_getNumOperands(MI) == 3 &&
1573 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1574 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1575 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1576 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1577 // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1578 AsmString = "fble,a,pn $\x03, $\x01";
1579 break;
1580 }
1581 if (MCInst_getNumOperands(MI) == 3 &&
1582 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1583 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1584 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1585 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1586 // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1587 AsmString = "fbule,a,pn $\x03, $\x01";
1588 break;
1589 }
1590 if (MCInst_getNumOperands(MI) == 3 &&
1591 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1592 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1593 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1594 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1595 // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1596 AsmString = "fbo,a,pn $\x03, $\x01";
1597 break;
1598 }
1599 return NULL;
1600 case SP_BPFCCNT:
1601 if (MCInst_getNumOperands(MI) == 3 &&
1602 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1603 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1604 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1605 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1606 // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1607 AsmString = "fba,pn $\x03, $\x01";
1608 break;
1609 }
1610 if (MCInst_getNumOperands(MI) == 3 &&
1611 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1612 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1613 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1614 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1615 // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1616 AsmString = "fbn,pn $\x03, $\x01";
1617 break;
1618 }
1619 if (MCInst_getNumOperands(MI) == 3 &&
1620 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1621 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1622 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1623 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1624 // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1625 AsmString = "fbu,pn $\x03, $\x01";
1626 break;
1627 }
1628 if (MCInst_getNumOperands(MI) == 3 &&
1629 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1630 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1631 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1632 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1633 // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1634 AsmString = "fbg,pn $\x03, $\x01";
1635 break;
1636 }
1637 if (MCInst_getNumOperands(MI) == 3 &&
1638 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1639 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1640 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1641 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1642 // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1643 AsmString = "fbug,pn $\x03, $\x01";
1644 break;
1645 }
1646 if (MCInst_getNumOperands(MI) == 3 &&
1647 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1648 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1649 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1650 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1651 // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1652 AsmString = "fbl,pn $\x03, $\x01";
1653 break;
1654 }
1655 if (MCInst_getNumOperands(MI) == 3 &&
1656 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1657 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1658 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1659 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1660 // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1661 AsmString = "fbul,pn $\x03, $\x01";
1662 break;
1663 }
1664 if (MCInst_getNumOperands(MI) == 3 &&
1665 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1666 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1667 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1668 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1669 // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1670 AsmString = "fblg,pn $\x03, $\x01";
1671 break;
1672 }
1673 if (MCInst_getNumOperands(MI) == 3 &&
1674 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1675 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1676 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1677 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1678 // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1679 AsmString = "fbne,pn $\x03, $\x01";
1680 break;
1681 }
1682 if (MCInst_getNumOperands(MI) == 3 &&
1683 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1684 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1685 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1686 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1687 // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1688 AsmString = "fbe,pn $\x03, $\x01";
1689 break;
1690 }
1691 if (MCInst_getNumOperands(MI) == 3 &&
1692 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1693 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1694 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1695 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1696 // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1697 AsmString = "fbue,pn $\x03, $\x01";
1698 break;
1699 }
1700 if (MCInst_getNumOperands(MI) == 3 &&
1701 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1702 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1703 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1704 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1705 // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1706 AsmString = "fbge,pn $\x03, $\x01";
1707 break;
1708 }
1709 if (MCInst_getNumOperands(MI) == 3 &&
1710 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1711 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1712 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1713 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1714 // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1715 AsmString = "fbuge,pn $\x03, $\x01";
1716 break;
1717 }
1718 if (MCInst_getNumOperands(MI) == 3 &&
1719 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1720 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1721 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1722 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1723 // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1724 AsmString = "fble,pn $\x03, $\x01";
1725 break;
1726 }
1727 if (MCInst_getNumOperands(MI) == 3 &&
1728 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1729 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1730 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1731 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1732 // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1733 AsmString = "fbule,pn $\x03, $\x01";
1734 break;
1735 }
1736 if (MCInst_getNumOperands(MI) == 3 &&
1737 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1738 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1739 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1740 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1741 // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1742 AsmString = "fbo,pn $\x03, $\x01";
1743 break;
1744 }
1745 return NULL;
1746 case SP_BPICCANT:
1747 if (MCInst_getNumOperands(MI) == 2 &&
1748 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1749 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1750 // (BPICCANT brtarget:$imm, 8)
1751 AsmString = "ba,a,pn %icc, $\x01";
1752 break;
1753 }
1754 if (MCInst_getNumOperands(MI) == 2 &&
1755 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1756 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1757 // (BPICCANT brtarget:$imm, 0)
1758 AsmString = "bn,a,pn %icc, $\x01";
1759 break;
1760 }
1761 if (MCInst_getNumOperands(MI) == 2 &&
1762 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1763 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1764 // (BPICCANT brtarget:$imm, 9)
1765 AsmString = "bne,a,pn %icc, $\x01";
1766 break;
1767 }
1768 if (MCInst_getNumOperands(MI) == 2 &&
1769 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1770 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1771 // (BPICCANT brtarget:$imm, 1)
1772 AsmString = "be,a,pn %icc, $\x01";
1773 break;
1774 }
1775 if (MCInst_getNumOperands(MI) == 2 &&
1776 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1777 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1778 // (BPICCANT brtarget:$imm, 10)
1779 AsmString = "bg,a,pn %icc, $\x01";
1780 break;
1781 }
1782 if (MCInst_getNumOperands(MI) == 2 &&
1783 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1784 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1785 // (BPICCANT brtarget:$imm, 2)
1786 AsmString = "ble,a,pn %icc, $\x01";
1787 break;
1788 }
1789 if (MCInst_getNumOperands(MI) == 2 &&
1790 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1791 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1792 // (BPICCANT brtarget:$imm, 11)
1793 AsmString = "bge,a,pn %icc, $\x01";
1794 break;
1795 }
1796 if (MCInst_getNumOperands(MI) == 2 &&
1797 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1798 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1799 // (BPICCANT brtarget:$imm, 3)
1800 AsmString = "bl,a,pn %icc, $\x01";
1801 break;
1802 }
1803 if (MCInst_getNumOperands(MI) == 2 &&
1804 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1805 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1806 // (BPICCANT brtarget:$imm, 12)
1807 AsmString = "bgu,a,pn %icc, $\x01";
1808 break;
1809 }
1810 if (MCInst_getNumOperands(MI) == 2 &&
1811 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1812 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1813 // (BPICCANT brtarget:$imm, 4)
1814 AsmString = "bleu,a,pn %icc, $\x01";
1815 break;
1816 }
1817 if (MCInst_getNumOperands(MI) == 2 &&
1818 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1819 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1820 // (BPICCANT brtarget:$imm, 13)
1821 AsmString = "bcc,a,pn %icc, $\x01";
1822 break;
1823 }
1824 if (MCInst_getNumOperands(MI) == 2 &&
1825 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1826 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1827 // (BPICCANT brtarget:$imm, 5)
1828 AsmString = "bcs,a,pn %icc, $\x01";
1829 break;
1830 }
1831 if (MCInst_getNumOperands(MI) == 2 &&
1832 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1833 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1834 // (BPICCANT brtarget:$imm, 14)
1835 AsmString = "bpos,a,pn %icc, $\x01";
1836 break;
1837 }
1838 if (MCInst_getNumOperands(MI) == 2 &&
1839 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1840 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1841 // (BPICCANT brtarget:$imm, 6)
1842 AsmString = "bneg,a,pn %icc, $\x01";
1843 break;
1844 }
1845 if (MCInst_getNumOperands(MI) == 2 &&
1846 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1847 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1848 // (BPICCANT brtarget:$imm, 15)
1849 AsmString = "bvc,a,pn %icc, $\x01";
1850 break;
1851 }
1852 if (MCInst_getNumOperands(MI) == 2 &&
1853 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1854 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1855 // (BPICCANT brtarget:$imm, 7)
1856 AsmString = "bvs,a,pn %icc, $\x01";
1857 break;
1858 }
1859 return NULL;
1860 case SP_BPICCNT:
1861 if (MCInst_getNumOperands(MI) == 2 &&
1862 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1863 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1864 // (BPICCNT brtarget:$imm, 8)
1865 AsmString = "ba,pn %icc, $\x01";
1866 break;
1867 }
1868 if (MCInst_getNumOperands(MI) == 2 &&
1869 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1870 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1871 // (BPICCNT brtarget:$imm, 0)
1872 AsmString = "bn,pn %icc, $\x01";
1873 break;
1874 }
1875 if (MCInst_getNumOperands(MI) == 2 &&
1876 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1877 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1878 // (BPICCNT brtarget:$imm, 9)
1879 AsmString = "bne,pn %icc, $\x01";
1880 break;
1881 }
1882 if (MCInst_getNumOperands(MI) == 2 &&
1883 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1884 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1885 // (BPICCNT brtarget:$imm, 1)
1886 AsmString = "be,pn %icc, $\x01";
1887 break;
1888 }
1889 if (MCInst_getNumOperands(MI) == 2 &&
1890 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1891 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1892 // (BPICCNT brtarget:$imm, 10)
1893 AsmString = "bg,pn %icc, $\x01";
1894 break;
1895 }
1896 if (MCInst_getNumOperands(MI) == 2 &&
1897 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1898 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1899 // (BPICCNT brtarget:$imm, 2)
1900 AsmString = "ble,pn %icc, $\x01";
1901 break;
1902 }
1903 if (MCInst_getNumOperands(MI) == 2 &&
1904 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1905 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1906 // (BPICCNT brtarget:$imm, 11)
1907 AsmString = "bge,pn %icc, $\x01";
1908 break;
1909 }
1910 if (MCInst_getNumOperands(MI) == 2 &&
1911 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1912 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1913 // (BPICCNT brtarget:$imm, 3)
1914 AsmString = "bl,pn %icc, $\x01";
1915 break;
1916 }
1917 if (MCInst_getNumOperands(MI) == 2 &&
1918 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1919 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1920 // (BPICCNT brtarget:$imm, 12)
1921 AsmString = "bgu,pn %icc, $\x01";
1922 break;
1923 }
1924 if (MCInst_getNumOperands(MI) == 2 &&
1925 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1926 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1927 // (BPICCNT brtarget:$imm, 4)
1928 AsmString = "bleu,pn %icc, $\x01";
1929 break;
1930 }
1931 if (MCInst_getNumOperands(MI) == 2 &&
1932 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1933 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1934 // (BPICCNT brtarget:$imm, 13)
1935 AsmString = "bcc,pn %icc, $\x01";
1936 break;
1937 }
1938 if (MCInst_getNumOperands(MI) == 2 &&
1939 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1940 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1941 // (BPICCNT brtarget:$imm, 5)
1942 AsmString = "bcs,pn %icc, $\x01";
1943 break;
1944 }
1945 if (MCInst_getNumOperands(MI) == 2 &&
1946 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1947 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1948 // (BPICCNT brtarget:$imm, 14)
1949 AsmString = "bpos,pn %icc, $\x01";
1950 break;
1951 }
1952 if (MCInst_getNumOperands(MI) == 2 &&
1953 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1954 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1955 // (BPICCNT brtarget:$imm, 6)
1956 AsmString = "bneg,pn %icc, $\x01";
1957 break;
1958 }
1959 if (MCInst_getNumOperands(MI) == 2 &&
1960 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1961 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1962 // (BPICCNT brtarget:$imm, 15)
1963 AsmString = "bvc,pn %icc, $\x01";
1964 break;
1965 }
1966 if (MCInst_getNumOperands(MI) == 2 &&
1967 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1968 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1969 // (BPICCNT brtarget:$imm, 7)
1970 AsmString = "bvs,pn %icc, $\x01";
1971 break;
1972 }
1973 return NULL;
1974 case SP_BPXCCANT:
1975 if (MCInst_getNumOperands(MI) == 2 &&
1976 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1977 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1978 // (BPXCCANT brtarget:$imm, 8)
1979 AsmString = "ba,a,pn %xcc, $\x01";
1980 break;
1981 }
1982 if (MCInst_getNumOperands(MI) == 2 &&
1983 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1984 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1985 // (BPXCCANT brtarget:$imm, 0)
1986 AsmString = "bn,a,pn %xcc, $\x01";
1987 break;
1988 }
1989 if (MCInst_getNumOperands(MI) == 2 &&
1990 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1991 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1992 // (BPXCCANT brtarget:$imm, 9)
1993 AsmString = "bne,a,pn %xcc, $\x01";
1994 break;
1995 }
1996 if (MCInst_getNumOperands(MI) == 2 &&
1997 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1998 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1999 // (BPXCCANT brtarget:$imm, 1)
2000 AsmString = "be,a,pn %xcc, $\x01";
2001 break;
2002 }
2003 if (MCInst_getNumOperands(MI) == 2 &&
2004 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2005 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2006 // (BPXCCANT brtarget:$imm, 10)
2007 AsmString = "bg,a,pn %xcc, $\x01";
2008 break;
2009 }
2010 if (MCInst_getNumOperands(MI) == 2 &&
2011 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2012 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2013 // (BPXCCANT brtarget:$imm, 2)
2014 AsmString = "ble,a,pn %xcc, $\x01";
2015 break;
2016 }
2017 if (MCInst_getNumOperands(MI) == 2 &&
2018 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2019 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2020 // (BPXCCANT brtarget:$imm, 11)
2021 AsmString = "bge,a,pn %xcc, $\x01";
2022 break;
2023 }
2024 if (MCInst_getNumOperands(MI) == 2 &&
2025 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2026 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2027 // (BPXCCANT brtarget:$imm, 3)
2028 AsmString = "bl,a,pn %xcc, $\x01";
2029 break;
2030 }
2031 if (MCInst_getNumOperands(MI) == 2 &&
2032 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2033 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2034 // (BPXCCANT brtarget:$imm, 12)
2035 AsmString = "bgu,a,pn %xcc, $\x01";
2036 break;
2037 }
2038 if (MCInst_getNumOperands(MI) == 2 &&
2039 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2040 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2041 // (BPXCCANT brtarget:$imm, 4)
2042 AsmString = "bleu,a,pn %xcc, $\x01";
2043 break;
2044 }
2045 if (MCInst_getNumOperands(MI) == 2 &&
2046 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2047 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2048 // (BPXCCANT brtarget:$imm, 13)
2049 AsmString = "bcc,a,pn %xcc, $\x01";
2050 break;
2051 }
2052 if (MCInst_getNumOperands(MI) == 2 &&
2053 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2054 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2055 // (BPXCCANT brtarget:$imm, 5)
2056 AsmString = "bcs,a,pn %xcc, $\x01";
2057 break;
2058 }
2059 if (MCInst_getNumOperands(MI) == 2 &&
2060 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2061 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2062 // (BPXCCANT brtarget:$imm, 14)
2063 AsmString = "bpos,a,pn %xcc, $\x01";
2064 break;
2065 }
2066 if (MCInst_getNumOperands(MI) == 2 &&
2067 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2068 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2069 // (BPXCCANT brtarget:$imm, 6)
2070 AsmString = "bneg,a,pn %xcc, $\x01";
2071 break;
2072 }
2073 if (MCInst_getNumOperands(MI) == 2 &&
2074 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2075 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2076 // (BPXCCANT brtarget:$imm, 15)
2077 AsmString = "bvc,a,pn %xcc, $\x01";
2078 break;
2079 }
2080 if (MCInst_getNumOperands(MI) == 2 &&
2081 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2082 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2083 // (BPXCCANT brtarget:$imm, 7)
2084 AsmString = "bvs,a,pn %xcc, $\x01";
2085 break;
2086 }
2087 return NULL;
2088 case SP_BPXCCNT:
2089 if (MCInst_getNumOperands(MI) == 2 &&
2090 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2091 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2092 // (BPXCCNT brtarget:$imm, 8)
2093 AsmString = "ba,pn %xcc, $\x01";
2094 break;
2095 }
2096 if (MCInst_getNumOperands(MI) == 2 &&
2097 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2098 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2099 // (BPXCCNT brtarget:$imm, 0)
2100 AsmString = "bn,pn %xcc, $\x01";
2101 break;
2102 }
2103 if (MCInst_getNumOperands(MI) == 2 &&
2104 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2105 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2106 // (BPXCCNT brtarget:$imm, 9)
2107 AsmString = "bne,pn %xcc, $\x01";
2108 break;
2109 }
2110 if (MCInst_getNumOperands(MI) == 2 &&
2111 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2112 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2113 // (BPXCCNT brtarget:$imm, 1)
2114 AsmString = "be,pn %xcc, $\x01";
2115 break;
2116 }
2117 if (MCInst_getNumOperands(MI) == 2 &&
2118 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2119 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2120 // (BPXCCNT brtarget:$imm, 10)
2121 AsmString = "bg,pn %xcc, $\x01";
2122 break;
2123 }
2124 if (MCInst_getNumOperands(MI) == 2 &&
2125 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2126 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2127 // (BPXCCNT brtarget:$imm, 2)
2128 AsmString = "ble,pn %xcc, $\x01";
2129 break;
2130 }
2131 if (MCInst_getNumOperands(MI) == 2 &&
2132 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2133 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2134 // (BPXCCNT brtarget:$imm, 11)
2135 AsmString = "bge,pn %xcc, $\x01";
2136 break;
2137 }
2138 if (MCInst_getNumOperands(MI) == 2 &&
2139 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2140 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2141 // (BPXCCNT brtarget:$imm, 3)
2142 AsmString = "bl,pn %xcc, $\x01";
2143 break;
2144 }
2145 if (MCInst_getNumOperands(MI) == 2 &&
2146 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2147 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2148 // (BPXCCNT brtarget:$imm, 12)
2149 AsmString = "bgu,pn %xcc, $\x01";
2150 break;
2151 }
2152 if (MCInst_getNumOperands(MI) == 2 &&
2153 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2154 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2155 // (BPXCCNT brtarget:$imm, 4)
2156 AsmString = "bleu,pn %xcc, $\x01";
2157 break;
2158 }
2159 if (MCInst_getNumOperands(MI) == 2 &&
2160 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2161 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2162 // (BPXCCNT brtarget:$imm, 13)
2163 AsmString = "bcc,pn %xcc, $\x01";
2164 break;
2165 }
2166 if (MCInst_getNumOperands(MI) == 2 &&
2167 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2168 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2169 // (BPXCCNT brtarget:$imm, 5)
2170 AsmString = "bcs,pn %xcc, $\x01";
2171 break;
2172 }
2173 if (MCInst_getNumOperands(MI) == 2 &&
2174 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2175 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2176 // (BPXCCNT brtarget:$imm, 14)
2177 AsmString = "bpos,pn %xcc, $\x01";
2178 break;
2179 }
2180 if (MCInst_getNumOperands(MI) == 2 &&
2181 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2182 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2183 // (BPXCCNT brtarget:$imm, 6)
2184 AsmString = "bneg,pn %xcc, $\x01";
2185 break;
2186 }
2187 if (MCInst_getNumOperands(MI) == 2 &&
2188 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2189 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2190 // (BPXCCNT brtarget:$imm, 15)
2191 AsmString = "bvc,pn %xcc, $\x01";
2192 break;
2193 }
2194 if (MCInst_getNumOperands(MI) == 2 &&
2195 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2196 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2197 // (BPXCCNT brtarget:$imm, 7)
2198 AsmString = "bvs,pn %xcc, $\x01";
2199 break;
2200 }
2201 return NULL;
2202 case SP_FMOVD_ICC:
2203 if (MCInst_getNumOperands(MI) == 3 &&
2204 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2205 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2206 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2207 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2208 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2209 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2210 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2211 AsmString = "fmovda %icc, $\x02, $\x01";
2212 break;
2213 }
2214 if (MCInst_getNumOperands(MI) == 3 &&
2215 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2216 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2217 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2218 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2219 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2220 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2221 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2222 AsmString = "fmovdn %icc, $\x02, $\x01";
2223 break;
2224 }
2225 if (MCInst_getNumOperands(MI) == 3 &&
2226 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2227 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2228 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2229 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2230 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2231 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2232 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2233 AsmString = "fmovdne %icc, $\x02, $\x01";
2234 break;
2235 }
2236 if (MCInst_getNumOperands(MI) == 3 &&
2237 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2238 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2239 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2240 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2241 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2242 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2243 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2244 AsmString = "fmovde %icc, $\x02, $\x01";
2245 break;
2246 }
2247 if (MCInst_getNumOperands(MI) == 3 &&
2248 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2249 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2250 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2251 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2252 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2253 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2254 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2255 AsmString = "fmovdg %icc, $\x02, $\x01";
2256 break;
2257 }
2258 if (MCInst_getNumOperands(MI) == 3 &&
2259 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2260 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2261 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2262 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2263 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2264 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2265 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2266 AsmString = "fmovdle %icc, $\x02, $\x01";
2267 break;
2268 }
2269 if (MCInst_getNumOperands(MI) == 3 &&
2270 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2271 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2272 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2273 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2274 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2275 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2276 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2277 AsmString = "fmovdge %icc, $\x02, $\x01";
2278 break;
2279 }
2280 if (MCInst_getNumOperands(MI) == 3 &&
2281 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2282 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2283 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2284 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2285 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2286 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2287 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2288 AsmString = "fmovdl %icc, $\x02, $\x01";
2289 break;
2290 }
2291 if (MCInst_getNumOperands(MI) == 3 &&
2292 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2293 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2294 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2295 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2296 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2297 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2298 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2299 AsmString = "fmovdgu %icc, $\x02, $\x01";
2300 break;
2301 }
2302 if (MCInst_getNumOperands(MI) == 3 &&
2303 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2304 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2305 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2306 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2307 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2308 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2309 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2310 AsmString = "fmovdleu %icc, $\x02, $\x01";
2311 break;
2312 }
2313 if (MCInst_getNumOperands(MI) == 3 &&
2314 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2315 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2316 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2317 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2318 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2319 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2320 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2321 AsmString = "fmovdcc %icc, $\x02, $\x01";
2322 break;
2323 }
2324 if (MCInst_getNumOperands(MI) == 3 &&
2325 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2326 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2327 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2328 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2329 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2330 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2331 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2332 AsmString = "fmovdcs %icc, $\x02, $\x01";
2333 break;
2334 }
2335 if (MCInst_getNumOperands(MI) == 3 &&
2336 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2337 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2338 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2339 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2340 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2341 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2342 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2343 AsmString = "fmovdpos %icc, $\x02, $\x01";
2344 break;
2345 }
2346 if (MCInst_getNumOperands(MI) == 3 &&
2347 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2348 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2349 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2350 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2351 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2352 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2353 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2354 AsmString = "fmovdneg %icc, $\x02, $\x01";
2355 break;
2356 }
2357 if (MCInst_getNumOperands(MI) == 3 &&
2358 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2359 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2360 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2361 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2362 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2363 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2364 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2365 AsmString = "fmovdvc %icc, $\x02, $\x01";
2366 break;
2367 }
2368 if (MCInst_getNumOperands(MI) == 3 &&
2369 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2370 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2371 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2372 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2373 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2374 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2375 // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2376 AsmString = "fmovdvs %icc, $\x02, $\x01";
2377 break;
2378 }
2379 return NULL;
2380 case SP_FMOVD_XCC:
2381 if (MCInst_getNumOperands(MI) == 3 &&
2382 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2383 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2384 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2385 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2386 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2387 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2388 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2389 AsmString = "fmovda %xcc, $\x02, $\x01";
2390 break;
2391 }
2392 if (MCInst_getNumOperands(MI) == 3 &&
2393 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2394 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2395 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2396 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2397 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2398 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2399 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2400 AsmString = "fmovdn %xcc, $\x02, $\x01";
2401 break;
2402 }
2403 if (MCInst_getNumOperands(MI) == 3 &&
2404 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2405 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2406 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2407 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2408 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2409 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2410 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2411 AsmString = "fmovdne %xcc, $\x02, $\x01";
2412 break;
2413 }
2414 if (MCInst_getNumOperands(MI) == 3 &&
2415 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2416 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2417 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2418 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2419 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2420 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2421 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2422 AsmString = "fmovde %xcc, $\x02, $\x01";
2423 break;
2424 }
2425 if (MCInst_getNumOperands(MI) == 3 &&
2426 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2427 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2428 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2429 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2430 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2431 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2432 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2433 AsmString = "fmovdg %xcc, $\x02, $\x01";
2434 break;
2435 }
2436 if (MCInst_getNumOperands(MI) == 3 &&
2437 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2438 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2439 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2440 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2441 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2442 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2443 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2444 AsmString = "fmovdle %xcc, $\x02, $\x01";
2445 break;
2446 }
2447 if (MCInst_getNumOperands(MI) == 3 &&
2448 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2449 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2450 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2451 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2452 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2453 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2454 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2455 AsmString = "fmovdge %xcc, $\x02, $\x01";
2456 break;
2457 }
2458 if (MCInst_getNumOperands(MI) == 3 &&
2459 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2460 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2461 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2462 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2463 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2464 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2465 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2466 AsmString = "fmovdl %xcc, $\x02, $\x01";
2467 break;
2468 }
2469 if (MCInst_getNumOperands(MI) == 3 &&
2470 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2471 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2472 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2473 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2474 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2475 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2476 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2477 AsmString = "fmovdgu %xcc, $\x02, $\x01";
2478 break;
2479 }
2480 if (MCInst_getNumOperands(MI) == 3 &&
2481 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2482 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2483 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2484 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2485 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2486 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2487 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2488 AsmString = "fmovdleu %xcc, $\x02, $\x01";
2489 break;
2490 }
2491 if (MCInst_getNumOperands(MI) == 3 &&
2492 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2493 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2494 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2495 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2496 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2497 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2498 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2499 AsmString = "fmovdcc %xcc, $\x02, $\x01";
2500 break;
2501 }
2502 if (MCInst_getNumOperands(MI) == 3 &&
2503 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2504 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2505 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2506 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2507 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2508 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2509 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2510 AsmString = "fmovdcs %xcc, $\x02, $\x01";
2511 break;
2512 }
2513 if (MCInst_getNumOperands(MI) == 3 &&
2514 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2515 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2516 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2517 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2518 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2519 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2520 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2521 AsmString = "fmovdpos %xcc, $\x02, $\x01";
2522 break;
2523 }
2524 if (MCInst_getNumOperands(MI) == 3 &&
2525 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2526 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2527 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2528 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2529 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2530 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2531 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2532 AsmString = "fmovdneg %xcc, $\x02, $\x01";
2533 break;
2534 }
2535 if (MCInst_getNumOperands(MI) == 3 &&
2536 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2537 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2538 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2539 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2540 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2541 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2542 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2543 AsmString = "fmovdvc %xcc, $\x02, $\x01";
2544 break;
2545 }
2546 if (MCInst_getNumOperands(MI) == 3 &&
2547 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2548 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2549 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2550 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2551 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2552 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2553 // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2554 AsmString = "fmovdvs %xcc, $\x02, $\x01";
2555 break;
2556 }
2557 return NULL;
2558 case SP_FMOVQ_ICC:
2559 if (MCInst_getNumOperands(MI) == 3 &&
2560 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2561 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2562 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2563 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2564 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2565 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2566 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2567 AsmString = "fmovqa %icc, $\x02, $\x01";
2568 break;
2569 }
2570 if (MCInst_getNumOperands(MI) == 3 &&
2571 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2572 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2573 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2574 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2575 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2576 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2577 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2578 AsmString = "fmovqn %icc, $\x02, $\x01";
2579 break;
2580 }
2581 if (MCInst_getNumOperands(MI) == 3 &&
2582 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2583 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2584 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2585 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2586 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2587 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2588 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2589 AsmString = "fmovqne %icc, $\x02, $\x01";
2590 break;
2591 }
2592 if (MCInst_getNumOperands(MI) == 3 &&
2593 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2594 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2595 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2596 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2597 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2598 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2599 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2600 AsmString = "fmovqe %icc, $\x02, $\x01";
2601 break;
2602 }
2603 if (MCInst_getNumOperands(MI) == 3 &&
2604 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2605 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2606 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2607 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2608 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2609 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2610 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2611 AsmString = "fmovqg %icc, $\x02, $\x01";
2612 break;
2613 }
2614 if (MCInst_getNumOperands(MI) == 3 &&
2615 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2616 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2617 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2618 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2619 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2620 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2621 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2622 AsmString = "fmovqle %icc, $\x02, $\x01";
2623 break;
2624 }
2625 if (MCInst_getNumOperands(MI) == 3 &&
2626 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2627 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2628 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2629 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2630 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2631 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2632 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2633 AsmString = "fmovqge %icc, $\x02, $\x01";
2634 break;
2635 }
2636 if (MCInst_getNumOperands(MI) == 3 &&
2637 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2638 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2639 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2640 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2641 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2642 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2643 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2644 AsmString = "fmovql %icc, $\x02, $\x01";
2645 break;
2646 }
2647 if (MCInst_getNumOperands(MI) == 3 &&
2648 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2649 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2650 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2651 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2652 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2653 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2654 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2655 AsmString = "fmovqgu %icc, $\x02, $\x01";
2656 break;
2657 }
2658 if (MCInst_getNumOperands(MI) == 3 &&
2659 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2660 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2661 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2662 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2663 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2664 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2665 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2666 AsmString = "fmovqleu %icc, $\x02, $\x01";
2667 break;
2668 }
2669 if (MCInst_getNumOperands(MI) == 3 &&
2670 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2671 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2672 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2673 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2674 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2675 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2676 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2677 AsmString = "fmovqcc %icc, $\x02, $\x01";
2678 break;
2679 }
2680 if (MCInst_getNumOperands(MI) == 3 &&
2681 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2682 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2683 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2684 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2685 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2686 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2687 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2688 AsmString = "fmovqcs %icc, $\x02, $\x01";
2689 break;
2690 }
2691 if (MCInst_getNumOperands(MI) == 3 &&
2692 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2693 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2694 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2695 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2696 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2697 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2698 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2699 AsmString = "fmovqpos %icc, $\x02, $\x01";
2700 break;
2701 }
2702 if (MCInst_getNumOperands(MI) == 3 &&
2703 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2704 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2705 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2706 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2707 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2708 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2709 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2710 AsmString = "fmovqneg %icc, $\x02, $\x01";
2711 break;
2712 }
2713 if (MCInst_getNumOperands(MI) == 3 &&
2714 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2715 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2716 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2717 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2718 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2719 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2720 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2721 AsmString = "fmovqvc %icc, $\x02, $\x01";
2722 break;
2723 }
2724 if (MCInst_getNumOperands(MI) == 3 &&
2725 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2726 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2727 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2728 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2729 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2730 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2731 // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2732 AsmString = "fmovqvs %icc, $\x02, $\x01";
2733 break;
2734 }
2735 return NULL;
2736 case SP_FMOVQ_XCC:
2737 if (MCInst_getNumOperands(MI) == 3 &&
2738 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2739 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2740 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2741 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2742 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2743 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2744 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2745 AsmString = "fmovqa %xcc, $\x02, $\x01";
2746 break;
2747 }
2748 if (MCInst_getNumOperands(MI) == 3 &&
2749 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2750 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2751 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2752 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2753 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2754 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2755 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2756 AsmString = "fmovqn %xcc, $\x02, $\x01";
2757 break;
2758 }
2759 if (MCInst_getNumOperands(MI) == 3 &&
2760 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2761 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2762 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2763 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2764 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2765 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2766 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2767 AsmString = "fmovqne %xcc, $\x02, $\x01";
2768 break;
2769 }
2770 if (MCInst_getNumOperands(MI) == 3 &&
2771 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2772 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2773 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2774 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2775 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2776 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2777 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2778 AsmString = "fmovqe %xcc, $\x02, $\x01";
2779 break;
2780 }
2781 if (MCInst_getNumOperands(MI) == 3 &&
2782 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2783 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2784 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2785 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2786 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2787 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2788 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2789 AsmString = "fmovqg %xcc, $\x02, $\x01";
2790 break;
2791 }
2792 if (MCInst_getNumOperands(MI) == 3 &&
2793 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2794 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2795 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2796 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2797 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2798 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2799 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2800 AsmString = "fmovqle %xcc, $\x02, $\x01";
2801 break;
2802 }
2803 if (MCInst_getNumOperands(MI) == 3 &&
2804 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2805 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2806 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2807 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2808 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2809 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2810 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2811 AsmString = "fmovqge %xcc, $\x02, $\x01";
2812 break;
2813 }
2814 if (MCInst_getNumOperands(MI) == 3 &&
2815 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2816 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2817 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2818 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2819 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2820 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2821 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2822 AsmString = "fmovql %xcc, $\x02, $\x01";
2823 break;
2824 }
2825 if (MCInst_getNumOperands(MI) == 3 &&
2826 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2827 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2828 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2829 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2830 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2831 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2832 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2833 AsmString = "fmovqgu %xcc, $\x02, $\x01";
2834 break;
2835 }
2836 if (MCInst_getNumOperands(MI) == 3 &&
2837 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2838 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2839 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2840 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2841 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2842 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2843 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2844 AsmString = "fmovqleu %xcc, $\x02, $\x01";
2845 break;
2846 }
2847 if (MCInst_getNumOperands(MI) == 3 &&
2848 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2849 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2850 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2851 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2852 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2853 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2854 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2855 AsmString = "fmovqcc %xcc, $\x02, $\x01";
2856 break;
2857 }
2858 if (MCInst_getNumOperands(MI) == 3 &&
2859 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2860 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2861 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2862 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2863 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2864 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2865 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2866 AsmString = "fmovqcs %xcc, $\x02, $\x01";
2867 break;
2868 }
2869 if (MCInst_getNumOperands(MI) == 3 &&
2870 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2871 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2872 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2873 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2874 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2875 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2876 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2877 AsmString = "fmovqpos %xcc, $\x02, $\x01";
2878 break;
2879 }
2880 if (MCInst_getNumOperands(MI) == 3 &&
2881 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2882 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2883 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2884 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2885 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2886 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2887 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2888 AsmString = "fmovqneg %xcc, $\x02, $\x01";
2889 break;
2890 }
2891 if (MCInst_getNumOperands(MI) == 3 &&
2892 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2893 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2894 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2895 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2896 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2897 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2898 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2899 AsmString = "fmovqvc %xcc, $\x02, $\x01";
2900 break;
2901 }
2902 if (MCInst_getNumOperands(MI) == 3 &&
2903 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2904 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2905 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2906 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2907 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2908 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2909 // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2910 AsmString = "fmovqvs %xcc, $\x02, $\x01";
2911 break;
2912 }
2913 return NULL;
2914 case SP_FMOVS_ICC:
2915 if (MCInst_getNumOperands(MI) == 3 &&
2916 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2917 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2918 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2919 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2920 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2921 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2922 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2923 AsmString = "fmovsa %icc, $\x02, $\x01";
2924 break;
2925 }
2926 if (MCInst_getNumOperands(MI) == 3 &&
2927 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2928 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2929 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2930 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2931 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2932 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2933 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2934 AsmString = "fmovsn %icc, $\x02, $\x01";
2935 break;
2936 }
2937 if (MCInst_getNumOperands(MI) == 3 &&
2938 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2939 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2940 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2941 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2942 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2943 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2944 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2945 AsmString = "fmovsne %icc, $\x02, $\x01";
2946 break;
2947 }
2948 if (MCInst_getNumOperands(MI) == 3 &&
2949 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2950 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2951 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2952 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2953 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2954 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2955 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2956 AsmString = "fmovse %icc, $\x02, $\x01";
2957 break;
2958 }
2959 if (MCInst_getNumOperands(MI) == 3 &&
2960 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2961 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2962 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2963 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2964 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2965 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2966 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2967 AsmString = "fmovsg %icc, $\x02, $\x01";
2968 break;
2969 }
2970 if (MCInst_getNumOperands(MI) == 3 &&
2971 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2972 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2973 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2974 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2975 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2976 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2977 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2978 AsmString = "fmovsle %icc, $\x02, $\x01";
2979 break;
2980 }
2981 if (MCInst_getNumOperands(MI) == 3 &&
2982 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2983 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2984 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2985 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2986 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2987 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2988 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2989 AsmString = "fmovsge %icc, $\x02, $\x01";
2990 break;
2991 }
2992 if (MCInst_getNumOperands(MI) == 3 &&
2993 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2994 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2995 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2996 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2997 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2998 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2999 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3000 AsmString = "fmovsl %icc, $\x02, $\x01";
3001 break;
3002 }
3003 if (MCInst_getNumOperands(MI) == 3 &&
3004 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3005 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3006 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3007 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3008 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3009 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3010 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3011 AsmString = "fmovsgu %icc, $\x02, $\x01";
3012 break;
3013 }
3014 if (MCInst_getNumOperands(MI) == 3 &&
3015 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3016 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3017 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3018 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3019 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3020 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3021 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3022 AsmString = "fmovsleu %icc, $\x02, $\x01";
3023 break;
3024 }
3025 if (MCInst_getNumOperands(MI) == 3 &&
3026 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3027 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3028 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3029 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3030 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3031 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3032 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3033 AsmString = "fmovscc %icc, $\x02, $\x01";
3034 break;
3035 }
3036 if (MCInst_getNumOperands(MI) == 3 &&
3037 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3038 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3039 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3040 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3041 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3042 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3043 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3044 AsmString = "fmovscs %icc, $\x02, $\x01";
3045 break;
3046 }
3047 if (MCInst_getNumOperands(MI) == 3 &&
3048 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3049 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3050 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3051 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3052 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3053 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3054 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3055 AsmString = "fmovspos %icc, $\x02, $\x01";
3056 break;
3057 }
3058 if (MCInst_getNumOperands(MI) == 3 &&
3059 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3060 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3061 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3062 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3063 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3064 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3065 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3066 AsmString = "fmovsneg %icc, $\x02, $\x01";
3067 break;
3068 }
3069 if (MCInst_getNumOperands(MI) == 3 &&
3070 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3071 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3072 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3073 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3074 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3075 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3076 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3077 AsmString = "fmovsvc %icc, $\x02, $\x01";
3078 break;
3079 }
3080 if (MCInst_getNumOperands(MI) == 3 &&
3081 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3082 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3083 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3084 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3085 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3086 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3087 // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3088 AsmString = "fmovsvs %icc, $\x02, $\x01";
3089 break;
3090 }
3091 return NULL;
3092 case SP_FMOVS_XCC:
3093 if (MCInst_getNumOperands(MI) == 3 &&
3094 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3095 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3096 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3097 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3098 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3099 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3100 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3101 AsmString = "fmovsa %xcc, $\x02, $\x01";
3102 break;
3103 }
3104 if (MCInst_getNumOperands(MI) == 3 &&
3105 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3106 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3107 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3108 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3109 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3110 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3111 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3112 AsmString = "fmovsn %xcc, $\x02, $\x01";
3113 break;
3114 }
3115 if (MCInst_getNumOperands(MI) == 3 &&
3116 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3117 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3118 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3119 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3120 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3121 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3122 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3123 AsmString = "fmovsne %xcc, $\x02, $\x01";
3124 break;
3125 }
3126 if (MCInst_getNumOperands(MI) == 3 &&
3127 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3128 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3129 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3130 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3131 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3132 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3133 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3134 AsmString = "fmovse %xcc, $\x02, $\x01";
3135 break;
3136 }
3137 if (MCInst_getNumOperands(MI) == 3 &&
3138 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3139 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3140 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3141 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3142 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3143 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3144 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3145 AsmString = "fmovsg %xcc, $\x02, $\x01";
3146 break;
3147 }
3148 if (MCInst_getNumOperands(MI) == 3 &&
3149 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3150 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3151 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3152 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3153 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3154 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3155 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3156 AsmString = "fmovsle %xcc, $\x02, $\x01";
3157 break;
3158 }
3159 if (MCInst_getNumOperands(MI) == 3 &&
3160 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3161 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3162 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3163 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3164 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3165 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3166 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3167 AsmString = "fmovsge %xcc, $\x02, $\x01";
3168 break;
3169 }
3170 if (MCInst_getNumOperands(MI) == 3 &&
3171 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3172 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3173 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3174 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3175 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3176 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3177 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3178 AsmString = "fmovsl %xcc, $\x02, $\x01";
3179 break;
3180 }
3181 if (MCInst_getNumOperands(MI) == 3 &&
3182 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3183 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3184 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3185 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3186 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3187 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3188 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3189 AsmString = "fmovsgu %xcc, $\x02, $\x01";
3190 break;
3191 }
3192 if (MCInst_getNumOperands(MI) == 3 &&
3193 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3194 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3195 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3196 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3197 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3198 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3199 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3200 AsmString = "fmovsleu %xcc, $\x02, $\x01";
3201 break;
3202 }
3203 if (MCInst_getNumOperands(MI) == 3 &&
3204 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3205 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3206 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3207 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3208 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3209 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3210 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3211 AsmString = "fmovscc %xcc, $\x02, $\x01";
3212 break;
3213 }
3214 if (MCInst_getNumOperands(MI) == 3 &&
3215 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3216 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3217 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3218 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3219 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3220 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3221 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3222 AsmString = "fmovscs %xcc, $\x02, $\x01";
3223 break;
3224 }
3225 if (MCInst_getNumOperands(MI) == 3 &&
3226 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3227 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3228 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3229 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3230 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3231 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3232 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3233 AsmString = "fmovspos %xcc, $\x02, $\x01";
3234 break;
3235 }
3236 if (MCInst_getNumOperands(MI) == 3 &&
3237 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3238 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3239 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3240 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3241 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3242 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3243 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3244 AsmString = "fmovsneg %xcc, $\x02, $\x01";
3245 break;
3246 }
3247 if (MCInst_getNumOperands(MI) == 3 &&
3248 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3249 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3250 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3251 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3252 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3253 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3254 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3255 AsmString = "fmovsvc %xcc, $\x02, $\x01";
3256 break;
3257 }
3258 if (MCInst_getNumOperands(MI) == 3 &&
3259 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3260 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3261 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3262 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3263 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3264 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3265 // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3266 AsmString = "fmovsvs %xcc, $\x02, $\x01";
3267 break;
3268 }
3269 return NULL;
3270 case SP_MOVICCri:
3271 if (MCInst_getNumOperands(MI) == 3 &&
3272 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3273 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3274 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3275 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3276 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3277 AsmString = "mova %icc, $\x02, $\x01";
3278 break;
3279 }
3280 if (MCInst_getNumOperands(MI) == 3 &&
3281 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3282 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3283 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3284 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3285 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3286 AsmString = "movn %icc, $\x02, $\x01";
3287 break;
3288 }
3289 if (MCInst_getNumOperands(MI) == 3 &&
3290 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3291 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3292 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3293 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3294 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3295 AsmString = "movne %icc, $\x02, $\x01";
3296 break;
3297 }
3298 if (MCInst_getNumOperands(MI) == 3 &&
3299 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3300 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3301 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3302 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3303 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3304 AsmString = "move %icc, $\x02, $\x01";
3305 break;
3306 }
3307 if (MCInst_getNumOperands(MI) == 3 &&
3308 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3309 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3310 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3311 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3312 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3313 AsmString = "movg %icc, $\x02, $\x01";
3314 break;
3315 }
3316 if (MCInst_getNumOperands(MI) == 3 &&
3317 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3318 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3319 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3320 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3321 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3322 AsmString = "movle %icc, $\x02, $\x01";
3323 break;
3324 }
3325 if (MCInst_getNumOperands(MI) == 3 &&
3326 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3327 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3328 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3329 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3330 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3331 AsmString = "movge %icc, $\x02, $\x01";
3332 break;
3333 }
3334 if (MCInst_getNumOperands(MI) == 3 &&
3335 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3336 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3337 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3338 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3339 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3340 AsmString = "movl %icc, $\x02, $\x01";
3341 break;
3342 }
3343 if (MCInst_getNumOperands(MI) == 3 &&
3344 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3345 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3346 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3347 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3348 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3349 AsmString = "movgu %icc, $\x02, $\x01";
3350 break;
3351 }
3352 if (MCInst_getNumOperands(MI) == 3 &&
3353 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3354 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3355 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3356 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3357 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3358 AsmString = "movleu %icc, $\x02, $\x01";
3359 break;
3360 }
3361 if (MCInst_getNumOperands(MI) == 3 &&
3362 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3363 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3364 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3365 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3366 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3367 AsmString = "movcc %icc, $\x02, $\x01";
3368 break;
3369 }
3370 if (MCInst_getNumOperands(MI) == 3 &&
3371 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3372 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3373 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3374 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3375 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3376 AsmString = "movcs %icc, $\x02, $\x01";
3377 break;
3378 }
3379 if (MCInst_getNumOperands(MI) == 3 &&
3380 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3381 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3382 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3383 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3384 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3385 AsmString = "movpos %icc, $\x02, $\x01";
3386 break;
3387 }
3388 if (MCInst_getNumOperands(MI) == 3 &&
3389 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3390 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3391 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3392 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3393 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3394 AsmString = "movneg %icc, $\x02, $\x01";
3395 break;
3396 }
3397 if (MCInst_getNumOperands(MI) == 3 &&
3398 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3399 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3400 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3401 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3402 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3403 AsmString = "movvc %icc, $\x02, $\x01";
3404 break;
3405 }
3406 if (MCInst_getNumOperands(MI) == 3 &&
3407 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3408 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3409 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3410 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3411 // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3412 AsmString = "movvs %icc, $\x02, $\x01";
3413 break;
3414 }
3415 return NULL;
3416 case SP_MOVICCrr:
3417 if (MCInst_getNumOperands(MI) == 3 &&
3418 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3419 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3420 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3421 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3422 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3423 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3424 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3425 AsmString = "mova %icc, $\x02, $\x01";
3426 break;
3427 }
3428 if (MCInst_getNumOperands(MI) == 3 &&
3429 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3430 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3431 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3432 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3433 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3434 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3435 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3436 AsmString = "movn %icc, $\x02, $\x01";
3437 break;
3438 }
3439 if (MCInst_getNumOperands(MI) == 3 &&
3440 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3441 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3442 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3443 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3444 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3445 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3446 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3447 AsmString = "movne %icc, $\x02, $\x01";
3448 break;
3449 }
3450 if (MCInst_getNumOperands(MI) == 3 &&
3451 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3452 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3453 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3454 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3455 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3456 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3457 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3458 AsmString = "move %icc, $\x02, $\x01";
3459 break;
3460 }
3461 if (MCInst_getNumOperands(MI) == 3 &&
3462 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3463 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3464 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3465 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3466 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3467 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3468 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3469 AsmString = "movg %icc, $\x02, $\x01";
3470 break;
3471 }
3472 if (MCInst_getNumOperands(MI) == 3 &&
3473 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3474 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3475 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3476 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3477 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3478 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3479 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3480 AsmString = "movle %icc, $\x02, $\x01";
3481 break;
3482 }
3483 if (MCInst_getNumOperands(MI) == 3 &&
3484 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3485 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3486 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3487 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3488 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3489 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3490 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3491 AsmString = "movge %icc, $\x02, $\x01";
3492 break;
3493 }
3494 if (MCInst_getNumOperands(MI) == 3 &&
3495 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3496 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3497 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3498 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3499 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3500 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3501 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3502 AsmString = "movl %icc, $\x02, $\x01";
3503 break;
3504 }
3505 if (MCInst_getNumOperands(MI) == 3 &&
3506 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3507 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3508 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3509 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3510 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3511 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3512 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3513 AsmString = "movgu %icc, $\x02, $\x01";
3514 break;
3515 }
3516 if (MCInst_getNumOperands(MI) == 3 &&
3517 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3518 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3519 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3520 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3521 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3522 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3523 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3524 AsmString = "movleu %icc, $\x02, $\x01";
3525 break;
3526 }
3527 if (MCInst_getNumOperands(MI) == 3 &&
3528 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3529 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3530 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3531 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3532 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3533 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3534 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3535 AsmString = "movcc %icc, $\x02, $\x01";
3536 break;
3537 }
3538 if (MCInst_getNumOperands(MI) == 3 &&
3539 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3540 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3541 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3542 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3543 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3544 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3545 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3546 AsmString = "movcs %icc, $\x02, $\x01";
3547 break;
3548 }
3549 if (MCInst_getNumOperands(MI) == 3 &&
3550 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3551 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3552 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3553 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3554 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3555 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3556 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3557 AsmString = "movpos %icc, $\x02, $\x01";
3558 break;
3559 }
3560 if (MCInst_getNumOperands(MI) == 3 &&
3561 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3562 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3563 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3564 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3565 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3566 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3567 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3568 AsmString = "movneg %icc, $\x02, $\x01";
3569 break;
3570 }
3571 if (MCInst_getNumOperands(MI) == 3 &&
3572 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3573 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3574 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3575 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3576 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3577 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3578 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3579 AsmString = "movvc %icc, $\x02, $\x01";
3580 break;
3581 }
3582 if (MCInst_getNumOperands(MI) == 3 &&
3583 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3584 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3585 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3586 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3587 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3588 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3589 // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3590 AsmString = "movvs %icc, $\x02, $\x01";
3591 break;
3592 }
3593 return NULL;
3594 case SP_MOVXCCri:
3595 if (MCInst_getNumOperands(MI) == 3 &&
3596 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3597 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3598 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3599 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3600 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3601 AsmString = "mova %xcc, $\x02, $\x01";
3602 break;
3603 }
3604 if (MCInst_getNumOperands(MI) == 3 &&
3605 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3606 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3607 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3608 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3609 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3610 AsmString = "movn %xcc, $\x02, $\x01";
3611 break;
3612 }
3613 if (MCInst_getNumOperands(MI) == 3 &&
3614 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3615 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3616 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3617 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3618 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3619 AsmString = "movne %xcc, $\x02, $\x01";
3620 break;
3621 }
3622 if (MCInst_getNumOperands(MI) == 3 &&
3623 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3624 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3625 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3626 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3627 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3628 AsmString = "move %xcc, $\x02, $\x01";
3629 break;
3630 }
3631 if (MCInst_getNumOperands(MI) == 3 &&
3632 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3633 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3634 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3635 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3636 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3637 AsmString = "movg %xcc, $\x02, $\x01";
3638 break;
3639 }
3640 if (MCInst_getNumOperands(MI) == 3 &&
3641 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3642 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3643 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3644 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3645 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3646 AsmString = "movle %xcc, $\x02, $\x01";
3647 break;
3648 }
3649 if (MCInst_getNumOperands(MI) == 3 &&
3650 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3651 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3652 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3653 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3654 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3655 AsmString = "movge %xcc, $\x02, $\x01";
3656 break;
3657 }
3658 if (MCInst_getNumOperands(MI) == 3 &&
3659 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3660 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3661 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3662 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3663 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3664 AsmString = "movl %xcc, $\x02, $\x01";
3665 break;
3666 }
3667 if (MCInst_getNumOperands(MI) == 3 &&
3668 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3669 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3670 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3671 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3672 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3673 AsmString = "movgu %xcc, $\x02, $\x01";
3674 break;
3675 }
3676 if (MCInst_getNumOperands(MI) == 3 &&
3677 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3678 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3679 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3680 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3681 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3682 AsmString = "movleu %xcc, $\x02, $\x01";
3683 break;
3684 }
3685 if (MCInst_getNumOperands(MI) == 3 &&
3686 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3687 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3688 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3689 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3690 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3691 AsmString = "movcc %xcc, $\x02, $\x01";
3692 break;
3693 }
3694 if (MCInst_getNumOperands(MI) == 3 &&
3695 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3696 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3697 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3698 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3699 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3700 AsmString = "movcs %xcc, $\x02, $\x01";
3701 break;
3702 }
3703 if (MCInst_getNumOperands(MI) == 3 &&
3704 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3705 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3706 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3707 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3708 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3709 AsmString = "movpos %xcc, $\x02, $\x01";
3710 break;
3711 }
3712 if (MCInst_getNumOperands(MI) == 3 &&
3713 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3714 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3715 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3716 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3717 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3718 AsmString = "movneg %xcc, $\x02, $\x01";
3719 break;
3720 }
3721 if (MCInst_getNumOperands(MI) == 3 &&
3722 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3723 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3724 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3725 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3726 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3727 AsmString = "movvc %xcc, $\x02, $\x01";
3728 break;
3729 }
3730 if (MCInst_getNumOperands(MI) == 3 &&
3731 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3732 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3733 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3734 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3735 // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3736 AsmString = "movvs %xcc, $\x02, $\x01";
3737 break;
3738 }
3739 return NULL;
3740 case SP_MOVXCCrr:
3741 if (MCInst_getNumOperands(MI) == 3 &&
3742 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3743 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3744 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3745 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3746 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3747 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3748 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3749 AsmString = "mova %xcc, $\x02, $\x01";
3750 break;
3751 }
3752 if (MCInst_getNumOperands(MI) == 3 &&
3753 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3754 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3755 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3756 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3757 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3758 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3759 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3760 AsmString = "movn %xcc, $\x02, $\x01";
3761 break;
3762 }
3763 if (MCInst_getNumOperands(MI) == 3 &&
3764 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3765 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3766 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3767 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3768 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3769 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3770 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3771 AsmString = "movne %xcc, $\x02, $\x01";
3772 break;
3773 }
3774 if (MCInst_getNumOperands(MI) == 3 &&
3775 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3776 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3777 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3778 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3779 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3780 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3781 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3782 AsmString = "move %xcc, $\x02, $\x01";
3783 break;
3784 }
3785 if (MCInst_getNumOperands(MI) == 3 &&
3786 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3787 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3788 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3789 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3790 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3791 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3792 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3793 AsmString = "movg %xcc, $\x02, $\x01";
3794 break;
3795 }
3796 if (MCInst_getNumOperands(MI) == 3 &&
3797 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3798 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3799 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3800 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3801 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3802 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3803 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3804 AsmString = "movle %xcc, $\x02, $\x01";
3805 break;
3806 }
3807 if (MCInst_getNumOperands(MI) == 3 &&
3808 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3809 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3810 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3811 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3812 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3813 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3814 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3815 AsmString = "movge %xcc, $\x02, $\x01";
3816 break;
3817 }
3818 if (MCInst_getNumOperands(MI) == 3 &&
3819 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3820 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3821 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3822 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3823 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3824 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3825 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3826 AsmString = "movl %xcc, $\x02, $\x01";
3827 break;
3828 }
3829 if (MCInst_getNumOperands(MI) == 3 &&
3830 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3831 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3832 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3833 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3834 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3835 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3836 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3837 AsmString = "movgu %xcc, $\x02, $\x01";
3838 break;
3839 }
3840 if (MCInst_getNumOperands(MI) == 3 &&
3841 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3842 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3843 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3844 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3845 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3846 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3847 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3848 AsmString = "movleu %xcc, $\x02, $\x01";
3849 break;
3850 }
3851 if (MCInst_getNumOperands(MI) == 3 &&
3852 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3853 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3854 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3855 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3856 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3857 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3858 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3859 AsmString = "movcc %xcc, $\x02, $\x01";
3860 break;
3861 }
3862 if (MCInst_getNumOperands(MI) == 3 &&
3863 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3864 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3865 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3866 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3867 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3868 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3869 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3870 AsmString = "movcs %xcc, $\x02, $\x01";
3871 break;
3872 }
3873 if (MCInst_getNumOperands(MI) == 3 &&
3874 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3875 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3876 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3877 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3878 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3879 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3880 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3881 AsmString = "movpos %xcc, $\x02, $\x01";
3882 break;
3883 }
3884 if (MCInst_getNumOperands(MI) == 3 &&
3885 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3886 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3887 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3888 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3889 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3890 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3891 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3892 AsmString = "movneg %xcc, $\x02, $\x01";
3893 break;
3894 }
3895 if (MCInst_getNumOperands(MI) == 3 &&
3896 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3897 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3898 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3899 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3900 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3901 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3902 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3903 AsmString = "movvc %xcc, $\x02, $\x01";
3904 break;
3905 }
3906 if (MCInst_getNumOperands(MI) == 3 &&
3907 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3908 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3909 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3910 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3911 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3912 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3913 // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3914 AsmString = "movvs %xcc, $\x02, $\x01";
3915 break;
3916 }
3917 return NULL;
3918 case SP_ORri:
3919 if (MCInst_getNumOperands(MI) == 3 &&
3920 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3921 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3922 MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3923 // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3924 AsmString = "mov $\x03, $\x01";
3925 break;
3926 }
3927 return NULL;
3928 case SP_ORrr:
3929 if (MCInst_getNumOperands(MI) == 3 &&
3930 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3931 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3932 MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3933 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3934 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3935 // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3936 AsmString = "mov $\x03, $\x01";
3937 break;
3938 }
3939 return NULL;
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]3940 case SP_RESTORErr:
3941 if (MCInst_getNumOperands(MI) == 3 &&
3942 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3943 MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3944 MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3945 // (RESTORErr G0, G0, G0)
3946 AsmString = "restore";
3947 break;
3948 }
3949 return NULL;
3950 case SP_RET:
3951 if (MCInst_getNumOperands(MI) == 1 &&
3952 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3953 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3954 // (RET 8)
3955 AsmString = "ret";
3956 break;
3957 }
3958 return NULL;
3959 case SP_RETL:
3960 if (MCInst_getNumOperands(MI) == 1 &&
3961 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3962 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3963 // (RETL 8)
3964 AsmString = "retl";
3965 break;
3966 }
3967 return NULL;
Nguyen Anh Quynh159ddbd2014-08-15 16:35:12 +0800[diff] [blame]3968 case SP_TXCCri:
3969 if (MCInst_getNumOperands(MI) == 3 &&
3970 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3971 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3972 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3973 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3974 // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3975 AsmString = "ta %xcc, $\x01 + $\x02";
3976 break;
3977 }
3978 if (MCInst_getNumOperands(MI) == 3 &&
3979 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3980 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3981 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3982 // (TXCCri G0, i32imm:$imm, 8)
3983 AsmString = "ta %xcc, $\x02";
3984 break;
3985 }
3986 if (MCInst_getNumOperands(MI) == 3 &&
3987 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3988 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3989 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3990 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3991 // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3992 AsmString = "tn %xcc, $\x01 + $\x02";
3993 break;
3994 }
3995 if (MCInst_getNumOperands(MI) == 3 &&
3996 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3997 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3998 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3999 // (TXCCri G0, i32imm:$imm, 0)
4000 AsmString = "tn %xcc, $\x02";
4001 break;
4002 }
4003 if (MCInst_getNumOperands(MI) == 3 &&
4004 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4005 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4006 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4007 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4008 // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4009 AsmString = "tne %xcc, $\x01 + $\x02";
4010 break;
4011 }
4012 if (MCInst_getNumOperands(MI) == 3 &&
4013 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4014 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4015 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4016 // (TXCCri G0, i32imm:$imm, 9)
4017 AsmString = "tne %xcc, $\x02";
4018 break;
4019 }
4020 if (MCInst_getNumOperands(MI) == 3 &&
4021 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4022 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4023 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4024 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4025 // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4026 AsmString = "te %xcc, $\x01 + $\x02";
4027 break;
4028 }
4029 if (MCInst_getNumOperands(MI) == 3 &&
4030 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4031 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4032 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4033 // (TXCCri G0, i32imm:$imm, 1)
4034 AsmString = "te %xcc, $\x02";
4035 break;
4036 }
4037 if (MCInst_getNumOperands(MI) == 3 &&
4038 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4039 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4040 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4041 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4042 // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4043 AsmString = "tg %xcc, $\x01 + $\x02";
4044 break;
4045 }
4046 if (MCInst_getNumOperands(MI) == 3 &&
4047 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4048 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4049 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4050 // (TXCCri G0, i32imm:$imm, 10)
4051 AsmString = "tg %xcc, $\x02";
4052 break;
4053 }
4054 if (MCInst_getNumOperands(MI) == 3 &&
4055 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4056 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4057 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4058 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4059 // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4060 AsmString = "tle %xcc, $\x01 + $\x02";
4061 break;
4062 }
4063 if (MCInst_getNumOperands(MI) == 3 &&
4064 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4065 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4066 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4067 // (TXCCri G0, i32imm:$imm, 2)
4068 AsmString = "tle %xcc, $\x02";
4069 break;
4070 }
4071 if (MCInst_getNumOperands(MI) == 3 &&
4072 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4073 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4074 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4075 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4076 // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4077 AsmString = "tge %xcc, $\x01 + $\x02";
4078 break;
4079 }
4080 if (MCInst_getNumOperands(MI) == 3 &&
4081 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4082 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4083 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4084 // (TXCCri G0, i32imm:$imm, 11)
4085 AsmString = "tge %xcc, $\x02";
4086 break;
4087 }
4088 if (MCInst_getNumOperands(MI) == 3 &&
4089 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4090 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4091 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4092 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4093 // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4094 AsmString = "tl %xcc, $\x01 + $\x02";
4095 break;
4096 }
4097 if (MCInst_getNumOperands(MI) == 3 &&
4098 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4099 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4100 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4101 // (TXCCri G0, i32imm:$imm, 3)
4102 AsmString = "tl %xcc, $\x02";
4103 break;
4104 }
4105 if (MCInst_getNumOperands(MI) == 3 &&
4106 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4107 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4108 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4109 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4110 // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4111 AsmString = "tgu %xcc, $\x01 + $\x02";
4112 break;
4113 }
4114 if (MCInst_getNumOperands(MI) == 3 &&
4115 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4116 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4117 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4118 // (TXCCri G0, i32imm:$imm, 12)
4119 AsmString = "tgu %xcc, $\x02";
4120 break;
4121 }
4122 if (MCInst_getNumOperands(MI) == 3 &&
4123 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4124 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4125 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4126 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4127 // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4128 AsmString = "tleu %xcc, $\x01 + $\x02";
4129 break;
4130 }
4131 if (MCInst_getNumOperands(MI) == 3 &&
4132 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4133 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4134 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4135 // (TXCCri G0, i32imm:$imm, 4)
4136 AsmString = "tleu %xcc, $\x02";
4137 break;
4138 }
4139 if (MCInst_getNumOperands(MI) == 3 &&
4140 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4141 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4142 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4143 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4144 // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4145 AsmString = "tcc %xcc, $\x01 + $\x02";
4146 break;
4147 }
4148 if (MCInst_getNumOperands(MI) == 3 &&
4149 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4150 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4151 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4152 // (TXCCri G0, i32imm:$imm, 13)
4153 AsmString = "tcc %xcc, $\x02";
4154 break;
4155 }
4156 if (MCInst_getNumOperands(MI) == 3 &&
4157 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4158 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4159 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4160 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4161 // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4162 AsmString = "tcs %xcc, $\x01 + $\x02";
4163 break;
4164 }
4165 if (MCInst_getNumOperands(MI) == 3 &&
4166 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4167 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4168 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4169 // (TXCCri G0, i32imm:$imm, 5)
4170 AsmString = "tcs %xcc, $\x02";
4171 break;
4172 }
4173 if (MCInst_getNumOperands(MI) == 3 &&
4174 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4175 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4176 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4177 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4178 // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4179 AsmString = "tpos %xcc, $\x01 + $\x02";
4180 break;
4181 }
4182 if (MCInst_getNumOperands(MI) == 3 &&
4183 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4184 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4185 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4186 // (TXCCri G0, i32imm:$imm, 14)
4187 AsmString = "tpos %xcc, $\x02";
4188 break;
4189 }
4190 if (MCInst_getNumOperands(MI) == 3 &&
4191 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4192 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4193 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4194 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4195 // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4196 AsmString = "tneg %xcc, $\x01 + $\x02";
4197 break;
4198 }
4199 if (MCInst_getNumOperands(MI) == 3 &&
4200 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4201 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4202 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4203 // (TXCCri G0, i32imm:$imm, 6)
4204 AsmString = "tneg %xcc, $\x02";
4205 break;
4206 }
4207 if (MCInst_getNumOperands(MI) == 3 &&
4208 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4209 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4210 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4211 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4212 // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4213 AsmString = "tvc %xcc, $\x01 + $\x02";
4214 break;
4215 }
4216 if (MCInst_getNumOperands(MI) == 3 &&
4217 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4218 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4219 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4220 // (TXCCri G0, i32imm:$imm, 15)
4221 AsmString = "tvc %xcc, $\x02";
4222 break;
4223 }
4224 if (MCInst_getNumOperands(MI) == 3 &&
4225 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4226 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4227 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4228 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4229 // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4230 AsmString = "tvs %xcc, $\x01 + $\x02";
4231 break;
4232 }
4233 if (MCInst_getNumOperands(MI) == 3 &&
4234 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4235 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4236 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4237 // (TXCCri G0, i32imm:$imm, 7)
4238 AsmString = "tvs %xcc, $\x02";
4239 break;
4240 }
4241 return NULL;
4242 case SP_TXCCrr:
4243 if (MCInst_getNumOperands(MI) == 3 &&
4244 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4245 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4246 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4247 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4248 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4249 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4250 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4251 AsmString = "ta %xcc, $\x01 + $\x02";
4252 break;
4253 }
4254 if (MCInst_getNumOperands(MI) == 3 &&
4255 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4256 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4257 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4258 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4259 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4260 // (TXCCrr G0, IntRegs:$rs2, 8)
4261 AsmString = "ta %xcc, $\x02";
4262 break;
4263 }
4264 if (MCInst_getNumOperands(MI) == 3 &&
4265 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4266 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4267 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4268 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4269 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4270 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4271 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4272 AsmString = "tn %xcc, $\x01 + $\x02";
4273 break;
4274 }
4275 if (MCInst_getNumOperands(MI) == 3 &&
4276 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4277 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4278 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4279 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4280 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4281 // (TXCCrr G0, IntRegs:$rs2, 0)
4282 AsmString = "tn %xcc, $\x02";
4283 break;
4284 }
4285 if (MCInst_getNumOperands(MI) == 3 &&
4286 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4287 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4288 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4289 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4290 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4291 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4292 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4293 AsmString = "tne %xcc, $\x01 + $\x02";
4294 break;
4295 }
4296 if (MCInst_getNumOperands(MI) == 3 &&
4297 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4298 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4299 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4300 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4301 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4302 // (TXCCrr G0, IntRegs:$rs2, 9)
4303 AsmString = "tne %xcc, $\x02";
4304 break;
4305 }
4306 if (MCInst_getNumOperands(MI) == 3 &&
4307 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4308 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4309 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4310 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4311 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4312 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4313 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4314 AsmString = "te %xcc, $\x01 + $\x02";
4315 break;
4316 }
4317 if (MCInst_getNumOperands(MI) == 3 &&
4318 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4319 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4320 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4321 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4322 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4323 // (TXCCrr G0, IntRegs:$rs2, 1)
4324 AsmString = "te %xcc, $\x02";
4325 break;
4326 }
4327 if (MCInst_getNumOperands(MI) == 3 &&
4328 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4329 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4330 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4331 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4332 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4333 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4334 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4335 AsmString = "tg %xcc, $\x01 + $\x02";
4336 break;
4337 }
4338 if (MCInst_getNumOperands(MI) == 3 &&
4339 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4340 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4341 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4342 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4343 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4344 // (TXCCrr G0, IntRegs:$rs2, 10)
4345 AsmString = "tg %xcc, $\x02";
4346 break;
4347 }
4348 if (MCInst_getNumOperands(MI) == 3 &&
4349 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4350 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4351 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4352 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4353 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4354 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4355 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4356 AsmString = "tle %xcc, $\x01 + $\x02";
4357 break;
4358 }
4359 if (MCInst_getNumOperands(MI) == 3 &&
4360 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4361 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4362 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4363 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4364 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4365 // (TXCCrr G0, IntRegs:$rs2, 2)
4366 AsmString = "tle %xcc, $\x02";
4367 break;
4368 }
4369 if (MCInst_getNumOperands(MI) == 3 &&
4370 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4371 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4372 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4373 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4374 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4375 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4376 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4377 AsmString = "tge %xcc, $\x01 + $\x02";
4378 break;
4379 }
4380 if (MCInst_getNumOperands(MI) == 3 &&
4381 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4382 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4383 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4384 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4385 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4386 // (TXCCrr G0, IntRegs:$rs2, 11)
4387 AsmString = "tge %xcc, $\x02";
4388 break;
4389 }
4390 if (MCInst_getNumOperands(MI) == 3 &&
4391 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4392 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4393 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4394 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4395 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4396 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4397 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4398 AsmString = "tl %xcc, $\x01 + $\x02";
4399 break;
4400 }
4401 if (MCInst_getNumOperands(MI) == 3 &&
4402 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4403 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4404 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4405 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4406 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4407 // (TXCCrr G0, IntRegs:$rs2, 3)
4408 AsmString = "tl %xcc, $\x02";
4409 break;
4410 }
4411 if (MCInst_getNumOperands(MI) == 3 &&
4412 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4413 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4414 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4415 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4416 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4417 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4418 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4419 AsmString = "tgu %xcc, $\x01 + $\x02";
4420 break;
4421 }
4422 if (MCInst_getNumOperands(MI) == 3 &&
4423 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4424 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4425 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4426 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4427 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4428 // (TXCCrr G0, IntRegs:$rs2, 12)
4429 AsmString = "tgu %xcc, $\x02";
4430 break;
4431 }
4432 if (MCInst_getNumOperands(MI) == 3 &&
4433 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4434 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4435 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4436 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4437 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4438 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4439 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4440 AsmString = "tleu %xcc, $\x01 + $\x02";
4441 break;
4442 }
4443 if (MCInst_getNumOperands(MI) == 3 &&
4444 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4445 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4446 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4447 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4448 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4449 // (TXCCrr G0, IntRegs:$rs2, 4)
4450 AsmString = "tleu %xcc, $\x02";
4451 break;
4452 }
4453 if (MCInst_getNumOperands(MI) == 3 &&
4454 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4455 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4456 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4457 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4458 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4459 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4460 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4461 AsmString = "tcc %xcc, $\x01 + $\x02";
4462 break;
4463 }
4464 if (MCInst_getNumOperands(MI) == 3 &&
4465 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4466 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4467 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4468 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4469 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4470 // (TXCCrr G0, IntRegs:$rs2, 13)
4471 AsmString = "tcc %xcc, $\x02";
4472 break;
4473 }
4474 if (MCInst_getNumOperands(MI) == 3 &&
4475 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4476 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4477 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4478 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4479 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4480 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4481 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4482 AsmString = "tcs %xcc, $\x01 + $\x02";
4483 break;
4484 }
4485 if (MCInst_getNumOperands(MI) == 3 &&
4486 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4487 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4488 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4489 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4490 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4491 // (TXCCrr G0, IntRegs:$rs2, 5)
4492 AsmString = "tcs %xcc, $\x02";
4493 break;
4494 }
4495 if (MCInst_getNumOperands(MI) == 3 &&
4496 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4497 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4498 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4499 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4500 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4501 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4502 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4503 AsmString = "tpos %xcc, $\x01 + $\x02";
4504 break;
4505 }
4506 if (MCInst_getNumOperands(MI) == 3 &&
4507 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4508 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4509 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4510 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4511 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4512 // (TXCCrr G0, IntRegs:$rs2, 14)
4513 AsmString = "tpos %xcc, $\x02";
4514 break;
4515 }
4516 if (MCInst_getNumOperands(MI) == 3 &&
4517 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4518 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4519 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4520 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4521 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4522 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4523 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4524 AsmString = "tneg %xcc, $\x01 + $\x02";
4525 break;
4526 }
4527 if (MCInst_getNumOperands(MI) == 3 &&
4528 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4529 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4530 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4531 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4532 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4533 // (TXCCrr G0, IntRegs:$rs2, 6)
4534 AsmString = "tneg %xcc, $\x02";
4535 break;
4536 }
4537 if (MCInst_getNumOperands(MI) == 3 &&
4538 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4539 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4540 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4541 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4542 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4543 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4544 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4545 AsmString = "tvc %xcc, $\x01 + $\x02";
4546 break;
4547 }
4548 if (MCInst_getNumOperands(MI) == 3 &&
4549 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4550 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4551 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4552 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4553 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4554 // (TXCCrr G0, IntRegs:$rs2, 15)
4555 AsmString = "tvc %xcc, $\x02";
4556 break;
4557 }
4558 if (MCInst_getNumOperands(MI) == 3 &&
4559 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4560 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4561 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4562 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4563 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4564 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4565 // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4566 AsmString = "tvs %xcc, $\x01 + $\x02";
4567 break;
4568 }
4569 if (MCInst_getNumOperands(MI) == 3 &&
4570 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4571 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4572 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4573 MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4574 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4575 // (TXCCrr G0, IntRegs:$rs2, 7)
4576 AsmString = "tvs %xcc, $\x02";
4577 break;
4578 }
4579 return NULL;
4580 case SP_V9FCMPD:
4581 if (MCInst_getNumOperands(MI) == 3 &&
4582 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4583 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4584 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4585 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4586 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4587 // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4588 AsmString = "fcmpd $\x02, $\x03";
4589 break;
4590 }
4591 return NULL;
4592 case SP_V9FCMPED:
4593 if (MCInst_getNumOperands(MI) == 3 &&
4594 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4595 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4596 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4597 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4598 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4599 // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4600 AsmString = "fcmped $\x02, $\x03";
4601 break;
4602 }
4603 return NULL;
4604 case SP_V9FCMPEQ:
4605 if (MCInst_getNumOperands(MI) == 3 &&
4606 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4607 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4608 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4609 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4610 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4611 // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4612 AsmString = "fcmpeq $\x02, $\x03";
4613 break;
4614 }
4615 return NULL;
4616 case SP_V9FCMPES:
4617 if (MCInst_getNumOperands(MI) == 3 &&
4618 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4619 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4620 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4621 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4622 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4623 // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4624 AsmString = "fcmpes $\x02, $\x03";
4625 break;
4626 }
4627 return NULL;
4628 case SP_V9FCMPQ:
4629 if (MCInst_getNumOperands(MI) == 3 &&
4630 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4631 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4632 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4633 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4634 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4635 // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4636 AsmString = "fcmpq $\x02, $\x03";
4637 break;
4638 }
4639 return NULL;
4640 case SP_V9FCMPS:
4641 if (MCInst_getNumOperands(MI) == 3 &&
4642 MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4643 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4644 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4645 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4646 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4647 // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4648 AsmString = "fcmps $\x02, $\x03";
4649 break;
4650 }
4651 return NULL;
4652 case SP_V9FMOVD_FCC:
4653 if (MCInst_getNumOperands(MI) == 4 &&
4654 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4655 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4656 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4657 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4658 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4659 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4660 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4661 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4662 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4663 AsmString = "fmovda $\x02, $\x03, $\x01";
4664 break;
4665 }
4666 if (MCInst_getNumOperands(MI) == 4 &&
4667 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4668 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4669 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4670 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4671 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4672 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4673 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4674 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4675 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4676 AsmString = "fmovdn $\x02, $\x03, $\x01";
4677 break;
4678 }
4679 if (MCInst_getNumOperands(MI) == 4 &&
4680 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4681 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4682 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4683 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4684 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4685 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4686 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4687 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4688 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4689 AsmString = "fmovdu $\x02, $\x03, $\x01";
4690 break;
4691 }
4692 if (MCInst_getNumOperands(MI) == 4 &&
4693 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4694 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4695 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4696 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4697 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4698 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4699 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4700 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4701 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4702 AsmString = "fmovdg $\x02, $\x03, $\x01";
4703 break;
4704 }
4705 if (MCInst_getNumOperands(MI) == 4 &&
4706 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4707 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4708 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4709 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4710 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4711 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4712 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4713 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4714 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4715 AsmString = "fmovdug $\x02, $\x03, $\x01";
4716 break;
4717 }
4718 if (MCInst_getNumOperands(MI) == 4 &&
4719 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4720 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4721 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4722 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4723 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4724 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4725 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4726 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4727 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4728 AsmString = "fmovdl $\x02, $\x03, $\x01";
4729 break;
4730 }
4731 if (MCInst_getNumOperands(MI) == 4 &&
4732 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4733 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4734 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4735 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4736 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4737 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4738 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4739 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4740 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4741 AsmString = "fmovdul $\x02, $\x03, $\x01";
4742 break;
4743 }
4744 if (MCInst_getNumOperands(MI) == 4 &&
4745 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4746 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4747 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4748 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4749 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4750 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4751 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4752 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4753 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4754 AsmString = "fmovdlg $\x02, $\x03, $\x01";
4755 break;
4756 }
4757 if (MCInst_getNumOperands(MI) == 4 &&
4758 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4759 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4760 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4761 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4762 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4763 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4764 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4765 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4766 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4767 AsmString = "fmovdne $\x02, $\x03, $\x01";
4768 break;
4769 }
4770 if (MCInst_getNumOperands(MI) == 4 &&
4771 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4772 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4773 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4774 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4775 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4776 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4777 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4778 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4779 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4780 AsmString = "fmovde $\x02, $\x03, $\x01";
4781 break;
4782 }
4783 if (MCInst_getNumOperands(MI) == 4 &&
4784 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4785 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4786 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4787 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4788 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4789 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4790 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4791 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4792 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4793 AsmString = "fmovdue $\x02, $\x03, $\x01";
4794 break;
4795 }
4796 if (MCInst_getNumOperands(MI) == 4 &&
4797 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4798 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4799 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4800 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4801 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4802 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4803 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4804 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4805 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4806 AsmString = "fmovdge $\x02, $\x03, $\x01";
4807 break;
4808 }
4809 if (MCInst_getNumOperands(MI) == 4 &&
4810 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4811 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4812 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4813 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4814 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4815 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4816 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4817 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4818 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4819 AsmString = "fmovduge $\x02, $\x03, $\x01";
4820 break;
4821 }
4822 if (MCInst_getNumOperands(MI) == 4 &&
4823 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4824 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4825 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4826 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4827 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4828 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4829 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4830 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4831 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4832 AsmString = "fmovdle $\x02, $\x03, $\x01";
4833 break;
4834 }
4835 if (MCInst_getNumOperands(MI) == 4 &&
4836 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4837 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4838 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4839 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4840 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4841 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4842 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4843 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4844 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4845 AsmString = "fmovdule $\x02, $\x03, $\x01";
4846 break;
4847 }
4848 if (MCInst_getNumOperands(MI) == 4 &&
4849 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4850 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4851 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4852 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4853 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4854 GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4855 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4856 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4857 // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4858 AsmString = "fmovdo $\x02, $\x03, $\x01";
4859 break;
4860 }
4861 return NULL;
4862 case SP_V9FMOVQ_FCC:
4863 if (MCInst_getNumOperands(MI) == 4 &&
4864 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4865 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4866 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4867 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4868 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4869 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4870 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4871 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4872 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4873 AsmString = "fmovqa $\x02, $\x03, $\x01";
4874 break;
4875 }
4876 if (MCInst_getNumOperands(MI) == 4 &&
4877 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4878 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4879 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4880 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4881 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4882 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4883 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4884 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4885 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4886 AsmString = "fmovqn $\x02, $\x03, $\x01";
4887 break;
4888 }
4889 if (MCInst_getNumOperands(MI) == 4 &&
4890 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4891 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4892 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4893 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4894 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4895 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4896 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4897 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4898 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4899 AsmString = "fmovqu $\x02, $\x03, $\x01";
4900 break;
4901 }
4902 if (MCInst_getNumOperands(MI) == 4 &&
4903 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4904 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4905 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4906 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4907 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4908 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4909 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4910 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4911 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4912 AsmString = "fmovqg $\x02, $\x03, $\x01";
4913 break;
4914 }
4915 if (MCInst_getNumOperands(MI) == 4 &&
4916 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4917 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4918 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4919 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4920 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4921 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4922 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4923 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4924 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4925 AsmString = "fmovqug $\x02, $\x03, $\x01";
4926 break;
4927 }
4928 if (MCInst_getNumOperands(MI) == 4 &&
4929 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4930 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4931 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4932 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4933 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4934 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4935 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4936 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4937 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4938 AsmString = "fmovql $\x02, $\x03, $\x01";
4939 break;
4940 }
4941 if (MCInst_getNumOperands(MI) == 4 &&
4942 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4943 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4944 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4945 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4946 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4947 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4948 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4949 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4950 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4951 AsmString = "fmovqul $\x02, $\x03, $\x01";
4952 break;
4953 }
4954 if (MCInst_getNumOperands(MI) == 4 &&
4955 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4956 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4957 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4958 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4959 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4960 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4961 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4962 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4963 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4964 AsmString = "fmovqlg $\x02, $\x03, $\x01";
4965 break;
4966 }
4967 if (MCInst_getNumOperands(MI) == 4 &&
4968 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4969 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4970 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4971 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4972 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4973 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4974 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4975 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4976 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4977 AsmString = "fmovqne $\x02, $\x03, $\x01";
4978 break;
4979 }
4980 if (MCInst_getNumOperands(MI) == 4 &&
4981 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4982 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4983 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4984 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4985 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4986 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4987 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4988 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4989 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4990 AsmString = "fmovqe $\x02, $\x03, $\x01";
4991 break;
4992 }
4993 if (MCInst_getNumOperands(MI) == 4 &&
4994 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4995 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4996 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4997 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4998 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4999 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5000 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5001 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5002 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5003 AsmString = "fmovque $\x02, $\x03, $\x01";
5004 break;
5005 }
5006 if (MCInst_getNumOperands(MI) == 4 &&
5007 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5008 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5009 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5010 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5011 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5012 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5013 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5014 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5015 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5016 AsmString = "fmovqge $\x02, $\x03, $\x01";
5017 break;
5018 }
5019 if (MCInst_getNumOperands(MI) == 4 &&
5020 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5021 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5022 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5023 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5024 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5025 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5026 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5027 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5028 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5029 AsmString = "fmovquge $\x02, $\x03, $\x01";
5030 break;
5031 }
5032 if (MCInst_getNumOperands(MI) == 4 &&
5033 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5034 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5035 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5036 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5037 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5038 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5039 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5040 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5041 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5042 AsmString = "fmovqle $\x02, $\x03, $\x01";
5043 break;
5044 }
5045 if (MCInst_getNumOperands(MI) == 4 &&
5046 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5047 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5048 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5049 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5050 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5051 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5052 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5053 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5054 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5055 AsmString = "fmovqule $\x02, $\x03, $\x01";
5056 break;
5057 }
5058 if (MCInst_getNumOperands(MI) == 4 &&
5059 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5060 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5061 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5062 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5063 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5064 GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5065 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5066 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5067 // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5068 AsmString = "fmovqo $\x02, $\x03, $\x01";
5069 break;
5070 }
5071 return NULL;
5072 case SP_V9FMOVS_FCC:
5073 if (MCInst_getNumOperands(MI) == 4 &&
5074 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5075 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5076 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5077 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5078 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5079 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5080 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5081 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5082 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5083 AsmString = "fmovsa $\x02, $\x03, $\x01";
5084 break;
5085 }
5086 if (MCInst_getNumOperands(MI) == 4 &&
5087 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5088 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5089 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5090 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5091 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5092 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5093 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5094 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5095 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5096 AsmString = "fmovsn $\x02, $\x03, $\x01";
5097 break;
5098 }
5099 if (MCInst_getNumOperands(MI) == 4 &&
5100 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5101 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5102 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5103 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5104 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5105 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5106 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5107 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5108 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5109 AsmString = "fmovsu $\x02, $\x03, $\x01";
5110 break;
5111 }
5112 if (MCInst_getNumOperands(MI) == 4 &&
5113 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5114 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5115 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5116 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5117 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5118 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5119 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5120 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5121 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5122 AsmString = "fmovsg $\x02, $\x03, $\x01";
5123 break;
5124 }
5125 if (MCInst_getNumOperands(MI) == 4 &&
5126 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5127 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5128 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5129 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5130 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5131 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5132 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5133 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5134 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5135 AsmString = "fmovsug $\x02, $\x03, $\x01";
5136 break;
5137 }
5138 if (MCInst_getNumOperands(MI) == 4 &&
5139 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5140 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5141 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5142 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5143 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5144 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5145 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5146 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5147 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5148 AsmString = "fmovsl $\x02, $\x03, $\x01";
5149 break;
5150 }
5151 if (MCInst_getNumOperands(MI) == 4 &&
5152 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5153 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5154 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5155 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5156 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5157 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5158 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5159 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5160 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5161 AsmString = "fmovsul $\x02, $\x03, $\x01";
5162 break;
5163 }
5164 if (MCInst_getNumOperands(MI) == 4 &&
5165 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5166 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5167 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5168 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5169 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5170 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5171 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5172 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5173 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5174 AsmString = "fmovslg $\x02, $\x03, $\x01";
5175 break;
5176 }
5177 if (MCInst_getNumOperands(MI) == 4 &&
5178 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5179 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5180 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5181 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5182 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5183 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5184 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5185 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5186 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5187 AsmString = "fmovsne $\x02, $\x03, $\x01";
5188 break;
5189 }
5190 if (MCInst_getNumOperands(MI) == 4 &&
5191 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5192 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5193 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5194 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5195 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5196 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5197 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5198 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5199 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5200 AsmString = "fmovse $\x02, $\x03, $\x01";
5201 break;
5202 }
5203 if (MCInst_getNumOperands(MI) == 4 &&
5204 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5205 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5206 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5207 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5208 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5209 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5210 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5211 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5212 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5213 AsmString = "fmovsue $\x02, $\x03, $\x01";
5214 break;
5215 }
5216 if (MCInst_getNumOperands(MI) == 4 &&
5217 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5218 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5219 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5220 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5221 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5222 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5223 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5224 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5225 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5226 AsmString = "fmovsge $\x02, $\x03, $\x01";
5227 break;
5228 }
5229 if (MCInst_getNumOperands(MI) == 4 &&
5230 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5231 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5232 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5233 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5234 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5235 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5236 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5237 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5238 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5239 AsmString = "fmovsuge $\x02, $\x03, $\x01";
5240 break;
5241 }
5242 if (MCInst_getNumOperands(MI) == 4 &&
5243 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5244 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5245 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5246 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5247 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5248 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5249 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5250 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5251 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5252 AsmString = "fmovsle $\x02, $\x03, $\x01";
5253 break;
5254 }
5255 if (MCInst_getNumOperands(MI) == 4 &&
5256 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5257 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5258 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5259 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5260 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5261 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5262 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5263 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5264 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5265 AsmString = "fmovsule $\x02, $\x03, $\x01";
5266 break;
5267 }
5268 if (MCInst_getNumOperands(MI) == 4 &&
5269 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5270 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5271 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5272 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5273 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5274 GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5275 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5276 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5277 // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5278 AsmString = "fmovso $\x02, $\x03, $\x01";
5279 break;
5280 }
5281 return NULL;
5282 case SP_V9MOVFCCri:
5283 if (MCInst_getNumOperands(MI) == 4 &&
5284 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5285 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5286 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5287 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5288 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5289 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5290 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5291 AsmString = "mova $\x02, $\x03, $\x01";
5292 break;
5293 }
5294 if (MCInst_getNumOperands(MI) == 4 &&
5295 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5296 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5297 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5298 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5299 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5300 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5301 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5302 AsmString = "movn $\x02, $\x03, $\x01";
5303 break;
5304 }
5305 if (MCInst_getNumOperands(MI) == 4 &&
5306 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5307 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5308 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5309 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5310 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5311 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5312 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5313 AsmString = "movu $\x02, $\x03, $\x01";
5314 break;
5315 }
5316 if (MCInst_getNumOperands(MI) == 4 &&
5317 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5318 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5319 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5320 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5321 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5322 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5323 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5324 AsmString = "movg $\x02, $\x03, $\x01";
5325 break;
5326 }
5327 if (MCInst_getNumOperands(MI) == 4 &&
5328 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5329 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5330 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5331 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5332 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5333 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5334 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5335 AsmString = "movug $\x02, $\x03, $\x01";
5336 break;
5337 }
5338 if (MCInst_getNumOperands(MI) == 4 &&
5339 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5340 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5341 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5342 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5343 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5344 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5345 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5346 AsmString = "movl $\x02, $\x03, $\x01";
5347 break;
5348 }
5349 if (MCInst_getNumOperands(MI) == 4 &&
5350 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5351 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5352 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5353 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5354 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5355 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5356 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5357 AsmString = "movul $\x02, $\x03, $\x01";
5358 break;
5359 }
5360 if (MCInst_getNumOperands(MI) == 4 &&
5361 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5362 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5363 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5364 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5365 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5366 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5367 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5368 AsmString = "movlg $\x02, $\x03, $\x01";
5369 break;
5370 }
5371 if (MCInst_getNumOperands(MI) == 4 &&
5372 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5373 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5374 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5375 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5376 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5377 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5378 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5379 AsmString = "movne $\x02, $\x03, $\x01";
5380 break;
5381 }
5382 if (MCInst_getNumOperands(MI) == 4 &&
5383 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5384 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5385 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5386 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5387 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5388 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5389 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5390 AsmString = "move $\x02, $\x03, $\x01";
5391 break;
5392 }
5393 if (MCInst_getNumOperands(MI) == 4 &&
5394 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5395 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5396 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5397 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5398 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5399 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5400 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5401 AsmString = "movue $\x02, $\x03, $\x01";
5402 break;
5403 }
5404 if (MCInst_getNumOperands(MI) == 4 &&
5405 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5406 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5407 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5408 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5409 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5410 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5411 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5412 AsmString = "movge $\x02, $\x03, $\x01";
5413 break;
5414 }
5415 if (MCInst_getNumOperands(MI) == 4 &&
5416 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5417 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5418 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5419 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5420 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5421 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5422 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5423 AsmString = "movuge $\x02, $\x03, $\x01";
5424 break;
5425 }
5426 if (MCInst_getNumOperands(MI) == 4 &&
5427 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5428 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5429 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5430 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5431 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5432 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5433 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5434 AsmString = "movle $\x02, $\x03, $\x01";
5435 break;
5436 }
5437 if (MCInst_getNumOperands(MI) == 4 &&
5438 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5439 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5440 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5441 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5442 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5443 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5444 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5445 AsmString = "movule $\x02, $\x03, $\x01";
5446 break;
5447 }
5448 if (MCInst_getNumOperands(MI) == 4 &&
5449 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5450 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5451 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5452 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5453 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5454 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5455 // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5456 AsmString = "movo $\x02, $\x03, $\x01";
5457 break;
5458 }
5459 return NULL;
5460 case SP_V9MOVFCCrr:
5461 if (MCInst_getNumOperands(MI) == 4 &&
5462 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5463 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5464 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5465 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5466 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5467 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5468 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5469 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5470 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5471 AsmString = "mova $\x02, $\x03, $\x01";
5472 break;
5473 }
5474 if (MCInst_getNumOperands(MI) == 4 &&
5475 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5476 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5477 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5478 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5479 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5480 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5481 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5482 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5483 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5484 AsmString = "movn $\x02, $\x03, $\x01";
5485 break;
5486 }
5487 if (MCInst_getNumOperands(MI) == 4 &&
5488 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5489 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5490 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5491 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5492 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5493 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5494 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5495 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5496 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5497 AsmString = "movu $\x02, $\x03, $\x01";
5498 break;
5499 }
5500 if (MCInst_getNumOperands(MI) == 4 &&
5501 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5502 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5503 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5504 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5505 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5506 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5507 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5508 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5509 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5510 AsmString = "movg $\x02, $\x03, $\x01";
5511 break;
5512 }
5513 if (MCInst_getNumOperands(MI) == 4 &&
5514 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5515 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5516 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5517 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5518 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5519 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5520 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5521 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5522 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5523 AsmString = "movug $\x02, $\x03, $\x01";
5524 break;
5525 }
5526 if (MCInst_getNumOperands(MI) == 4 &&
5527 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5528 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5529 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5530 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5531 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5532 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5533 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5534 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5535 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5536 AsmString = "movl $\x02, $\x03, $\x01";
5537 break;
5538 }
5539 if (MCInst_getNumOperands(MI) == 4 &&
5540 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5541 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5542 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5543 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5544 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5545 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5546 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5547 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5548 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5549 AsmString = "movul $\x02, $\x03, $\x01";
5550 break;
5551 }
5552 if (MCInst_getNumOperands(MI) == 4 &&
5553 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5554 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5555 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5556 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5557 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5558 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5559 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5560 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5561 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5562 AsmString = "movlg $\x02, $\x03, $\x01";
5563 break;
5564 }
5565 if (MCInst_getNumOperands(MI) == 4 &&
5566 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5567 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5568 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5569 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5570 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5571 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5572 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5573 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5574 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5575 AsmString = "movne $\x02, $\x03, $\x01";
5576 break;
5577 }
5578 if (MCInst_getNumOperands(MI) == 4 &&
5579 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5580 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5581 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5582 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5583 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5584 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5585 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5586 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5587 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5588 AsmString = "move $\x02, $\x03, $\x01";
5589 break;
5590 }
5591 if (MCInst_getNumOperands(MI) == 4 &&
5592 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5593 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5594 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5595 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5596 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5597 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5598 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5599 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5600 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5601 AsmString = "movue $\x02, $\x03, $\x01";
5602 break;
5603 }
5604 if (MCInst_getNumOperands(MI) == 4 &&
5605 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5606 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5607 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5608 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5609 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5610 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5611 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5612 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5613 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5614 AsmString = "movge $\x02, $\x03, $\x01";
5615 break;
5616 }
5617 if (MCInst_getNumOperands(MI) == 4 &&
5618 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5619 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5620 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5621 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5622 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5623 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5624 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5625 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5626 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5627 AsmString = "movuge $\x02, $\x03, $\x01";
5628 break;
5629 }
5630 if (MCInst_getNumOperands(MI) == 4 &&
5631 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5632 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5633 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5634 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5635 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5636 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5637 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5638 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5639 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5640 AsmString = "movle $\x02, $\x03, $\x01";
5641 break;
5642 }
5643 if (MCInst_getNumOperands(MI) == 4 &&
5644 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5645 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5646 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5647 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5648 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5649 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5650 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5651 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5652 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5653 AsmString = "movule $\x02, $\x03, $\x01";
5654 break;
5655 }
5656 if (MCInst_getNumOperands(MI) == 4 &&
5657 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5658 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5659 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5660 GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5661 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5662 GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5663 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5664 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5665 // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5666 AsmString = "movo $\x02, $\x03, $\x01";
5667 break;
5668 }
5669 return NULL;
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]5670 }
5671
5672 tmp = cs_strdup(AsmString);
5673 AsmMnem = tmp;
Nguyen Anh Quynhb1e87e32014-08-25 23:27:33 +0800[diff] [blame]5674 for(AsmOps = tmp; *AsmOps; AsmOps++) {
5675 if (*AsmOps == ' ' || *AsmOps == '\t') {
5676 *AsmOps = '\0';
5677 AsmOps++;
5678 break;
5679 }
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]5680 }
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]5681 SStream_concat0(OS, AsmMnem);
Nguyen Anh Quynh14b684e2014-08-25 23:45:52 +0800[diff] [blame]5682 if (*AsmOps) {
Nguyen Anh Quynh9b91de02014-06-16 12:51:07 +0800[diff] [blame]5683 SStream_concat0(OS, "\t");
Nguyen Anh Quynhb6f4c1d2014-11-11 07:02:13 +0800[diff] [blame]5684 if (strstr(AsmOps, "icc"))
5685 Sparc_addReg(MI, SPARC_REG_ICC);
5686 if (strstr(AsmOps, "xcc"))
5687 Sparc_addReg(MI, SPARC_REG_XCC);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]5688 for (c = AsmOps; *c; c++) {
5689 if (*c == '$') {
5690 c += 1;
Nguyen Anh Quynh159ddbd2014-08-15 16:35:12 +0800[diff] [blame]5691 if (*c == (char)0xff) {
5692 c += 1;
5693 OpIdx = *c - 1;
5694 c += 1;
5695 PrintMethodIdx = *c - 1;
5696 printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5697 } else
5698 printOperand(MI, *c - 1, OS);
Nguyen Anh Quynh05e27132014-03-10 11:58:57 +0800[diff] [blame]5699 } else {
5700 SStream_concat(OS, "%c", *c);
5701 }
5702 }
5703 }
5704 return tmp;
5705}
5706
5707#endif // PRINT_ALIAS_INSTR