Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1 | /* Capstone Unified Disassembler Engine */ |
| 2 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */ |
| 3 | |
| 4 | #include <stdio.h> // debug |
| 5 | #include <string.h> |
| 6 | |
| 7 | #include "../../include/arm64.h" |
| 8 | #include "../../utils.h" |
| 9 | |
| 10 | #include "mapping.h" |
| 11 | |
| 12 | #define GET_INSTRINFO_ENUM |
| 13 | #include "AArch64GenInstrInfo.inc" |
| 14 | |
| 15 | static name_map reg_name_maps[] = { |
| 16 | { ARM64_REG_INVALID, NULL }, |
| 17 | { ARM64_REG_NZCV, "nzcv"}, |
| 18 | { ARM64_REG_WSP, "wsp"}, |
| 19 | { ARM64_REG_WZR, "wzr"}, |
| 20 | { ARM64_REG_SP, "sp"}, |
| 21 | { ARM64_REG_XZR, "xzr"}, |
| 22 | { ARM64_REG_B0, "b0"}, |
| 23 | { ARM64_REG_B1, "b1"}, |
| 24 | { ARM64_REG_B2, "b2"}, |
| 25 | { ARM64_REG_B3, "b3"}, |
| 26 | { ARM64_REG_B4, "b4"}, |
| 27 | { ARM64_REG_B5, "b5"}, |
| 28 | { ARM64_REG_B6, "b6"}, |
| 29 | { ARM64_REG_B7, "b7"}, |
| 30 | { ARM64_REG_B8, "b8"}, |
| 31 | { ARM64_REG_B9, "b9"}, |
| 32 | { ARM64_REG_B10, "b10"}, |
| 33 | { ARM64_REG_B11, "b11"}, |
| 34 | { ARM64_REG_B12, "b12"}, |
| 35 | { ARM64_REG_B13, "b13"}, |
| 36 | { ARM64_REG_B14, "b14"}, |
| 37 | { ARM64_REG_B15, "b15"}, |
| 38 | { ARM64_REG_B16, "b16"}, |
| 39 | { ARM64_REG_B17, "b17"}, |
| 40 | { ARM64_REG_B18, "b18"}, |
| 41 | { ARM64_REG_B19, "b19"}, |
| 42 | { ARM64_REG_B20, "b20"}, |
| 43 | { ARM64_REG_B21, "b21"}, |
| 44 | { ARM64_REG_B22, "b22"}, |
| 45 | { ARM64_REG_B23, "b23"}, |
| 46 | { ARM64_REG_B24, "b24"}, |
| 47 | { ARM64_REG_B25, "b25"}, |
| 48 | { ARM64_REG_B26, "b26"}, |
| 49 | { ARM64_REG_B27, "b27"}, |
| 50 | { ARM64_REG_B28, "b28"}, |
| 51 | { ARM64_REG_B29, "b29"}, |
| 52 | { ARM64_REG_B30, "b30"}, |
| 53 | { ARM64_REG_B31, "b31"}, |
| 54 | { ARM64_REG_D0, "d0"}, |
| 55 | { ARM64_REG_D1, "d1"}, |
| 56 | { ARM64_REG_D2, "d2"}, |
| 57 | { ARM64_REG_D3, "d3"}, |
| 58 | { ARM64_REG_D4, "d4"}, |
| 59 | { ARM64_REG_D5, "d5"}, |
| 60 | { ARM64_REG_D6, "d6"}, |
| 61 | { ARM64_REG_D7, "d7"}, |
| 62 | { ARM64_REG_D8, "d8"}, |
| 63 | { ARM64_REG_D9, "d9"}, |
| 64 | { ARM64_REG_D10, "d10"}, |
| 65 | { ARM64_REG_D11, "d11"}, |
| 66 | { ARM64_REG_D12, "d12"}, |
| 67 | { ARM64_REG_D13, "d13"}, |
| 68 | { ARM64_REG_D14, "d14"}, |
| 69 | { ARM64_REG_D15, "d15"}, |
| 70 | { ARM64_REG_D16, "d16"}, |
| 71 | { ARM64_REG_D17, "d17"}, |
| 72 | { ARM64_REG_D18, "d18"}, |
| 73 | { ARM64_REG_D19, "d19"}, |
| 74 | { ARM64_REG_D20, "d20"}, |
| 75 | { ARM64_REG_D21, "d21"}, |
| 76 | { ARM64_REG_D22, "d22"}, |
| 77 | { ARM64_REG_D23, "d23"}, |
| 78 | { ARM64_REG_D24, "d24"}, |
| 79 | { ARM64_REG_D25, "d25"}, |
| 80 | { ARM64_REG_D26, "d26"}, |
| 81 | { ARM64_REG_D27, "d27"}, |
| 82 | { ARM64_REG_D28, "d28"}, |
| 83 | { ARM64_REG_D29, "d29"}, |
| 84 | { ARM64_REG_D30, "d30"}, |
| 85 | { ARM64_REG_D31, "d31"}, |
| 86 | { ARM64_REG_H0, "h0"}, |
| 87 | { ARM64_REG_H1, "h1"}, |
| 88 | { ARM64_REG_H2, "h2"}, |
| 89 | { ARM64_REG_H3, "h3"}, |
| 90 | { ARM64_REG_H4, "h4"}, |
| 91 | { ARM64_REG_H5, "h5"}, |
| 92 | { ARM64_REG_H6, "h6"}, |
| 93 | { ARM64_REG_H7, "h7"}, |
| 94 | { ARM64_REG_H8, "h8"}, |
| 95 | { ARM64_REG_H9, "h9"}, |
| 96 | { ARM64_REG_H10, "h10"}, |
| 97 | { ARM64_REG_H11, "h11"}, |
| 98 | { ARM64_REG_H12, "h12"}, |
| 99 | { ARM64_REG_H13, "h13"}, |
| 100 | { ARM64_REG_H14, "h14"}, |
| 101 | { ARM64_REG_H15, "h15"}, |
| 102 | { ARM64_REG_H16, "h16"}, |
| 103 | { ARM64_REG_H17, "h17"}, |
| 104 | { ARM64_REG_H18, "h18"}, |
| 105 | { ARM64_REG_H19, "h19"}, |
| 106 | { ARM64_REG_H20, "h20"}, |
| 107 | { ARM64_REG_H21, "h21"}, |
| 108 | { ARM64_REG_H22, "h22"}, |
| 109 | { ARM64_REG_H23, "h23"}, |
| 110 | { ARM64_REG_H24, "h24"}, |
| 111 | { ARM64_REG_H25, "h25"}, |
| 112 | { ARM64_REG_H26, "h26"}, |
| 113 | { ARM64_REG_H27, "h27"}, |
| 114 | { ARM64_REG_H28, "h28"}, |
| 115 | { ARM64_REG_H29, "h29"}, |
| 116 | { ARM64_REG_H30, "h30"}, |
| 117 | { ARM64_REG_H31, "h31"}, |
| 118 | { ARM64_REG_Q0, "q0"}, |
| 119 | { ARM64_REG_Q1, "q1"}, |
| 120 | { ARM64_REG_Q2, "q2"}, |
| 121 | { ARM64_REG_Q3, "q3"}, |
| 122 | { ARM64_REG_Q4, "q4"}, |
| 123 | { ARM64_REG_Q5, "q5"}, |
| 124 | { ARM64_REG_Q6, "q6"}, |
| 125 | { ARM64_REG_Q7, "q7"}, |
| 126 | { ARM64_REG_Q8, "q8"}, |
| 127 | { ARM64_REG_Q9, "q9"}, |
| 128 | { ARM64_REG_Q10, "q10"}, |
| 129 | { ARM64_REG_Q11, "q11"}, |
| 130 | { ARM64_REG_Q12, "q12"}, |
| 131 | { ARM64_REG_Q13, "q13"}, |
| 132 | { ARM64_REG_Q14, "q14"}, |
| 133 | { ARM64_REG_Q15, "q15"}, |
| 134 | { ARM64_REG_Q16, "q16"}, |
| 135 | { ARM64_REG_Q17, "q17"}, |
| 136 | { ARM64_REG_Q18, "q18"}, |
| 137 | { ARM64_REG_Q19, "q19"}, |
| 138 | { ARM64_REG_Q20, "q20"}, |
| 139 | { ARM64_REG_Q21, "q21"}, |
| 140 | { ARM64_REG_Q22, "q22"}, |
| 141 | { ARM64_REG_Q23, "q23"}, |
| 142 | { ARM64_REG_Q24, "q24"}, |
| 143 | { ARM64_REG_Q25, "q25"}, |
| 144 | { ARM64_REG_Q26, "q26"}, |
| 145 | { ARM64_REG_Q27, "q27"}, |
| 146 | { ARM64_REG_Q28, "q28"}, |
| 147 | { ARM64_REG_Q29, "q29"}, |
| 148 | { ARM64_REG_Q30, "q30"}, |
| 149 | { ARM64_REG_Q31, "q31"}, |
| 150 | { ARM64_REG_S0, "s0"}, |
| 151 | { ARM64_REG_S1, "s1"}, |
| 152 | { ARM64_REG_S2, "s2"}, |
| 153 | { ARM64_REG_S3, "s3"}, |
| 154 | { ARM64_REG_S4, "s4"}, |
| 155 | { ARM64_REG_S5, "s5"}, |
| 156 | { ARM64_REG_S6, "s6"}, |
| 157 | { ARM64_REG_S7, "s7"}, |
| 158 | { ARM64_REG_S8, "s8"}, |
| 159 | { ARM64_REG_S9, "s9"}, |
| 160 | { ARM64_REG_S10, "s10"}, |
| 161 | { ARM64_REG_S11, "s11"}, |
| 162 | { ARM64_REG_S12, "s12"}, |
| 163 | { ARM64_REG_S13, "s13"}, |
| 164 | { ARM64_REG_S14, "s14"}, |
| 165 | { ARM64_REG_S15, "s15"}, |
| 166 | { ARM64_REG_S16, "s16"}, |
| 167 | { ARM64_REG_S17, "s17"}, |
| 168 | { ARM64_REG_S18, "s18"}, |
| 169 | { ARM64_REG_S19, "s19"}, |
| 170 | { ARM64_REG_S20, "s20"}, |
| 171 | { ARM64_REG_S21, "s21"}, |
| 172 | { ARM64_REG_S22, "s22"}, |
| 173 | { ARM64_REG_S23, "s23"}, |
| 174 | { ARM64_REG_S24, "s24"}, |
| 175 | { ARM64_REG_S25, "s25"}, |
| 176 | { ARM64_REG_S26, "s26"}, |
| 177 | { ARM64_REG_S27, "s27"}, |
| 178 | { ARM64_REG_S28, "s28"}, |
| 179 | { ARM64_REG_S29, "s29"}, |
| 180 | { ARM64_REG_S30, "s30"}, |
| 181 | { ARM64_REG_S31, "s31"}, |
| 182 | { ARM64_REG_W0, "w0"}, |
| 183 | { ARM64_REG_W1, "w1"}, |
| 184 | { ARM64_REG_W2, "w2"}, |
| 185 | { ARM64_REG_W3, "w3"}, |
| 186 | { ARM64_REG_W4, "w4"}, |
| 187 | { ARM64_REG_W5, "w5"}, |
| 188 | { ARM64_REG_W6, "w6"}, |
| 189 | { ARM64_REG_W7, "w7"}, |
| 190 | { ARM64_REG_W8, "w8"}, |
| 191 | { ARM64_REG_W9, "w9"}, |
| 192 | { ARM64_REG_W10, "w10"}, |
| 193 | { ARM64_REG_W11, "w11"}, |
| 194 | { ARM64_REG_W12, "w12"}, |
| 195 | { ARM64_REG_W13, "w13"}, |
| 196 | { ARM64_REG_W14, "w14"}, |
| 197 | { ARM64_REG_W15, "w15"}, |
| 198 | { ARM64_REG_W16, "w16"}, |
| 199 | { ARM64_REG_W17, "w17"}, |
| 200 | { ARM64_REG_W18, "w18"}, |
| 201 | { ARM64_REG_W19, "w19"}, |
| 202 | { ARM64_REG_W20, "w20"}, |
| 203 | { ARM64_REG_W21, "w21"}, |
| 204 | { ARM64_REG_W22, "w22"}, |
| 205 | { ARM64_REG_W23, "w23"}, |
| 206 | { ARM64_REG_W24, "w24"}, |
| 207 | { ARM64_REG_W25, "w25"}, |
| 208 | { ARM64_REG_W26, "w26"}, |
| 209 | { ARM64_REG_W27, "w27"}, |
| 210 | { ARM64_REG_W28, "w28"}, |
| 211 | { ARM64_REG_W29, "w29"}, |
| 212 | { ARM64_REG_W30, "w30"}, |
| 213 | { ARM64_REG_X0, "x0"}, |
| 214 | { ARM64_REG_X1, "x1"}, |
| 215 | { ARM64_REG_X2, "x2"}, |
| 216 | { ARM64_REG_X3, "x3"}, |
| 217 | { ARM64_REG_X4, "x4"}, |
| 218 | { ARM64_REG_X5, "x5"}, |
| 219 | { ARM64_REG_X6, "x6"}, |
| 220 | { ARM64_REG_X7, "x7"}, |
| 221 | { ARM64_REG_X8, "x8"}, |
| 222 | { ARM64_REG_X9, "x9"}, |
| 223 | { ARM64_REG_X10, "x10"}, |
| 224 | { ARM64_REG_X11, "x11"}, |
| 225 | { ARM64_REG_X12, "x12"}, |
| 226 | { ARM64_REG_X13, "x13"}, |
| 227 | { ARM64_REG_X14, "x14"}, |
| 228 | { ARM64_REG_X15, "x15"}, |
| 229 | { ARM64_REG_X16, "x16"}, |
| 230 | { ARM64_REG_X17, "x17"}, |
| 231 | { ARM64_REG_X18, "x18"}, |
| 232 | { ARM64_REG_X19, "x19"}, |
| 233 | { ARM64_REG_X20, "x20"}, |
| 234 | { ARM64_REG_X21, "x21"}, |
| 235 | { ARM64_REG_X22, "x22"}, |
| 236 | { ARM64_REG_X23, "x23"}, |
| 237 | { ARM64_REG_X24, "x24"}, |
| 238 | { ARM64_REG_X25, "x25"}, |
| 239 | { ARM64_REG_X26, "x26"}, |
| 240 | { ARM64_REG_X27, "x27"}, |
| 241 | { ARM64_REG_X28, "x28"}, |
| 242 | { ARM64_REG_X29, "x29"}, |
| 243 | { ARM64_REG_X30, "x30"}, |
| 244 | }; |
| 245 | |
| 246 | char *AArch64_reg_name(unsigned int reg) |
| 247 | { |
| 248 | if (reg >= ARM64_REG_MAX) |
| 249 | return NULL; |
| 250 | |
| 251 | return reg_name_maps[reg].name; |
| 252 | } |
| 253 | |
| 254 | static insn_map insns[] = { |
| 255 | { AArch64_ADCSwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 256 | { AArch64_ADCSxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 257 | { AArch64_ADCwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 258 | { AArch64_ADCxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 259 | { AArch64_ADDHN2vvv_16b8h, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 260 | { AArch64_ADDHN2vvv_4s2d, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 261 | { AArch64_ADDHN2vvv_8h4s, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 262 | { AArch64_ADDHNvvv_2s2d, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 263 | { AArch64_ADDHNvvv_4h4s, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 264 | { AArch64_ADDHNvvv_8b8h, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 265 | { AArch64_ADDP_16B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 266 | { AArch64_ADDP_2D, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 267 | { AArch64_ADDP_2S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 268 | { AArch64_ADDP_4H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 269 | { AArch64_ADDP_4S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 270 | { AArch64_ADDP_8B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 271 | { AArch64_ADDP_8H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 272 | { AArch64_ADDSwww_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 273 | { AArch64_ADDSwww_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 274 | { AArch64_ADDSwww_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 275 | { AArch64_ADDSwww_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 276 | { AArch64_ADDSwww_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 277 | { AArch64_ADDSwww_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 278 | { AArch64_ADDSwww_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 279 | { AArch64_ADDSwww_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 280 | { AArch64_ADDSwww_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 281 | { AArch64_ADDSwww_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 282 | { AArch64_ADDSwww_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 283 | { AArch64_ADDSxxw_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 284 | { AArch64_ADDSxxw_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 285 | { AArch64_ADDSxxw_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 286 | { AArch64_ADDSxxw_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 287 | { AArch64_ADDSxxw_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 288 | { AArch64_ADDSxxw_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 289 | { AArch64_ADDSxxx_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 290 | { AArch64_ADDSxxx_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 291 | { AArch64_ADDSxxx_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 292 | { AArch64_ADDSxxx_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 293 | { AArch64_ADDSxxx_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 294 | { AArch64_ADDddd, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 295 | { AArch64_ADDvvv_16B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 296 | { AArch64_ADDvvv_2D, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 297 | { AArch64_ADDvvv_2S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 298 | { AArch64_ADDvvv_4H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 299 | { AArch64_ADDvvv_4S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 300 | { AArch64_ADDvvv_8B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 301 | { AArch64_ADDvvv_8H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 302 | { AArch64_ADDwwi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 303 | { AArch64_ADDwwi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 304 | { AArch64_ADDwwi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 305 | { AArch64_ADDwwi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 306 | { AArch64_ADDwwi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 307 | { AArch64_ADDwwi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 308 | { AArch64_ADDwww_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 309 | { AArch64_ADDwww_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 310 | { AArch64_ADDwww_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 311 | { AArch64_ADDwww_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 312 | { AArch64_ADDwww_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 313 | { AArch64_ADDwww_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 314 | { AArch64_ADDwww_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 315 | { AArch64_ADDwww_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 316 | { AArch64_ADDwww_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 317 | { AArch64_ADDwww_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 318 | { AArch64_ADDwww_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 319 | { AArch64_ADDxxi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 320 | { AArch64_ADDxxi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 321 | { AArch64_ADDxxi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 322 | { AArch64_ADDxxi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 323 | { AArch64_ADDxxi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 324 | { AArch64_ADDxxi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 325 | { AArch64_ADDxxw_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 326 | { AArch64_ADDxxw_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 327 | { AArch64_ADDxxw_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 328 | { AArch64_ADDxxw_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 329 | { AArch64_ADDxxw_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 330 | { AArch64_ADDxxw_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 331 | { AArch64_ADDxxx_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 332 | { AArch64_ADDxxx_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 333 | { AArch64_ADDxxx_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 334 | { AArch64_ADDxxx_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 335 | { AArch64_ADDxxx_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } }, |
| 336 | { AArch64_ADRPxi, ARM64_INS_ADRP, { 0 }, { 0 }, { 0 } }, |
| 337 | { AArch64_ADRxi, ARM64_INS_ADR, { 0 }, { 0 }, { 0 } }, |
| 338 | { AArch64_ANDSwwi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 339 | { AArch64_ANDSwww_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 340 | { AArch64_ANDSwww_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 341 | { AArch64_ANDSwww_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 342 | { AArch64_ANDSwww_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 343 | { AArch64_ANDSxxi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 344 | { AArch64_ANDSxxx_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 345 | { AArch64_ANDSxxx_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 346 | { AArch64_ANDSxxx_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 347 | { AArch64_ANDSxxx_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 348 | { AArch64_ANDvvv_16B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 349 | { AArch64_ANDvvv_8B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 350 | { AArch64_ANDwwi, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 351 | { AArch64_ANDwww_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 352 | { AArch64_ANDwww_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 353 | { AArch64_ANDwww_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 354 | { AArch64_ANDwww_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 355 | { AArch64_ANDxxi, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 356 | { AArch64_ANDxxx_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 357 | { AArch64_ANDxxx_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 358 | { AArch64_ANDxxx_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 359 | { AArch64_ANDxxx_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 } }, |
| 360 | { AArch64_ASRVwww, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } }, |
| 361 | { AArch64_ASRVxxx, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } }, |
| 362 | { AArch64_ASRwwi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } }, |
| 363 | { AArch64_ASRxxi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } }, |
| 364 | { AArch64_ATix, ARM64_INS_AT, { 0 }, { 0 }, { 0 } }, |
| 365 | { AArch64_BFIwwii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 } }, |
| 366 | { AArch64_BFIxxii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 } }, |
| 367 | { AArch64_BFMwwii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 } }, |
| 368 | { AArch64_BFMxxii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 } }, |
| 369 | { AArch64_BFXILwwii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 } }, |
| 370 | { AArch64_BFXILxxii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 } }, |
| 371 | { AArch64_BICSwww_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 372 | { AArch64_BICSwww_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 373 | { AArch64_BICSwww_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 374 | { AArch64_BICSwww_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 375 | { AArch64_BICSxxx_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 376 | { AArch64_BICSxxx_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 377 | { AArch64_BICSxxx_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 378 | { AArch64_BICSxxx_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 379 | { AArch64_BICvi_lsl_2S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 380 | { AArch64_BICvi_lsl_4H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 381 | { AArch64_BICvi_lsl_4S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 382 | { AArch64_BICvi_lsl_8H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 383 | { AArch64_BICvvv_16B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 384 | { AArch64_BICvvv_8B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 385 | { AArch64_BICwww_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } }, |
| 386 | { AArch64_BICwww_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } }, |
| 387 | { AArch64_BICwww_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } }, |
| 388 | { AArch64_BICwww_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } }, |
| 389 | { AArch64_BICxxx_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } }, |
| 390 | { AArch64_BICxxx_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } }, |
| 391 | { AArch64_BICxxx_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } }, |
| 392 | { AArch64_BICxxx_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } }, |
| 393 | { AArch64_BIFvvv_16B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 394 | { AArch64_BIFvvv_8B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 395 | { AArch64_BITvvv_16B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 396 | { AArch64_BITvvv_8B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 397 | { AArch64_BLRx, ARM64_INS_BLR, { 0 }, { ARM64_REG_X30, 0 }, { 0 } }, |
| 398 | { AArch64_BLimm, ARM64_INS_BL, { 0 }, { ARM64_REG_X30, 0 }, { 0 } }, |
| 399 | { AArch64_BRKi, ARM64_INS_BRK, { 0 }, { 0 }, { 0 } }, |
| 400 | { AArch64_BRx, ARM64_INS_BR, { 0 }, { 0 }, { 0 } }, |
| 401 | { AArch64_BSLvvv_16B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 402 | { AArch64_BSLvvv_8B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 403 | { AArch64_Bcc, ARM64_INS_B, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 404 | { AArch64_Bimm, ARM64_INS_B, { 0 }, { 0 }, { 0 } }, |
| 405 | { AArch64_CBNZw, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 } }, |
| 406 | { AArch64_CBNZx, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 } }, |
| 407 | { AArch64_CBZw, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 } }, |
| 408 | { AArch64_CBZx, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 } }, |
| 409 | { AArch64_CCMNwi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 410 | { AArch64_CCMNww, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 411 | { AArch64_CCMNxi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 412 | { AArch64_CCMNxx, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 413 | { AArch64_CCMPwi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 414 | { AArch64_CCMPww, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 415 | { AArch64_CCMPxi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 416 | { AArch64_CCMPxx, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 417 | { AArch64_CLREXi, ARM64_INS_CLREX, { 0 }, { 0 }, { 0 } }, |
| 418 | { AArch64_CLSww, ARM64_INS_CLS, { 0 }, { 0 }, { 0 } }, |
| 419 | { AArch64_CLSxx, ARM64_INS_CLS, { 0 }, { 0 }, { 0 } }, |
| 420 | { AArch64_CLZww, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 } }, |
| 421 | { AArch64_CLZxx, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 } }, |
| 422 | { AArch64_CMEQvvi_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 423 | { AArch64_CMEQvvi_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 424 | { AArch64_CMEQvvi_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 425 | { AArch64_CMEQvvi_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 426 | { AArch64_CMEQvvi_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 427 | { AArch64_CMEQvvi_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 428 | { AArch64_CMEQvvi_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 429 | { AArch64_CMEQvvv_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 430 | { AArch64_CMEQvvv_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 431 | { AArch64_CMEQvvv_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 432 | { AArch64_CMEQvvv_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 433 | { AArch64_CMEQvvv_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 434 | { AArch64_CMEQvvv_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 435 | { AArch64_CMEQvvv_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 436 | { AArch64_CMGEvvi_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 437 | { AArch64_CMGEvvi_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 438 | { AArch64_CMGEvvi_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 439 | { AArch64_CMGEvvi_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 440 | { AArch64_CMGEvvi_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 441 | { AArch64_CMGEvvi_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 442 | { AArch64_CMGEvvi_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 443 | { AArch64_CMGEvvv_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 444 | { AArch64_CMGEvvv_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 445 | { AArch64_CMGEvvv_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 446 | { AArch64_CMGEvvv_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 447 | { AArch64_CMGEvvv_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 448 | { AArch64_CMGEvvv_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 449 | { AArch64_CMGEvvv_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 450 | { AArch64_CMGTvvi_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 451 | { AArch64_CMGTvvi_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 452 | { AArch64_CMGTvvi_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 453 | { AArch64_CMGTvvi_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 454 | { AArch64_CMGTvvi_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 455 | { AArch64_CMGTvvi_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 456 | { AArch64_CMGTvvi_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 457 | { AArch64_CMGTvvv_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 458 | { AArch64_CMGTvvv_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 459 | { AArch64_CMGTvvv_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 460 | { AArch64_CMGTvvv_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 461 | { AArch64_CMGTvvv_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 462 | { AArch64_CMGTvvv_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 463 | { AArch64_CMGTvvv_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 464 | { AArch64_CMHIvvv_16B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 465 | { AArch64_CMHIvvv_2D, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 466 | { AArch64_CMHIvvv_2S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 467 | { AArch64_CMHIvvv_4H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 468 | { AArch64_CMHIvvv_4S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 469 | { AArch64_CMHIvvv_8B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 470 | { AArch64_CMHIvvv_8H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 471 | { AArch64_CMHSvvv_16B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 472 | { AArch64_CMHSvvv_2D, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 473 | { AArch64_CMHSvvv_2S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 474 | { AArch64_CMHSvvv_4H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 475 | { AArch64_CMHSvvv_4S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 476 | { AArch64_CMHSvvv_8B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 477 | { AArch64_CMHSvvv_8H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 478 | { AArch64_CMLEvvi_16B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 479 | { AArch64_CMLEvvi_2D, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 480 | { AArch64_CMLEvvi_2S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 481 | { AArch64_CMLEvvi_4H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 482 | { AArch64_CMLEvvi_4S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 483 | { AArch64_CMLEvvi_8B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 484 | { AArch64_CMLEvvi_8H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 485 | { AArch64_CMLTvvi_16B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 486 | { AArch64_CMLTvvi_2D, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 487 | { AArch64_CMLTvvi_2S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 488 | { AArch64_CMLTvvi_4H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 489 | { AArch64_CMLTvvi_4S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 490 | { AArch64_CMLTvvi_8B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 491 | { AArch64_CMLTvvi_8H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 492 | { AArch64_CMNww_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 493 | { AArch64_CMNww_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 494 | { AArch64_CMNww_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 495 | { AArch64_CMNww_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 496 | { AArch64_CMNww_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 497 | { AArch64_CMNww_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 498 | { AArch64_CMNww_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 499 | { AArch64_CMNww_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 500 | { AArch64_CMNww_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 501 | { AArch64_CMNww_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 502 | { AArch64_CMNww_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 503 | { AArch64_CMNxw_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 504 | { AArch64_CMNxw_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 505 | { AArch64_CMNxw_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 506 | { AArch64_CMNxw_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 507 | { AArch64_CMNxw_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 508 | { AArch64_CMNxw_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 509 | { AArch64_CMNxx_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 510 | { AArch64_CMNxx_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 511 | { AArch64_CMNxx_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 512 | { AArch64_CMNxx_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 513 | { AArch64_CMNxx_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 514 | { AArch64_CMPww_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 515 | { AArch64_CMPww_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 516 | { AArch64_CMPww_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 517 | { AArch64_CMPww_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 518 | { AArch64_CMPww_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 519 | { AArch64_CMPww_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 520 | { AArch64_CMPww_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 521 | { AArch64_CMPww_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 522 | { AArch64_CMPww_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 523 | { AArch64_CMPww_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 524 | { AArch64_CMPww_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 525 | { AArch64_CMPxw_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 526 | { AArch64_CMPxw_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 527 | { AArch64_CMPxw_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 528 | { AArch64_CMPxw_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 529 | { AArch64_CMPxw_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 530 | { AArch64_CMPxw_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 531 | { AArch64_CMPxx_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 532 | { AArch64_CMPxx_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 533 | { AArch64_CMPxx_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 534 | { AArch64_CMPxx_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 535 | { AArch64_CMPxx_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 536 | { AArch64_CMTSTvvv_16B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 537 | { AArch64_CMTSTvvv_2D, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 538 | { AArch64_CMTSTvvv_2S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 539 | { AArch64_CMTSTvvv_4H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 540 | { AArch64_CMTSTvvv_4S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 541 | { AArch64_CMTSTvvv_8B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 542 | { AArch64_CMTSTvvv_8H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 543 | { AArch64_CRC32B_www, ARM64_INS_CRC32B, { 0 }, { 0 }, { 0 } }, |
| 544 | { AArch64_CRC32CB_www, ARM64_INS_CRC32CB, { 0 }, { 0 }, { 0 } }, |
| 545 | { AArch64_CRC32CH_www, ARM64_INS_CRC32CH, { 0 }, { 0 }, { 0 } }, |
| 546 | { AArch64_CRC32CW_www, ARM64_INS_CRC32CW, { 0 }, { 0 }, { 0 } }, |
| 547 | { AArch64_CRC32CX_wwx, ARM64_INS_CRC32CX, { 0 }, { 0 }, { 0 } }, |
| 548 | { AArch64_CRC32H_www, ARM64_INS_CRC32H, { 0 }, { 0 }, { 0 } }, |
| 549 | { AArch64_CRC32W_www, ARM64_INS_CRC32W, { 0 }, { 0 }, { 0 } }, |
| 550 | { AArch64_CRC32X_wwx, ARM64_INS_CRC32X, { 0 }, { 0 }, { 0 } }, |
| 551 | { AArch64_CSELwwwc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 552 | { AArch64_CSELxxxc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 553 | { AArch64_CSINCwwwc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 554 | { AArch64_CSINCxxxc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 555 | { AArch64_CSINVwwwc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 556 | { AArch64_CSINVxxxc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 557 | { AArch64_CSNEGwwwc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 558 | { AArch64_CSNEGxxxc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 559 | { AArch64_DCPS1i, ARM64_INS_DCPS1, { 0 }, { 0 }, { 0 } }, |
| 560 | { AArch64_DCPS2i, ARM64_INS_DCPS2, { 0 }, { 0 }, { 0 } }, |
| 561 | { AArch64_DCPS3i, ARM64_INS_DCPS3, { 0 }, { 0 }, { 0 } }, |
| 562 | { AArch64_DCix, ARM64_INS_DC, { 0 }, { 0 }, { 0 } }, |
| 563 | { AArch64_DMBi, ARM64_INS_DMB, { 0 }, { 0 }, { 0 } }, |
| 564 | { AArch64_DRPS, ARM64_INS_DRPS, { 0 }, { 0 }, { 0 } }, |
| 565 | { AArch64_DSBi, ARM64_INS_DSB, { 0 }, { 0 }, { 0 } }, |
| 566 | { AArch64_EONwww_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } }, |
| 567 | { AArch64_EONwww_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 } }, |
| 568 | { AArch64_EONwww_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } }, |
| 569 | { AArch64_EONwww_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 } }, |
| 570 | { AArch64_EONxxx_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } }, |
| 571 | { AArch64_EONxxx_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 } }, |
| 572 | { AArch64_EONxxx_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } }, |
| 573 | { AArch64_EONxxx_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 } }, |
| 574 | { AArch64_EORvvv_16B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 575 | { AArch64_EORvvv_8B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 576 | { AArch64_EORwwi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 577 | { AArch64_EORwww_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 578 | { AArch64_EORwww_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 579 | { AArch64_EORwww_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 580 | { AArch64_EORwww_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 581 | { AArch64_EORxxi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 582 | { AArch64_EORxxx_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 583 | { AArch64_EORxxx_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 584 | { AArch64_EORxxx_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 585 | { AArch64_EORxxx_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } }, |
| 586 | { AArch64_ERET, ARM64_INS_ERET, { 0 }, { 0 }, { 0 } }, |
| 587 | { AArch64_EXTRwwwi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 } }, |
| 588 | { AArch64_EXTRxxxi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 } }, |
| 589 | { AArch64_FABDvvv_2D, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 590 | { AArch64_FABDvvv_2S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 591 | { AArch64_FABDvvv_4S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 592 | { AArch64_FABSdd, ARM64_INS_FABS, { 0 }, { 0 }, { 0 } }, |
| 593 | { AArch64_FABSss, ARM64_INS_FABS, { 0 }, { 0 }, { 0 } }, |
| 594 | { AArch64_FACGEvvv_2D, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 595 | { AArch64_FACGEvvv_2S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 596 | { AArch64_FACGEvvv_4S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 597 | { AArch64_FACGTvvv_2D, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 598 | { AArch64_FACGTvvv_2S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 599 | { AArch64_FACGTvvv_4S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 600 | { AArch64_FADDP_2D, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 601 | { AArch64_FADDP_2S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 602 | { AArch64_FADDP_4S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 603 | { AArch64_FADDddd, ARM64_INS_FADD, { 0 }, { 0 }, { 0 } }, |
| 604 | { AArch64_FADDsss, ARM64_INS_FADD, { 0 }, { 0 }, { 0 } }, |
| 605 | { AArch64_FADDvvv_2D, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 606 | { AArch64_FADDvvv_2S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 607 | { AArch64_FADDvvv_4S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 608 | { AArch64_FCCMPEdd, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 609 | { AArch64_FCCMPEss, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 610 | { AArch64_FCCMPdd, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 611 | { AArch64_FCCMPss, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 612 | { AArch64_FCMEQvvi_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 613 | { AArch64_FCMEQvvi_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 614 | { AArch64_FCMEQvvi_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 615 | { AArch64_FCMEQvvv_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 616 | { AArch64_FCMEQvvv_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 617 | { AArch64_FCMEQvvv_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 618 | { AArch64_FCMGEvvi_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 619 | { AArch64_FCMGEvvi_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 620 | { AArch64_FCMGEvvi_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 621 | { AArch64_FCMGEvvv_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 622 | { AArch64_FCMGEvvv_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 623 | { AArch64_FCMGEvvv_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 624 | { AArch64_FCMGTvvi_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 625 | { AArch64_FCMGTvvi_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 626 | { AArch64_FCMGTvvi_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 627 | { AArch64_FCMGTvvv_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 628 | { AArch64_FCMGTvvv_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 629 | { AArch64_FCMGTvvv_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 630 | { AArch64_FCMLEvvi_2D, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 631 | { AArch64_FCMLEvvi_2S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 632 | { AArch64_FCMLEvvi_4S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 633 | { AArch64_FCMLTvvi_2D, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 634 | { AArch64_FCMLTvvi_2S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 635 | { AArch64_FCMLTvvi_4S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 636 | { AArch64_FCMPdd_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 637 | { AArch64_FCMPdd_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 638 | { AArch64_FCMPdi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 639 | { AArch64_FCMPdi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 640 | { AArch64_FCMPsi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 641 | { AArch64_FCMPsi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 642 | { AArch64_FCMPss_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 643 | { AArch64_FCMPss_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 644 | { AArch64_FCSELdddc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 645 | { AArch64_FCSELsssc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 646 | { AArch64_FCVTASwd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } }, |
| 647 | { AArch64_FCVTASws, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } }, |
| 648 | { AArch64_FCVTASxd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } }, |
| 649 | { AArch64_FCVTASxs, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } }, |
| 650 | { AArch64_FCVTAUwd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } }, |
| 651 | { AArch64_FCVTAUws, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } }, |
| 652 | { AArch64_FCVTAUxd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } }, |
| 653 | { AArch64_FCVTAUxs, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } }, |
| 654 | { AArch64_FCVTMSwd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } }, |
| 655 | { AArch64_FCVTMSws, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } }, |
| 656 | { AArch64_FCVTMSxd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } }, |
| 657 | { AArch64_FCVTMSxs, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } }, |
| 658 | { AArch64_FCVTMUwd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } }, |
| 659 | { AArch64_FCVTMUws, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } }, |
| 660 | { AArch64_FCVTMUxd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } }, |
| 661 | { AArch64_FCVTMUxs, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } }, |
| 662 | { AArch64_FCVTNSwd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } }, |
| 663 | { AArch64_FCVTNSws, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } }, |
| 664 | { AArch64_FCVTNSxd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } }, |
| 665 | { AArch64_FCVTNSxs, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } }, |
| 666 | { AArch64_FCVTNUwd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } }, |
| 667 | { AArch64_FCVTNUws, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } }, |
| 668 | { AArch64_FCVTNUxd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } }, |
| 669 | { AArch64_FCVTNUxs, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } }, |
| 670 | { AArch64_FCVTPSwd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } }, |
| 671 | { AArch64_FCVTPSws, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } }, |
| 672 | { AArch64_FCVTPSxd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } }, |
| 673 | { AArch64_FCVTPSxs, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } }, |
| 674 | { AArch64_FCVTPUwd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } }, |
| 675 | { AArch64_FCVTPUws, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } }, |
| 676 | { AArch64_FCVTPUxd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } }, |
| 677 | { AArch64_FCVTPUxs, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } }, |
| 678 | { AArch64_FCVTZSwd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } }, |
| 679 | { AArch64_FCVTZSwdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } }, |
| 680 | { AArch64_FCVTZSws, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } }, |
| 681 | { AArch64_FCVTZSwsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } }, |
| 682 | { AArch64_FCVTZSxd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } }, |
| 683 | { AArch64_FCVTZSxdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } }, |
| 684 | { AArch64_FCVTZSxs, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } }, |
| 685 | { AArch64_FCVTZSxsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } }, |
| 686 | { AArch64_FCVTZUwd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } }, |
| 687 | { AArch64_FCVTZUwdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } }, |
| 688 | { AArch64_FCVTZUws, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } }, |
| 689 | { AArch64_FCVTZUwsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } }, |
| 690 | { AArch64_FCVTZUxd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } }, |
| 691 | { AArch64_FCVTZUxdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } }, |
| 692 | { AArch64_FCVTZUxs, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } }, |
| 693 | { AArch64_FCVTZUxsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } }, |
| 694 | { AArch64_FCVTdh, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } }, |
| 695 | { AArch64_FCVTds, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } }, |
| 696 | { AArch64_FCVThd, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } }, |
| 697 | { AArch64_FCVThs, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } }, |
| 698 | { AArch64_FCVTsd, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } }, |
| 699 | { AArch64_FCVTsh, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } }, |
| 700 | { AArch64_FDIVddd, ARM64_INS_FDIV, { 0 }, { 0 }, { 0 } }, |
| 701 | { AArch64_FDIVsss, ARM64_INS_FDIV, { 0 }, { 0 }, { 0 } }, |
| 702 | { AArch64_FDIVvvv_2D, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 703 | { AArch64_FDIVvvv_2S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 704 | { AArch64_FDIVvvv_4S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 705 | { AArch64_FMADDdddd, ARM64_INS_FMADD, { 0 }, { 0 }, { 0 } }, |
| 706 | { AArch64_FMADDssss, ARM64_INS_FMADD, { 0 }, { 0 }, { 0 } }, |
| 707 | { AArch64_FMAXNMPvvv_2D, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 708 | { AArch64_FMAXNMPvvv_2S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 709 | { AArch64_FMAXNMPvvv_4S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 710 | { AArch64_FMAXNMddd, ARM64_INS_FMAXNM, { 0 }, { 0 }, { 0 } }, |
| 711 | { AArch64_FMAXNMsss, ARM64_INS_FMAXNM, { 0 }, { 0 }, { 0 } }, |
| 712 | { AArch64_FMAXNMvvv_2D, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 713 | { AArch64_FMAXNMvvv_2S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 714 | { AArch64_FMAXNMvvv_4S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 715 | { AArch64_FMAXPvvv_2D, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 716 | { AArch64_FMAXPvvv_2S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 717 | { AArch64_FMAXPvvv_4S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 718 | { AArch64_FMAXddd, ARM64_INS_FMAX, { 0 }, { 0 }, { 0 } }, |
| 719 | { AArch64_FMAXsss, ARM64_INS_FMAX, { 0 }, { 0 }, { 0 } }, |
| 720 | { AArch64_FMAXvvv_2D, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 721 | { AArch64_FMAXvvv_2S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 722 | { AArch64_FMAXvvv_4S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 723 | { AArch64_FMINNMPvvv_2D, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 724 | { AArch64_FMINNMPvvv_2S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 725 | { AArch64_FMINNMPvvv_4S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 726 | { AArch64_FMINNMddd, ARM64_INS_FMINNM, { 0 }, { 0 }, { 0 } }, |
| 727 | { AArch64_FMINNMsss, ARM64_INS_FMINNM, { 0 }, { 0 }, { 0 } }, |
| 728 | { AArch64_FMINNMvvv_2D, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 729 | { AArch64_FMINNMvvv_2S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 730 | { AArch64_FMINNMvvv_4S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 731 | { AArch64_FMINPvvv_2D, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 732 | { AArch64_FMINPvvv_2S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 733 | { AArch64_FMINPvvv_4S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 734 | { AArch64_FMINddd, ARM64_INS_FMIN, { 0 }, { 0 }, { 0 } }, |
| 735 | { AArch64_FMINsss, ARM64_INS_FMIN, { 0 }, { 0 }, { 0 } }, |
| 736 | { AArch64_FMINvvv_2D, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 737 | { AArch64_FMINvvv_2S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 738 | { AArch64_FMINvvv_4S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 739 | { AArch64_FMLAvvv_2D, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 740 | { AArch64_FMLAvvv_2S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 741 | { AArch64_FMLAvvv_4S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 742 | { AArch64_FMLSvvv_2D, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 743 | { AArch64_FMLSvvv_2S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 744 | { AArch64_FMLSvvv_4S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 745 | { AArch64_FMOVdd, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 746 | { AArch64_FMOVdi, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 747 | { AArch64_FMOVdx, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 748 | { AArch64_FMOVsi, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 749 | { AArch64_FMOVss, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 750 | { AArch64_FMOVsw, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 751 | { AArch64_FMOVvi_2D, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 752 | { AArch64_FMOVvi_2S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 753 | { AArch64_FMOVvi_4S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 754 | { AArch64_FMOVvx, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 755 | { AArch64_FMOVws, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 756 | { AArch64_FMOVxd, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 757 | { AArch64_FMOVxv, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } }, |
| 758 | { AArch64_FMSUBdddd, ARM64_INS_FMSUB, { 0 }, { 0 }, { 0 } }, |
| 759 | { AArch64_FMSUBssss, ARM64_INS_FMSUB, { 0 }, { 0 }, { 0 } }, |
| 760 | { AArch64_FMULXvvv_2D, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 761 | { AArch64_FMULXvvv_2S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 762 | { AArch64_FMULXvvv_4S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 763 | { AArch64_FMULddd, ARM64_INS_FMUL, { 0 }, { 0 }, { 0 } }, |
| 764 | { AArch64_FMULsss, ARM64_INS_FMUL, { 0 }, { 0 }, { 0 } }, |
| 765 | { AArch64_FMULvvv_2D, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 766 | { AArch64_FMULvvv_2S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 767 | { AArch64_FMULvvv_4S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 768 | { AArch64_FNEGdd, ARM64_INS_FNEG, { 0 }, { 0 }, { 0 } }, |
| 769 | { AArch64_FNEGss, ARM64_INS_FNEG, { 0 }, { 0 }, { 0 } }, |
| 770 | { AArch64_FNMADDdddd, ARM64_INS_FNMADD, { 0 }, { 0 }, { 0 } }, |
| 771 | { AArch64_FNMADDssss, ARM64_INS_FNMADD, { 0 }, { 0 }, { 0 } }, |
| 772 | { AArch64_FNMSUBdddd, ARM64_INS_FNMSUB, { 0 }, { 0 }, { 0 } }, |
| 773 | { AArch64_FNMSUBssss, ARM64_INS_FNMSUB, { 0 }, { 0 }, { 0 } }, |
| 774 | { AArch64_FNMULddd, ARM64_INS_FNMUL, { 0 }, { 0 }, { 0 } }, |
| 775 | { AArch64_FNMULsss, ARM64_INS_FNMUL, { 0 }, { 0 }, { 0 } }, |
| 776 | { AArch64_FRECPSvvv_2D, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 777 | { AArch64_FRECPSvvv_2S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 778 | { AArch64_FRECPSvvv_4S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 779 | { AArch64_FRINTAdd, ARM64_INS_FRINTA, { 0 }, { 0 }, { 0 } }, |
| 780 | { AArch64_FRINTAss, ARM64_INS_FRINTA, { 0 }, { 0 }, { 0 } }, |
| 781 | { AArch64_FRINTIdd, ARM64_INS_FRINTI, { 0 }, { 0 }, { 0 } }, |
| 782 | { AArch64_FRINTIss, ARM64_INS_FRINTI, { 0 }, { 0 }, { 0 } }, |
| 783 | { AArch64_FRINTMdd, ARM64_INS_FRINTM, { 0 }, { 0 }, { 0 } }, |
| 784 | { AArch64_FRINTMss, ARM64_INS_FRINTM, { 0 }, { 0 }, { 0 } }, |
| 785 | { AArch64_FRINTNdd, ARM64_INS_FRINTN, { 0 }, { 0 }, { 0 } }, |
| 786 | { AArch64_FRINTNss, ARM64_INS_FRINTN, { 0 }, { 0 }, { 0 } }, |
| 787 | { AArch64_FRINTPdd, ARM64_INS_FRINTP, { 0 }, { 0 }, { 0 } }, |
| 788 | { AArch64_FRINTPss, ARM64_INS_FRINTP, { 0 }, { 0 }, { 0 } }, |
| 789 | { AArch64_FRINTXdd, ARM64_INS_FRINTX, { 0 }, { 0 }, { 0 } }, |
| 790 | { AArch64_FRINTXss, ARM64_INS_FRINTX, { 0 }, { 0 }, { 0 } }, |
| 791 | { AArch64_FRINTZdd, ARM64_INS_FRINTZ, { 0 }, { 0 }, { 0 } }, |
| 792 | { AArch64_FRINTZss, ARM64_INS_FRINTZ, { 0 }, { 0 }, { 0 } }, |
| 793 | { AArch64_FRSQRTSvvv_2D, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 794 | { AArch64_FRSQRTSvvv_2S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 795 | { AArch64_FRSQRTSvvv_4S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 796 | { AArch64_FSQRTdd, ARM64_INS_FSQRT, { 0 }, { 0 }, { 0 } }, |
| 797 | { AArch64_FSQRTss, ARM64_INS_FSQRT, { 0 }, { 0 }, { 0 } }, |
| 798 | { AArch64_FSUBddd, ARM64_INS_FSUB, { 0 }, { 0 }, { 0 } }, |
| 799 | { AArch64_FSUBsss, ARM64_INS_FSUB, { 0 }, { 0 }, { 0 } }, |
| 800 | { AArch64_FSUBvvv_2D, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 801 | { AArch64_FSUBvvv_2S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 802 | { AArch64_FSUBvvv_4S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 803 | { AArch64_HINTi, ARM64_INS_HINT, { 0 }, { 0 }, { 0 } }, |
| 804 | { AArch64_HLTi, ARM64_INS_HLT, { 0 }, { 0 }, { 0 } }, |
| 805 | { AArch64_HVCi, ARM64_INS_HVC, { 0 }, { 0 }, { 0 } }, |
| 806 | { AArch64_ICi, ARM64_INS_IC, { 0 }, { 0 }, { 0 } }, |
| 807 | { AArch64_ICix, ARM64_INS_IC, { 0 }, { 0 }, { 0 } }, |
| 808 | { AArch64_INSELb, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 809 | { AArch64_INSELd, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 810 | { AArch64_INSELh, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 811 | { AArch64_INSELs, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 812 | { AArch64_INSbw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 813 | { AArch64_INSdx, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 814 | { AArch64_INShw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 815 | { AArch64_INSsw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 816 | { AArch64_ISBi, ARM64_INS_ISB, { 0 }, { 0 }, { 0 } }, |
| 817 | { AArch64_LDAR_byte, ARM64_INS_LDARB, { 0 }, { 0 }, { 0 } }, |
| 818 | { AArch64_LDAR_dword, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 } }, |
| 819 | { AArch64_LDAR_hword, ARM64_INS_LDARH, { 0 }, { 0 }, { 0 } }, |
| 820 | { AArch64_LDAR_word, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 } }, |
| 821 | { AArch64_LDAXP_dword, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 } }, |
| 822 | { AArch64_LDAXP_word, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 } }, |
| 823 | { AArch64_LDAXR_byte, ARM64_INS_LDAXRB, { 0 }, { 0 }, { 0 } }, |
| 824 | { AArch64_LDAXR_dword, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 } }, |
| 825 | { AArch64_LDAXR_hword, ARM64_INS_LDAXRH, { 0 }, { 0 }, { 0 } }, |
| 826 | { AArch64_LDAXR_word, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 } }, |
| 827 | { AArch64_LDPSWx, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } }, |
| 828 | { AArch64_LDPSWx_PostInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } }, |
| 829 | { AArch64_LDPSWx_PreInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } }, |
| 830 | { AArch64_LDRSBw, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 831 | { AArch64_LDRSBw_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 832 | { AArch64_LDRSBw_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 833 | { AArch64_LDRSBw_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 } }, |
| 834 | { AArch64_LDRSBw_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 835 | { AArch64_LDRSBw_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 836 | { AArch64_LDRSBx, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 837 | { AArch64_LDRSBx_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 838 | { AArch64_LDRSBx_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 839 | { AArch64_LDRSBx_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 } }, |
| 840 | { AArch64_LDRSBx_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 841 | { AArch64_LDRSBx_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } }, |
| 842 | { AArch64_LDRSHw, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 843 | { AArch64_LDRSHw_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 844 | { AArch64_LDRSHw_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 845 | { AArch64_LDRSHw_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 } }, |
| 846 | { AArch64_LDRSHw_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 847 | { AArch64_LDRSHw_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 848 | { AArch64_LDRSHx, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 849 | { AArch64_LDRSHx_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 850 | { AArch64_LDRSHx_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 851 | { AArch64_LDRSHx_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 } }, |
| 852 | { AArch64_LDRSHx_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 853 | { AArch64_LDRSHx_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } }, |
| 854 | { AArch64_LDRSWx, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } }, |
| 855 | { AArch64_LDRSWx_PostInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } }, |
| 856 | { AArch64_LDRSWx_PreInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } }, |
| 857 | { AArch64_LDRSWx_Wm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } }, |
| 858 | { AArch64_LDRSWx_Xm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } }, |
| 859 | { AArch64_LDRSWx_lit, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } }, |
| 860 | { AArch64_LDRd_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 861 | { AArch64_LDRq_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 862 | { AArch64_LDRs_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 863 | { AArch64_LDRw_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 864 | { AArch64_LDRx_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 865 | { AArch64_LDTRSBw, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 } }, |
| 866 | { AArch64_LDTRSBx, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 } }, |
| 867 | { AArch64_LDTRSHw, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 } }, |
| 868 | { AArch64_LDTRSHx, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 } }, |
| 869 | { AArch64_LDTRSWx, ARM64_INS_LDTRSW, { 0 }, { 0 }, { 0 } }, |
| 870 | { AArch64_LDURSWx, ARM64_INS_LDURSW, { 0 }, { 0 }, { 0 } }, |
| 871 | { AArch64_LDXP_dword, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 } }, |
| 872 | { AArch64_LDXP_word, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 } }, |
| 873 | { AArch64_LDXR_byte, ARM64_INS_LDXRB, { 0 }, { 0 }, { 0 } }, |
| 874 | { AArch64_LDXR_dword, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 } }, |
| 875 | { AArch64_LDXR_hword, ARM64_INS_LDXRH, { 0 }, { 0 }, { 0 } }, |
| 876 | { AArch64_LDXR_word, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 } }, |
| 877 | { AArch64_LS16_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } }, |
| 878 | { AArch64_LS16_LDUR, ARM64_INS_LDURH, { 0 }, { 0 }, { 0 } }, |
| 879 | { AArch64_LS16_PostInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } }, |
| 880 | { AArch64_LS16_PostInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } }, |
| 881 | { AArch64_LS16_PreInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } }, |
| 882 | { AArch64_LS16_PreInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } }, |
| 883 | { AArch64_LS16_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } }, |
| 884 | { AArch64_LS16_STUR, ARM64_INS_STURH, { 0 }, { 0 }, { 0 } }, |
| 885 | { AArch64_LS16_UnPriv_LDR, ARM64_INS_LDTRH, { 0 }, { 0 }, { 0 } }, |
| 886 | { AArch64_LS16_UnPriv_STR, ARM64_INS_STTRH, { 0 }, { 0 }, { 0 } }, |
| 887 | { AArch64_LS16_Wm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } }, |
| 888 | { AArch64_LS16_Wm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } }, |
| 889 | { AArch64_LS16_Xm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } }, |
| 890 | { AArch64_LS16_Xm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } }, |
| 891 | { AArch64_LS32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 892 | { AArch64_LS32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } }, |
| 893 | { AArch64_LS32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 894 | { AArch64_LS32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 895 | { AArch64_LS32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 896 | { AArch64_LS32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 897 | { AArch64_LS32_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 898 | { AArch64_LS32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } }, |
| 899 | { AArch64_LS32_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 } }, |
| 900 | { AArch64_LS32_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 } }, |
| 901 | { AArch64_LS32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 902 | { AArch64_LS32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 903 | { AArch64_LS32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 904 | { AArch64_LS32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 905 | { AArch64_LS64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 906 | { AArch64_LS64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } }, |
| 907 | { AArch64_LS64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 908 | { AArch64_LS64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 909 | { AArch64_LS64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 910 | { AArch64_LS64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 911 | { AArch64_LS64_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 912 | { AArch64_LS64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } }, |
| 913 | { AArch64_LS64_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 } }, |
| 914 | { AArch64_LS64_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 } }, |
| 915 | { AArch64_LS64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 916 | { AArch64_LS64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 917 | { AArch64_LS64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 918 | { AArch64_LS64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 919 | { AArch64_LS8_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } }, |
| 920 | { AArch64_LS8_LDUR, ARM64_INS_LDURB, { 0 }, { 0 }, { 0 } }, |
| 921 | { AArch64_LS8_PostInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } }, |
| 922 | { AArch64_LS8_PostInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } }, |
| 923 | { AArch64_LS8_PreInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } }, |
| 924 | { AArch64_LS8_PreInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } }, |
| 925 | { AArch64_LS8_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } }, |
| 926 | { AArch64_LS8_STUR, ARM64_INS_STURB, { 0 }, { 0 }, { 0 } }, |
| 927 | { AArch64_LS8_UnPriv_LDR, ARM64_INS_LDTRB, { 0 }, { 0 }, { 0 } }, |
| 928 | { AArch64_LS8_UnPriv_STR, ARM64_INS_STTRB, { 0 }, { 0 }, { 0 } }, |
| 929 | { AArch64_LS8_Wm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } }, |
| 930 | { AArch64_LS8_Wm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } }, |
| 931 | { AArch64_LS8_Xm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } }, |
| 932 | { AArch64_LS8_Xm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } }, |
| 933 | { AArch64_LSFP128_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 934 | { AArch64_LSFP128_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } }, |
| 935 | { AArch64_LSFP128_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 936 | { AArch64_LSFP128_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 937 | { AArch64_LSFP128_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 938 | { AArch64_LSFP128_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 939 | { AArch64_LSFP128_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 940 | { AArch64_LSFP128_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } }, |
| 941 | { AArch64_LSFP128_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 942 | { AArch64_LSFP128_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 943 | { AArch64_LSFP128_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 944 | { AArch64_LSFP128_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 945 | { AArch64_LSFP16_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 946 | { AArch64_LSFP16_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } }, |
| 947 | { AArch64_LSFP16_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 948 | { AArch64_LSFP16_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 949 | { AArch64_LSFP16_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 950 | { AArch64_LSFP16_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 951 | { AArch64_LSFP16_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 952 | { AArch64_LSFP16_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } }, |
| 953 | { AArch64_LSFP16_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 954 | { AArch64_LSFP16_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 955 | { AArch64_LSFP16_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 956 | { AArch64_LSFP16_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 957 | { AArch64_LSFP32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 958 | { AArch64_LSFP32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } }, |
| 959 | { AArch64_LSFP32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 960 | { AArch64_LSFP32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 961 | { AArch64_LSFP32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 962 | { AArch64_LSFP32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 963 | { AArch64_LSFP32_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 964 | { AArch64_LSFP32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } }, |
| 965 | { AArch64_LSFP32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 966 | { AArch64_LSFP32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 967 | { AArch64_LSFP32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 968 | { AArch64_LSFP32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 969 | { AArch64_LSFP64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 970 | { AArch64_LSFP64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } }, |
| 971 | { AArch64_LSFP64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 972 | { AArch64_LSFP64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 973 | { AArch64_LSFP64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 974 | { AArch64_LSFP64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 975 | { AArch64_LSFP64_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 976 | { AArch64_LSFP64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } }, |
| 977 | { AArch64_LSFP64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 978 | { AArch64_LSFP64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 979 | { AArch64_LSFP64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 980 | { AArch64_LSFP64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 981 | { AArch64_LSFP8_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 982 | { AArch64_LSFP8_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } }, |
| 983 | { AArch64_LSFP8_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 984 | { AArch64_LSFP8_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 985 | { AArch64_LSFP8_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 986 | { AArch64_LSFP8_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 987 | { AArch64_LSFP8_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 988 | { AArch64_LSFP8_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } }, |
| 989 | { AArch64_LSFP8_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 990 | { AArch64_LSFP8_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 991 | { AArch64_LSFP8_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } }, |
| 992 | { AArch64_LSFP8_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } }, |
| 993 | { AArch64_LSFPPair128_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 994 | { AArch64_LSFPPair128_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } }, |
| 995 | { AArch64_LSFPPair128_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } }, |
| 996 | { AArch64_LSFPPair128_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 997 | { AArch64_LSFPPair128_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 998 | { AArch64_LSFPPair128_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 999 | { AArch64_LSFPPair128_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1000 | { AArch64_LSFPPair128_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1001 | { AArch64_LSFPPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1002 | { AArch64_LSFPPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } }, |
| 1003 | { AArch64_LSFPPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } }, |
| 1004 | { AArch64_LSFPPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1005 | { AArch64_LSFPPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1006 | { AArch64_LSFPPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1007 | { AArch64_LSFPPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1008 | { AArch64_LSFPPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1009 | { AArch64_LSFPPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1010 | { AArch64_LSFPPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } }, |
| 1011 | { AArch64_LSFPPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } }, |
| 1012 | { AArch64_LSFPPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1013 | { AArch64_LSFPPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1014 | { AArch64_LSFPPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1015 | { AArch64_LSFPPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1016 | { AArch64_LSFPPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1017 | { AArch64_LSLVwww, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } }, |
| 1018 | { AArch64_LSLVxxx, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } }, |
| 1019 | { AArch64_LSLwwi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } }, |
| 1020 | { AArch64_LSLxxi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } }, |
| 1021 | { AArch64_LSPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1022 | { AArch64_LSPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } }, |
| 1023 | { AArch64_LSPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } }, |
| 1024 | { AArch64_LSPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1025 | { AArch64_LSPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1026 | { AArch64_LSPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1027 | { AArch64_LSPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1028 | { AArch64_LSPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1029 | { AArch64_LSPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1030 | { AArch64_LSPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } }, |
| 1031 | { AArch64_LSPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } }, |
| 1032 | { AArch64_LSPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1033 | { AArch64_LSPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1034 | { AArch64_LSPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } }, |
| 1035 | { AArch64_LSPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1036 | { AArch64_LSPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } }, |
| 1037 | { AArch64_LSRVwww, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } }, |
| 1038 | { AArch64_LSRVxxx, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } }, |
| 1039 | { AArch64_LSRwwi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } }, |
| 1040 | { AArch64_LSRxxi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } }, |
| 1041 | { AArch64_MADDwwww, ARM64_INS_MADD, { 0 }, { 0 }, { 0 } }, |
| 1042 | { AArch64_MADDxxxx, ARM64_INS_MADD, { 0 }, { 0 }, { 0 } }, |
| 1043 | { AArch64_MLAvvv_16B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1044 | { AArch64_MLAvvv_2S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1045 | { AArch64_MLAvvv_4H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1046 | { AArch64_MLAvvv_4S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1047 | { AArch64_MLAvvv_8B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1048 | { AArch64_MLAvvv_8H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1049 | { AArch64_MLSvvv_16B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1050 | { AArch64_MLSvvv_2S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1051 | { AArch64_MLSvvv_4H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1052 | { AArch64_MLSvvv_4S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1053 | { AArch64_MLSvvv_8B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1054 | { AArch64_MLSvvv_8H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1055 | { AArch64_MOVIdi, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1056 | { AArch64_MOVIvi_16B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1057 | { AArch64_MOVIvi_2D, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1058 | { AArch64_MOVIvi_8B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1059 | { AArch64_MOVIvi_lsl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1060 | { AArch64_MOVIvi_lsl_4H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1061 | { AArch64_MOVIvi_lsl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1062 | { AArch64_MOVIvi_lsl_8H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1063 | { AArch64_MOVIvi_msl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1064 | { AArch64_MOVIvi_msl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1065 | { AArch64_MOVKwii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 } }, |
| 1066 | { AArch64_MOVKxii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 } }, |
| 1067 | { AArch64_MOVNwii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 } }, |
| 1068 | { AArch64_MOVNxii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 } }, |
| 1069 | { AArch64_MOVZwii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 } }, |
| 1070 | { AArch64_MOVZxii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 } }, |
| 1071 | { AArch64_MRSxi, ARM64_INS_MRS, { 0 }, { 0 }, { 0 } }, |
| 1072 | { AArch64_MSRii, ARM64_INS_MSR, { 0 }, { 0 }, { 0 } }, |
| 1073 | { AArch64_MSRix, ARM64_INS_MSR, { 0 }, { 0 }, { 0 } }, |
| 1074 | { AArch64_MSUBwwww, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 } }, |
| 1075 | { AArch64_MSUBxxxx, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 } }, |
| 1076 | { AArch64_MULvvv_16B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1077 | { AArch64_MULvvv_2S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1078 | { AArch64_MULvvv_4H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1079 | { AArch64_MULvvv_4S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1080 | { AArch64_MULvvv_8B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1081 | { AArch64_MULvvv_8H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1082 | { AArch64_MVNIvi_lsl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1083 | { AArch64_MVNIvi_lsl_4H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1084 | { AArch64_MVNIvi_lsl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1085 | { AArch64_MVNIvi_lsl_8H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1086 | { AArch64_MVNIvi_msl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1087 | { AArch64_MVNIvi_msl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1088 | { AArch64_MVNww_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } }, |
| 1089 | { AArch64_MVNww_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } }, |
| 1090 | { AArch64_MVNww_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } }, |
| 1091 | { AArch64_MVNww_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } }, |
| 1092 | { AArch64_MVNxx_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } }, |
| 1093 | { AArch64_MVNxx_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } }, |
| 1094 | { AArch64_MVNxx_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } }, |
| 1095 | { AArch64_MVNxx_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } }, |
| 1096 | { AArch64_ORNvvv_16B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1097 | { AArch64_ORNvvv_8B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1098 | { AArch64_ORNwww_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } }, |
| 1099 | { AArch64_ORNwww_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } }, |
| 1100 | { AArch64_ORNwww_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } }, |
| 1101 | { AArch64_ORNwww_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } }, |
| 1102 | { AArch64_ORNxxx_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } }, |
| 1103 | { AArch64_ORNxxx_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } }, |
| 1104 | { AArch64_ORNxxx_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } }, |
| 1105 | { AArch64_ORNxxx_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } }, |
| 1106 | { AArch64_ORRvi_lsl_2S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1107 | { AArch64_ORRvi_lsl_4H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1108 | { AArch64_ORRvi_lsl_4S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1109 | { AArch64_ORRvi_lsl_8H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1110 | { AArch64_ORRvvv_16B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1111 | { AArch64_ORRvvv_8B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1112 | { AArch64_ORRwwi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1113 | { AArch64_ORRwww_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1114 | { AArch64_ORRwww_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1115 | { AArch64_ORRwww_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1116 | { AArch64_ORRwww_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1117 | { AArch64_ORRxxi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1118 | { AArch64_ORRxxx_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1119 | { AArch64_ORRxxx_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1120 | { AArch64_ORRxxx_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1121 | { AArch64_ORRxxx_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } }, |
| 1122 | { AArch64_PMULL2vvv_8h16b, ARM64_INS_PMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1123 | { AArch64_PMULLvvv_8h8b, ARM64_INS_PMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1124 | { AArch64_PMULvvv_16B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1125 | { AArch64_PMULvvv_8B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1126 | { AArch64_PRFM, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } }, |
| 1127 | { AArch64_PRFM_Wm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } }, |
| 1128 | { AArch64_PRFM_Xm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } }, |
| 1129 | { AArch64_PRFM_lit, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } }, |
| 1130 | { AArch64_PRFUM, ARM64_INS_PRFUM, { 0 }, { 0 }, { 0 } }, |
| 1131 | { AArch64_QRSHRUNvvi_16B, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1132 | { AArch64_QRSHRUNvvi_2S, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1133 | { AArch64_QRSHRUNvvi_4H, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1134 | { AArch64_QRSHRUNvvi_4S, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1135 | { AArch64_QRSHRUNvvi_8B, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1136 | { AArch64_QRSHRUNvvi_8H, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1137 | { AArch64_QSHRUNvvi_16B, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1138 | { AArch64_QSHRUNvvi_2S, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1139 | { AArch64_QSHRUNvvi_4H, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1140 | { AArch64_QSHRUNvvi_4S, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1141 | { AArch64_QSHRUNvvi_8B, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1142 | { AArch64_QSHRUNvvi_8H, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1143 | { AArch64_RADDHN2vvv_16b8h, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1144 | { AArch64_RADDHN2vvv_4s2d, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1145 | { AArch64_RADDHN2vvv_8h4s, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1146 | { AArch64_RADDHNvvv_2s2d, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1147 | { AArch64_RADDHNvvv_4h4s, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1148 | { AArch64_RADDHNvvv_8b8h, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1149 | { AArch64_RBITww, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 } }, |
| 1150 | { AArch64_RBITxx, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 } }, |
| 1151 | { AArch64_RETx, ARM64_INS_RET, { 0 }, { 0 }, { 0 } }, |
| 1152 | { AArch64_REV16ww, ARM64_INS_REV16, { 0 }, { 0 }, { 0 } }, |
| 1153 | { AArch64_REV16xx, ARM64_INS_REV16, { 0 }, { 0 }, { 0 } }, |
| 1154 | { AArch64_REV32xx, ARM64_INS_REV32, { 0 }, { 0 }, { 0 } }, |
| 1155 | { AArch64_REVww, ARM64_INS_REV, { 0 }, { 0 }, { 0 } }, |
| 1156 | { AArch64_REVxx, ARM64_INS_REV, { 0 }, { 0 }, { 0 } }, |
| 1157 | { AArch64_RORVwww, ARM64_INS_ROR, { 0 }, { 0 }, { 0 } }, |
| 1158 | { AArch64_RORVxxx, ARM64_INS_ROR, { 0 }, { 0 }, { 0 } }, |
| 1159 | { AArch64_RSHRNvvi_16B, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1160 | { AArch64_RSHRNvvi_2S, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1161 | { AArch64_RSHRNvvi_4H, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1162 | { AArch64_RSHRNvvi_4S, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1163 | { AArch64_RSHRNvvi_8B, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1164 | { AArch64_RSHRNvvi_8H, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1165 | { AArch64_RSUBHN2vvv_16b8h, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1166 | { AArch64_RSUBHN2vvv_4s2d, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1167 | { AArch64_RSUBHN2vvv_8h4s, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1168 | { AArch64_RSUBHNvvv_2s2d, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1169 | { AArch64_RSUBHNvvv_4h4s, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1170 | { AArch64_RSUBHNvvv_8b8h, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1171 | { AArch64_SABAL2vvv_2d2s, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1172 | { AArch64_SABAL2vvv_4s4h, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1173 | { AArch64_SABAL2vvv_8h8b, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1174 | { AArch64_SABALvvv_2d2s, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1175 | { AArch64_SABALvvv_4s4h, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1176 | { AArch64_SABALvvv_8h8b, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1177 | { AArch64_SABAvvv_16B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1178 | { AArch64_SABAvvv_2S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1179 | { AArch64_SABAvvv_4H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1180 | { AArch64_SABAvvv_4S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1181 | { AArch64_SABAvvv_8B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1182 | { AArch64_SABAvvv_8H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1183 | { AArch64_SABDL2vvv_2d2s, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1184 | { AArch64_SABDL2vvv_4s4h, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1185 | { AArch64_SABDL2vvv_8h8b, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1186 | { AArch64_SABDLvvv_2d2s, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1187 | { AArch64_SABDLvvv_4s4h, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1188 | { AArch64_SABDLvvv_8h8b, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1189 | { AArch64_SABDvvv_16B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1190 | { AArch64_SABDvvv_2S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1191 | { AArch64_SABDvvv_4H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1192 | { AArch64_SABDvvv_4S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1193 | { AArch64_SABDvvv_8B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1194 | { AArch64_SABDvvv_8H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1195 | { AArch64_SADDL2vvv_2d4s, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1196 | { AArch64_SADDL2vvv_4s8h, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1197 | { AArch64_SADDL2vvv_8h16b, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1198 | { AArch64_SADDLvvv_2d2s, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1199 | { AArch64_SADDLvvv_4s4h, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1200 | { AArch64_SADDLvvv_8h8b, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1201 | { AArch64_SADDW2vvv_2d4s, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1202 | { AArch64_SADDW2vvv_4s8h, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1203 | { AArch64_SADDW2vvv_8h16b, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1204 | { AArch64_SADDWvvv_2d2s, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1205 | { AArch64_SADDWvvv_4s4h, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1206 | { AArch64_SADDWvvv_8h8b, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1207 | { AArch64_SBCSwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1208 | { AArch64_SBCSxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1209 | { AArch64_SBCwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 1210 | { AArch64_SBCxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 1211 | { AArch64_SBFIZwwii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 } }, |
| 1212 | { AArch64_SBFIZxxii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 } }, |
| 1213 | { AArch64_SBFMwwii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 } }, |
| 1214 | { AArch64_SBFMxxii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 } }, |
| 1215 | { AArch64_SBFXwwii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 } }, |
| 1216 | { AArch64_SBFXxxii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 } }, |
| 1217 | { AArch64_SCVTFdw, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } }, |
| 1218 | { AArch64_SCVTFdwi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } }, |
| 1219 | { AArch64_SCVTFdx, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } }, |
| 1220 | { AArch64_SCVTFdxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } }, |
| 1221 | { AArch64_SCVTFsw, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } }, |
| 1222 | { AArch64_SCVTFswi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } }, |
| 1223 | { AArch64_SCVTFsx, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } }, |
| 1224 | { AArch64_SCVTFsxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } }, |
| 1225 | { AArch64_SDIVwww, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 } }, |
| 1226 | { AArch64_SDIVxxx, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 } }, |
| 1227 | { AArch64_SHADDvvv_16B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1228 | { AArch64_SHADDvvv_2S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1229 | { AArch64_SHADDvvv_4H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1230 | { AArch64_SHADDvvv_4S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1231 | { AArch64_SHADDvvv_8B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1232 | { AArch64_SHADDvvv_8H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1233 | { AArch64_SHLvvi_16B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1234 | { AArch64_SHLvvi_2D, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1235 | { AArch64_SHLvvi_2S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1236 | { AArch64_SHLvvi_4H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1237 | { AArch64_SHLvvi_4S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1238 | { AArch64_SHLvvi_8B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1239 | { AArch64_SHLvvi_8H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1240 | { AArch64_SHRNvvi_16B, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1241 | { AArch64_SHRNvvi_2S, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1242 | { AArch64_SHRNvvi_4H, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1243 | { AArch64_SHRNvvi_4S, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1244 | { AArch64_SHRNvvi_8B, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1245 | { AArch64_SHRNvvi_8H, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1246 | { AArch64_SHSUBvvv_16B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1247 | { AArch64_SHSUBvvv_2S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1248 | { AArch64_SHSUBvvv_4H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1249 | { AArch64_SHSUBvvv_4S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1250 | { AArch64_SHSUBvvv_8B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1251 | { AArch64_SHSUBvvv_8H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1252 | { AArch64_SLIvvi_16B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1253 | { AArch64_SLIvvi_2D, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1254 | { AArch64_SLIvvi_2S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1255 | { AArch64_SLIvvi_4H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1256 | { AArch64_SLIvvi_4S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1257 | { AArch64_SLIvvi_8B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1258 | { AArch64_SLIvvi_8H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1259 | { AArch64_SMADDLxwwx, ARM64_INS_SMADDL, { 0 }, { 0 }, { 0 } }, |
| 1260 | { AArch64_SMAXPvvv_16B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1261 | { AArch64_SMAXPvvv_2S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1262 | { AArch64_SMAXPvvv_4H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1263 | { AArch64_SMAXPvvv_4S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1264 | { AArch64_SMAXPvvv_8B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1265 | { AArch64_SMAXPvvv_8H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1266 | { AArch64_SMAXvvv_16B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1267 | { AArch64_SMAXvvv_2S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1268 | { AArch64_SMAXvvv_4H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1269 | { AArch64_SMAXvvv_4S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1270 | { AArch64_SMAXvvv_8B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1271 | { AArch64_SMAXvvv_8H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1272 | { AArch64_SMCi, ARM64_INS_SMC, { 0 }, { 0 }, { 0 } }, |
| 1273 | { AArch64_SMINPvvv_16B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1274 | { AArch64_SMINPvvv_2S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1275 | { AArch64_SMINPvvv_4H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1276 | { AArch64_SMINPvvv_4S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1277 | { AArch64_SMINPvvv_8B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1278 | { AArch64_SMINPvvv_8H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1279 | { AArch64_SMINvvv_16B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1280 | { AArch64_SMINvvv_2S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1281 | { AArch64_SMINvvv_4H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1282 | { AArch64_SMINvvv_4S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1283 | { AArch64_SMINvvv_8B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1284 | { AArch64_SMINvvv_8H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1285 | { AArch64_SMLAL2vvv_2d4s, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1286 | { AArch64_SMLAL2vvv_4s8h, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1287 | { AArch64_SMLAL2vvv_8h16b, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1288 | { AArch64_SMLALvvv_2d2s, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1289 | { AArch64_SMLALvvv_4s4h, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1290 | { AArch64_SMLALvvv_8h8b, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1291 | { AArch64_SMLSL2vvv_2d4s, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1292 | { AArch64_SMLSL2vvv_4s8h, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1293 | { AArch64_SMLSL2vvv_8h16b, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1294 | { AArch64_SMLSLvvv_2d2s, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1295 | { AArch64_SMLSLvvv_4s4h, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1296 | { AArch64_SMLSLvvv_8h8b, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1297 | { AArch64_SMOVwb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1298 | { AArch64_SMOVwh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1299 | { AArch64_SMOVxb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1300 | { AArch64_SMOVxh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1301 | { AArch64_SMOVxs, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1302 | { AArch64_SMSUBLxwwx, ARM64_INS_SMSUBL, { 0 }, { 0 }, { 0 } }, |
| 1303 | { AArch64_SMULHxxx, ARM64_INS_SMULH, { 0 }, { 0 }, { 0 } }, |
| 1304 | { AArch64_SMULL2vvv_2d4s, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1305 | { AArch64_SMULL2vvv_4s8h, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1306 | { AArch64_SMULL2vvv_8h16b, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1307 | { AArch64_SMULLvvv_2d2s, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1308 | { AArch64_SMULLvvv_4s4h, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1309 | { AArch64_SMULLvvv_8h8b, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1310 | { AArch64_SQADDbbb, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1311 | { AArch64_SQADDddd, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1312 | { AArch64_SQADDhhh, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1313 | { AArch64_SQADDsss, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1314 | { AArch64_SQADDvvv_16B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1315 | { AArch64_SQADDvvv_2D, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1316 | { AArch64_SQADDvvv_2S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1317 | { AArch64_SQADDvvv_4H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1318 | { AArch64_SQADDvvv_4S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1319 | { AArch64_SQADDvvv_8B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1320 | { AArch64_SQADDvvv_8H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1321 | { AArch64_SQDMLAL2vvv_2d4s, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1322 | { AArch64_SQDMLAL2vvv_4s8h, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1323 | { AArch64_SQDMLALvvv_2d2s, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1324 | { AArch64_SQDMLALvvv_4s4h, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1325 | { AArch64_SQDMLSL2vvv_2d4s, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1326 | { AArch64_SQDMLSL2vvv_4s8h, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1327 | { AArch64_SQDMLSLvvv_2d2s, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1328 | { AArch64_SQDMLSLvvv_4s4h, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1329 | { AArch64_SQDMULHvvv_2S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1330 | { AArch64_SQDMULHvvv_4H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1331 | { AArch64_SQDMULHvvv_4S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1332 | { AArch64_SQDMULHvvv_8H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1333 | { AArch64_SQDMULL2vvv_2d4s, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1334 | { AArch64_SQDMULL2vvv_4s8h, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1335 | { AArch64_SQDMULLvvv_2d2s, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1336 | { AArch64_SQDMULLvvv_4s4h, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1337 | { AArch64_SQRDMULHvvv_2S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1338 | { AArch64_SQRDMULHvvv_4H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1339 | { AArch64_SQRDMULHvvv_4S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1340 | { AArch64_SQRDMULHvvv_8H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1341 | { AArch64_SQRSHLbbb, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1342 | { AArch64_SQRSHLddd, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1343 | { AArch64_SQRSHLhhh, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1344 | { AArch64_SQRSHLsss, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1345 | { AArch64_SQRSHLvvv_16B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1346 | { AArch64_SQRSHLvvv_2D, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1347 | { AArch64_SQRSHLvvv_2S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1348 | { AArch64_SQRSHLvvv_4H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1349 | { AArch64_SQRSHLvvv_4S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1350 | { AArch64_SQRSHLvvv_8B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1351 | { AArch64_SQRSHLvvv_8H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1352 | { AArch64_SQRSHRNvvi_16B, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1353 | { AArch64_SQRSHRNvvi_2S, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1354 | { AArch64_SQRSHRNvvi_4H, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1355 | { AArch64_SQRSHRNvvi_4S, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1356 | { AArch64_SQRSHRNvvi_8B, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1357 | { AArch64_SQRSHRNvvi_8H, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1358 | { AArch64_SQSHLUvvi_16B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1359 | { AArch64_SQSHLUvvi_2D, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1360 | { AArch64_SQSHLUvvi_2S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1361 | { AArch64_SQSHLUvvi_4H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1362 | { AArch64_SQSHLUvvi_4S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1363 | { AArch64_SQSHLUvvi_8B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1364 | { AArch64_SQSHLUvvi_8H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1365 | { AArch64_SQSHLbbb, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1366 | { AArch64_SQSHLddd, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1367 | { AArch64_SQSHLhhh, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1368 | { AArch64_SQSHLsss, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1369 | { AArch64_SQSHLvvi_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1370 | { AArch64_SQSHLvvi_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1371 | { AArch64_SQSHLvvi_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1372 | { AArch64_SQSHLvvi_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1373 | { AArch64_SQSHLvvi_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1374 | { AArch64_SQSHLvvi_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1375 | { AArch64_SQSHLvvi_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1376 | { AArch64_SQSHLvvv_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1377 | { AArch64_SQSHLvvv_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1378 | { AArch64_SQSHLvvv_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1379 | { AArch64_SQSHLvvv_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1380 | { AArch64_SQSHLvvv_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1381 | { AArch64_SQSHLvvv_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1382 | { AArch64_SQSHLvvv_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1383 | { AArch64_SQSHRNvvi_16B, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1384 | { AArch64_SQSHRNvvi_2S, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1385 | { AArch64_SQSHRNvvi_4H, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1386 | { AArch64_SQSHRNvvi_4S, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1387 | { AArch64_SQSHRNvvi_8B, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1388 | { AArch64_SQSHRNvvi_8H, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1389 | { AArch64_SQSUBbbb, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1390 | { AArch64_SQSUBddd, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1391 | { AArch64_SQSUBhhh, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1392 | { AArch64_SQSUBsss, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1393 | { AArch64_SQSUBvvv_16B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1394 | { AArch64_SQSUBvvv_2D, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1395 | { AArch64_SQSUBvvv_2S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1396 | { AArch64_SQSUBvvv_4H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1397 | { AArch64_SQSUBvvv_4S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1398 | { AArch64_SQSUBvvv_8B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1399 | { AArch64_SQSUBvvv_8H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1400 | { AArch64_SRHADDvvv_16B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1401 | { AArch64_SRHADDvvv_2S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1402 | { AArch64_SRHADDvvv_4H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1403 | { AArch64_SRHADDvvv_4S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1404 | { AArch64_SRHADDvvv_8B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1405 | { AArch64_SRHADDvvv_8H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1406 | { AArch64_SRIvvi_16B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1407 | { AArch64_SRIvvi_2D, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1408 | { AArch64_SRIvvi_2S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1409 | { AArch64_SRIvvi_4H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1410 | { AArch64_SRIvvi_4S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1411 | { AArch64_SRIvvi_8B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1412 | { AArch64_SRIvvi_8H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1413 | { AArch64_SRSHLddd, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1414 | { AArch64_SRSHLvvv_16B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1415 | { AArch64_SRSHLvvv_2D, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1416 | { AArch64_SRSHLvvv_2S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1417 | { AArch64_SRSHLvvv_4H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1418 | { AArch64_SRSHLvvv_4S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1419 | { AArch64_SRSHLvvv_8B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1420 | { AArch64_SRSHLvvv_8H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1421 | { AArch64_SRSHRvvi_16B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1422 | { AArch64_SRSHRvvi_2D, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1423 | { AArch64_SRSHRvvi_2S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1424 | { AArch64_SRSHRvvi_4H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1425 | { AArch64_SRSHRvvi_4S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1426 | { AArch64_SRSHRvvi_8B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1427 | { AArch64_SRSHRvvi_8H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1428 | { AArch64_SRSRAvvi_16B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1429 | { AArch64_SRSRAvvi_2D, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1430 | { AArch64_SRSRAvvi_2S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1431 | { AArch64_SRSRAvvi_4H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1432 | { AArch64_SRSRAvvi_4S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1433 | { AArch64_SRSRAvvi_8B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1434 | { AArch64_SRSRAvvi_8H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1435 | { AArch64_SSHLLvvi_16B, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1436 | { AArch64_SSHLLvvi_2S, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1437 | { AArch64_SSHLLvvi_4H, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1438 | { AArch64_SSHLLvvi_4S, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1439 | { AArch64_SSHLLvvi_8B, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1440 | { AArch64_SSHLLvvi_8H, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1441 | { AArch64_SSHLddd, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1442 | { AArch64_SSHLvvv_16B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1443 | { AArch64_SSHLvvv_2D, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1444 | { AArch64_SSHLvvv_2S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1445 | { AArch64_SSHLvvv_4H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1446 | { AArch64_SSHLvvv_4S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1447 | { AArch64_SSHLvvv_8B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1448 | { AArch64_SSHLvvv_8H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1449 | { AArch64_SSHRvvi_16B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1450 | { AArch64_SSHRvvi_2D, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1451 | { AArch64_SSHRvvi_2S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1452 | { AArch64_SSHRvvi_4H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1453 | { AArch64_SSHRvvi_4S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1454 | { AArch64_SSHRvvi_8B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1455 | { AArch64_SSHRvvi_8H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1456 | { AArch64_SSRAvvi_16B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1457 | { AArch64_SSRAvvi_2D, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1458 | { AArch64_SSRAvvi_2S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1459 | { AArch64_SSRAvvi_4H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1460 | { AArch64_SSRAvvi_4S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1461 | { AArch64_SSRAvvi_8B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1462 | { AArch64_SSRAvvi_8H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1463 | { AArch64_SSUBL2vvv_2d4s, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1464 | { AArch64_SSUBL2vvv_4s8h, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1465 | { AArch64_SSUBL2vvv_8h16b, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1466 | { AArch64_SSUBLvvv_2d2s, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1467 | { AArch64_SSUBLvvv_4s4h, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1468 | { AArch64_SSUBLvvv_8h8b, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1469 | { AArch64_SSUBW2vvv_2d4s, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1470 | { AArch64_SSUBW2vvv_4s8h, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1471 | { AArch64_SSUBW2vvv_8h16b, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1472 | { AArch64_SSUBWvvv_2d2s, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1473 | { AArch64_SSUBWvvv_4s4h, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1474 | { AArch64_SSUBWvvv_8h8b, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1475 | { AArch64_STLR_byte, ARM64_INS_STLRB, { 0 }, { 0 }, { 0 } }, |
| 1476 | { AArch64_STLR_dword, ARM64_INS_STLR, { 0 }, { 0 }, { 0 } }, |
| 1477 | { AArch64_STLR_hword, ARM64_INS_STLRH, { 0 }, { 0 }, { 0 } }, |
| 1478 | { AArch64_STLR_word, ARM64_INS_STLR, { 0 }, { 0 }, { 0 } }, |
| 1479 | { AArch64_STLXP_dword, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 } }, |
| 1480 | { AArch64_STLXP_word, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 } }, |
| 1481 | { AArch64_STLXR_byte, ARM64_INS_STLXRB, { 0 }, { 0 }, { 0 } }, |
| 1482 | { AArch64_STLXR_dword, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 } }, |
| 1483 | { AArch64_STLXR_hword, ARM64_INS_STLXRH, { 0 }, { 0 }, { 0 } }, |
| 1484 | { AArch64_STLXR_word, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 } }, |
| 1485 | { AArch64_STXP_dword, ARM64_INS_STXP, { 0 }, { 0 }, { 0 } }, |
| 1486 | { AArch64_STXP_word, ARM64_INS_STXP, { 0 }, { 0 }, { 0 } }, |
| 1487 | { AArch64_STXR_byte, ARM64_INS_STXRB, { 0 }, { 0 }, { 0 } }, |
| 1488 | { AArch64_STXR_dword, ARM64_INS_STXR, { 0 }, { 0 }, { 0 } }, |
| 1489 | { AArch64_STXR_hword, ARM64_INS_STXRH, { 0 }, { 0 }, { 0 } }, |
| 1490 | { AArch64_STXR_word, ARM64_INS_STXR, { 0 }, { 0 }, { 0 } }, |
| 1491 | { AArch64_SUBHN2vvv_16b8h, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1492 | { AArch64_SUBHN2vvv_4s2d, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1493 | { AArch64_SUBHN2vvv_8h4s, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1494 | { AArch64_SUBHNvvv_2s2d, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1495 | { AArch64_SUBHNvvv_4h4s, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1496 | { AArch64_SUBHNvvv_8b8h, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1497 | { AArch64_SUBSwww_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1498 | { AArch64_SUBSwww_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1499 | { AArch64_SUBSwww_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1500 | { AArch64_SUBSwww_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1501 | { AArch64_SUBSwww_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1502 | { AArch64_SUBSwww_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1503 | { AArch64_SUBSwww_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1504 | { AArch64_SUBSwww_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1505 | { AArch64_SUBSwww_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1506 | { AArch64_SUBSwww_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1507 | { AArch64_SUBSwww_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1508 | { AArch64_SUBSxxw_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1509 | { AArch64_SUBSxxw_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1510 | { AArch64_SUBSxxw_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1511 | { AArch64_SUBSxxw_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1512 | { AArch64_SUBSxxw_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1513 | { AArch64_SUBSxxw_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1514 | { AArch64_SUBSxxx_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1515 | { AArch64_SUBSxxx_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1516 | { AArch64_SUBSxxx_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1517 | { AArch64_SUBSxxx_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1518 | { AArch64_SUBSxxx_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1519 | { AArch64_SUBddd, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1520 | { AArch64_SUBvvv_16B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1521 | { AArch64_SUBvvv_2D, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1522 | { AArch64_SUBvvv_2S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1523 | { AArch64_SUBvvv_4H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1524 | { AArch64_SUBvvv_4S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1525 | { AArch64_SUBvvv_8B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1526 | { AArch64_SUBvvv_8H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1527 | { AArch64_SUBwwi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1528 | { AArch64_SUBwwi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1529 | { AArch64_SUBwwi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1530 | { AArch64_SUBwwi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1531 | { AArch64_SUBwwi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1532 | { AArch64_SUBwwi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1533 | { AArch64_SUBwww_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1534 | { AArch64_SUBwww_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1535 | { AArch64_SUBwww_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1536 | { AArch64_SUBwww_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1537 | { AArch64_SUBwww_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1538 | { AArch64_SUBwww_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1539 | { AArch64_SUBwww_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1540 | { AArch64_SUBwww_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1541 | { AArch64_SUBwww_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1542 | { AArch64_SUBwww_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1543 | { AArch64_SUBwww_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1544 | { AArch64_SUBxxi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1545 | { AArch64_SUBxxi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1546 | { AArch64_SUBxxi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1547 | { AArch64_SUBxxi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1548 | { AArch64_SUBxxi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1549 | { AArch64_SUBxxi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1550 | { AArch64_SUBxxw_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1551 | { AArch64_SUBxxw_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1552 | { AArch64_SUBxxw_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1553 | { AArch64_SUBxxw_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1554 | { AArch64_SUBxxw_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1555 | { AArch64_SUBxxw_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1556 | { AArch64_SUBxxx_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1557 | { AArch64_SUBxxx_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1558 | { AArch64_SUBxxx_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1559 | { AArch64_SUBxxx_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1560 | { AArch64_SUBxxx_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } }, |
| 1561 | { AArch64_SVCi, ARM64_INS_SVC, { 0 }, { 0 }, { 0 } }, |
| 1562 | { AArch64_SXTBww, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 } }, |
| 1563 | { AArch64_SXTBxw, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 } }, |
| 1564 | { AArch64_SXTHww, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 } }, |
| 1565 | { AArch64_SXTHxw, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 } }, |
| 1566 | { AArch64_SXTWxw, ARM64_INS_SXTW, { 0 }, { 0 }, { 0 } }, |
| 1567 | { AArch64_SYSLxicci, ARM64_INS_SYSL, { 0 }, { 0 }, { 0 } }, |
| 1568 | { AArch64_SYSiccix, ARM64_INS_SYS, { 0 }, { 0 }, { 0 } }, |
| 1569 | { AArch64_TBNZwii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 } }, |
| 1570 | { AArch64_TBNZxii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 } }, |
| 1571 | { AArch64_TBZwii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 } }, |
| 1572 | { AArch64_TBZxii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 } }, |
| 1573 | { AArch64_TLBIi, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 } }, |
| 1574 | { AArch64_TLBIix, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 } }, |
| 1575 | { AArch64_TSTww_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1576 | { AArch64_TSTww_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1577 | { AArch64_TSTww_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1578 | { AArch64_TSTww_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1579 | { AArch64_TSTxx_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1580 | { AArch64_TSTxx_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1581 | { AArch64_TSTxx_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1582 | { AArch64_TSTxx_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1583 | { AArch64_UABAL2vvv_2d2s, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1584 | { AArch64_UABAL2vvv_4s4h, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1585 | { AArch64_UABAL2vvv_8h8b, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1586 | { AArch64_UABALvvv_2d2s, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1587 | { AArch64_UABALvvv_4s4h, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1588 | { AArch64_UABALvvv_8h8b, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1589 | { AArch64_UABAvvv_16B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1590 | { AArch64_UABAvvv_2S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1591 | { AArch64_UABAvvv_4H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1592 | { AArch64_UABAvvv_4S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1593 | { AArch64_UABAvvv_8B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1594 | { AArch64_UABAvvv_8H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1595 | { AArch64_UABDL2vvv_2d2s, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1596 | { AArch64_UABDL2vvv_4s4h, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1597 | { AArch64_UABDL2vvv_8h8b, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1598 | { AArch64_UABDLvvv_2d2s, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1599 | { AArch64_UABDLvvv_4s4h, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1600 | { AArch64_UABDLvvv_8h8b, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1601 | { AArch64_UABDvvv_16B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1602 | { AArch64_UABDvvv_2S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1603 | { AArch64_UABDvvv_4H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1604 | { AArch64_UABDvvv_4S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1605 | { AArch64_UABDvvv_8B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1606 | { AArch64_UABDvvv_8H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1607 | { AArch64_UADDL2vvv_2d4s, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1608 | { AArch64_UADDL2vvv_4s8h, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1609 | { AArch64_UADDL2vvv_8h16b, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1610 | { AArch64_UADDLvvv_2d2s, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1611 | { AArch64_UADDLvvv_4s4h, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1612 | { AArch64_UADDLvvv_8h8b, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1613 | { AArch64_UADDW2vvv_2d4s, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1614 | { AArch64_UADDW2vvv_4s8h, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1615 | { AArch64_UADDW2vvv_8h16b, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1616 | { AArch64_UADDWvvv_2d2s, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1617 | { AArch64_UADDWvvv_4s4h, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1618 | { AArch64_UADDWvvv_8h8b, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1619 | { AArch64_UBFIZwwii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 } }, |
| 1620 | { AArch64_UBFIZxxii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 } }, |
| 1621 | { AArch64_UBFMwwii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 } }, |
| 1622 | { AArch64_UBFMxxii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 } }, |
| 1623 | { AArch64_UBFXwwii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 } }, |
| 1624 | { AArch64_UBFXxxii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 } }, |
| 1625 | { AArch64_UCVTFdw, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } }, |
| 1626 | { AArch64_UCVTFdwi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } }, |
| 1627 | { AArch64_UCVTFdx, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } }, |
| 1628 | { AArch64_UCVTFdxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } }, |
| 1629 | { AArch64_UCVTFsw, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } }, |
| 1630 | { AArch64_UCVTFswi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } }, |
| 1631 | { AArch64_UCVTFsx, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } }, |
| 1632 | { AArch64_UCVTFsxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } }, |
| 1633 | { AArch64_UDIVwww, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 } }, |
| 1634 | { AArch64_UDIVxxx, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 } }, |
| 1635 | { AArch64_UHADDvvv_16B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1636 | { AArch64_UHADDvvv_2S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1637 | { AArch64_UHADDvvv_4H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1638 | { AArch64_UHADDvvv_4S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1639 | { AArch64_UHADDvvv_8B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1640 | { AArch64_UHADDvvv_8H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1641 | { AArch64_UHSUBvvv_16B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1642 | { AArch64_UHSUBvvv_2S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1643 | { AArch64_UHSUBvvv_4H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1644 | { AArch64_UHSUBvvv_4S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1645 | { AArch64_UHSUBvvv_8B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1646 | { AArch64_UHSUBvvv_8H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1647 | { AArch64_UMADDLxwwx, ARM64_INS_UMADDL, { 0 }, { 0 }, { 0 } }, |
| 1648 | { AArch64_UMAXPvvv_16B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1649 | { AArch64_UMAXPvvv_2S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1650 | { AArch64_UMAXPvvv_4H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1651 | { AArch64_UMAXPvvv_4S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1652 | { AArch64_UMAXPvvv_8B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1653 | { AArch64_UMAXPvvv_8H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1654 | { AArch64_UMAXvvv_16B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1655 | { AArch64_UMAXvvv_2S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1656 | { AArch64_UMAXvvv_4H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1657 | { AArch64_UMAXvvv_4S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1658 | { AArch64_UMAXvvv_8B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1659 | { AArch64_UMAXvvv_8H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1660 | { AArch64_UMINPvvv_16B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1661 | { AArch64_UMINPvvv_2S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1662 | { AArch64_UMINPvvv_4H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1663 | { AArch64_UMINPvvv_4S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1664 | { AArch64_UMINPvvv_8B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1665 | { AArch64_UMINPvvv_8H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1666 | { AArch64_UMINvvv_16B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1667 | { AArch64_UMINvvv_2S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1668 | { AArch64_UMINvvv_4H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1669 | { AArch64_UMINvvv_4S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1670 | { AArch64_UMINvvv_8B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1671 | { AArch64_UMINvvv_8H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1672 | { AArch64_UMLAL2vvv_2d4s, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1673 | { AArch64_UMLAL2vvv_4s8h, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1674 | { AArch64_UMLAL2vvv_8h16b, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1675 | { AArch64_UMLALvvv_2d2s, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1676 | { AArch64_UMLALvvv_4s4h, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1677 | { AArch64_UMLALvvv_8h8b, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1678 | { AArch64_UMLSL2vvv_2d4s, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1679 | { AArch64_UMLSL2vvv_4s8h, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1680 | { AArch64_UMLSL2vvv_8h16b, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1681 | { AArch64_UMLSLvvv_2d2s, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1682 | { AArch64_UMLSLvvv_4s4h, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1683 | { AArch64_UMLSLvvv_8h8b, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1684 | { AArch64_UMOVwb, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1685 | { AArch64_UMOVwh, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1686 | { AArch64_UMOVws, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1687 | { AArch64_UMOVxd, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1688 | { AArch64_UMSUBLxwwx, ARM64_INS_UMSUBL, { 0 }, { 0 }, { 0 } }, |
| 1689 | { AArch64_UMULHxxx, ARM64_INS_UMULH, { 0 }, { 0 }, { 0 } }, |
| 1690 | { AArch64_UMULL2vvv_2d4s, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1691 | { AArch64_UMULL2vvv_4s8h, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1692 | { AArch64_UMULL2vvv_8h16b, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1693 | { AArch64_UMULLvvv_2d2s, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1694 | { AArch64_UMULLvvv_4s4h, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1695 | { AArch64_UMULLvvv_8h8b, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1696 | { AArch64_UQADDbbb, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1697 | { AArch64_UQADDddd, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1698 | { AArch64_UQADDhhh, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1699 | { AArch64_UQADDsss, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1700 | { AArch64_UQADDvvv_16B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1701 | { AArch64_UQADDvvv_2D, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1702 | { AArch64_UQADDvvv_2S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1703 | { AArch64_UQADDvvv_4H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1704 | { AArch64_UQADDvvv_4S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1705 | { AArch64_UQADDvvv_8B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1706 | { AArch64_UQADDvvv_8H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1707 | { AArch64_UQRSHLbbb, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1708 | { AArch64_UQRSHLddd, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1709 | { AArch64_UQRSHLhhh, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1710 | { AArch64_UQRSHLsss, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1711 | { AArch64_UQRSHLvvv_16B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1712 | { AArch64_UQRSHLvvv_2D, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1713 | { AArch64_UQRSHLvvv_2S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1714 | { AArch64_UQRSHLvvv_4H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1715 | { AArch64_UQRSHLvvv_4S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1716 | { AArch64_UQRSHLvvv_8B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1717 | { AArch64_UQRSHLvvv_8H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1718 | { AArch64_UQRSHRNvvi_16B, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1719 | { AArch64_UQRSHRNvvi_2S, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1720 | { AArch64_UQRSHRNvvi_4H, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1721 | { AArch64_UQRSHRNvvi_4S, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1722 | { AArch64_UQRSHRNvvi_8B, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1723 | { AArch64_UQRSHRNvvi_8H, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1724 | { AArch64_UQSHLbbb, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1725 | { AArch64_UQSHLddd, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1726 | { AArch64_UQSHLhhh, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1727 | { AArch64_UQSHLsss, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1728 | { AArch64_UQSHLvvi_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1729 | { AArch64_UQSHLvvi_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1730 | { AArch64_UQSHLvvi_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1731 | { AArch64_UQSHLvvi_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1732 | { AArch64_UQSHLvvi_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1733 | { AArch64_UQSHLvvi_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1734 | { AArch64_UQSHLvvi_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1735 | { AArch64_UQSHLvvv_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1736 | { AArch64_UQSHLvvv_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1737 | { AArch64_UQSHLvvv_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1738 | { AArch64_UQSHLvvv_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1739 | { AArch64_UQSHLvvv_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1740 | { AArch64_UQSHLvvv_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1741 | { AArch64_UQSHLvvv_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1742 | { AArch64_UQSHRNvvi_16B, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1743 | { AArch64_UQSHRNvvi_2S, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1744 | { AArch64_UQSHRNvvi_4H, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1745 | { AArch64_UQSHRNvvi_4S, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1746 | { AArch64_UQSHRNvvi_8B, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1747 | { AArch64_UQSHRNvvi_8H, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1748 | { AArch64_UQSUBbbb, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1749 | { AArch64_UQSUBddd, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1750 | { AArch64_UQSUBhhh, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1751 | { AArch64_UQSUBsss, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1752 | { AArch64_UQSUBvvv_16B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1753 | { AArch64_UQSUBvvv_2D, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1754 | { AArch64_UQSUBvvv_2S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1755 | { AArch64_UQSUBvvv_4H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1756 | { AArch64_UQSUBvvv_4S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1757 | { AArch64_UQSUBvvv_8B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1758 | { AArch64_UQSUBvvv_8H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1759 | { AArch64_URHADDvvv_16B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1760 | { AArch64_URHADDvvv_2S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1761 | { AArch64_URHADDvvv_4H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1762 | { AArch64_URHADDvvv_4S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1763 | { AArch64_URHADDvvv_8B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1764 | { AArch64_URHADDvvv_8H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1765 | { AArch64_URSHLddd, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1766 | { AArch64_URSHLvvv_16B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1767 | { AArch64_URSHLvvv_2D, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1768 | { AArch64_URSHLvvv_2S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1769 | { AArch64_URSHLvvv_4H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1770 | { AArch64_URSHLvvv_4S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1771 | { AArch64_URSHLvvv_8B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1772 | { AArch64_URSHLvvv_8H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1773 | { AArch64_URSHRvvi_16B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1774 | { AArch64_URSHRvvi_2D, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1775 | { AArch64_URSHRvvi_2S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1776 | { AArch64_URSHRvvi_4H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1777 | { AArch64_URSHRvvi_4S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1778 | { AArch64_URSHRvvi_8B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1779 | { AArch64_URSHRvvi_8H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1780 | { AArch64_URSRAvvi_16B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1781 | { AArch64_URSRAvvi_2D, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1782 | { AArch64_URSRAvvi_2S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1783 | { AArch64_URSRAvvi_4H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1784 | { AArch64_URSRAvvi_4S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1785 | { AArch64_URSRAvvi_8B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1786 | { AArch64_URSRAvvi_8H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1787 | { AArch64_USHLLvvi_16B, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1788 | { AArch64_USHLLvvi_2S, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1789 | { AArch64_USHLLvvi_4H, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1790 | { AArch64_USHLLvvi_4S, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1791 | { AArch64_USHLLvvi_8B, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1792 | { AArch64_USHLLvvi_8H, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1793 | { AArch64_USHLddd, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1794 | { AArch64_USHLvvv_16B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1795 | { AArch64_USHLvvv_2D, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1796 | { AArch64_USHLvvv_2S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1797 | { AArch64_USHLvvv_4H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1798 | { AArch64_USHLvvv_4S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1799 | { AArch64_USHLvvv_8B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1800 | { AArch64_USHLvvv_8H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1801 | { AArch64_USHRvvi_16B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1802 | { AArch64_USHRvvi_2D, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1803 | { AArch64_USHRvvi_2S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1804 | { AArch64_USHRvvi_4H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1805 | { AArch64_USHRvvi_4S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1806 | { AArch64_USHRvvi_8B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1807 | { AArch64_USHRvvi_8H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1808 | { AArch64_USRAvvi_16B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1809 | { AArch64_USRAvvi_2D, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1810 | { AArch64_USRAvvi_2S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1811 | { AArch64_USRAvvi_4H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1812 | { AArch64_USRAvvi_4S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1813 | { AArch64_USRAvvi_8B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1814 | { AArch64_USRAvvi_8H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1815 | { AArch64_USUBL2vvv_2d4s, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1816 | { AArch64_USUBL2vvv_4s8h, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1817 | { AArch64_USUBL2vvv_8h16b, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1818 | { AArch64_USUBLvvv_2d2s, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1819 | { AArch64_USUBLvvv_4s4h, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1820 | { AArch64_USUBLvvv_8h8b, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1821 | { AArch64_USUBW2vvv_2d4s, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1822 | { AArch64_USUBW2vvv_4s8h, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1823 | { AArch64_USUBW2vvv_8h16b, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1824 | { AArch64_USUBWvvv_2d2s, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1825 | { AArch64_USUBWvvv_4s4h, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1826 | { AArch64_USUBWvvv_8h8b, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1827 | { AArch64_UXTBww, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 } }, |
| 1828 | { AArch64_UXTBxw, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 } }, |
| 1829 | { AArch64_UXTHww, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 } }, |
| 1830 | { AArch64_UXTHxw, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 } }, |
| 1831 | { AArch64_VCVTf2xs_2D, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1832 | { AArch64_VCVTf2xs_2S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1833 | { AArch64_VCVTf2xs_4S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1834 | { AArch64_VCVTf2xu_2D, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1835 | { AArch64_VCVTf2xu_2S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1836 | { AArch64_VCVTf2xu_4S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1837 | { AArch64_VCVTxs2f_2D, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1838 | { AArch64_VCVTxs2f_2S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1839 | { AArch64_VCVTxs2f_4S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1840 | { AArch64_VCVTxu2f_2D, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1841 | { AArch64_VCVTxu2f_2S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1842 | { AArch64_VCVTxu2f_4S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } }, |
| 1843 | }; |
| 1844 | |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame^] | 1845 | // some alias instruction only need to be defined locally to satisfy |
| 1846 | // some lookup functions |
| 1847 | // just make sure these IDs never reuse any other IDs ARM_INS_* |
| 1848 | #define ARM64_INS_NEGS -1 |
| 1849 | #define ARM64_INS_NGCS -2 |
| 1850 | |
| 1851 | // all alias instructions & their semantic infos |
| 1852 | static insn_map alias_insns[] = { |
| 1853 | { AArch64_MSUBwwww, ARM64_INS_MNEG, { 0 }, { 0 }, { 0 } }, |
| 1854 | { AArch64_UMSUBLxwwx, ARM64_INS_UMNEGL, { 0 }, { 0 }, { 0 } }, |
| 1855 | { AArch64_SMSUBLxwwx, ARM64_INS_SMNEGL, { 0 }, { 0 }, { 0 } }, |
| 1856 | // MOV can be mapped back to ADD or ORR, but its semantic info is always same |
| 1857 | { AArch64_ADDwwi_lsl0_s, ARM64_INS_MOV, { 0 }, { 0 }, { 0 } }, |
| 1858 | // { AArch64_ADDxxi_lsl0_s, ARM64_INS_MOV, { 0 }, { 0 }, { 0 } }, |
| 1859 | // { AArch64_ORRwww_lsl, ARM64_INS_MOV, { 0 }, { 0 }, { 0 } }, |
| 1860 | // { AArch64_ORRxxx_lsl, ARM64_INS_MOV, { 0 }, { 0 }, { 0 } }, |
| 1861 | { AArch64_HINTi, ARM64_INS_NOP, { 0 }, { 0 }, { 0 } }, |
| 1862 | { AArch64_HINTi, ARM64_INS_YIELD, { 0 }, { 0 }, { 0 } }, |
| 1863 | { AArch64_HINTi, ARM64_INS_WFE, { 0 }, { 0 }, { 0 } }, |
| 1864 | { AArch64_HINTi, ARM64_INS_WFI, { 0 }, { 0 }, { 0 } }, |
| 1865 | { AArch64_HINTi, ARM64_INS_SEV, { 0 }, { 0 }, { 0 } }, |
| 1866 | { AArch64_HINTi, ARM64_INS_SEVL, { 0 }, { 0 }, { 0 } }, |
| 1867 | { AArch64_SBCwww, ARM64_INS_NGC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } }, |
| 1868 | { AArch64_SBCSwww, ARM64_INS_NGCS, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1869 | { AArch64_SUBSwww_lsl, ARM64_INS_NEGS, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1870 | // { AArch64_SUBSxxx_lsl, ARM64_INS_NEGS, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, |
| 1871 | { AArch64_SUBxxx_lsl, ARM64_INS_NEG, { 0 }, { 0 }, { 0 } }, |
| 1872 | // { AArch64_SUBwww_lsl, ARM64_INS_NEG, { 0 }, { 0 }, { 0 } }, |
| 1873 | }; |
| 1874 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1875 | void AArch64_get_insn_id(cs_insn *insn, unsigned int id) |
| 1876 | { |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame^] | 1877 | // try alias insn first |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1878 | int i = insn_find(insns, ARR_SIZE(insns), id); |
| 1879 | if (i != -1) { |
| 1880 | insn->id = insns[i].mapid; |
| 1881 | memcpy(insn->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); |
| 1882 | memcpy(insn->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); |
| 1883 | memcpy(insn->groups, insns[i].groups, sizeof(insns[i].groups)); |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame^] | 1884 | // call cs_reg_write() with handle = 1 to pass handle check |
| 1885 | // we only need to find if this insn modifies ARM64_REG_NZCV |
Nguyen Anh Quynh | e1611f0 | 2013-11-30 12:37:26 +0800 | [diff] [blame] | 1886 | insn->arm64.update_flags = cs_reg_write(1, insn, ARM64_REG_NZCV); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1887 | } |
| 1888 | } |
| 1889 | |
Nguyen Anh Quynh | 6b7abe3 | 2013-11-30 00:54:24 +0800 | [diff] [blame] | 1890 | // given public insn id, return internal instruction ID |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1891 | unsigned int AArch64_get_insn_id2(unsigned int id) |
| 1892 | { |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame^] | 1893 | unsigned int res = insn_reverse_id(insns, ARR_SIZE(insns), id); |
| 1894 | if (!res) // is this alias insn? |
| 1895 | res = insn_reverse_id(alias_insns, ARR_SIZE(alias_insns), id); |
| 1896 | |
| 1897 | return res; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1898 | } |
| 1899 | |
| 1900 | static name_map insn_name_maps[] = { |
| 1901 | { ARM64_INS_INVALID, NULL }, |
| 1902 | { ARM64_INS_ADC, "ADC" }, |
| 1903 | { ARM64_INS_ADDHN2, "ADDHN2" }, |
| 1904 | { ARM64_INS_ADDHN, "ADDHN" }, |
| 1905 | { ARM64_INS_ADDP, "ADDP" }, |
| 1906 | { ARM64_INS_ADD, "ADD" }, |
| 1907 | { ARM64_INS_CMN, "CMN" }, |
| 1908 | { ARM64_INS_ADRP, "ADRP" }, |
| 1909 | { ARM64_INS_ADR, "ADR" }, |
| 1910 | { ARM64_INS_AND, "AND" }, |
| 1911 | { ARM64_INS_ASR, "ASR" }, |
| 1912 | { ARM64_INS_AT, "AT" }, |
| 1913 | { ARM64_INS_BFI, "BFI" }, |
| 1914 | { ARM64_INS_BFM, "BFM" }, |
| 1915 | { ARM64_INS_BFXIL, "BFXIL" }, |
| 1916 | { ARM64_INS_BIC, "BIC" }, |
| 1917 | { ARM64_INS_BIF, "BIF" }, |
| 1918 | { ARM64_INS_BIT, "BIT" }, |
| 1919 | { ARM64_INS_BLR, "BLR" }, |
| 1920 | { ARM64_INS_BL, "BL" }, |
| 1921 | { ARM64_INS_BRK, "BRK" }, |
| 1922 | { ARM64_INS_BR, "BR" }, |
| 1923 | { ARM64_INS_BSL, "BSL" }, |
| 1924 | { ARM64_INS_B, "B" }, |
| 1925 | { ARM64_INS_CBNZ, "CBNZ" }, |
| 1926 | { ARM64_INS_CBZ, "CBZ" }, |
| 1927 | { ARM64_INS_CCMN, "CCMN" }, |
| 1928 | { ARM64_INS_CCMP, "CCMP" }, |
| 1929 | { ARM64_INS_CLREX, "CLREX" }, |
| 1930 | { ARM64_INS_CLS, "CLS" }, |
| 1931 | { ARM64_INS_CLZ, "CLZ" }, |
| 1932 | { ARM64_INS_CMEQ, "CMEQ" }, |
| 1933 | { ARM64_INS_CMGE, "CMGE" }, |
| 1934 | { ARM64_INS_CMGT, "CMGT" }, |
| 1935 | { ARM64_INS_CMHI, "CMHI" }, |
| 1936 | { ARM64_INS_CMHS, "CMHS" }, |
| 1937 | { ARM64_INS_CMLE, "CMLE" }, |
| 1938 | { ARM64_INS_CMLT, "CMLT" }, |
| 1939 | { ARM64_INS_CMP, "CMP" }, |
| 1940 | { ARM64_INS_CMTST, "CMTST" }, |
| 1941 | { ARM64_INS_CRC32B, "CRC32B" }, |
| 1942 | { ARM64_INS_CRC32CB, "CRC32CB" }, |
| 1943 | { ARM64_INS_CRC32CH, "CRC32CH" }, |
| 1944 | { ARM64_INS_CRC32CW, "CRC32CW" }, |
| 1945 | { ARM64_INS_CRC32CX, "CRC32CX" }, |
| 1946 | { ARM64_INS_CRC32H, "CRC32H" }, |
| 1947 | { ARM64_INS_CRC32W, "CRC32W" }, |
| 1948 | { ARM64_INS_CRC32X, "CRC32X" }, |
| 1949 | { ARM64_INS_CSEL, "CSEL" }, |
| 1950 | { ARM64_INS_CSINC, "CSINC" }, |
| 1951 | { ARM64_INS_CSINV, "CSINV" }, |
| 1952 | { ARM64_INS_CSNEG, "CSNEG" }, |
| 1953 | { ARM64_INS_DCPS1, "DCPS1" }, |
| 1954 | { ARM64_INS_DCPS2, "DCPS2" }, |
| 1955 | { ARM64_INS_DCPS3, "DCPS3" }, |
| 1956 | { ARM64_INS_DC, "DC" }, |
| 1957 | { ARM64_INS_DMB, "DMB" }, |
| 1958 | { ARM64_INS_DRPS, "DRPS" }, |
| 1959 | { ARM64_INS_DSB, "DSB" }, |
| 1960 | { ARM64_INS_EON, "EON" }, |
| 1961 | { ARM64_INS_EOR, "EOR" }, |
| 1962 | { ARM64_INS_ERET, "ERET" }, |
| 1963 | { ARM64_INS_EXTR, "EXTR" }, |
| 1964 | { ARM64_INS_FABD, "FABD" }, |
| 1965 | { ARM64_INS_FABS, "FABS" }, |
| 1966 | { ARM64_INS_FACGE, "FACGE" }, |
| 1967 | { ARM64_INS_FACGT, "FACGT" }, |
| 1968 | { ARM64_INS_FADDP, "FADDP" }, |
| 1969 | { ARM64_INS_FADD, "FADD" }, |
| 1970 | { ARM64_INS_FCCMPE, "FCCMPE" }, |
| 1971 | { ARM64_INS_FCCMP, "FCCMP" }, |
| 1972 | { ARM64_INS_FCMEQ, "FCMEQ" }, |
| 1973 | { ARM64_INS_FCMGE, "FCMGE" }, |
| 1974 | { ARM64_INS_FCMGT, "FCMGT" }, |
| 1975 | { ARM64_INS_FCMLE, "FCMLE" }, |
| 1976 | { ARM64_INS_FCMLT, "FCMLT" }, |
| 1977 | { ARM64_INS_FCMP, "FCMP" }, |
| 1978 | { ARM64_INS_FCMPE, "FCMPE" }, |
| 1979 | { ARM64_INS_FCSEL, "FCSEL" }, |
| 1980 | { ARM64_INS_FCVTAS, "FCVTAS" }, |
| 1981 | { ARM64_INS_FCVTAU, "FCVTAU" }, |
| 1982 | { ARM64_INS_FCVTMS, "FCVTMS" }, |
| 1983 | { ARM64_INS_FCVTMU, "FCVTMU" }, |
| 1984 | { ARM64_INS_FCVTNS, "FCVTNS" }, |
| 1985 | { ARM64_INS_FCVTNU, "FCVTNU" }, |
| 1986 | { ARM64_INS_FCVTPS, "FCVTPS" }, |
| 1987 | { ARM64_INS_FCVTPU, "FCVTPU" }, |
| 1988 | { ARM64_INS_FCVTZS, "FCVTZS" }, |
| 1989 | { ARM64_INS_FCVTZU, "FCVTZU" }, |
| 1990 | { ARM64_INS_FCVT, "FCVT" }, |
| 1991 | { ARM64_INS_FDIV, "FDIV" }, |
| 1992 | { ARM64_INS_FMADD, "FMADD" }, |
| 1993 | { ARM64_INS_FMAXNMP, "FMAXNMP" }, |
| 1994 | { ARM64_INS_FMAXNM, "FMAXNM" }, |
| 1995 | { ARM64_INS_FMAXP, "FMAXP" }, |
| 1996 | { ARM64_INS_FMAX, "FMAX" }, |
| 1997 | { ARM64_INS_FMINNMP, "FMINNMP" }, |
| 1998 | { ARM64_INS_FMINNM, "FMINNM" }, |
| 1999 | { ARM64_INS_FMINP, "FMINP" }, |
| 2000 | { ARM64_INS_FMIN, "FMIN" }, |
| 2001 | { ARM64_INS_FMLA, "FMLA" }, |
| 2002 | { ARM64_INS_FMLS, "FMLS" }, |
| 2003 | { ARM64_INS_FMOV, "FMOV" }, |
| 2004 | { ARM64_INS_FMSUB, "FMSUB" }, |
| 2005 | { ARM64_INS_FMULX, "FMULX" }, |
| 2006 | { ARM64_INS_FMUL, "FMUL" }, |
| 2007 | { ARM64_INS_FNEG, "FNEG" }, |
| 2008 | { ARM64_INS_FNMADD, "FNMADD" }, |
| 2009 | { ARM64_INS_FNMSUB, "FNMSUB" }, |
| 2010 | { ARM64_INS_FNMUL, "FNMUL" }, |
| 2011 | { ARM64_INS_FRECPS, "FRECPS" }, |
| 2012 | { ARM64_INS_FRINTA, "FRINTA" }, |
| 2013 | { ARM64_INS_FRINTI, "FRINTI" }, |
| 2014 | { ARM64_INS_FRINTM, "FRINTM" }, |
| 2015 | { ARM64_INS_FRINTN, "FRINTN" }, |
| 2016 | { ARM64_INS_FRINTP, "FRINTP" }, |
| 2017 | { ARM64_INS_FRINTX, "FRINTX" }, |
| 2018 | { ARM64_INS_FRINTZ, "FRINTZ" }, |
| 2019 | { ARM64_INS_FRSQRTS, "FRSQRTS" }, |
| 2020 | { ARM64_INS_FSQRT, "FSQRT" }, |
| 2021 | { ARM64_INS_FSUB, "FSUB" }, |
| 2022 | { ARM64_INS_HINT, "HINT" }, |
| 2023 | { ARM64_INS_HLT, "HLT" }, |
| 2024 | { ARM64_INS_HVC, "HVC" }, |
| 2025 | { ARM64_INS_IC, "IC" }, |
| 2026 | { ARM64_INS_INS, "INS" }, |
| 2027 | { ARM64_INS_ISB, "ISB" }, |
| 2028 | { ARM64_INS_LDARB, "LDARB" }, |
| 2029 | { ARM64_INS_LDAR, "LDAR" }, |
| 2030 | { ARM64_INS_LDARH, "LDARH" }, |
| 2031 | { ARM64_INS_LDAXP, "LDAXP" }, |
| 2032 | { ARM64_INS_LDAXRB, "LDAXRB" }, |
| 2033 | { ARM64_INS_LDAXR, "LDAXR" }, |
| 2034 | { ARM64_INS_LDAXRH, "LDAXRH" }, |
| 2035 | { ARM64_INS_LDPSW, "LDPSW" }, |
| 2036 | { ARM64_INS_LDRSB, "LDRSB" }, |
| 2037 | { ARM64_INS_LDURSB, "LDURSB" }, |
| 2038 | { ARM64_INS_LDRSH, "LDRSH" }, |
| 2039 | { ARM64_INS_LDURSH, "LDURSH" }, |
| 2040 | { ARM64_INS_LDRSW, "LDRSW" }, |
| 2041 | { ARM64_INS_LDR, "LDR" }, |
| 2042 | { ARM64_INS_LDTRSB, "LDTRSB" }, |
| 2043 | { ARM64_INS_LDTRSH, "LDTRSH" }, |
| 2044 | { ARM64_INS_LDTRSW, "LDTRSW" }, |
| 2045 | { ARM64_INS_LDURSW, "LDURSW" }, |
| 2046 | { ARM64_INS_LDXP, "LDXP" }, |
| 2047 | { ARM64_INS_LDXRB, "LDXRB" }, |
| 2048 | { ARM64_INS_LDXR, "LDXR" }, |
| 2049 | { ARM64_INS_LDXRH, "LDXRH" }, |
| 2050 | { ARM64_INS_LDRH, "LDRH" }, |
| 2051 | { ARM64_INS_LDURH, "LDURH" }, |
| 2052 | { ARM64_INS_STRH, "STRH" }, |
| 2053 | { ARM64_INS_STURH, "STURH" }, |
| 2054 | { ARM64_INS_LDTRH, "LDTRH" }, |
| 2055 | { ARM64_INS_STTRH, "STTRH" }, |
| 2056 | { ARM64_INS_LDUR, "LDUR" }, |
| 2057 | { ARM64_INS_STR, "STR" }, |
| 2058 | { ARM64_INS_STUR, "STUR" }, |
| 2059 | { ARM64_INS_LDTR, "LDTR" }, |
| 2060 | { ARM64_INS_STTR, "STTR" }, |
| 2061 | { ARM64_INS_LDRB, "LDRB" }, |
| 2062 | { ARM64_INS_LDURB, "LDURB" }, |
| 2063 | { ARM64_INS_STRB, "STRB" }, |
| 2064 | { ARM64_INS_STURB, "STURB" }, |
| 2065 | { ARM64_INS_LDTRB, "LDTRB" }, |
| 2066 | { ARM64_INS_STTRB, "STTRB" }, |
| 2067 | { ARM64_INS_LDP, "LDP" }, |
| 2068 | { ARM64_INS_LDNP, "LDNP" }, |
| 2069 | { ARM64_INS_STNP, "STNP" }, |
| 2070 | { ARM64_INS_STP, "STP" }, |
| 2071 | { ARM64_INS_LSL, "LSL" }, |
| 2072 | { ARM64_INS_LSR, "LSR" }, |
| 2073 | { ARM64_INS_MADD, "MADD" }, |
| 2074 | { ARM64_INS_MLA, "MLA" }, |
| 2075 | { ARM64_INS_MLS, "MLS" }, |
| 2076 | { ARM64_INS_MOVI, "MOVI" }, |
| 2077 | { ARM64_INS_MOVK, "MOVK" }, |
| 2078 | { ARM64_INS_MOVN, "MOVN" }, |
| 2079 | { ARM64_INS_MOVZ, "MOVZ" }, |
| 2080 | { ARM64_INS_MRS, "MRS" }, |
| 2081 | { ARM64_INS_MSR, "MSR" }, |
| 2082 | { ARM64_INS_MSUB, "MSUB" }, |
| 2083 | { ARM64_INS_MUL, "MUL" }, |
| 2084 | { ARM64_INS_MVNI, "MVNI" }, |
| 2085 | { ARM64_INS_MVN, "MVN" }, |
| 2086 | { ARM64_INS_ORN, "ORN" }, |
| 2087 | { ARM64_INS_ORR, "ORR" }, |
| 2088 | { ARM64_INS_PMULL2, "PMULL2" }, |
| 2089 | { ARM64_INS_PMULL, "PMULL" }, |
| 2090 | { ARM64_INS_PMUL, "PMUL" }, |
| 2091 | { ARM64_INS_PRFM, "PRFM" }, |
| 2092 | { ARM64_INS_PRFUM, "PRFUM" }, |
| 2093 | { ARM64_INS_SQRSHRUN2, "SQRSHRUN2" }, |
| 2094 | { ARM64_INS_SQRSHRUN, "SQRSHRUN" }, |
| 2095 | { ARM64_INS_SQSHRUN2, "SQSHRUN2" }, |
| 2096 | { ARM64_INS_SQSHRUN, "SQSHRUN" }, |
| 2097 | { ARM64_INS_RADDHN2, "RADDHN2" }, |
| 2098 | { ARM64_INS_RADDHN, "RADDHN" }, |
| 2099 | { ARM64_INS_RBIT, "RBIT" }, |
| 2100 | { ARM64_INS_RET, "RET" }, |
| 2101 | { ARM64_INS_REV16, "REV16" }, |
| 2102 | { ARM64_INS_REV32, "REV32" }, |
| 2103 | { ARM64_INS_REV, "REV" }, |
| 2104 | { ARM64_INS_ROR, "ROR" }, |
| 2105 | { ARM64_INS_RSHRN2, "RSHRN2" }, |
| 2106 | { ARM64_INS_RSHRN, "RSHRN" }, |
| 2107 | { ARM64_INS_RSUBHN2, "RSUBHN2" }, |
| 2108 | { ARM64_INS_RSUBHN, "RSUBHN" }, |
| 2109 | { ARM64_INS_SABAL2, "SABAL2" }, |
| 2110 | { ARM64_INS_SABAL, "SABAL" }, |
| 2111 | { ARM64_INS_SABA, "SABA" }, |
| 2112 | { ARM64_INS_SABDL2, "SABDL2" }, |
| 2113 | { ARM64_INS_SABDL, "SABDL" }, |
| 2114 | { ARM64_INS_SABD, "SABD" }, |
| 2115 | { ARM64_INS_SADDL2, "SADDL2" }, |
| 2116 | { ARM64_INS_SADDL, "SADDL" }, |
| 2117 | { ARM64_INS_SADDW2, "SADDW2" }, |
| 2118 | { ARM64_INS_SADDW, "SADDW" }, |
| 2119 | { ARM64_INS_SBC, "SBC" }, |
| 2120 | { ARM64_INS_SBFIZ, "SBFIZ" }, |
| 2121 | { ARM64_INS_SBFM, "SBFM" }, |
| 2122 | { ARM64_INS_SBFX, "SBFX" }, |
| 2123 | { ARM64_INS_SCVTF, "SCVTF" }, |
| 2124 | { ARM64_INS_SDIV, "SDIV" }, |
| 2125 | { ARM64_INS_SHADD, "SHADD" }, |
| 2126 | { ARM64_INS_SHL, "SHL" }, |
| 2127 | { ARM64_INS_SHRN2, "SHRN2" }, |
| 2128 | { ARM64_INS_SHRN, "SHRN" }, |
| 2129 | { ARM64_INS_SHSUB, "SHSUB" }, |
| 2130 | { ARM64_INS_SLI, "SLI" }, |
| 2131 | { ARM64_INS_SMADDL, "SMADDL" }, |
| 2132 | { ARM64_INS_SMAXP, "SMAXP" }, |
| 2133 | { ARM64_INS_SMAX, "SMAX" }, |
| 2134 | { ARM64_INS_SMC, "SMC" }, |
| 2135 | { ARM64_INS_SMINP, "SMINP" }, |
| 2136 | { ARM64_INS_SMIN, "SMIN" }, |
| 2137 | { ARM64_INS_SMLAL2, "SMLAL2" }, |
| 2138 | { ARM64_INS_SMLAL, "SMLAL" }, |
| 2139 | { ARM64_INS_SMLSL2, "SMLSL2" }, |
| 2140 | { ARM64_INS_SMLSL, "SMLSL" }, |
| 2141 | { ARM64_INS_SMOV, "SMOV" }, |
| 2142 | { ARM64_INS_SMSUBL, "SMSUBL" }, |
| 2143 | { ARM64_INS_SMULH, "SMULH" }, |
| 2144 | { ARM64_INS_SMULL2, "SMULL2" }, |
| 2145 | { ARM64_INS_SMULL, "SMULL" }, |
| 2146 | { ARM64_INS_SQADD, "SQADD" }, |
| 2147 | { ARM64_INS_SQDMLAL2, "SQDMLAL2" }, |
| 2148 | { ARM64_INS_SQDMLAL, "SQDMLAL" }, |
| 2149 | { ARM64_INS_SQDMLSL2, "SQDMLSL2" }, |
| 2150 | { ARM64_INS_SQDMLSL, "SQDMLSL" }, |
| 2151 | { ARM64_INS_SQDMULH, "SQDMULH" }, |
| 2152 | { ARM64_INS_SQDMULL2, "SQDMULL2" }, |
| 2153 | { ARM64_INS_SQDMULL, "SQDMULL" }, |
| 2154 | { ARM64_INS_SQRDMULH, "SQRDMULH" }, |
| 2155 | { ARM64_INS_SQRSHL, "SQRSHL" }, |
| 2156 | { ARM64_INS_SQRSHRN2, "SQRSHRN2" }, |
| 2157 | { ARM64_INS_SQRSHRN, "SQRSHRN" }, |
| 2158 | { ARM64_INS_SQSHLU, "SQSHLU" }, |
| 2159 | { ARM64_INS_SQSHL, "SQSHL" }, |
| 2160 | { ARM64_INS_SQSHRN2, "SQSHRN2" }, |
| 2161 | { ARM64_INS_SQSHRN, "SQSHRN" }, |
| 2162 | { ARM64_INS_SQSUB, "SQSUB" }, |
| 2163 | { ARM64_INS_SRHADD, "SRHADD" }, |
| 2164 | { ARM64_INS_SRI, "SRI" }, |
| 2165 | { ARM64_INS_SRSHL, "SRSHL" }, |
| 2166 | { ARM64_INS_SRSHR, "SRSHR" }, |
| 2167 | { ARM64_INS_SRSRA, "SRSRA" }, |
| 2168 | { ARM64_INS_SSHLL2, "SSHLL2" }, |
| 2169 | { ARM64_INS_SSHLL, "SSHLL" }, |
| 2170 | { ARM64_INS_SSHL, "SSHL" }, |
| 2171 | { ARM64_INS_SSHR, "SSHR" }, |
| 2172 | { ARM64_INS_SSRA, "SSRA" }, |
| 2173 | { ARM64_INS_SSUBL2, "SSUBL2" }, |
| 2174 | { ARM64_INS_SSUBL, "SSUBL" }, |
| 2175 | { ARM64_INS_SSUBW2, "SSUBW2" }, |
| 2176 | { ARM64_INS_SSUBW, "SSUBW" }, |
| 2177 | { ARM64_INS_STLRB, "STLRB" }, |
| 2178 | { ARM64_INS_STLR, "STLR" }, |
| 2179 | { ARM64_INS_STLRH, "STLRH" }, |
| 2180 | { ARM64_INS_STLXP, "STLXP" }, |
| 2181 | { ARM64_INS_STLXRB, "STLXRB" }, |
| 2182 | { ARM64_INS_STLXR, "STLXR" }, |
| 2183 | { ARM64_INS_STLXRH, "STLXRH" }, |
| 2184 | { ARM64_INS_STXP, "STXP" }, |
| 2185 | { ARM64_INS_STXRB, "STXRB" }, |
| 2186 | { ARM64_INS_STXR, "STXR" }, |
| 2187 | { ARM64_INS_STXRH, "STXRH" }, |
| 2188 | { ARM64_INS_SUBHN2, "SUBHN2" }, |
| 2189 | { ARM64_INS_SUBHN, "SUBHN" }, |
| 2190 | { ARM64_INS_SUB, "SUB" }, |
| 2191 | { ARM64_INS_SVC, "SVC" }, |
| 2192 | { ARM64_INS_SXTB, "SXTB" }, |
| 2193 | { ARM64_INS_SXTH, "SXTH" }, |
| 2194 | { ARM64_INS_SXTW, "SXTW" }, |
| 2195 | { ARM64_INS_SYSL, "SYSL" }, |
| 2196 | { ARM64_INS_SYS, "SYS" }, |
| 2197 | { ARM64_INS_TBNZ, "TBNZ" }, |
| 2198 | { ARM64_INS_TBZ, "TBZ" }, |
| 2199 | { ARM64_INS_TLBI, "TLBI" }, |
| 2200 | { ARM64_INS_TST, "TST" }, |
| 2201 | { ARM64_INS_UABAL2, "UABAL2" }, |
| 2202 | { ARM64_INS_UABAL, "UABAL" }, |
| 2203 | { ARM64_INS_UABA, "UABA" }, |
| 2204 | { ARM64_INS_UABDL2, "UABDL2" }, |
| 2205 | { ARM64_INS_UABDL, "UABDL" }, |
| 2206 | { ARM64_INS_UABD, "UABD" }, |
| 2207 | { ARM64_INS_UADDL2, "UADDL2" }, |
| 2208 | { ARM64_INS_UADDL, "UADDL" }, |
| 2209 | { ARM64_INS_UADDW2, "UADDW2" }, |
| 2210 | { ARM64_INS_UADDW, "UADDW" }, |
| 2211 | { ARM64_INS_UBFIZ, "UBFIZ" }, |
| 2212 | { ARM64_INS_UBFM, "UBFM" }, |
| 2213 | { ARM64_INS_UBFX, "UBFX" }, |
| 2214 | { ARM64_INS_UCVTF, "UCVTF" }, |
| 2215 | { ARM64_INS_UDIV, "UDIV" }, |
| 2216 | { ARM64_INS_UHADD, "UHADD" }, |
| 2217 | { ARM64_INS_UHSUB, "UHSUB" }, |
| 2218 | { ARM64_INS_UMADDL, "UMADDL" }, |
| 2219 | { ARM64_INS_UMAXP, "UMAXP" }, |
| 2220 | { ARM64_INS_UMAX, "UMAX" }, |
| 2221 | { ARM64_INS_UMINP, "UMINP" }, |
| 2222 | { ARM64_INS_UMIN, "UMIN" }, |
| 2223 | { ARM64_INS_UMLAL2, "UMLAL2" }, |
| 2224 | { ARM64_INS_UMLAL, "UMLAL" }, |
| 2225 | { ARM64_INS_UMLSL2, "UMLSL2" }, |
| 2226 | { ARM64_INS_UMLSL, "UMLSL" }, |
| 2227 | { ARM64_INS_UMOV, "UMOV" }, |
| 2228 | { ARM64_INS_UMSUBL, "UMSUBL" }, |
| 2229 | { ARM64_INS_UMULH, "UMULH" }, |
| 2230 | { ARM64_INS_UMULL2, "UMULL2" }, |
| 2231 | { ARM64_INS_UMULL, "UMULL" }, |
| 2232 | { ARM64_INS_UQADD, "UQADD" }, |
| 2233 | { ARM64_INS_UQRSHL, "UQRSHL" }, |
| 2234 | { ARM64_INS_UQRSHRN2, "UQRSHRN2" }, |
| 2235 | { ARM64_INS_UQRSHRN, "UQRSHRN" }, |
| 2236 | { ARM64_INS_UQSHL, "UQSHL" }, |
| 2237 | { ARM64_INS_UQSHRN2, "UQSHRN2" }, |
| 2238 | { ARM64_INS_UQSHRN, "UQSHRN" }, |
| 2239 | { ARM64_INS_UQSUB, "UQSUB" }, |
| 2240 | { ARM64_INS_URHADD, "URHADD" }, |
| 2241 | { ARM64_INS_URSHL, "URSHL" }, |
| 2242 | { ARM64_INS_URSHR, "URSHR" }, |
| 2243 | { ARM64_INS_URSRA, "URSRA" }, |
| 2244 | { ARM64_INS_USHLL2, "USHLL2" }, |
| 2245 | { ARM64_INS_USHLL, "USHLL" }, |
| 2246 | { ARM64_INS_USHL, "USHL" }, |
| 2247 | { ARM64_INS_USHR, "USHR" }, |
| 2248 | { ARM64_INS_USRA, "USRA" }, |
| 2249 | { ARM64_INS_USUBL2, "USUBL2" }, |
| 2250 | { ARM64_INS_USUBL, "USUBL" }, |
| 2251 | { ARM64_INS_USUBW2, "USUBW2" }, |
| 2252 | { ARM64_INS_USUBW, "USUBW" }, |
| 2253 | { ARM64_INS_UXTB, "UXTB" }, |
| 2254 | { ARM64_INS_UXTH, "UXTH" }, |
| 2255 | }; |
| 2256 | |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame^] | 2257 | // map *S & alias instructions back to original id |
| 2258 | static name_map alias_insn_name_maps[] = { |
| 2259 | { ARM64_INS_ADC, "ADCS" }, |
| 2260 | { ARM64_INS_AND, "ANDS" }, |
| 2261 | { ARM64_INS_ADD, "ADDS" }, |
| 2262 | { ARM64_INS_BIC, "BICS" }, |
| 2263 | { ARM64_INS_SBC, "SBCS" }, |
| 2264 | { ARM64_INS_SUB, "SUBS" }, |
| 2265 | |
| 2266 | // alias insn |
| 2267 | { ARM64_INS_MNEG, "MNEG" }, |
| 2268 | { ARM64_INS_UMNEGL, "UMNEGL" }, |
| 2269 | { ARM64_INS_SMNEGL, "SMNEGL" }, |
| 2270 | { ARM64_INS_MOV, "MOV" }, |
| 2271 | { ARM64_INS_NOP, "NOP" }, |
| 2272 | { ARM64_INS_YIELD, "YIELD" }, |
| 2273 | { ARM64_INS_WFE, "WFE" }, |
| 2274 | { ARM64_INS_WFI, "WFI" }, |
| 2275 | { ARM64_INS_SEV, "SEV" }, |
| 2276 | { ARM64_INS_SEVL, "SEVL" }, |
| 2277 | { ARM64_INS_NGC, "NGC" }, |
| 2278 | { ARM64_INS_NGCS, "NGCS" }, |
| 2279 | { ARM64_INS_NEG, "NEG" }, |
| 2280 | { ARM64_INS_NEGS, "NEGS" }, |
| 2281 | }; |
| 2282 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2283 | char *AArch64_insn_name(unsigned int id) |
| 2284 | { |
| 2285 | if (id >= ARM64_INS_MAX) |
| 2286 | return NULL; |
| 2287 | |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame^] | 2288 | // try with alias insn first |
| 2289 | int i; |
| 2290 | for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { |
| 2291 | if (alias_insn_name_maps[i].id == id) |
| 2292 | return alias_insn_name_maps[i].name; |
| 2293 | } |
| 2294 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2295 | return insn_name_maps[id].name; |
| 2296 | } |
| 2297 | |
Nguyen Anh Quynh | 6b7abe3 | 2013-11-30 00:54:24 +0800 | [diff] [blame] | 2298 | // map instruction name to public instruction ID |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2299 | arm64_reg AArch64_map_insn(char *name) |
| 2300 | { |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2301 | // NOTE: skip first NULL name in insn_name_maps |
| 2302 | int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); |
| 2303 | |
| 2304 | if (i == -1) |
| 2305 | // try again with 'special' insn that is not available in insn_name_maps |
Nguyen Anh Quynh | ad61c49 | 2013-11-30 16:23:31 +0800 | [diff] [blame^] | 2306 | i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2307 | |
| 2308 | return (i != -1)? i : ARM64_REG_INVALID; |
| 2309 | } |
| 2310 | |