Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1 | //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file includes code for rendering MCInst instances as AT&T-style |
| 11 | // assembly. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | /* Capstone Disassembler Engine */ |
| 16 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */ |
| 17 | |
| 18 | #include <ctype.h> |
| 19 | #include <inttypes.h> |
| 20 | #include <stdio.h> |
| 21 | #include <stdlib.h> |
| 22 | #include <string.h> |
| 23 | |
| 24 | #include "../../utils.h" |
| 25 | #include "../../MCInst.h" |
| 26 | #include "../../SStream.h" |
| 27 | #include "../../MCRegisterInfo.h" |
| 28 | #include "mapping.h" |
| 29 | |
| 30 | #define markup(x) "" |
| 31 | |
| 32 | |
| 33 | const char *X86ATT_getRegisterName(unsigned RegNo); |
| 34 | |
| 35 | static void printMemReference(MCInst *MI, unsigned Op, SStream *O); |
| 36 | |
| 37 | static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) |
| 38 | { |
| 39 | SStream_concat(O, "OPAQUE PTR "); |
| 40 | printMemReference(MI, OpNo, O); |
| 41 | } |
| 42 | |
| 43 | static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 44 | { |
| 45 | SStream_concat(O, "BYTE PTR "); |
| 46 | printMemReference(MI, OpNo, O); |
| 47 | } |
| 48 | |
| 49 | static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 50 | { |
| 51 | SStream_concat(O, "WORD PTR "); |
| 52 | printMemReference(MI, OpNo, O); |
| 53 | } |
| 54 | |
| 55 | static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 56 | { |
| 57 | SStream_concat(O, "DWORD PTR "); |
| 58 | printMemReference(MI, OpNo, O); |
| 59 | } |
| 60 | |
| 61 | static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 62 | { |
| 63 | SStream_concat(O, "QWORD PTR "); |
| 64 | printMemReference(MI, OpNo, O); |
| 65 | } |
| 66 | |
| 67 | static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 68 | { |
| 69 | SStream_concat(O, "XMMWORD PTR "); |
| 70 | printMemReference(MI, OpNo, O); |
| 71 | } |
| 72 | |
| 73 | static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 74 | { |
| 75 | SStream_concat(O, "YMMWORD PTR "); |
| 76 | printMemReference(MI, OpNo, O); |
| 77 | } |
| 78 | |
| 79 | static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 80 | { |
| 81 | printMemReference(MI, OpNo, O); |
| 82 | } |
| 83 | |
| 84 | static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 85 | { |
| 86 | SStream_concat(O, "DWORD PTR "); |
| 87 | printMemReference(MI, OpNo, O); |
| 88 | } |
| 89 | |
| 90 | static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 91 | { |
| 92 | SStream_concat(O, "QWORD PTR "); |
| 93 | printMemReference(MI, OpNo, O); |
| 94 | } |
| 95 | |
| 96 | static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 97 | { |
| 98 | SStream_concat(O, "XWORD PTR "); |
| 99 | printMemReference(MI, OpNo, O); |
| 100 | } |
| 101 | |
| 102 | static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 103 | { |
| 104 | SStream_concat(O, "XMMWORD PTR "); |
| 105 | printMemReference(MI, OpNo, O); |
| 106 | } |
| 107 | |
| 108 | static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 109 | { |
| 110 | SStream_concat(O, "YMMWORD PTR "); |
| 111 | printMemReference(MI, OpNo, O); |
| 112 | } |
| 113 | |
| 114 | static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 115 | { |
| 116 | printMemReference(MI, OpNo, O); |
| 117 | } |
| 118 | |
| 119 | static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) |
| 120 | { |
| 121 | MCOperand *DispSpec = MCInst_getOperand(MI, Op); |
| 122 | |
| 123 | SStream_concat(O, "%s", markup("<mem:")); |
| 124 | |
| 125 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_MEM; |
| 126 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.base = X86_REG_INVALID; |
| 127 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.index = X86_REG_INVALID; |
| 128 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.scale = 1; |
| 129 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.disp = 0; |
| 130 | |
| 131 | if (MCOperand_isImm(DispSpec)) { |
| 132 | int64_t imm = MCOperand_getImm(DispSpec); |
| 133 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.disp = imm; |
| 134 | if (imm < 0) |
| 135 | SStream_concat(O, "-0x%"PRIx64, -imm); |
| 136 | else |
| 137 | SStream_concat(O, "0x%"PRIx64, imm); |
| 138 | } |
| 139 | |
| 140 | SStream_concat(O, "%s", markup(">")); |
| 141 | |
| 142 | MI->pub_insn.x86.op_count++; |
| 143 | } |
| 144 | |
| 145 | static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) |
| 146 | { |
Nguyen Anh Quynh | b9b3d29 | 2013-12-02 16:21:55 +0800 | [diff] [blame] | 147 | // If this has a segment register, print it. |
| 148 | // this is a hack. will fix it later |
| 149 | if (MI->pub_insn.x86.segment) { |
| 150 | SStream_concat(O, "%%%s:", X86_reg_name(MI->pub_insn.x86.segment)); |
| 151 | } |
| 152 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 153 | printMemOffset(MI, OpNo, O); |
| 154 | } |
| 155 | |
| 156 | static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) |
| 157 | { |
Nguyen Anh Quynh | b9b3d29 | 2013-12-02 16:21:55 +0800 | [diff] [blame] | 158 | // If this has a segment register, print it. |
| 159 | // this is a hack. will fix it later |
| 160 | if (MI->pub_insn.x86.segment) { |
| 161 | SStream_concat(O, "%%%s:", X86_reg_name(MI->pub_insn.x86.segment)); |
| 162 | } |
| 163 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 164 | printMemOffset(MI, OpNo, O); |
| 165 | } |
| 166 | |
| 167 | static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) |
| 168 | { |
Nguyen Anh Quynh | b9b3d29 | 2013-12-02 16:21:55 +0800 | [diff] [blame] | 169 | // If this has a segment register, print it. |
| 170 | // this is a hack. will fix it later |
| 171 | if (MI->pub_insn.x86.segment) { |
| 172 | SStream_concat(O, "%%%s:", X86_reg_name(MI->pub_insn.x86.segment)); |
| 173 | } |
| 174 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 175 | printMemOffset(MI, OpNo, O); |
| 176 | } |
| 177 | |
| 178 | static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) |
| 179 | { |
| 180 | printMemOffset(MI, OpNo, O); |
| 181 | } |
| 182 | |
| 183 | static void printRegName(SStream *OS, unsigned RegNo); |
| 184 | |
| 185 | static void printSSECC(MCInst *MI, unsigned Op, SStream *OS) |
| 186 | { |
| 187 | int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xf; |
| 188 | switch (Imm) { |
| 189 | default: break; // never reach |
| 190 | case 0: SStream_concat(OS, "eq"); break; |
| 191 | case 1: SStream_concat(OS, "lt"); break; |
| 192 | case 2: SStream_concat(OS, "le"); break; |
| 193 | case 3: SStream_concat(OS, "unord"); break; |
| 194 | case 4: SStream_concat(OS, "neq"); break; |
| 195 | case 5: SStream_concat(OS, "nlt"); break; |
| 196 | case 6: SStream_concat(OS, "nle"); break; |
| 197 | case 7: SStream_concat(OS, "ord"); break; |
| 198 | case 8: SStream_concat(OS, "eq_uq"); break; |
| 199 | case 9: SStream_concat(OS, "nge"); break; |
| 200 | case 0xa: SStream_concat(OS, "ngt"); break; |
| 201 | case 0xb: SStream_concat(OS, "false"); break; |
| 202 | case 0xc: SStream_concat(OS, "neq_oq"); break; |
| 203 | case 0xd: SStream_concat(OS, "ge"); break; |
| 204 | case 0xe: SStream_concat(OS, "gt"); break; |
| 205 | case 0xf: SStream_concat(OS, "true"); break; |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | static void printAVXCC(MCInst *MI, unsigned Op, SStream *O) |
| 210 | { |
| 211 | int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f; |
| 212 | switch (Imm) { |
| 213 | default: printf("Invalid avxcc argument!\n"); break; |
| 214 | case 0: SStream_concat(O, "eq"); break; |
| 215 | case 1: SStream_concat(O, "lt"); break; |
| 216 | case 2: SStream_concat(O, "le"); break; |
| 217 | case 3: SStream_concat(O, "unord"); break; |
| 218 | case 4: SStream_concat(O, "neq"); break; |
| 219 | case 5: SStream_concat(O, "nlt"); break; |
| 220 | case 6: SStream_concat(O, "nle"); break; |
| 221 | case 7: SStream_concat(O, "ord"); break; |
| 222 | case 8: SStream_concat(O, "eq_uq"); break; |
| 223 | case 9: SStream_concat(O, "nge"); break; |
| 224 | case 0xa: SStream_concat(O, "ngt"); break; |
| 225 | case 0xb: SStream_concat(O, "false"); break; |
| 226 | case 0xc: SStream_concat(O, "neq_oq"); break; |
| 227 | case 0xd: SStream_concat(O, "ge"); break; |
| 228 | case 0xe: SStream_concat(O, "gt"); break; |
| 229 | case 0xf: SStream_concat(O, "true"); break; |
| 230 | case 0x10: SStream_concat(O, "eq_os"); break; |
| 231 | case 0x11: SStream_concat(O, "lt_oq"); break; |
| 232 | case 0x12: SStream_concat(O, "le_oq"); break; |
| 233 | case 0x13: SStream_concat(O, "unord_s"); break; |
| 234 | case 0x14: SStream_concat(O, "neq_us"); break; |
| 235 | case 0x15: SStream_concat(O, "nlt_uq"); break; |
| 236 | case 0x16: SStream_concat(O, "nle_uq"); break; |
| 237 | case 0x17: SStream_concat(O, "ord_s"); break; |
| 238 | case 0x18: SStream_concat(O, "eq_us"); break; |
| 239 | case 0x19: SStream_concat(O, "nge_uq"); break; |
| 240 | case 0x1a: SStream_concat(O, "ngt_uq"); break; |
| 241 | case 0x1b: SStream_concat(O, "false_os"); break; |
| 242 | case 0x1c: SStream_concat(O, "neq_os"); break; |
| 243 | case 0x1d: SStream_concat(O, "ge_oq"); break; |
| 244 | case 0x1e: SStream_concat(O, "gt_oq"); break; |
| 245 | case 0x1f: SStream_concat(O, "true_us"); break; |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | /// printPCRelImm - This is used to print an immediate value that ends up |
| 250 | /// being encoded as a pc-relative value (e.g. for jumps and calls). These |
| 251 | /// print slightly differently than normal immediates. For example, a $ is not |
| 252 | /// emitted. |
| 253 | static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) |
| 254 | { |
| 255 | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
| 256 | if (MCOperand_isImm(Op)) { |
| 257 | int64_t imm = MCOperand_getImm(Op) + MI->pub_insn.size + MI->pub_insn.address; |
| 258 | if (imm < 0) |
| 259 | SStream_concat(O, "-0x%"PRIx64, -imm); |
| 260 | else |
| 261 | SStream_concat(O, "0x%"PRIx64, imm); |
| 262 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_IMM; |
| 263 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].imm = imm; |
| 264 | MI->pub_insn.x86.op_count++; |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
| 269 | { |
| 270 | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
| 271 | if (MCOperand_isReg(Op)) { |
| 272 | printRegName(O, MCOperand_getReg(Op)); |
| 273 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_REG; |
| 274 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].reg = MCOperand_getReg(Op); |
| 275 | MI->pub_insn.x86.op_count++; |
| 276 | } else if (MCOperand_isImm(Op)) { |
| 277 | // Print X86 immediates as signed values. |
| 278 | int64_t imm = MCOperand_getImm(Op); |
Nguyen Anh Quynh | 8fcec67 | 2013-12-02 22:03:30 +0800 | [diff] [blame] | 279 | SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">")); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 280 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_IMM; |
| 281 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].imm = imm; |
| 282 | MI->pub_insn.x86.op_count++; |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | // local printOperand, without updating public operands |
| 287 | static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
| 288 | { |
| 289 | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
| 290 | if (MCOperand_isReg(Op)) { |
| 291 | printRegName(O, MCOperand_getReg(Op)); |
| 292 | } else if (MCOperand_isImm(Op)) { |
| 293 | // Print X86 immediates as signed values. |
| 294 | int64_t imm = MCOperand_getImm(Op); |
| 295 | if (imm < 0) |
| 296 | SStream_concat(O, "%s$-0x%"PRIx64"%s", markup("<imm:"), -imm, markup(">")); |
| 297 | else |
| 298 | SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">")); |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | static void printMemReference(MCInst *MI, unsigned Op, SStream *O) |
| 303 | { |
| 304 | MCOperand *BaseReg = MCInst_getOperand(MI, Op); |
| 305 | MCOperand *IndexReg = MCInst_getOperand(MI, Op+2); |
| 306 | MCOperand *DispSpec = MCInst_getOperand(MI, Op+3); |
| 307 | MCOperand *SegReg = MCInst_getOperand(MI, Op+4); |
| 308 | |
| 309 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_MEM; |
| 310 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.base = MCOperand_getReg(BaseReg); |
| 311 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.index = MCOperand_getReg(IndexReg); |
| 312 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.scale = 1; |
| 313 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.disp = 0; |
| 314 | |
| 315 | SStream_concat(O, markup("<mem:")); |
| 316 | |
| 317 | // If this has a segment register, print it. |
| 318 | if (MCOperand_getReg(SegReg)) { |
| 319 | _printOperand(MI, Op+4, O); |
| 320 | SStream_concat(O, ":"); |
| 321 | } |
| 322 | |
| 323 | if (MCOperand_isImm(DispSpec)) { |
| 324 | int64_t DispVal = MCOperand_getImm(DispSpec); |
| 325 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.disp = DispVal; |
| 326 | if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) { |
| 327 | if (DispVal < 0) |
| 328 | SStream_concat(O, "-0x%"PRIx64, -DispVal); |
| 329 | else |
| 330 | SStream_concat(O, "0x%"PRIx64, DispVal); |
| 331 | } |
| 332 | } |
| 333 | |
| 334 | if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { |
| 335 | SStream_concat(O, "("); |
| 336 | |
| 337 | if (MCOperand_getReg(BaseReg)) |
| 338 | _printOperand(MI, Op, O); |
| 339 | |
| 340 | if (MCOperand_getReg(IndexReg)) { |
| 341 | SStream_concat(O, ", "); |
| 342 | _printOperand(MI, Op+2, O); |
| 343 | unsigned ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1)); |
| 344 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.scale = ScaleVal; |
| 345 | if (ScaleVal != 1) { |
| 346 | SStream_concat(O, ", %s%u%s", markup("<imm:"), ScaleVal, markup(">")); |
| 347 | } |
| 348 | } |
| 349 | SStream_concat(O, ")"); |
| 350 | } |
| 351 | |
| 352 | SStream_concat(O, markup(">")); |
| 353 | |
| 354 | MI->pub_insn.x86.op_count++; |
| 355 | } |
| 356 | |
| 357 | #include "X86InstPrinter.h" |
| 358 | |
| 359 | #define GET_INSTRINFO_ENUM |
| 360 | #include "X86GenInstrInfo.inc" |
| 361 | |
| 362 | #define GET_REGINFO_ENUM |
| 363 | #include "X86GenRegisterInfo.inc" |
| 364 | |
| 365 | // Include the auto-generated portion of the assembly writer. |
| 366 | #define PRINT_ALIAS_INSTR |
| 367 | #include "X86GenAsmWriter.inc" |
| 368 | |
| 369 | static void printRegName(SStream *OS, unsigned RegNo) |
| 370 | { |
| 371 | SStream_concat(OS, "%s%%%s%s", markup("<reg:"), getRegisterName(RegNo), markup(">")); |
| 372 | } |
| 373 | |
| 374 | // get the first op from the asm buffer |
| 375 | // NOTE: make sure firstop is big enough to contain the resulted string |
| 376 | static void get_last_op(char *buffer, char *lastop) |
| 377 | { |
| 378 | char *comma = strrchr(buffer, ','); |
| 379 | if (comma) { |
| 380 | // skip a space after the comma |
| 381 | strcpy(lastop, comma + 2); |
| 382 | } else // no op |
| 383 | lastop[0] = '\0'; |
| 384 | } |
| 385 | |
| 386 | void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) |
| 387 | { |
| 388 | // FIXME |
| 389 | //const MCInstrDesc *Desc = MII.get(MI->getOpcode()); |
| 390 | //uint64_t TSFlags = Desc.TSFlags; |
| 391 | |
| 392 | //if (TSFlags & X86II::LOCK) |
| 393 | // OS << "\tlock\n"; |
| 394 | |
| 395 | // Try to print any aliases first. |
| 396 | if (printAliasInstr(MI, OS)) { |
| 397 | char *mnem = strdup(OS->buffer); |
| 398 | char *tab = strchr(mnem, '\t'); |
| 399 | if (tab) |
| 400 | *tab = '\0'; |
| 401 | // reflect the new insn name (alias) in the opcode |
| 402 | MCInst_setOpcode(MI, X86_get_insn_id2(X86_map_insn(mnem))); |
| 403 | free(mnem); |
| 404 | } else |
| 405 | printInstruction(MI, OS); |
| 406 | |
| 407 | // first op can be embedded in the asm by llvm. |
| 408 | // so we have to handle that case to not miss the first op. |
| 409 | char lastop[32]; |
| 410 | get_last_op(OS->buffer, lastop); |
| 411 | char *acc_regs[] = {"rax", "eax", "ax", "al", NULL}; |
| 412 | if (lastop[0] == '%' && str_in_list(acc_regs, lastop+1)) { |
| 413 | // this is one of the registers AL, AX, EAX, RAX |
| 414 | // canonicalize the register name first |
| 415 | //int i; |
| 416 | //for (i = 1; lastop[i]; i++) |
| 417 | // lastop[i] = tolower(lastop[i]); |
| 418 | if (MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count - 1].type != X86_OP_REG) { |
| 419 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_REG; |
| 420 | MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].reg = x86_map_regname(lastop + 1); |
| 421 | MI->pub_insn.x86.op_count++; |
| 422 | } |
| 423 | } |
| 424 | } |
| 425 | |