Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / capstone / c80d840ffce9f9bcb1ab0aeb9e890884cad7ebbf / . / include / xcore.h
blob: 5bc67705f88977707f8674f6d3666f036db38cd9 [file] [log] [blame]
Nguyen Anh Quynhc80d8402014-05-26 23:02:48 +0800[diff] [blame^]1#ifndef CAPSTONE_XCORE_H
2#define CAPSTONE_XCORE_H
3
4/* Capstone Disassembly Engine */
5/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
6
7#ifdef __cplusplus
8extern "C" {
9#endif
10
11#include <stdint.h>
12#include "platform.h"
13
14#ifdef _MSC_VER
15#pragma warning(disable:4201)
16#endif
17
18//> Operand type for instruction's operands
19typedef enum xcore_op_type {
20 XCORE_OP_INVALID = 0, // Uninitialized.
21 XCORE_OP_REG, // Register operand.
22 XCORE_OP_IMM, // Immediate operand.
23 XCORE_OP_MEM, // Memory operand
24} xcore_op_type;
25
26// Instruction's operand referring to memory
27// This is associated with XCORE_OP_MEM operand type above
28typedef struct xcore_op_mem {
29 uint8_t base; // base register
30 uint8_t index; // index register
31 int32_t disp; // displacement/offset value
32 int direct; // +1: forward, -1: backward
33} xcore_op_mem;
34
35// Instruction operand
36typedef struct cs_xcore_op {
37 xcore_op_type type; // operand type
38 union {
39 unsigned int reg; // register value for REG operand
40 int32_t imm; // immediate value for IMM operand
41 xcore_op_mem mem; // base/disp value for MEM operand
42 };
43} cs_xcore_op;
44
45// Instruction structure
46typedef struct cs_xcore {
47 // Number of operands of this instruction,
48 // or 0 when instruction has no operand.
49 uint8_t op_count;
50 cs_xcore_op operands[8]; // operands for this instruction.
51} cs_xcore;
52
53//> XCore registers
54typedef enum xcore_reg {
55 XCORE_REG_INVALID = 0,
56
57 XCORE_REG_CP,
58 XCORE_REG_DP,
59 XCORE_REG_LR,
60 XCORE_REG_SP,
61 XCORE_REG_R0,
62 XCORE_REG_R1,
63 XCORE_REG_R2,
64 XCORE_REG_R3,
65 XCORE_REG_R4,
66 XCORE_REG_R5,
67 XCORE_REG_R6,
68 XCORE_REG_R7,
69 XCORE_REG_R8,
70 XCORE_REG_R9,
71 XCORE_REG_R10,
72 XCORE_REG_R11,
73
74 XCORE_REG_MAX,
75} xcore_reg;
76
77//> XCore instruction
78typedef enum xcore_insn {
79 XCORE_INS_INVALID = 0,
80
81 XCORE_INS_ADD,
82 XCORE_INS_ANDNOT,
83 XCORE_INS_AND,
84 XCORE_INS_ASHR,
85 XCORE_INS_BAU,
86 XCORE_INS_BITREV,
87 XCORE_INS_BLA,
88 XCORE_INS_BLAT,
89 XCORE_INS_BL,
90 XCORE_INS_BF,
91 XCORE_INS_BT,
92 XCORE_INS_BU,
93 XCORE_INS_BRU,
94 XCORE_INS_BYTEREV,
95 XCORE_INS_CHKCT,
96 XCORE_INS_CLRE,
97 XCORE_INS_CLRPT,
98 XCORE_INS_CLRSR,
99 XCORE_INS_CLZ,
100 XCORE_INS_CRC8,
101 XCORE_INS_CRC32,
102 XCORE_INS_DCALL,
103 XCORE_INS_DENTSP,
104 XCORE_INS_DGETREG,
105 XCORE_INS_DIVS,
106 XCORE_INS_DIVU,
107 XCORE_INS_DRESTSP,
108 XCORE_INS_DRET,
109 XCORE_INS_ECALLF,
110 XCORE_INS_ECALLT,
111 XCORE_INS_EDU,
112 XCORE_INS_EEF,
113 XCORE_INS_EET,
114 XCORE_INS_EEU,
115 XCORE_INS_ENDIN,
116 XCORE_INS_ENTSP,
117 XCORE_INS_EQ,
118 XCORE_INS_EXTDP,
119 XCORE_INS_EXTSP,
120 XCORE_INS_FREER,
121 XCORE_INS_FREET,
122 XCORE_INS_GETD,
123 XCORE_INS_GET,
124 XCORE_INS_GETN,
125 XCORE_INS_GETR,
126 XCORE_INS_GETSR,
127 XCORE_INS_GETST,
128 XCORE_INS_GETTS,
129 XCORE_INS_INCT,
130 XCORE_INS_INIT,
131 XCORE_INS_INPW,
132 XCORE_INS_INSHR,
133 XCORE_INS_INT,
134 XCORE_INS_IN,
135 XCORE_INS_KCALL,
136 XCORE_INS_KENTSP,
137 XCORE_INS_KRESTSP,
138 XCORE_INS_KRET,
139 XCORE_INS_LADD,
140 XCORE_INS_LD16S,
141 XCORE_INS_LD8U,
142 XCORE_INS_LDA16,
143 XCORE_INS_LDAP,
144 XCORE_INS_LDAW,
145 XCORE_INS_LDC,
146 XCORE_INS_LDW,
147 XCORE_INS_LDIVU,
148 XCORE_INS_LMUL,
149 XCORE_INS_LSS,
150 XCORE_INS_LSUB,
151 XCORE_INS_LSU,
152 XCORE_INS_MACCS,
153 XCORE_INS_MACCU,
154 XCORE_INS_MJOIN,
155 XCORE_INS_MKMSK,
156 XCORE_INS_MSYNC,
157 XCORE_INS_MUL,
158 XCORE_INS_NEG,
159 XCORE_INS_NOT,
160 XCORE_INS_OR,
161 XCORE_INS_OUTCT,
162 XCORE_INS_OUTPW,
163 XCORE_INS_OUTSHR,
164 XCORE_INS_OUTT,
165 XCORE_INS_OUT,
166 XCORE_INS_PEEK,
167 XCORE_INS_REMS,
168 XCORE_INS_REMU,
169 XCORE_INS_RETSP,
170 XCORE_INS_SETCLK,
171 XCORE_INS_SET,
172 XCORE_INS_SETC,
173 XCORE_INS_SETD,
174 XCORE_INS_SETEV,
175 XCORE_INS_SETN,
176 XCORE_INS_SETPSC,
177 XCORE_INS_SETPT,
178 XCORE_INS_SETRDY,
179 XCORE_INS_SETSR,
180 XCORE_INS_SETTW,
181 XCORE_INS_SETV,
182 XCORE_INS_SEXT,
183 XCORE_INS_SHL,
184 XCORE_INS_SHR,
185 XCORE_INS_SSYNC,
186 XCORE_INS_ST16,
187 XCORE_INS_ST8,
188 XCORE_INS_STW,
189 XCORE_INS_SUB,
190 XCORE_INS_SYNCR,
191 XCORE_INS_TESTCT,
192 XCORE_INS_TESTLCL,
193 XCORE_INS_TESTWCT,
194 XCORE_INS_TSETMR,
195 XCORE_INS_START,
196 XCORE_INS_WAITEF,
197 XCORE_INS_WAITET,
198 XCORE_INS_WAITEU,
199 XCORE_INS_XOR,
200 XCORE_INS_ZEXT,
201
202 XCORE_INS_MAX, // <-- mark the end of the list of instructions
203} xcore_insn;
204
205//> Group of XCore instructions
206typedef enum xcore_insn_group {
207 XCORE_GRP_INVALID = 0,
208
209 XCORE_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
210
211 XCORE_GRP_MAX, // <-- mark the end of the list of groups
212} xcore_insn_group;
213
214#ifdef __cplusplus
215}
216#endif
217
218#endif