Nguyen Anh Quynh | dd40750 | 2014-01-19 23:51:34 +0800 | [diff] [blame] | 1 | #ifndef CAPSTONE_ARM_H |
| 2 | #define CAPSTONE_ARM_H |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 3 | |
Nguyen Anh Quynh | 7751fbe | 2014-04-28 11:23:14 +0800 | [diff] [blame] | 4 | /* Capstone Disassembly Engine */ |
| 5 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 6 | |
| 7 | #ifdef __cplusplus |
| 8 | extern "C" { |
| 9 | #endif |
| 10 | |
| 11 | #include <stdint.h> |
Nguyen Anh Quynh | cb59106 | 2014-05-15 21:51:02 +0800 | [diff] [blame] | 12 | #include "platform.h" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 13 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 14 | #ifdef _MSC_VER |
| 15 | #pragma warning(disable:4201) |
| 16 | #endif |
| 17 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 18 | //> ARM shift type |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 19 | typedef enum arm_shifter { |
| 20 | ARM_SFT_INVALID = 0, |
| 21 | ARM_SFT_ASR, // shift with immediate const |
| 22 | ARM_SFT_LSL, // shift with immediate const |
| 23 | ARM_SFT_LSR, // shift with immediate const |
| 24 | ARM_SFT_ROR, // shift with immediate const |
| 25 | ARM_SFT_RRX, // shift with immediate const |
| 26 | ARM_SFT_ASR_REG, // shift with register |
| 27 | ARM_SFT_LSL_REG, // shift with register |
| 28 | ARM_SFT_LSR_REG, // shift with register |
| 29 | ARM_SFT_ROR_REG, // shift with register |
| 30 | ARM_SFT_RRX_REG, // shift with register |
| 31 | } arm_shifter; |
| 32 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 33 | //> ARM condition code |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 34 | typedef enum arm_cc { |
| 35 | ARM_CC_INVALID = 0, |
| 36 | ARM_CC_EQ, // Equal Equal |
| 37 | ARM_CC_NE, // Not equal Not equal, or unordered |
| 38 | ARM_CC_HS, // Carry set >, ==, or unordered |
| 39 | ARM_CC_LO, // Carry clear Less than |
| 40 | ARM_CC_MI, // Minus, negative Less than |
| 41 | ARM_CC_PL, // Plus, positive or zero >, ==, or unordered |
| 42 | ARM_CC_VS, // Overflow Unordered |
| 43 | ARM_CC_VC, // No overflow Not unordered |
| 44 | ARM_CC_HI, // Unsigned higher Greater than, or unordered |
| 45 | ARM_CC_LS, // Unsigned lower or same Less than or equal |
| 46 | ARM_CC_GE, // Greater than or equal Greater than or equal |
| 47 | ARM_CC_LT, // Less than Less than, or unordered |
| 48 | ARM_CC_GT, // Greater than Greater than |
| 49 | ARM_CC_LE, // Less than or equal <, ==, or unordered |
| 50 | ARM_CC_AL // Always (unconditional) Always (unconditional) |
| 51 | } arm_cc; |
| 52 | |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 53 | typedef enum arm_sysreg { |
| 54 | //> Special registers for MSR |
| 55 | ARM_SYSREG_INVALID = 0, |
| 56 | |
| 57 | // SPSR* registers can be OR combined |
| 58 | ARM_SYSREG_SPSR_C = 1, |
| 59 | ARM_SYSREG_SPSR_X = 2, |
| 60 | ARM_SYSREG_SPSR_S = 4, |
| 61 | ARM_SYSREG_SPSR_F = 8, |
| 62 | |
| 63 | // CPSR* registers can be OR combined |
| 64 | ARM_SYSREG_CPSR_C = 16, |
| 65 | ARM_SYSREG_CPSR_X = 32, |
| 66 | ARM_SYSREG_CPSR_S = 64, |
| 67 | ARM_SYSREG_CPSR_F = 128, |
| 68 | |
| 69 | // independent registers |
| 70 | ARM_SYSREG_APSR = 256, |
| 71 | ARM_SYSREG_APSR_G, |
| 72 | ARM_SYSREG_APSR_NZCVQ, |
| 73 | ARM_SYSREG_APSR_NZCVQG, |
| 74 | |
| 75 | ARM_SYSREG_IAPSR, |
| 76 | ARM_SYSREG_IAPSR_G, |
| 77 | ARM_SYSREG_IAPSR_NZCVQG, |
| 78 | |
| 79 | ARM_SYSREG_EAPSR, |
| 80 | ARM_SYSREG_EAPSR_G, |
| 81 | ARM_SYSREG_EAPSR_NZCVQG, |
| 82 | |
| 83 | ARM_SYSREG_XPSR, |
| 84 | ARM_SYSREG_XPSR_G, |
| 85 | ARM_SYSREG_XPSR_NZCVQG, |
| 86 | |
| 87 | ARM_SYSREG_IPSR, |
| 88 | ARM_SYSREG_EPSR, |
| 89 | ARM_SYSREG_IEPSR, |
| 90 | |
| 91 | ARM_SYSREG_MSP, |
| 92 | ARM_SYSREG_PSP, |
| 93 | ARM_SYSREG_PRIMASK, |
| 94 | ARM_SYSREG_BASEPRI, |
| 95 | ARM_SYSREG_BASEPRI_MAX, |
| 96 | ARM_SYSREG_FAULTMASK, |
| 97 | ARM_SYSREG_CONTROL, |
| 98 | } arm_sysreg; |
| 99 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 100 | //> Operand type for instruction's operands |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 101 | typedef enum arm_op_type { |
| 102 | ARM_OP_INVALID = 0, // Uninitialized. |
| 103 | ARM_OP_REG, // Register operand. |
Nguyen Anh Quynh | df3fb00 | 2013-12-19 12:41:32 +0800 | [diff] [blame] | 104 | ARM_OP_CIMM, // C-Immediate (coprocessor registers) |
| 105 | ARM_OP_PIMM, // P-Immediate (coprocessor registers) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 106 | ARM_OP_IMM, // Immediate operand. |
| 107 | ARM_OP_FP, // Floating-Point immediate operand. |
| 108 | ARM_OP_MEM, // Memory operand |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 109 | ARM_OP_SETEND, // operand for SETEND instruction |
| 110 | ARM_OP_SYSREG, // MSR/MSR special register operand |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 111 | } arm_op_type; |
| 112 | |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 113 | //> Operand type for SETEND instruction |
| 114 | typedef enum arm_setend_type { |
| 115 | ARM_SETEND_INVALID = 0, // Uninitialized. |
| 116 | ARM_SETEND_BE, // BE operand. |
| 117 | ARM_SETEND_LE, // LE operand |
| 118 | } arm_setend_type; |
| 119 | |
| 120 | typedef enum arm_cpsmode_type { |
| 121 | ARM_CPSMODE_INVALID = 0, |
| 122 | ARM_CPSMODE_IE = 2, |
| 123 | ARM_CPSMODE_ID = 3 |
| 124 | } arm_cpsmode_type; |
| 125 | |
| 126 | //> Operand type for SETEND instruction |
| 127 | typedef enum arm_cpsflag_type { |
| 128 | ARM_CPSFLAG_INVALID = 0, |
| 129 | ARM_CPSFLAG_F = 1, |
| 130 | ARM_CPSFLAG_I = 2, |
| 131 | ARM_CPSFLAG_A = 4, |
| 132 | ARM_CPSFLAG_NONE = 16, // no flag |
| 133 | } arm_cpsflag_type; |
| 134 | |
| 135 | //> Data type for elements of vector instructions. |
| 136 | typedef enum arm_vectordata_type { |
| 137 | ARM_VECTORDATA_INVALID = 0, |
| 138 | |
| 139 | // Integer type |
| 140 | ARM_VECTORDATA_I8, |
| 141 | ARM_VECTORDATA_I16, |
| 142 | ARM_VECTORDATA_I32, |
| 143 | ARM_VECTORDATA_I64, |
| 144 | |
| 145 | // Signed integer type |
| 146 | ARM_VECTORDATA_S8, |
| 147 | ARM_VECTORDATA_S16, |
| 148 | ARM_VECTORDATA_S32, |
| 149 | ARM_VECTORDATA_S64, |
| 150 | |
| 151 | // Unsigned integer type |
| 152 | ARM_VECTORDATA_U8, |
| 153 | ARM_VECTORDATA_U16, |
| 154 | ARM_VECTORDATA_U32, |
| 155 | ARM_VECTORDATA_U64, |
| 156 | |
| 157 | // Data type for VMUL/VMULL |
| 158 | ARM_VECTORDATA_P8, |
| 159 | |
| 160 | // Floating type |
| 161 | ARM_VECTORDATA_F32, |
| 162 | ARM_VECTORDATA_F64, |
| 163 | |
| 164 | // Convert float <-> float |
| 165 | ARM_VECTORDATA_F16F64, // f16.f64 |
| 166 | ARM_VECTORDATA_F64F16, // f64.f16 |
| 167 | ARM_VECTORDATA_F32F16, // f32.f16 |
| 168 | ARM_VECTORDATA_F16F32, // f32.f16 |
| 169 | ARM_VECTORDATA_F64F32, // f64.f32 |
| 170 | ARM_VECTORDATA_F32F64, // f32.f64 |
| 171 | |
| 172 | // Convert integer <-> float |
| 173 | ARM_VECTORDATA_S32F32, // s32.f32 |
| 174 | ARM_VECTORDATA_U32F32, // u32.f32 |
| 175 | ARM_VECTORDATA_F32S32, // f32.s32 |
| 176 | ARM_VECTORDATA_F32U32, // f32.u32 |
| 177 | ARM_VECTORDATA_F64S16, // f64.s16 |
| 178 | ARM_VECTORDATA_F32S16, // f32.s16 |
| 179 | ARM_VECTORDATA_F64S32, // f64.s32 |
| 180 | ARM_VECTORDATA_S16F64, // s16.f64 |
| 181 | ARM_VECTORDATA_S16F32, // s16.f64 |
| 182 | ARM_VECTORDATA_S32F64, // s32.f64 |
| 183 | ARM_VECTORDATA_U16F64, // u16.f64 |
| 184 | ARM_VECTORDATA_U16F32, // u16.f32 |
| 185 | ARM_VECTORDATA_U32F64, // u32.f64 |
| 186 | ARM_VECTORDATA_F64U16, // f64.u16 |
| 187 | ARM_VECTORDATA_F32U16, // f32.u16 |
| 188 | ARM_VECTORDATA_F64U32, // f64.u32 |
| 189 | } arm_vectordata_type; |
| 190 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 191 | // Instruction's operand referring to memory |
| 192 | // This is associated with ARM_OP_MEM operand type above |
| 193 | typedef struct arm_op_mem { |
| 194 | unsigned int base; // base register |
| 195 | unsigned int index; // index register |
| 196 | int scale; // scale for index register (can be 1, or -1) |
Nguyen Anh Quynh | b42a657 | 2013-11-29 17:40:07 +0800 | [diff] [blame] | 197 | int disp; // displacement/offset value |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 198 | } arm_op_mem; |
| 199 | |
| 200 | // Instruction operand |
| 201 | typedef struct cs_arm_op { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 202 | int vector_index; // Vector Index for some vector operands (or -1 if irrelevant) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 203 | struct { |
| 204 | arm_shifter type; |
| 205 | unsigned int value; |
| 206 | } shift; |
| 207 | arm_op_type type; // operand type |
| 208 | union { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 209 | unsigned int reg; // register value for REG/SYSREG operand |
Jason Oster | aa60b8c | 2014-05-23 21:55:04 -0700 | [diff] [blame] | 210 | int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 211 | double fp; // floating point value for FP operand |
| 212 | arm_op_mem mem; // base/index/scale/disp value for MEM operand |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 213 | arm_setend_type setend; // SETEND instruction's operand type |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 214 | }; |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 215 | // in some instructions, an operand can be subtracted or added to |
| 216 | // the base register, |
| 217 | bool subtracted; // if TRUE, this operand is subtracted. otherwise, it is added. |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 218 | } cs_arm_op; |
| 219 | |
| 220 | // Instruction structure |
| 221 | typedef struct cs_arm { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 222 | bool usermode; // User-mode registers to be loaded (for LDM/STM instructions) |
| 223 | int vector_size; // Scalar size for vector instructions |
| 224 | arm_vectordata_type vector_data; // Data type for elements of vector instructions |
| 225 | arm_cpsmode_type cps_mode; // CPS mode for CPS instruction |
| 226 | arm_cpsflag_type cps_flag; // CPS mode for CPS instruction |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 227 | arm_cc cc; // conditional code for this insn |
| 228 | bool update_flags; // does this insn update flags? |
| 229 | bool writeback; // does this insn write-back? |
| 230 | |
| 231 | // Number of operands of this instruction, |
| 232 | // or 0 when instruction has no operand. |
| 233 | uint8_t op_count; |
| 234 | |
Nguyen Anh Quynh | b99aec8 | 2014-01-13 23:29:39 +0800 | [diff] [blame] | 235 | cs_arm_op operands[36]; // operands for this instruction. |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 236 | } cs_arm; |
| 237 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 238 | //> ARM registers |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 239 | typedef enum arm_reg { |
| 240 | ARM_REG_INVALID = 0, |
| 241 | ARM_REG_APSR, |
| 242 | ARM_REG_APSR_NZCV, |
| 243 | ARM_REG_CPSR, |
| 244 | ARM_REG_FPEXC, |
| 245 | ARM_REG_FPINST, |
| 246 | ARM_REG_FPSCR, |
| 247 | ARM_REG_FPSCR_NZCV, |
| 248 | ARM_REG_FPSID, |
| 249 | ARM_REG_ITSTATE, |
| 250 | ARM_REG_LR, |
| 251 | ARM_REG_PC, |
| 252 | ARM_REG_SP, |
| 253 | ARM_REG_SPSR, |
| 254 | ARM_REG_D0, |
| 255 | ARM_REG_D1, |
| 256 | ARM_REG_D2, |
| 257 | ARM_REG_D3, |
| 258 | ARM_REG_D4, |
| 259 | ARM_REG_D5, |
| 260 | ARM_REG_D6, |
| 261 | ARM_REG_D7, |
| 262 | ARM_REG_D8, |
| 263 | ARM_REG_D9, |
| 264 | ARM_REG_D10, |
| 265 | ARM_REG_D11, |
| 266 | ARM_REG_D12, |
| 267 | ARM_REG_D13, |
| 268 | ARM_REG_D14, |
| 269 | ARM_REG_D15, |
| 270 | ARM_REG_D16, |
| 271 | ARM_REG_D17, |
| 272 | ARM_REG_D18, |
| 273 | ARM_REG_D19, |
| 274 | ARM_REG_D20, |
| 275 | ARM_REG_D21, |
| 276 | ARM_REG_D22, |
| 277 | ARM_REG_D23, |
| 278 | ARM_REG_D24, |
| 279 | ARM_REG_D25, |
| 280 | ARM_REG_D26, |
| 281 | ARM_REG_D27, |
| 282 | ARM_REG_D28, |
| 283 | ARM_REG_D29, |
| 284 | ARM_REG_D30, |
| 285 | ARM_REG_D31, |
| 286 | ARM_REG_FPINST2, |
| 287 | ARM_REG_MVFR0, |
| 288 | ARM_REG_MVFR1, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 289 | ARM_REG_MVFR2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 290 | ARM_REG_Q0, |
| 291 | ARM_REG_Q1, |
| 292 | ARM_REG_Q2, |
| 293 | ARM_REG_Q3, |
| 294 | ARM_REG_Q4, |
| 295 | ARM_REG_Q5, |
| 296 | ARM_REG_Q6, |
| 297 | ARM_REG_Q7, |
| 298 | ARM_REG_Q8, |
| 299 | ARM_REG_Q9, |
| 300 | ARM_REG_Q10, |
| 301 | ARM_REG_Q11, |
| 302 | ARM_REG_Q12, |
| 303 | ARM_REG_Q13, |
| 304 | ARM_REG_Q14, |
| 305 | ARM_REG_Q15, |
| 306 | ARM_REG_R0, |
| 307 | ARM_REG_R1, |
| 308 | ARM_REG_R2, |
| 309 | ARM_REG_R3, |
| 310 | ARM_REG_R4, |
| 311 | ARM_REG_R5, |
| 312 | ARM_REG_R6, |
| 313 | ARM_REG_R7, |
| 314 | ARM_REG_R8, |
| 315 | ARM_REG_R9, |
| 316 | ARM_REG_R10, |
| 317 | ARM_REG_R11, |
| 318 | ARM_REG_R12, |
| 319 | ARM_REG_S0, |
| 320 | ARM_REG_S1, |
| 321 | ARM_REG_S2, |
| 322 | ARM_REG_S3, |
| 323 | ARM_REG_S4, |
| 324 | ARM_REG_S5, |
| 325 | ARM_REG_S6, |
| 326 | ARM_REG_S7, |
| 327 | ARM_REG_S8, |
| 328 | ARM_REG_S9, |
| 329 | ARM_REG_S10, |
| 330 | ARM_REG_S11, |
| 331 | ARM_REG_S12, |
| 332 | ARM_REG_S13, |
| 333 | ARM_REG_S14, |
| 334 | ARM_REG_S15, |
| 335 | ARM_REG_S16, |
| 336 | ARM_REG_S17, |
| 337 | ARM_REG_S18, |
| 338 | ARM_REG_S19, |
| 339 | ARM_REG_S20, |
| 340 | ARM_REG_S21, |
| 341 | ARM_REG_S22, |
| 342 | ARM_REG_S23, |
| 343 | ARM_REG_S24, |
| 344 | ARM_REG_S25, |
| 345 | ARM_REG_S26, |
| 346 | ARM_REG_S27, |
| 347 | ARM_REG_S28, |
| 348 | ARM_REG_S29, |
| 349 | ARM_REG_S30, |
| 350 | ARM_REG_S31, |
Nguyen Anh Quynh | b39ef0b | 2013-12-04 11:52:28 +0800 | [diff] [blame] | 351 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 352 | ARM_REG_ENDING, // <-- mark the end of the list or registers |
Nguyen Anh Quynh | b39ef0b | 2013-12-04 11:52:28 +0800 | [diff] [blame] | 353 | |
Nguyen Anh Quynh | d06e2f5 | 2013-12-19 16:50:57 +0800 | [diff] [blame] | 354 | //> alias registers |
Nguyen Anh Quynh | b39ef0b | 2013-12-04 11:52:28 +0800 | [diff] [blame] | 355 | ARM_REG_R13 = ARM_REG_SP, |
| 356 | ARM_REG_R14 = ARM_REG_LR, |
| 357 | ARM_REG_R15 = ARM_REG_PC, |
Nguyen Anh Quynh | d06e2f5 | 2013-12-19 16:50:57 +0800 | [diff] [blame] | 358 | |
| 359 | ARM_REG_SB = ARM_REG_R9, |
| 360 | ARM_REG_SL = ARM_REG_R10, |
| 361 | ARM_REG_FP = ARM_REG_R11, |
| 362 | ARM_REG_IP = ARM_REG_R12, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 363 | } arm_reg; |
| 364 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 365 | //> ARM instruction |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 366 | typedef enum arm_insn { |
| 367 | ARM_INS_INVALID = 0, |
Nguyen Anh Quynh | 9cc56a3 | 2014-01-15 16:01:55 +0800 | [diff] [blame] | 368 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 369 | ARM_INS_ADC, |
| 370 | ARM_INS_ADD, |
| 371 | ARM_INS_ADR, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 372 | ARM_INS_AESD, |
| 373 | ARM_INS_AESE, |
| 374 | ARM_INS_AESIMC, |
| 375 | ARM_INS_AESMC, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 376 | ARM_INS_AND, |
| 377 | ARM_INS_BFC, |
| 378 | ARM_INS_BFI, |
| 379 | ARM_INS_BIC, |
| 380 | ARM_INS_BKPT, |
| 381 | ARM_INS_BL, |
| 382 | ARM_INS_BLX, |
| 383 | ARM_INS_BX, |
| 384 | ARM_INS_BXJ, |
| 385 | ARM_INS_B, |
| 386 | ARM_INS_CDP, |
| 387 | ARM_INS_CDP2, |
| 388 | ARM_INS_CLREX, |
| 389 | ARM_INS_CLZ, |
| 390 | ARM_INS_CMN, |
| 391 | ARM_INS_CMP, |
| 392 | ARM_INS_CPS, |
| 393 | ARM_INS_CRC32B, |
| 394 | ARM_INS_CRC32CB, |
| 395 | ARM_INS_CRC32CH, |
| 396 | ARM_INS_CRC32CW, |
| 397 | ARM_INS_CRC32H, |
| 398 | ARM_INS_CRC32W, |
| 399 | ARM_INS_DBG, |
| 400 | ARM_INS_DMB, |
| 401 | ARM_INS_DSB, |
| 402 | ARM_INS_EOR, |
| 403 | ARM_INS_VMOV, |
| 404 | ARM_INS_FLDMDBX, |
| 405 | ARM_INS_FLDMIAX, |
| 406 | ARM_INS_VMRS, |
| 407 | ARM_INS_FSTMDBX, |
| 408 | ARM_INS_FSTMIAX, |
| 409 | ARM_INS_HINT, |
| 410 | ARM_INS_HLT, |
| 411 | ARM_INS_ISB, |
| 412 | ARM_INS_LDA, |
| 413 | ARM_INS_LDAB, |
| 414 | ARM_INS_LDAEX, |
| 415 | ARM_INS_LDAEXB, |
| 416 | ARM_INS_LDAEXD, |
| 417 | ARM_INS_LDAEXH, |
| 418 | ARM_INS_LDAH, |
| 419 | ARM_INS_LDC2L, |
| 420 | ARM_INS_LDC2, |
| 421 | ARM_INS_LDCL, |
| 422 | ARM_INS_LDC, |
| 423 | ARM_INS_LDMDA, |
| 424 | ARM_INS_LDMDB, |
| 425 | ARM_INS_LDM, |
| 426 | ARM_INS_LDMIB, |
| 427 | ARM_INS_LDRBT, |
| 428 | ARM_INS_LDRB, |
| 429 | ARM_INS_LDRD, |
| 430 | ARM_INS_LDREX, |
| 431 | ARM_INS_LDREXB, |
| 432 | ARM_INS_LDREXD, |
| 433 | ARM_INS_LDREXH, |
| 434 | ARM_INS_LDRH, |
| 435 | ARM_INS_LDRHT, |
| 436 | ARM_INS_LDRSB, |
| 437 | ARM_INS_LDRSBT, |
| 438 | ARM_INS_LDRSH, |
| 439 | ARM_INS_LDRSHT, |
| 440 | ARM_INS_LDRT, |
| 441 | ARM_INS_LDR, |
| 442 | ARM_INS_MCR, |
| 443 | ARM_INS_MCR2, |
| 444 | ARM_INS_MCRR, |
| 445 | ARM_INS_MCRR2, |
| 446 | ARM_INS_MLA, |
| 447 | ARM_INS_MLS, |
| 448 | ARM_INS_MOV, |
| 449 | ARM_INS_MOVT, |
| 450 | ARM_INS_MOVW, |
| 451 | ARM_INS_MRC, |
| 452 | ARM_INS_MRC2, |
| 453 | ARM_INS_MRRC, |
| 454 | ARM_INS_MRRC2, |
| 455 | ARM_INS_MRS, |
| 456 | ARM_INS_MSR, |
| 457 | ARM_INS_MUL, |
| 458 | ARM_INS_MVN, |
| 459 | ARM_INS_ORR, |
| 460 | ARM_INS_PKHBT, |
| 461 | ARM_INS_PKHTB, |
| 462 | ARM_INS_PLDW, |
| 463 | ARM_INS_PLD, |
| 464 | ARM_INS_PLI, |
| 465 | ARM_INS_QADD, |
| 466 | ARM_INS_QADD16, |
| 467 | ARM_INS_QADD8, |
| 468 | ARM_INS_QASX, |
| 469 | ARM_INS_QDADD, |
| 470 | ARM_INS_QDSUB, |
| 471 | ARM_INS_QSAX, |
| 472 | ARM_INS_QSUB, |
| 473 | ARM_INS_QSUB16, |
| 474 | ARM_INS_QSUB8, |
| 475 | ARM_INS_RBIT, |
| 476 | ARM_INS_REV, |
| 477 | ARM_INS_REV16, |
| 478 | ARM_INS_REVSH, |
| 479 | ARM_INS_RFEDA, |
| 480 | ARM_INS_RFEDB, |
| 481 | ARM_INS_RFEIA, |
| 482 | ARM_INS_RFEIB, |
| 483 | ARM_INS_RSB, |
| 484 | ARM_INS_RSC, |
| 485 | ARM_INS_SADD16, |
| 486 | ARM_INS_SADD8, |
| 487 | ARM_INS_SASX, |
| 488 | ARM_INS_SBC, |
| 489 | ARM_INS_SBFX, |
| 490 | ARM_INS_SDIV, |
| 491 | ARM_INS_SEL, |
| 492 | ARM_INS_SETEND, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 493 | ARM_INS_SHA1C, |
| 494 | ARM_INS_SHA1H, |
| 495 | ARM_INS_SHA1M, |
| 496 | ARM_INS_SHA1P, |
| 497 | ARM_INS_SHA1SU0, |
| 498 | ARM_INS_SHA1SU1, |
| 499 | ARM_INS_SHA256H, |
| 500 | ARM_INS_SHA256H2, |
| 501 | ARM_INS_SHA256SU0, |
| 502 | ARM_INS_SHA256SU1, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 503 | ARM_INS_SHADD16, |
| 504 | ARM_INS_SHADD8, |
| 505 | ARM_INS_SHASX, |
| 506 | ARM_INS_SHSAX, |
| 507 | ARM_INS_SHSUB16, |
| 508 | ARM_INS_SHSUB8, |
| 509 | ARM_INS_SMC, |
| 510 | ARM_INS_SMLABB, |
| 511 | ARM_INS_SMLABT, |
| 512 | ARM_INS_SMLAD, |
| 513 | ARM_INS_SMLADX, |
| 514 | ARM_INS_SMLAL, |
| 515 | ARM_INS_SMLALBB, |
| 516 | ARM_INS_SMLALBT, |
| 517 | ARM_INS_SMLALD, |
| 518 | ARM_INS_SMLALDX, |
| 519 | ARM_INS_SMLALTB, |
| 520 | ARM_INS_SMLALTT, |
| 521 | ARM_INS_SMLATB, |
| 522 | ARM_INS_SMLATT, |
| 523 | ARM_INS_SMLAWB, |
| 524 | ARM_INS_SMLAWT, |
| 525 | ARM_INS_SMLSD, |
| 526 | ARM_INS_SMLSDX, |
| 527 | ARM_INS_SMLSLD, |
| 528 | ARM_INS_SMLSLDX, |
| 529 | ARM_INS_SMMLA, |
| 530 | ARM_INS_SMMLAR, |
| 531 | ARM_INS_SMMLS, |
| 532 | ARM_INS_SMMLSR, |
| 533 | ARM_INS_SMMUL, |
| 534 | ARM_INS_SMMULR, |
| 535 | ARM_INS_SMUAD, |
| 536 | ARM_INS_SMUADX, |
| 537 | ARM_INS_SMULBB, |
| 538 | ARM_INS_SMULBT, |
| 539 | ARM_INS_SMULL, |
| 540 | ARM_INS_SMULTB, |
| 541 | ARM_INS_SMULTT, |
| 542 | ARM_INS_SMULWB, |
| 543 | ARM_INS_SMULWT, |
| 544 | ARM_INS_SMUSD, |
| 545 | ARM_INS_SMUSDX, |
| 546 | ARM_INS_SRSDA, |
| 547 | ARM_INS_SRSDB, |
| 548 | ARM_INS_SRSIA, |
| 549 | ARM_INS_SRSIB, |
| 550 | ARM_INS_SSAT, |
| 551 | ARM_INS_SSAT16, |
| 552 | ARM_INS_SSAX, |
| 553 | ARM_INS_SSUB16, |
| 554 | ARM_INS_SSUB8, |
| 555 | ARM_INS_STC2L, |
| 556 | ARM_INS_STC2, |
| 557 | ARM_INS_STCL, |
| 558 | ARM_INS_STC, |
| 559 | ARM_INS_STL, |
| 560 | ARM_INS_STLB, |
| 561 | ARM_INS_STLEX, |
| 562 | ARM_INS_STLEXB, |
| 563 | ARM_INS_STLEXD, |
| 564 | ARM_INS_STLEXH, |
| 565 | ARM_INS_STLH, |
| 566 | ARM_INS_STMDA, |
| 567 | ARM_INS_STMDB, |
| 568 | ARM_INS_STM, |
| 569 | ARM_INS_STMIB, |
| 570 | ARM_INS_STRBT, |
| 571 | ARM_INS_STRB, |
| 572 | ARM_INS_STRD, |
| 573 | ARM_INS_STREX, |
| 574 | ARM_INS_STREXB, |
| 575 | ARM_INS_STREXD, |
| 576 | ARM_INS_STREXH, |
| 577 | ARM_INS_STRH, |
| 578 | ARM_INS_STRHT, |
| 579 | ARM_INS_STRT, |
| 580 | ARM_INS_STR, |
| 581 | ARM_INS_SUB, |
| 582 | ARM_INS_SVC, |
| 583 | ARM_INS_SWP, |
| 584 | ARM_INS_SWPB, |
| 585 | ARM_INS_SXTAB, |
| 586 | ARM_INS_SXTAB16, |
| 587 | ARM_INS_SXTAH, |
| 588 | ARM_INS_SXTB, |
| 589 | ARM_INS_SXTB16, |
| 590 | ARM_INS_SXTH, |
| 591 | ARM_INS_TEQ, |
| 592 | ARM_INS_TRAP, |
| 593 | ARM_INS_TST, |
| 594 | ARM_INS_UADD16, |
| 595 | ARM_INS_UADD8, |
| 596 | ARM_INS_UASX, |
| 597 | ARM_INS_UBFX, |
Nguyen Anh Quynh | b52f11f | 2014-08-13 22:38:15 +0800 | [diff] [blame] | 598 | ARM_INS_UDF, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 599 | ARM_INS_UDIV, |
| 600 | ARM_INS_UHADD16, |
| 601 | ARM_INS_UHADD8, |
| 602 | ARM_INS_UHASX, |
| 603 | ARM_INS_UHSAX, |
| 604 | ARM_INS_UHSUB16, |
| 605 | ARM_INS_UHSUB8, |
| 606 | ARM_INS_UMAAL, |
| 607 | ARM_INS_UMLAL, |
| 608 | ARM_INS_UMULL, |
| 609 | ARM_INS_UQADD16, |
| 610 | ARM_INS_UQADD8, |
| 611 | ARM_INS_UQASX, |
| 612 | ARM_INS_UQSAX, |
| 613 | ARM_INS_UQSUB16, |
| 614 | ARM_INS_UQSUB8, |
| 615 | ARM_INS_USAD8, |
| 616 | ARM_INS_USADA8, |
| 617 | ARM_INS_USAT, |
| 618 | ARM_INS_USAT16, |
| 619 | ARM_INS_USAX, |
| 620 | ARM_INS_USUB16, |
| 621 | ARM_INS_USUB8, |
| 622 | ARM_INS_UXTAB, |
| 623 | ARM_INS_UXTAB16, |
| 624 | ARM_INS_UXTAH, |
| 625 | ARM_INS_UXTB, |
| 626 | ARM_INS_UXTB16, |
| 627 | ARM_INS_UXTH, |
| 628 | ARM_INS_VABAL, |
| 629 | ARM_INS_VABA, |
| 630 | ARM_INS_VABDL, |
| 631 | ARM_INS_VABD, |
| 632 | ARM_INS_VABS, |
| 633 | ARM_INS_VACGE, |
| 634 | ARM_INS_VACGT, |
| 635 | ARM_INS_VADD, |
| 636 | ARM_INS_VADDHN, |
| 637 | ARM_INS_VADDL, |
| 638 | ARM_INS_VADDW, |
| 639 | ARM_INS_VAND, |
| 640 | ARM_INS_VBIC, |
| 641 | ARM_INS_VBIF, |
| 642 | ARM_INS_VBIT, |
| 643 | ARM_INS_VBSL, |
| 644 | ARM_INS_VCEQ, |
| 645 | ARM_INS_VCGE, |
| 646 | ARM_INS_VCGT, |
Nguyen Anh Quynh | 73bbbb3 | 2014-06-17 13:29:54 +0800 | [diff] [blame] | 647 | ARM_INS_VCLE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 648 | ARM_INS_VCLS, |
Nguyen Anh Quynh | 73bbbb3 | 2014-06-17 13:29:54 +0800 | [diff] [blame] | 649 | ARM_INS_VCLT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 650 | ARM_INS_VCLZ, |
| 651 | ARM_INS_VCMP, |
| 652 | ARM_INS_VCMPE, |
| 653 | ARM_INS_VCNT, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 654 | ARM_INS_VCVTA, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 655 | ARM_INS_VCVTB, |
| 656 | ARM_INS_VCVT, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 657 | ARM_INS_VCVTM, |
| 658 | ARM_INS_VCVTN, |
| 659 | ARM_INS_VCVTP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 660 | ARM_INS_VCVTT, |
| 661 | ARM_INS_VDIV, |
| 662 | ARM_INS_VDUP, |
| 663 | ARM_INS_VEOR, |
| 664 | ARM_INS_VEXT, |
| 665 | ARM_INS_VFMA, |
| 666 | ARM_INS_VFMS, |
| 667 | ARM_INS_VFNMA, |
| 668 | ARM_INS_VFNMS, |
| 669 | ARM_INS_VHADD, |
| 670 | ARM_INS_VHSUB, |
| 671 | ARM_INS_VLD1, |
| 672 | ARM_INS_VLD2, |
| 673 | ARM_INS_VLD3, |
| 674 | ARM_INS_VLD4, |
| 675 | ARM_INS_VLDMDB, |
| 676 | ARM_INS_VLDMIA, |
| 677 | ARM_INS_VLDR, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 678 | ARM_INS_VMAXNM, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 679 | ARM_INS_VMAX, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 680 | ARM_INS_VMINNM, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 681 | ARM_INS_VMIN, |
| 682 | ARM_INS_VMLA, |
| 683 | ARM_INS_VMLAL, |
| 684 | ARM_INS_VMLS, |
| 685 | ARM_INS_VMLSL, |
| 686 | ARM_INS_VMOVL, |
| 687 | ARM_INS_VMOVN, |
| 688 | ARM_INS_VMSR, |
| 689 | ARM_INS_VMUL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 690 | ARM_INS_VMULL, |
| 691 | ARM_INS_VMVN, |
| 692 | ARM_INS_VNEG, |
| 693 | ARM_INS_VNMLA, |
| 694 | ARM_INS_VNMLS, |
| 695 | ARM_INS_VNMUL, |
| 696 | ARM_INS_VORN, |
| 697 | ARM_INS_VORR, |
| 698 | ARM_INS_VPADAL, |
| 699 | ARM_INS_VPADDL, |
| 700 | ARM_INS_VPADD, |
| 701 | ARM_INS_VPMAX, |
| 702 | ARM_INS_VPMIN, |
| 703 | ARM_INS_VQABS, |
| 704 | ARM_INS_VQADD, |
| 705 | ARM_INS_VQDMLAL, |
| 706 | ARM_INS_VQDMLSL, |
| 707 | ARM_INS_VQDMULH, |
| 708 | ARM_INS_VQDMULL, |
| 709 | ARM_INS_VQMOVUN, |
| 710 | ARM_INS_VQMOVN, |
| 711 | ARM_INS_VQNEG, |
| 712 | ARM_INS_VQRDMULH, |
| 713 | ARM_INS_VQRSHL, |
| 714 | ARM_INS_VQRSHRN, |
| 715 | ARM_INS_VQRSHRUN, |
| 716 | ARM_INS_VQSHL, |
| 717 | ARM_INS_VQSHLU, |
| 718 | ARM_INS_VQSHRN, |
| 719 | ARM_INS_VQSHRUN, |
| 720 | ARM_INS_VQSUB, |
| 721 | ARM_INS_VRADDHN, |
| 722 | ARM_INS_VRECPE, |
| 723 | ARM_INS_VRECPS, |
| 724 | ARM_INS_VREV16, |
| 725 | ARM_INS_VREV32, |
| 726 | ARM_INS_VREV64, |
| 727 | ARM_INS_VRHADD, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 728 | ARM_INS_VRINTA, |
| 729 | ARM_INS_VRINTM, |
| 730 | ARM_INS_VRINTN, |
| 731 | ARM_INS_VRINTP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 732 | ARM_INS_VRINTR, |
| 733 | ARM_INS_VRINTX, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 734 | ARM_INS_VRINTZ, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 735 | ARM_INS_VRSHL, |
| 736 | ARM_INS_VRSHRN, |
| 737 | ARM_INS_VRSHR, |
| 738 | ARM_INS_VRSQRTE, |
| 739 | ARM_INS_VRSQRTS, |
| 740 | ARM_INS_VRSRA, |
| 741 | ARM_INS_VRSUBHN, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 742 | ARM_INS_VSELEQ, |
| 743 | ARM_INS_VSELGE, |
| 744 | ARM_INS_VSELGT, |
| 745 | ARM_INS_VSELVS, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 746 | ARM_INS_VSHLL, |
| 747 | ARM_INS_VSHL, |
| 748 | ARM_INS_VSHRN, |
| 749 | ARM_INS_VSHR, |
| 750 | ARM_INS_VSLI, |
| 751 | ARM_INS_VSQRT, |
| 752 | ARM_INS_VSRA, |
| 753 | ARM_INS_VSRI, |
| 754 | ARM_INS_VST1, |
| 755 | ARM_INS_VST2, |
| 756 | ARM_INS_VST3, |
| 757 | ARM_INS_VST4, |
| 758 | ARM_INS_VSTMDB, |
| 759 | ARM_INS_VSTMIA, |
| 760 | ARM_INS_VSTR, |
| 761 | ARM_INS_VSUB, |
| 762 | ARM_INS_VSUBHN, |
| 763 | ARM_INS_VSUBL, |
| 764 | ARM_INS_VSUBW, |
| 765 | ARM_INS_VSWP, |
| 766 | ARM_INS_VTBL, |
| 767 | ARM_INS_VTBX, |
| 768 | ARM_INS_VCVTR, |
| 769 | ARM_INS_VTRN, |
| 770 | ARM_INS_VTST, |
| 771 | ARM_INS_VUZP, |
| 772 | ARM_INS_VZIP, |
| 773 | ARM_INS_ADDW, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 774 | ARM_INS_ASR, |
| 775 | ARM_INS_DCPS1, |
| 776 | ARM_INS_DCPS2, |
| 777 | ARM_INS_DCPS3, |
| 778 | ARM_INS_IT, |
| 779 | ARM_INS_LSL, |
| 780 | ARM_INS_LSR, |
Nguyen Anh Quynh | 73bbbb3 | 2014-06-17 13:29:54 +0800 | [diff] [blame] | 781 | ARM_INS_ASRS, |
| 782 | ARM_INS_LSRS, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 783 | ARM_INS_ORN, |
| 784 | ARM_INS_ROR, |
| 785 | ARM_INS_RRX, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 786 | ARM_INS_SUBS, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 787 | ARM_INS_SUBW, |
| 788 | ARM_INS_TBB, |
| 789 | ARM_INS_TBH, |
| 790 | ARM_INS_CBNZ, |
| 791 | ARM_INS_CBZ, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 792 | ARM_INS_MOVS, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 793 | ARM_INS_POP, |
| 794 | ARM_INS_PUSH, |
Nguyen Anh Quynh | 9cc56a3 | 2014-01-15 16:01:55 +0800 | [diff] [blame] | 795 | |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 796 | // special instructions |
| 797 | ARM_INS_NOP, |
| 798 | ARM_INS_YIELD, |
| 799 | ARM_INS_WFE, |
| 800 | ARM_INS_WFI, |
| 801 | ARM_INS_SEV, |
| 802 | ARM_INS_SEVL, |
| 803 | ARM_INS_VPUSH, |
| 804 | ARM_INS_VPOP, |
| 805 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 806 | ARM_INS_ENDING, // <-- mark the end of the list of instructions |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 807 | } arm_insn; |
| 808 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 809 | //> Group of ARM instructions |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 810 | typedef enum arm_insn_group { |
| 811 | ARM_GRP_INVALID = 0, |
| 812 | ARM_GRP_CRYPTO, |
| 813 | ARM_GRP_DATABARRIER, |
| 814 | ARM_GRP_DIVIDE, |
| 815 | ARM_GRP_FPARMV8, |
| 816 | ARM_GRP_MULTPRO, |
| 817 | ARM_GRP_NEON, |
| 818 | ARM_GRP_T2EXTRACTPACK, |
| 819 | ARM_GRP_THUMB2DSP, |
| 820 | ARM_GRP_TRUSTZONE, |
| 821 | ARM_GRP_V4T, |
| 822 | ARM_GRP_V5T, |
| 823 | ARM_GRP_V5TE, |
| 824 | ARM_GRP_V6, |
| 825 | ARM_GRP_V6T2, |
| 826 | ARM_GRP_V7, |
| 827 | ARM_GRP_V8, |
| 828 | ARM_GRP_VFP2, |
| 829 | ARM_GRP_VFP3, |
| 830 | ARM_GRP_VFP4, |
| 831 | ARM_GRP_ARM, |
| 832 | ARM_GRP_MCLASS, |
| 833 | ARM_GRP_NOTMCLASS, |
| 834 | ARM_GRP_THUMB, |
| 835 | ARM_GRP_THUMB1ONLY, |
| 836 | ARM_GRP_THUMB2, |
| 837 | ARM_GRP_PREV8, |
| 838 | ARM_GRP_FPVMLX, |
| 839 | ARM_GRP_MULOPS, |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 840 | ARM_GRP_CRC, |
| 841 | ARM_GRP_DPVFP, |
| 842 | ARM_GRP_V6M, |
Nguyen Anh Quynh | ec0ed8e | 2013-12-02 13:55:38 +0800 | [diff] [blame] | 843 | |
Nguyen Anh Quynh | 3582bc1 | 2013-12-03 09:43:27 +0800 | [diff] [blame] | 844 | ARM_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) |
| 845 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 846 | ARM_GRP_ENDING, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 847 | } arm_insn_group; |
| 848 | |
| 849 | #ifdef __cplusplus |
| 850 | } |
| 851 | #endif |
| 852 | |
| 853 | #endif |