Nguyen Anh Quynh | dd40750 | 2014-01-19 23:51:34 +0800 | [diff] [blame] | 1 | #ifndef CAPSTONE_MIPS_H |
| 2 | #define CAPSTONE_MIPS_H |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 3 | |
Nguyen Anh Quynh | 7751fbe | 2014-04-28 11:23:14 +0800 | [diff] [blame] | 4 | /* Capstone Disassembly Engine */ |
| 5 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 6 | |
| 7 | #ifdef __cplusplus |
| 8 | extern "C" { |
| 9 | #endif |
| 10 | |
| 11 | #include <stdint.h> |
Nguyen Anh Quynh | cb59106 | 2014-05-15 21:51:02 +0800 | [diff] [blame] | 12 | #include "platform.h" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 13 | |
schwoop | 8a26bd3 | 2014-06-06 17:28:43 +0200 | [diff] [blame] | 14 | // GCC MIPS toolchain has a default macro called "mips" which breaks |
| 15 | // compilation |
| 16 | #undef mips |
| 17 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 18 | #ifdef _MSC_VER |
| 19 | #pragma warning(disable:4201) |
Nguyen Anh Quynh | b57c90d | 2014-01-23 21:43:08 +0800 | [diff] [blame] | 20 | #endif |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 21 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 22 | //> Operand type for instruction's operands |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 23 | typedef enum mips_op_type { |
| 24 | MIPS_OP_INVALID = 0, // Uninitialized. |
| 25 | MIPS_OP_REG, // Register operand. |
| 26 | MIPS_OP_IMM, // Immediate operand. |
| 27 | MIPS_OP_MEM, // Memory operand |
| 28 | } mips_op_type; |
| 29 | |
| 30 | // Instruction's operand referring to memory |
| 31 | // This is associated with MIPS_OP_MEM operand type above |
| 32 | typedef struct mips_op_mem { |
| 33 | unsigned int base; // base register |
| 34 | int64_t disp; // displacement/offset value |
| 35 | } mips_op_mem; |
| 36 | |
| 37 | // Instruction operand |
| 38 | typedef struct cs_mips_op { |
| 39 | mips_op_type type; // operand type |
| 40 | union { |
| 41 | unsigned int reg; // register value for REG operand |
Nguyen Anh Quynh | de319f8 | 2014-03-09 04:08:11 +0800 | [diff] [blame] | 42 | int64_t imm; // immediate value for IMM operand |
| 43 | mips_op_mem mem; // base/index/scale/disp value for MEM operand |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 44 | }; |
| 45 | } cs_mips_op; |
| 46 | |
| 47 | // Instruction structure |
| 48 | typedef struct cs_mips { |
| 49 | // Number of operands of this instruction, |
| 50 | // or 0 when instruction has no operand. |
| 51 | uint8_t op_count; |
| 52 | cs_mips_op operands[8]; // operands for this instruction. |
| 53 | } cs_mips; |
| 54 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 55 | //> MIPS registers |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 56 | typedef enum mips_reg { |
| 57 | MIPS_REG_INVALID = 0, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 58 | //> General purpose registers |
Nguyen Anh Quynh | ea5b79d | 2013-12-04 12:10:47 +0800 | [diff] [blame] | 59 | MIPS_REG_0, |
| 60 | MIPS_REG_1, |
| 61 | MIPS_REG_2, |
| 62 | MIPS_REG_3, |
| 63 | MIPS_REG_4, |
| 64 | MIPS_REG_5, |
| 65 | MIPS_REG_6, |
| 66 | MIPS_REG_7, |
| 67 | MIPS_REG_8, |
| 68 | MIPS_REG_9, |
| 69 | MIPS_REG_10, |
| 70 | MIPS_REG_11, |
| 71 | MIPS_REG_12, |
| 72 | MIPS_REG_13, |
| 73 | MIPS_REG_14, |
| 74 | MIPS_REG_15, |
| 75 | MIPS_REG_16, |
| 76 | MIPS_REG_17, |
| 77 | MIPS_REG_18, |
| 78 | MIPS_REG_19, |
| 79 | MIPS_REG_20, |
| 80 | MIPS_REG_21, |
| 81 | MIPS_REG_22, |
| 82 | MIPS_REG_23, |
| 83 | MIPS_REG_24, |
| 84 | MIPS_REG_25, |
| 85 | MIPS_REG_26, |
| 86 | MIPS_REG_27, |
| 87 | MIPS_REG_28, |
| 88 | MIPS_REG_29, |
| 89 | MIPS_REG_30, |
| 90 | MIPS_REG_31, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 91 | |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 92 | //> DSP registers |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 93 | MIPS_REG_DSPCCOND, |
| 94 | MIPS_REG_DSPCARRY, |
| 95 | MIPS_REG_DSPEFI, |
| 96 | MIPS_REG_DSPOUTFLAG, |
| 97 | MIPS_REG_DSPOUTFLAG16_19, |
| 98 | MIPS_REG_DSPOUTFLAG20, |
| 99 | MIPS_REG_DSPOUTFLAG21, |
| 100 | MIPS_REG_DSPOUTFLAG22, |
| 101 | MIPS_REG_DSPOUTFLAG23, |
| 102 | MIPS_REG_DSPPOS, |
| 103 | MIPS_REG_DSPSCOUNT, |
| 104 | |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 105 | //> ACC registers |
Nguyen Anh Quynh | ea5b79d | 2013-12-04 12:10:47 +0800 | [diff] [blame] | 106 | MIPS_REG_AC0, |
| 107 | MIPS_REG_AC1, |
| 108 | MIPS_REG_AC2, |
| 109 | MIPS_REG_AC3, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 110 | |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 111 | //> COP registers |
| 112 | MIPS_REG_CC0, |
| 113 | MIPS_REG_CC1, |
| 114 | MIPS_REG_CC2, |
| 115 | MIPS_REG_CC3, |
| 116 | MIPS_REG_CC4, |
| 117 | MIPS_REG_CC5, |
| 118 | MIPS_REG_CC6, |
| 119 | MIPS_REG_CC7, |
| 120 | |
| 121 | //> FPU registers |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 122 | MIPS_REG_F0, |
| 123 | MIPS_REG_F1, |
| 124 | MIPS_REG_F2, |
| 125 | MIPS_REG_F3, |
| 126 | MIPS_REG_F4, |
| 127 | MIPS_REG_F5, |
| 128 | MIPS_REG_F6, |
| 129 | MIPS_REG_F7, |
| 130 | MIPS_REG_F8, |
| 131 | MIPS_REG_F9, |
| 132 | MIPS_REG_F10, |
| 133 | MIPS_REG_F11, |
| 134 | MIPS_REG_F12, |
| 135 | MIPS_REG_F13, |
| 136 | MIPS_REG_F14, |
| 137 | MIPS_REG_F15, |
| 138 | MIPS_REG_F16, |
| 139 | MIPS_REG_F17, |
| 140 | MIPS_REG_F18, |
| 141 | MIPS_REG_F19, |
| 142 | MIPS_REG_F20, |
| 143 | MIPS_REG_F21, |
| 144 | MIPS_REG_F22, |
| 145 | MIPS_REG_F23, |
| 146 | MIPS_REG_F24, |
| 147 | MIPS_REG_F25, |
| 148 | MIPS_REG_F26, |
| 149 | MIPS_REG_F27, |
| 150 | MIPS_REG_F28, |
| 151 | MIPS_REG_F29, |
| 152 | MIPS_REG_F30, |
| 153 | MIPS_REG_F31, |
| 154 | |
| 155 | MIPS_REG_FCC0, |
| 156 | MIPS_REG_FCC1, |
| 157 | MIPS_REG_FCC2, |
| 158 | MIPS_REG_FCC3, |
| 159 | MIPS_REG_FCC4, |
| 160 | MIPS_REG_FCC5, |
| 161 | MIPS_REG_FCC6, |
| 162 | MIPS_REG_FCC7, |
| 163 | |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 164 | //> AFPR128 |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 165 | MIPS_REG_W0, |
| 166 | MIPS_REG_W1, |
| 167 | MIPS_REG_W2, |
| 168 | MIPS_REG_W3, |
| 169 | MIPS_REG_W4, |
| 170 | MIPS_REG_W5, |
| 171 | MIPS_REG_W6, |
| 172 | MIPS_REG_W7, |
| 173 | MIPS_REG_W8, |
| 174 | MIPS_REG_W9, |
| 175 | MIPS_REG_W10, |
| 176 | MIPS_REG_W11, |
| 177 | MIPS_REG_W12, |
| 178 | MIPS_REG_W13, |
| 179 | MIPS_REG_W14, |
| 180 | MIPS_REG_W15, |
| 181 | MIPS_REG_W16, |
| 182 | MIPS_REG_W17, |
| 183 | MIPS_REG_W18, |
| 184 | MIPS_REG_W19, |
| 185 | MIPS_REG_W20, |
| 186 | MIPS_REG_W21, |
| 187 | MIPS_REG_W22, |
| 188 | MIPS_REG_W23, |
| 189 | MIPS_REG_W24, |
| 190 | MIPS_REG_W25, |
| 191 | MIPS_REG_W26, |
| 192 | MIPS_REG_W27, |
| 193 | MIPS_REG_W28, |
| 194 | MIPS_REG_W29, |
| 195 | MIPS_REG_W30, |
| 196 | MIPS_REG_W31, |
| 197 | |
Nguyen Anh Quynh | ad89d25 | 2013-12-11 23:20:34 +0800 | [diff] [blame] | 198 | MIPS_REG_HI, |
| 199 | MIPS_REG_LO, |
| 200 | MIPS_REG_PC, |
| 201 | |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 202 | MIPS_REG_P0, |
| 203 | MIPS_REG_P1, |
| 204 | MIPS_REG_P2, |
| 205 | |
| 206 | MIPS_REG_MPL0, |
| 207 | MIPS_REG_MPL1, |
| 208 | MIPS_REG_MPL2, |
| 209 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 210 | MIPS_REG_ENDING, // <-- mark the end of the list or registers |
Nguyen Anh Quynh | ea5b79d | 2013-12-04 12:10:47 +0800 | [diff] [blame] | 211 | |
| 212 | // alias registers |
| 213 | MIPS_REG_ZERO = MIPS_REG_0, |
| 214 | MIPS_REG_AT = MIPS_REG_1, |
| 215 | MIPS_REG_V0 = MIPS_REG_2, |
| 216 | MIPS_REG_V1 = MIPS_REG_3, |
| 217 | MIPS_REG_A0 = MIPS_REG_4, |
| 218 | MIPS_REG_A1 = MIPS_REG_5, |
| 219 | MIPS_REG_A2 = MIPS_REG_6, |
| 220 | MIPS_REG_A3 = MIPS_REG_7, |
| 221 | MIPS_REG_T0 = MIPS_REG_8, |
| 222 | MIPS_REG_T1 = MIPS_REG_9, |
| 223 | MIPS_REG_T2 = MIPS_REG_10, |
| 224 | MIPS_REG_T3 = MIPS_REG_11, |
| 225 | MIPS_REG_T4 = MIPS_REG_12, |
| 226 | MIPS_REG_T5 = MIPS_REG_13, |
| 227 | MIPS_REG_T6 = MIPS_REG_14, |
| 228 | MIPS_REG_T7 = MIPS_REG_15, |
| 229 | MIPS_REG_S0 = MIPS_REG_16, |
| 230 | MIPS_REG_S1 = MIPS_REG_17, |
| 231 | MIPS_REG_S2 = MIPS_REG_18, |
| 232 | MIPS_REG_S3 = MIPS_REG_19, |
| 233 | MIPS_REG_S4 = MIPS_REG_20, |
| 234 | MIPS_REG_S5 = MIPS_REG_21, |
| 235 | MIPS_REG_S6 = MIPS_REG_22, |
| 236 | MIPS_REG_S7 = MIPS_REG_23, |
| 237 | MIPS_REG_T8 = MIPS_REG_24, |
| 238 | MIPS_REG_T9 = MIPS_REG_25, |
| 239 | MIPS_REG_K0 = MIPS_REG_26, |
| 240 | MIPS_REG_K1 = MIPS_REG_27, |
| 241 | MIPS_REG_GP = MIPS_REG_28, |
| 242 | MIPS_REG_SP = MIPS_REG_29, |
| 243 | MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, |
| 244 | MIPS_REG_RA = MIPS_REG_31, |
| 245 | |
| 246 | MIPS_REG_HI0 = MIPS_REG_AC0, |
| 247 | MIPS_REG_HI1 = MIPS_REG_AC1, |
| 248 | MIPS_REG_HI2 = MIPS_REG_AC2, |
| 249 | MIPS_REG_HI3 = MIPS_REG_AC3, |
| 250 | |
| 251 | MIPS_REG_LO0 = MIPS_REG_HI0, |
| 252 | MIPS_REG_LO1 = MIPS_REG_HI1, |
| 253 | MIPS_REG_LO2 = MIPS_REG_HI2, |
| 254 | MIPS_REG_LO3 = MIPS_REG_HI3, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 255 | } mips_reg; |
| 256 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 257 | //> MIPS instruction |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 258 | typedef enum mips_insn { |
| 259 | MIPS_INS_INVALID = 0, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 260 | |
| 261 | MIPS_INS_ABSQ_S, |
| 262 | MIPS_INS_ADD, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 263 | MIPS_INS_ADDIUPC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 264 | MIPS_INS_ADDQH, |
| 265 | MIPS_INS_ADDQH_R, |
| 266 | MIPS_INS_ADDQ, |
| 267 | MIPS_INS_ADDQ_S, |
| 268 | MIPS_INS_ADDSC, |
| 269 | MIPS_INS_ADDS_A, |
| 270 | MIPS_INS_ADDS_S, |
| 271 | MIPS_INS_ADDS_U, |
| 272 | MIPS_INS_ADDUH, |
| 273 | MIPS_INS_ADDUH_R, |
| 274 | MIPS_INS_ADDU, |
| 275 | MIPS_INS_ADDU_S, |
| 276 | MIPS_INS_ADDVI, |
| 277 | MIPS_INS_ADDV, |
| 278 | MIPS_INS_ADDWC, |
| 279 | MIPS_INS_ADD_A, |
| 280 | MIPS_INS_ADDI, |
| 281 | MIPS_INS_ADDIU, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 282 | MIPS_INS_ALIGN, |
| 283 | MIPS_INS_ALUIPC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 284 | MIPS_INS_AND, |
| 285 | MIPS_INS_ANDI, |
| 286 | MIPS_INS_APPEND, |
| 287 | MIPS_INS_ASUB_S, |
| 288 | MIPS_INS_ASUB_U, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 289 | MIPS_INS_AUI, |
| 290 | MIPS_INS_AUIPC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 291 | MIPS_INS_AVER_S, |
| 292 | MIPS_INS_AVER_U, |
| 293 | MIPS_INS_AVE_S, |
| 294 | MIPS_INS_AVE_U, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 295 | MIPS_INS_BADDU, |
| 296 | MIPS_INS_BAL, |
| 297 | MIPS_INS_BALC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 298 | MIPS_INS_BALIGN, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 299 | MIPS_INS_BC, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 300 | MIPS_INS_BC0F, |
| 301 | MIPS_INS_BC0FL, |
| 302 | MIPS_INS_BC0T, |
| 303 | MIPS_INS_BC0TL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 304 | MIPS_INS_BC1EQZ, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 305 | MIPS_INS_BC1F, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 306 | MIPS_INS_BC1FL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 307 | MIPS_INS_BC1NEZ, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 308 | MIPS_INS_BC1T, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 309 | MIPS_INS_BC1TL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 310 | MIPS_INS_BC2EQZ, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 311 | MIPS_INS_BC2F, |
| 312 | MIPS_INS_BC2FL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 313 | MIPS_INS_BC2NEZ, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 314 | MIPS_INS_BC2T, |
| 315 | MIPS_INS_BC2TL, |
| 316 | MIPS_INS_BC3F, |
| 317 | MIPS_INS_BC3FL, |
| 318 | MIPS_INS_BC3T, |
| 319 | MIPS_INS_BC3TL, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 320 | MIPS_INS_BCLRI, |
| 321 | MIPS_INS_BCLR, |
| 322 | MIPS_INS_BEQ, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 323 | MIPS_INS_BEQC, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 324 | MIPS_INS_BEQL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 325 | MIPS_INS_BEQZALC, |
| 326 | MIPS_INS_BEQZC, |
| 327 | MIPS_INS_BGEC, |
| 328 | MIPS_INS_BGEUC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 329 | MIPS_INS_BGEZ, |
| 330 | MIPS_INS_BGEZAL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 331 | MIPS_INS_BGEZALC, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 332 | MIPS_INS_BGEZALL, |
| 333 | MIPS_INS_BGEZALS, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 334 | MIPS_INS_BGEZC, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 335 | MIPS_INS_BGEZL, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 336 | MIPS_INS_BGTZ, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 337 | MIPS_INS_BGTZALC, |
| 338 | MIPS_INS_BGTZC, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 339 | MIPS_INS_BGTZL, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 340 | MIPS_INS_BINSLI, |
| 341 | MIPS_INS_BINSL, |
| 342 | MIPS_INS_BINSRI, |
| 343 | MIPS_INS_BINSR, |
| 344 | MIPS_INS_BITREV, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 345 | MIPS_INS_BITSWAP, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 346 | MIPS_INS_BLEZ, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 347 | MIPS_INS_BLEZALC, |
| 348 | MIPS_INS_BLEZC, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 349 | MIPS_INS_BLEZL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 350 | MIPS_INS_BLTC, |
| 351 | MIPS_INS_BLTUC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 352 | MIPS_INS_BLTZ, |
| 353 | MIPS_INS_BLTZAL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 354 | MIPS_INS_BLTZALC, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 355 | MIPS_INS_BLTZALL, |
| 356 | MIPS_INS_BLTZALS, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 357 | MIPS_INS_BLTZC, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 358 | MIPS_INS_BLTZL, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 359 | MIPS_INS_BMNZI, |
| 360 | MIPS_INS_BMNZ, |
| 361 | MIPS_INS_BMZI, |
| 362 | MIPS_INS_BMZ, |
| 363 | MIPS_INS_BNE, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 364 | MIPS_INS_BNEC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 365 | MIPS_INS_BNEGI, |
| 366 | MIPS_INS_BNEG, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 367 | MIPS_INS_BNEL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 368 | MIPS_INS_BNEZALC, |
| 369 | MIPS_INS_BNEZC, |
| 370 | MIPS_INS_BNVC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 371 | MIPS_INS_BNZ, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 372 | MIPS_INS_BOVC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 373 | MIPS_INS_BPOSGE32, |
| 374 | MIPS_INS_BREAK, |
| 375 | MIPS_INS_BSELI, |
| 376 | MIPS_INS_BSEL, |
| 377 | MIPS_INS_BSETI, |
| 378 | MIPS_INS_BSET, |
| 379 | MIPS_INS_BZ, |
| 380 | MIPS_INS_BEQZ, |
| 381 | MIPS_INS_B, |
| 382 | MIPS_INS_BNEZ, |
| 383 | MIPS_INS_BTEQZ, |
| 384 | MIPS_INS_BTNEZ, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 385 | MIPS_INS_CACHE, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 386 | MIPS_INS_CEIL, |
| 387 | MIPS_INS_CEQI, |
| 388 | MIPS_INS_CEQ, |
| 389 | MIPS_INS_CFC1, |
| 390 | MIPS_INS_CFCMSA, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 391 | MIPS_INS_CINS, |
| 392 | MIPS_INS_CINS32, |
| 393 | MIPS_INS_CLASS, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 394 | MIPS_INS_CLEI_S, |
| 395 | MIPS_INS_CLEI_U, |
| 396 | MIPS_INS_CLE_S, |
| 397 | MIPS_INS_CLE_U, |
| 398 | MIPS_INS_CLO, |
| 399 | MIPS_INS_CLTI_S, |
| 400 | MIPS_INS_CLTI_U, |
| 401 | MIPS_INS_CLT_S, |
| 402 | MIPS_INS_CLT_U, |
| 403 | MIPS_INS_CLZ, |
| 404 | MIPS_INS_CMPGDU, |
| 405 | MIPS_INS_CMPGU, |
| 406 | MIPS_INS_CMPU, |
| 407 | MIPS_INS_CMP, |
| 408 | MIPS_INS_COPY_S, |
| 409 | MIPS_INS_COPY_U, |
| 410 | MIPS_INS_CTC1, |
| 411 | MIPS_INS_CTCMSA, |
| 412 | MIPS_INS_CVT, |
| 413 | MIPS_INS_C, |
| 414 | MIPS_INS_CMPI, |
| 415 | MIPS_INS_DADD, |
| 416 | MIPS_INS_DADDI, |
| 417 | MIPS_INS_DADDIU, |
| 418 | MIPS_INS_DADDU, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 419 | MIPS_INS_DAHI, |
| 420 | MIPS_INS_DALIGN, |
| 421 | MIPS_INS_DATI, |
| 422 | MIPS_INS_DAUI, |
| 423 | MIPS_INS_DBITSWAP, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 424 | MIPS_INS_DCLO, |
| 425 | MIPS_INS_DCLZ, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 426 | MIPS_INS_DDIV, |
| 427 | MIPS_INS_DDIVU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 428 | MIPS_INS_DERET, |
| 429 | MIPS_INS_DEXT, |
| 430 | MIPS_INS_DEXTM, |
| 431 | MIPS_INS_DEXTU, |
| 432 | MIPS_INS_DI, |
| 433 | MIPS_INS_DINS, |
| 434 | MIPS_INS_DINSM, |
| 435 | MIPS_INS_DINSU, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 436 | MIPS_INS_DIV, |
| 437 | MIPS_INS_DIVU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 438 | MIPS_INS_DIV_S, |
| 439 | MIPS_INS_DIV_U, |
Nguyen Anh Quynh | bc0b3b9 | 2014-02-19 15:13:20 +0800 | [diff] [blame] | 440 | MIPS_INS_DLSA, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 441 | MIPS_INS_DMFC0, |
| 442 | MIPS_INS_DMFC1, |
| 443 | MIPS_INS_DMFC2, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 444 | MIPS_INS_DMOD, |
| 445 | MIPS_INS_DMODU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 446 | MIPS_INS_DMTC0, |
| 447 | MIPS_INS_DMTC1, |
| 448 | MIPS_INS_DMTC2, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 449 | MIPS_INS_DMUH, |
| 450 | MIPS_INS_DMUHU, |
| 451 | MIPS_INS_DMUL, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 452 | MIPS_INS_DMULT, |
| 453 | MIPS_INS_DMULTU, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 454 | MIPS_INS_DMULU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 455 | MIPS_INS_DOTP_S, |
| 456 | MIPS_INS_DOTP_U, |
| 457 | MIPS_INS_DPADD_S, |
| 458 | MIPS_INS_DPADD_U, |
| 459 | MIPS_INS_DPAQX_SA, |
| 460 | MIPS_INS_DPAQX_S, |
| 461 | MIPS_INS_DPAQ_SA, |
| 462 | MIPS_INS_DPAQ_S, |
| 463 | MIPS_INS_DPAU, |
| 464 | MIPS_INS_DPAX, |
| 465 | MIPS_INS_DPA, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 466 | MIPS_INS_DPOP, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 467 | MIPS_INS_DPSQX_SA, |
| 468 | MIPS_INS_DPSQX_S, |
| 469 | MIPS_INS_DPSQ_SA, |
| 470 | MIPS_INS_DPSQ_S, |
| 471 | MIPS_INS_DPSUB_S, |
| 472 | MIPS_INS_DPSUB_U, |
| 473 | MIPS_INS_DPSU, |
| 474 | MIPS_INS_DPSX, |
| 475 | MIPS_INS_DPS, |
| 476 | MIPS_INS_DROTR, |
| 477 | MIPS_INS_DROTR32, |
| 478 | MIPS_INS_DROTRV, |
| 479 | MIPS_INS_DSBH, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 480 | MIPS_INS_DSHD, |
| 481 | MIPS_INS_DSLL, |
| 482 | MIPS_INS_DSLL32, |
| 483 | MIPS_INS_DSLLV, |
| 484 | MIPS_INS_DSRA, |
| 485 | MIPS_INS_DSRA32, |
| 486 | MIPS_INS_DSRAV, |
| 487 | MIPS_INS_DSRL, |
| 488 | MIPS_INS_DSRL32, |
| 489 | MIPS_INS_DSRLV, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 490 | MIPS_INS_DSUB, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 491 | MIPS_INS_DSUBU, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 492 | MIPS_INS_EHB, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 493 | MIPS_INS_EI, |
| 494 | MIPS_INS_ERET, |
| 495 | MIPS_INS_EXT, |
| 496 | MIPS_INS_EXTP, |
| 497 | MIPS_INS_EXTPDP, |
| 498 | MIPS_INS_EXTPDPV, |
| 499 | MIPS_INS_EXTPV, |
| 500 | MIPS_INS_EXTRV_RS, |
| 501 | MIPS_INS_EXTRV_R, |
| 502 | MIPS_INS_EXTRV_S, |
| 503 | MIPS_INS_EXTRV, |
| 504 | MIPS_INS_EXTR_RS, |
| 505 | MIPS_INS_EXTR_R, |
| 506 | MIPS_INS_EXTR_S, |
| 507 | MIPS_INS_EXTR, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 508 | MIPS_INS_EXTS, |
| 509 | MIPS_INS_EXTS32, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 510 | MIPS_INS_ABS, |
| 511 | MIPS_INS_FADD, |
| 512 | MIPS_INS_FCAF, |
| 513 | MIPS_INS_FCEQ, |
| 514 | MIPS_INS_FCLASS, |
| 515 | MIPS_INS_FCLE, |
| 516 | MIPS_INS_FCLT, |
| 517 | MIPS_INS_FCNE, |
| 518 | MIPS_INS_FCOR, |
| 519 | MIPS_INS_FCUEQ, |
| 520 | MIPS_INS_FCULE, |
| 521 | MIPS_INS_FCULT, |
| 522 | MIPS_INS_FCUNE, |
| 523 | MIPS_INS_FCUN, |
| 524 | MIPS_INS_FDIV, |
| 525 | MIPS_INS_FEXDO, |
| 526 | MIPS_INS_FEXP2, |
| 527 | MIPS_INS_FEXUPL, |
| 528 | MIPS_INS_FEXUPR, |
| 529 | MIPS_INS_FFINT_S, |
| 530 | MIPS_INS_FFINT_U, |
| 531 | MIPS_INS_FFQL, |
| 532 | MIPS_INS_FFQR, |
| 533 | MIPS_INS_FILL, |
| 534 | MIPS_INS_FLOG2, |
| 535 | MIPS_INS_FLOOR, |
| 536 | MIPS_INS_FMADD, |
| 537 | MIPS_INS_FMAX_A, |
| 538 | MIPS_INS_FMAX, |
| 539 | MIPS_INS_FMIN_A, |
| 540 | MIPS_INS_FMIN, |
| 541 | MIPS_INS_MOV, |
| 542 | MIPS_INS_FMSUB, |
| 543 | MIPS_INS_FMUL, |
| 544 | MIPS_INS_MUL, |
| 545 | MIPS_INS_NEG, |
| 546 | MIPS_INS_FRCP, |
| 547 | MIPS_INS_FRINT, |
| 548 | MIPS_INS_FRSQRT, |
| 549 | MIPS_INS_FSAF, |
| 550 | MIPS_INS_FSEQ, |
| 551 | MIPS_INS_FSLE, |
| 552 | MIPS_INS_FSLT, |
| 553 | MIPS_INS_FSNE, |
| 554 | MIPS_INS_FSOR, |
| 555 | MIPS_INS_FSQRT, |
| 556 | MIPS_INS_SQRT, |
| 557 | MIPS_INS_FSUB, |
| 558 | MIPS_INS_SUB, |
| 559 | MIPS_INS_FSUEQ, |
| 560 | MIPS_INS_FSULE, |
| 561 | MIPS_INS_FSULT, |
| 562 | MIPS_INS_FSUNE, |
| 563 | MIPS_INS_FSUN, |
| 564 | MIPS_INS_FTINT_S, |
| 565 | MIPS_INS_FTINT_U, |
| 566 | MIPS_INS_FTQ, |
| 567 | MIPS_INS_FTRUNC_S, |
| 568 | MIPS_INS_FTRUNC_U, |
| 569 | MIPS_INS_HADD_S, |
| 570 | MIPS_INS_HADD_U, |
| 571 | MIPS_INS_HSUB_S, |
| 572 | MIPS_INS_HSUB_U, |
| 573 | MIPS_INS_ILVEV, |
| 574 | MIPS_INS_ILVL, |
| 575 | MIPS_INS_ILVOD, |
| 576 | MIPS_INS_ILVR, |
| 577 | MIPS_INS_INS, |
| 578 | MIPS_INS_INSERT, |
| 579 | MIPS_INS_INSV, |
| 580 | MIPS_INS_INSVE, |
| 581 | MIPS_INS_J, |
| 582 | MIPS_INS_JAL, |
| 583 | MIPS_INS_JALR, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 584 | MIPS_INS_JALRS, |
| 585 | MIPS_INS_JALS, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 586 | MIPS_INS_JALX, |
| 587 | MIPS_INS_JIALC, |
| 588 | MIPS_INS_JIC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 589 | MIPS_INS_JR, |
Nguyen Anh Quynh | 5691dd4 | 2014-09-24 18:03:47 +0800 | [diff] [blame] | 590 | MIPS_INS_JRADDIUSP, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 591 | MIPS_INS_JRC, |
| 592 | MIPS_INS_JALRC, |
| 593 | MIPS_INS_LB, |
| 594 | MIPS_INS_LBUX, |
| 595 | MIPS_INS_LBU, |
| 596 | MIPS_INS_LD, |
| 597 | MIPS_INS_LDC1, |
| 598 | MIPS_INS_LDC2, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 599 | MIPS_INS_LDC3, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 600 | MIPS_INS_LDI, |
| 601 | MIPS_INS_LDL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 602 | MIPS_INS_LDPC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 603 | MIPS_INS_LDR, |
| 604 | MIPS_INS_LDXC1, |
| 605 | MIPS_INS_LH, |
| 606 | MIPS_INS_LHX, |
| 607 | MIPS_INS_LHU, |
| 608 | MIPS_INS_LL, |
| 609 | MIPS_INS_LLD, |
| 610 | MIPS_INS_LSA, |
| 611 | MIPS_INS_LUXC1, |
| 612 | MIPS_INS_LUI, |
| 613 | MIPS_INS_LW, |
| 614 | MIPS_INS_LWC1, |
| 615 | MIPS_INS_LWC2, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 616 | MIPS_INS_LWC3, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 617 | MIPS_INS_LWL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 618 | MIPS_INS_LWPC, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 619 | MIPS_INS_LWR, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 620 | MIPS_INS_LWUPC, |
Nguyen Anh Quynh | bc0b3b9 | 2014-02-19 15:13:20 +0800 | [diff] [blame] | 621 | MIPS_INS_LWU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 622 | MIPS_INS_LWX, |
| 623 | MIPS_INS_LWXC1, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 624 | MIPS_INS_LI, |
| 625 | MIPS_INS_MADD, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 626 | MIPS_INS_MADDF, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 627 | MIPS_INS_MADDR_Q, |
| 628 | MIPS_INS_MADDU, |
| 629 | MIPS_INS_MADDV, |
| 630 | MIPS_INS_MADD_Q, |
| 631 | MIPS_INS_MAQ_SA, |
| 632 | MIPS_INS_MAQ_S, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 633 | MIPS_INS_MAXA, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 634 | MIPS_INS_MAXI_S, |
| 635 | MIPS_INS_MAXI_U, |
| 636 | MIPS_INS_MAX_A, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 637 | MIPS_INS_MAX, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 638 | MIPS_INS_MAX_S, |
| 639 | MIPS_INS_MAX_U, |
| 640 | MIPS_INS_MFC0, |
| 641 | MIPS_INS_MFC1, |
| 642 | MIPS_INS_MFC2, |
| 643 | MIPS_INS_MFHC1, |
| 644 | MIPS_INS_MFHI, |
| 645 | MIPS_INS_MFLO, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 646 | MIPS_INS_MINA, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 647 | MIPS_INS_MINI_S, |
| 648 | MIPS_INS_MINI_U, |
| 649 | MIPS_INS_MIN_A, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 650 | MIPS_INS_MIN, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 651 | MIPS_INS_MIN_S, |
| 652 | MIPS_INS_MIN_U, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 653 | MIPS_INS_MOD, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 654 | MIPS_INS_MODSUB, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 655 | MIPS_INS_MODU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 656 | MIPS_INS_MOD_S, |
| 657 | MIPS_INS_MOD_U, |
| 658 | MIPS_INS_MOVE, |
| 659 | MIPS_INS_MOVF, |
| 660 | MIPS_INS_MOVN, |
| 661 | MIPS_INS_MOVT, |
| 662 | MIPS_INS_MOVZ, |
| 663 | MIPS_INS_MSUB, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 664 | MIPS_INS_MSUBF, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 665 | MIPS_INS_MSUBR_Q, |
| 666 | MIPS_INS_MSUBU, |
| 667 | MIPS_INS_MSUBV, |
| 668 | MIPS_INS_MSUB_Q, |
| 669 | MIPS_INS_MTC0, |
| 670 | MIPS_INS_MTC1, |
| 671 | MIPS_INS_MTC2, |
| 672 | MIPS_INS_MTHC1, |
| 673 | MIPS_INS_MTHI, |
| 674 | MIPS_INS_MTHLIP, |
| 675 | MIPS_INS_MTLO, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 676 | MIPS_INS_MTM0, |
| 677 | MIPS_INS_MTM1, |
| 678 | MIPS_INS_MTM2, |
| 679 | MIPS_INS_MTP0, |
| 680 | MIPS_INS_MTP1, |
| 681 | MIPS_INS_MTP2, |
| 682 | MIPS_INS_MUH, |
| 683 | MIPS_INS_MUHU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 684 | MIPS_INS_MULEQ_S, |
| 685 | MIPS_INS_MULEU_S, |
| 686 | MIPS_INS_MULQ_RS, |
| 687 | MIPS_INS_MULQ_S, |
| 688 | MIPS_INS_MULR_Q, |
| 689 | MIPS_INS_MULSAQ_S, |
| 690 | MIPS_INS_MULSA, |
| 691 | MIPS_INS_MULT, |
| 692 | MIPS_INS_MULTU, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 693 | MIPS_INS_MULU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 694 | MIPS_INS_MULV, |
| 695 | MIPS_INS_MUL_Q, |
| 696 | MIPS_INS_MUL_S, |
| 697 | MIPS_INS_NLOC, |
| 698 | MIPS_INS_NLZC, |
| 699 | MIPS_INS_NMADD, |
| 700 | MIPS_INS_NMSUB, |
| 701 | MIPS_INS_NOR, |
| 702 | MIPS_INS_NORI, |
| 703 | MIPS_INS_NOT, |
| 704 | MIPS_INS_OR, |
| 705 | MIPS_INS_ORI, |
| 706 | MIPS_INS_PACKRL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 707 | MIPS_INS_PAUSE, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 708 | MIPS_INS_PCKEV, |
| 709 | MIPS_INS_PCKOD, |
| 710 | MIPS_INS_PCNT, |
| 711 | MIPS_INS_PICK, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 712 | MIPS_INS_POP, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 713 | MIPS_INS_PRECEQU, |
| 714 | MIPS_INS_PRECEQ, |
| 715 | MIPS_INS_PRECEU, |
| 716 | MIPS_INS_PRECRQU_S, |
| 717 | MIPS_INS_PRECRQ, |
| 718 | MIPS_INS_PRECRQ_RS, |
| 719 | MIPS_INS_PRECR, |
| 720 | MIPS_INS_PRECR_SRA, |
| 721 | MIPS_INS_PRECR_SRA_R, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 722 | MIPS_INS_PREF, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 723 | MIPS_INS_PREPEND, |
| 724 | MIPS_INS_RADDU, |
| 725 | MIPS_INS_RDDSP, |
| 726 | MIPS_INS_RDHWR, |
| 727 | MIPS_INS_REPLV, |
| 728 | MIPS_INS_REPL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 729 | MIPS_INS_RINT, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 730 | MIPS_INS_ROTR, |
| 731 | MIPS_INS_ROTRV, |
| 732 | MIPS_INS_ROUND, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 733 | MIPS_INS_SAT_S, |
| 734 | MIPS_INS_SAT_U, |
| 735 | MIPS_INS_SB, |
| 736 | MIPS_INS_SC, |
| 737 | MIPS_INS_SCD, |
| 738 | MIPS_INS_SD, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 739 | MIPS_INS_SDBBP, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 740 | MIPS_INS_SDC1, |
| 741 | MIPS_INS_SDC2, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 742 | MIPS_INS_SDC3, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 743 | MIPS_INS_SDL, |
| 744 | MIPS_INS_SDR, |
| 745 | MIPS_INS_SDXC1, |
| 746 | MIPS_INS_SEB, |
| 747 | MIPS_INS_SEH, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 748 | MIPS_INS_SELEQZ, |
| 749 | MIPS_INS_SELNEZ, |
| 750 | MIPS_INS_SEL, |
| 751 | MIPS_INS_SEQ, |
| 752 | MIPS_INS_SEQI, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 753 | MIPS_INS_SH, |
| 754 | MIPS_INS_SHF, |
| 755 | MIPS_INS_SHILO, |
| 756 | MIPS_INS_SHILOV, |
| 757 | MIPS_INS_SHLLV, |
| 758 | MIPS_INS_SHLLV_S, |
| 759 | MIPS_INS_SHLL, |
| 760 | MIPS_INS_SHLL_S, |
| 761 | MIPS_INS_SHRAV, |
| 762 | MIPS_INS_SHRAV_R, |
| 763 | MIPS_INS_SHRA, |
| 764 | MIPS_INS_SHRA_R, |
| 765 | MIPS_INS_SHRLV, |
| 766 | MIPS_INS_SHRL, |
| 767 | MIPS_INS_SLDI, |
| 768 | MIPS_INS_SLD, |
| 769 | MIPS_INS_SLL, |
| 770 | MIPS_INS_SLLI, |
| 771 | MIPS_INS_SLLV, |
| 772 | MIPS_INS_SLT, |
| 773 | MIPS_INS_SLTI, |
| 774 | MIPS_INS_SLTIU, |
| 775 | MIPS_INS_SLTU, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 776 | MIPS_INS_SNE, |
| 777 | MIPS_INS_SNEI, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 778 | MIPS_INS_SPLATI, |
| 779 | MIPS_INS_SPLAT, |
| 780 | MIPS_INS_SRA, |
| 781 | MIPS_INS_SRAI, |
| 782 | MIPS_INS_SRARI, |
| 783 | MIPS_INS_SRAR, |
| 784 | MIPS_INS_SRAV, |
| 785 | MIPS_INS_SRL, |
| 786 | MIPS_INS_SRLI, |
| 787 | MIPS_INS_SRLRI, |
| 788 | MIPS_INS_SRLR, |
| 789 | MIPS_INS_SRLV, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 790 | MIPS_INS_SSNOP, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 791 | MIPS_INS_ST, |
| 792 | MIPS_INS_SUBQH, |
| 793 | MIPS_INS_SUBQH_R, |
| 794 | MIPS_INS_SUBQ, |
| 795 | MIPS_INS_SUBQ_S, |
| 796 | MIPS_INS_SUBSUS_U, |
| 797 | MIPS_INS_SUBSUU_S, |
| 798 | MIPS_INS_SUBS_S, |
| 799 | MIPS_INS_SUBS_U, |
| 800 | MIPS_INS_SUBUH, |
| 801 | MIPS_INS_SUBUH_R, |
| 802 | MIPS_INS_SUBU, |
| 803 | MIPS_INS_SUBU_S, |
| 804 | MIPS_INS_SUBVI, |
| 805 | MIPS_INS_SUBV, |
| 806 | MIPS_INS_SUXC1, |
| 807 | MIPS_INS_SW, |
| 808 | MIPS_INS_SWC1, |
| 809 | MIPS_INS_SWC2, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 810 | MIPS_INS_SWC3, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 811 | MIPS_INS_SWL, |
| 812 | MIPS_INS_SWR, |
| 813 | MIPS_INS_SWXC1, |
| 814 | MIPS_INS_SYNC, |
| 815 | MIPS_INS_SYSCALL, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 816 | MIPS_INS_TEQ, |
| 817 | MIPS_INS_TEQI, |
| 818 | MIPS_INS_TGE, |
| 819 | MIPS_INS_TGEI, |
| 820 | MIPS_INS_TGEIU, |
| 821 | MIPS_INS_TGEU, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 822 | MIPS_INS_TLBP, |
| 823 | MIPS_INS_TLBR, |
| 824 | MIPS_INS_TLBWI, |
| 825 | MIPS_INS_TLBWR, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 826 | MIPS_INS_TLT, |
| 827 | MIPS_INS_TLTI, |
| 828 | MIPS_INS_TLTIU, |
| 829 | MIPS_INS_TLTU, |
| 830 | MIPS_INS_TNE, |
| 831 | MIPS_INS_TNEI, |
| 832 | MIPS_INS_TRUNC, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 833 | MIPS_INS_V3MULU, |
| 834 | MIPS_INS_VMM0, |
| 835 | MIPS_INS_VMULU, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 836 | MIPS_INS_VSHF, |
| 837 | MIPS_INS_WAIT, |
| 838 | MIPS_INS_WRDSP, |
| 839 | MIPS_INS_WSBH, |
| 840 | MIPS_INS_XOR, |
| 841 | MIPS_INS_XORI, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 842 | |
Nguyen Anh Quynh | 75ef242 | 2014-01-14 23:08:20 +0800 | [diff] [blame] | 843 | //> some alias instructions |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 844 | MIPS_INS_NOP, |
Nguyen Anh Quynh | 66f6c22 | 2013-12-11 21:37:24 +0800 | [diff] [blame] | 845 | MIPS_INS_NEGU, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 846 | |
Nguyen Anh Quynh | 54f8cef | 2014-09-24 22:53:54 +0800 | [diff] [blame] | 847 | //> special instructions |
| 848 | MIPS_INS_JALR_HB, // jump and link with Hazard Barrier |
| 849 | MIPS_INS_JR_HB, // jump register with Hazard Barrier |
| 850 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 851 | MIPS_INS_ENDING, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 852 | } mips_insn; |
| 853 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 854 | //> Group of MIPS instructions |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 855 | typedef enum mips_insn_group { |
| 856 | MIPS_GRP_INVALID = 0, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 857 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 858 | MIPS_GRP_BITCOUNT, |
| 859 | MIPS_GRP_DSP, |
| 860 | MIPS_GRP_DSPR2, |
| 861 | MIPS_GRP_FPIDX, |
| 862 | MIPS_GRP_MSA, |
| 863 | MIPS_GRP_MIPS32R2, |
| 864 | MIPS_GRP_MIPS64, |
| 865 | MIPS_GRP_MIPS64R2, |
| 866 | MIPS_GRP_SEINREG, |
| 867 | MIPS_GRP_STDENC, |
| 868 | MIPS_GRP_SWAP, |
| 869 | MIPS_GRP_MICROMIPS, |
| 870 | MIPS_GRP_MIPS16MODE, |
| 871 | MIPS_GRP_FP64BIT, |
| 872 | MIPS_GRP_NONANSFPMATH, |
| 873 | MIPS_GRP_NOTFP64BIT, |
Nguyen Anh Quynh | 162409e | 2013-12-08 20:17:28 +0800 | [diff] [blame] | 874 | MIPS_GRP_NOTINMICROMIPS, |
Nguyen Anh Quynh | bc0b3b9 | 2014-02-19 15:13:20 +0800 | [diff] [blame] | 875 | MIPS_GRP_NOTNACL, |
Nguyen Anh Quynh | 0f0eb98 | 2014-08-14 18:26:39 +0800 | [diff] [blame] | 876 | MIPS_GRP_NOTMIPS32R6, |
| 877 | MIPS_GRP_NOTMIPS64R6, |
| 878 | MIPS_GRP_CNMIPS, |
| 879 | MIPS_GRP_MIPS32, |
| 880 | MIPS_GRP_MIPS32R6, |
| 881 | MIPS_GRP_MIPS64R6, |
| 882 | MIPS_GRP_MIPS2, |
| 883 | MIPS_GRP_MIPS3, |
| 884 | MIPS_GRP_MIPS3_32, |
| 885 | MIPS_GRP_MIPS3_32R2, |
| 886 | MIPS_GRP_MIPS4_32, |
| 887 | MIPS_GRP_MIPS4_32R2, |
| 888 | MIPS_GRP_MIPS5_32R2, |
| 889 | MIPS_GRP_GP32BIT, |
| 890 | MIPS_GRP_GP64BIT, |
Nguyen Anh Quynh | ec0ed8e | 2013-12-02 13:55:38 +0800 | [diff] [blame] | 891 | |
Nguyen Anh Quynh | 3582bc1 | 2013-12-03 09:43:27 +0800 | [diff] [blame] | 892 | MIPS_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps) |
| 893 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 894 | MIPS_GRP_ENDING, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 895 | } mips_insn_group; |
| 896 | |
| 897 | #ifdef __cplusplus |
| 898 | } |
| 899 | #endif |
| 900 | |
| 901 | #endif |