Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1 | (* Capstone Disassembler Engine |
| 2 | * By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> *) |
| 3 | |
| 4 | (* architecture specific info of instruction *) |
| 5 | type mips_op_mem = { |
| 6 | base: int; |
| 7 | displ: int |
| 8 | } |
| 9 | |
| 10 | type mips_op_value = |
| 11 | | MIPS_OP_INVALID of int |
| 12 | | MIPS_OP_REG of int |
| 13 | | MIPS_OP_IMM of int |
| 14 | | MIPS_OP_MEM of mips_op_mem |
| 15 | |
| 16 | type mips_op = { |
| 17 | value: mips_op_value; |
| 18 | } |
| 19 | |
| 20 | type cs_mips = { |
| 21 | op_count: int; |
| 22 | operands: mips_op array; |
| 23 | } |
| 24 | |
| 25 | (* MIPS registers - including alias registers *) |
| 26 | let _MIPS_REG_INVALID = 0;; |
| 27 | let _MIPS_REG_0 = 1;; |
| 28 | let _MIPS_REG_ZERO = _MIPS_REG_0;; |
| 29 | let _MIPS_REG_1 = 2;; |
| 30 | let _MIPS_REG_AT = _MIPS_REG_1;; |
| 31 | let _MIPS_REG_2 = 3;; |
| 32 | let _MIPS_REG_V0 = _MIPS_REG_2;; |
| 33 | let _MIPS_REG_3 = 4;; |
| 34 | let _MIPS_REG_V1 = _MIPS_REG_3;; |
| 35 | let _MIPS_REG_4 = 5;; |
| 36 | let _MIPS_REG_A0 = _MIPS_REG_4;; |
| 37 | let _MIPS_REG_5 = 6;; |
| 38 | let _MIPS_REG_A1 = _MIPS_REG_5;; |
| 39 | let _MIPS_REG_6 = 7;; |
| 40 | let _MIPS_REG_A2 = _MIPS_REG_6;; |
| 41 | let _MIPS_REG_7 = 8;; |
| 42 | let _MIPS_REG_A3 = _MIPS_REG_7;; |
| 43 | let _MIPS_REG_8 = 9;; |
| 44 | let _MIPS_REG_T0 = _MIPS_REG_8;; |
| 45 | let _MIPS_REG_9 = 10;; |
| 46 | let _MIPS_REG_T1 = _MIPS_REG_9;; |
| 47 | let _MIPS_REG_10 = 11;; |
| 48 | let _MIPS_REG_T2 = _MIPS_REG_10;; |
| 49 | let _MIPS_REG_11 = 12;; |
| 50 | let _MIPS_REG_T3 = _MIPS_REG_11;; |
| 51 | let _MIPS_REG_12 = 13;; |
| 52 | let _MIPS_REG_T4 = _MIPS_REG_12;; |
| 53 | let _MIPS_REG_13 = 14;; |
| 54 | let _MIPS_REG_T5 = _MIPS_REG_13;; |
| 55 | let _MIPS_REG_14 = 15;; |
| 56 | let _MIPS_REG_T6 = _MIPS_REG_14;; |
| 57 | let _MIPS_REG_15 = 16;; |
| 58 | let _MIPS_REG_T7 = _MIPS_REG_15;; |
| 59 | let _MIPS_REG_16 = 17;; |
| 60 | let _MIPS_REG_S0 = _MIPS_REG_16;; |
| 61 | let _MIPS_REG_17 = 18;; |
| 62 | let _MIPS_REG_S1 = _MIPS_REG_17;; |
| 63 | let _MIPS_REG_18 = 19;; |
| 64 | let _MIPS_REG_S2 = _MIPS_REG_18;; |
| 65 | let _MIPS_REG_19 = 20;; |
| 66 | let _MIPS_REG_S3 = _MIPS_REG_19;; |
| 67 | let _MIPS_REG_20 = 21;; |
| 68 | let _MIPS_REG_S4 = _MIPS_REG_20;; |
| 69 | let _MIPS_REG_21 = 22;; |
| 70 | let _MIPS_REG_S5 = _MIPS_REG_21;; |
| 71 | let _MIPS_REG_22 = 23;; |
| 72 | let _MIPS_REG_S6 = _MIPS_REG_22;; |
| 73 | let _MIPS_REG_23 = 24;; |
| 74 | let _MIPS_REG_S7 = _MIPS_REG_23;; |
| 75 | let _MIPS_REG_24 = 25;; |
| 76 | let _MIPS_REG_T8 = _MIPS_REG_24;; |
| 77 | let _MIPS_REG_25 = 26;; |
| 78 | let _MIPS_REG_T9 = _MIPS_REG_25;; |
| 79 | let _MIPS_REG_26 = 27;; |
| 80 | let _MIPS_REG_K0 = _MIPS_REG_26;; |
| 81 | let _MIPS_REG_27 = 28;; |
| 82 | let _MIPS_REG_K1 = _MIPS_REG_27;; |
| 83 | let _MIPS_REG_28 = 29;; |
| 84 | let _MIPS_REG_GP = _MIPS_REG_28;; |
| 85 | let _MIPS_REG_29 = 30;; |
| 86 | let _MIPS_REG_SP = _MIPS_REG_29;; |
| 87 | let _MIPS_REG_30 = 31;; |
| 88 | let _MIPS_REG_FP = _MIPS_REG_30;; |
| 89 | let _MIPS_REG_S8 = _MIPS_REG_30;; |
| 90 | let _MIPS_REG_31 = 32;; |
| 91 | let _MIPS_REG_RA = _MIPS_REG_31;; |
| 92 | let _MIPS_REG_DSPCCOND = 33;; |
| 93 | let _MIPS_REG_DSPCARRY = 34;; |
| 94 | let _MIPS_REG_DSPEFI = 35;; |
| 95 | let _MIPS_REG_DSPOUTFLAG = 36;; |
| 96 | let _MIPS_REG_DSPOUTFLAG16_19 = 37;; |
| 97 | let _MIPS_REG_DSPOUTFLAG20 = 38;; |
| 98 | let _MIPS_REG_DSPOUTFLAG21 = 39;; |
| 99 | let _MIPS_REG_DSPOUTFLAG22 = 40;; |
| 100 | let _MIPS_REG_DSPOUTFLAG23 = 41;; |
| 101 | let _MIPS_REG_DSPPOS = 42;; |
| 102 | let _MIPS_REG_DSPSCOUNT = 43;; |
| 103 | let _MIPS_REG_AC0 = 44;; |
| 104 | let _MIPS_REG_HI0 = _MIPS_REG_AC0;; |
| 105 | let _MIPS_REG_AC1 = 45;; |
| 106 | let _MIPS_REG_HI1 = _MIPS_REG_AC1;; |
| 107 | let _MIPS_REG_AC2 = 46;; |
| 108 | let _MIPS_REG_HI2 = _MIPS_REG_AC2;; |
| 109 | let _MIPS_REG_AC3 = 47;; |
| 110 | let _MIPS_REG_HI3 = _MIPS_REG_AC3;; |
| 111 | let _MIPS_REG_LO0 = _MIPS_REG_HI0;; |
| 112 | let _MIPS_REG_LO1 = _MIPS_REG_HI1;; |
| 113 | let _MIPS_REG_LO2 = _MIPS_REG_HI2;; |
| 114 | let _MIPS_REG_LO3 = _MIPS_REG_HI3;; |
| 115 | let _MIPS_REG_F0 = 48;; |
| 116 | let _MIPS_REG_F1 = 49;; |
| 117 | let _MIPS_REG_F2 = 50;; |
| 118 | let _MIPS_REG_F3 = 51;; |
| 119 | let _MIPS_REG_F4 = 52;; |
| 120 | let _MIPS_REG_F5 = 53;; |
| 121 | let _MIPS_REG_F6 = 54;; |
| 122 | let _MIPS_REG_F7 = 55;; |
| 123 | let _MIPS_REG_F8 = 56;; |
| 124 | let _MIPS_REG_F9 = 57;; |
| 125 | let _MIPS_REG_F10 = 58;; |
| 126 | let _MIPS_REG_F11 = 59;; |
| 127 | let _MIPS_REG_F12 = 60;; |
| 128 | let _MIPS_REG_F13 = 61;; |
| 129 | let _MIPS_REG_F14 = 62;; |
| 130 | let _MIPS_REG_F15 = 63;; |
| 131 | let _MIPS_REG_F16 = 64;; |
| 132 | let _MIPS_REG_F17 = 65;; |
| 133 | let _MIPS_REG_F18 = 66;; |
| 134 | let _MIPS_REG_F19 = 67;; |
| 135 | let _MIPS_REG_F20 = 68;; |
| 136 | let _MIPS_REG_F21 = 69;; |
| 137 | let _MIPS_REG_F22 = 70;; |
| 138 | let _MIPS_REG_F23 = 71;; |
| 139 | let _MIPS_REG_F24 = 72;; |
| 140 | let _MIPS_REG_F25 = 73;; |
| 141 | let _MIPS_REG_F26 = 74;; |
| 142 | let _MIPS_REG_F27 = 75;; |
| 143 | let _MIPS_REG_F28 = 76;; |
| 144 | let _MIPS_REG_F29 = 77;; |
| 145 | let _MIPS_REG_F30 = 78;; |
| 146 | let _MIPS_REG_F31 = 79;; |
| 147 | let _MIPS_REG_FCC0 = 80;; |
| 148 | let _MIPS_REG_FCC1 = 81;; |
| 149 | let _MIPS_REG_FCC2 = 82;; |
| 150 | let _MIPS_REG_FCC3 = 83;; |
| 151 | let _MIPS_REG_FCC4 = 84;; |
| 152 | let _MIPS_REG_FCC5 = 85;; |
| 153 | let _MIPS_REG_FCC6 = 86;; |
| 154 | let _MIPS_REG_FCC7 = 87;; |
| 155 | let _MIPS_REG_W0 = 88;; |
| 156 | let _MIPS_REG_W1 = 89;; |
| 157 | let _MIPS_REG_W2 = 90;; |
| 158 | let _MIPS_REG_W3 = 91;; |
| 159 | let _MIPS_REG_W4 = 92;; |
| 160 | let _MIPS_REG_W5 = 93;; |
| 161 | let _MIPS_REG_W6 = 94;; |
| 162 | let _MIPS_REG_W7 = 95;; |
| 163 | let _MIPS_REG_W8 = 96;; |
| 164 | let _MIPS_REG_W9 = 97;; |
| 165 | let _MIPS_REG_W10 = 98;; |
| 166 | let _MIPS_REG_W11 = 99;; |
| 167 | let _MIPS_REG_W12 = 100;; |
| 168 | let _MIPS_REG_W13 = 101;; |
| 169 | let _MIPS_REG_W14 = 102;; |
| 170 | let _MIPS_REG_W15 = 103;; |
| 171 | let _MIPS_REG_W16 = 104;; |
| 172 | let _MIPS_REG_W17 = 105;; |
| 173 | let _MIPS_REG_W18 = 106;; |
| 174 | let _MIPS_REG_W19 = 107;; |
| 175 | let _MIPS_REG_W20 = 108;; |
| 176 | let _MIPS_REG_W21 = 109;; |
| 177 | let _MIPS_REG_W22 = 110;; |
| 178 | let _MIPS_REG_W23 = 111;; |
| 179 | let _MIPS_REG_W24 = 112;; |
| 180 | let _MIPS_REG_W25 = 113;; |
| 181 | let _MIPS_REG_W26 = 114;; |
| 182 | let _MIPS_REG_W27 = 115;; |
| 183 | let _MIPS_REG_W28 = 116;; |
| 184 | let _MIPS_REG_W29 = 117;; |
| 185 | let _MIPS_REG_W30 = 118;; |
| 186 | let _MIPS_REG_W31 = 119;; |
| 187 | let _MIPS_REG_MAX = 120;; |
| 188 | |
| 189 | |
| 190 | (* MIPS instructions *) |
| 191 | let _MIPS_INS_INVALID = 0;; |
| 192 | let _MIPS_INS_ABSQ_S = 1;; |
| 193 | let _MIPS_INS_ADD = 2;; |
| 194 | let _MIPS_INS_ADDQH = 3;; |
| 195 | let _MIPS_INS_ADDQH_R = 4;; |
| 196 | let _MIPS_INS_ADDQ = 5;; |
| 197 | let _MIPS_INS_ADDQ_S = 6;; |
| 198 | let _MIPS_INS_ADDSC = 7;; |
| 199 | let _MIPS_INS_ADDS_A = 8;; |
| 200 | let _MIPS_INS_ADDS_S = 9;; |
| 201 | let _MIPS_INS_ADDS_U = 10;; |
| 202 | let _MIPS_INS_ADDUH = 11;; |
| 203 | let _MIPS_INS_ADDUH_R = 12;; |
| 204 | let _MIPS_INS_ADDU = 13;; |
| 205 | let _MIPS_INS_ADDU_S = 14;; |
| 206 | let _MIPS_INS_ADDVI = 15;; |
| 207 | let _MIPS_INS_ADDV = 16;; |
| 208 | let _MIPS_INS_ADDWC = 17;; |
| 209 | let _MIPS_INS_ADD_A = 18;; |
| 210 | let _MIPS_INS_ADDI = 19;; |
| 211 | let _MIPS_INS_ADDIU = 20;; |
| 212 | let _MIPS_INS_AND = 21;; |
| 213 | let _MIPS_INS_ANDI = 22;; |
| 214 | let _MIPS_INS_APPEND = 23;; |
| 215 | let _MIPS_INS_ASUB_S = 24;; |
| 216 | let _MIPS_INS_ASUB_U = 25;; |
| 217 | let _MIPS_INS_AVER_S = 26;; |
| 218 | let _MIPS_INS_AVER_U = 27;; |
| 219 | let _MIPS_INS_AVE_S = 28;; |
| 220 | let _MIPS_INS_AVE_U = 29;; |
| 221 | let _MIPS_INS_BALIGN = 30;; |
| 222 | let _MIPS_INS_BC1F = 31;; |
| 223 | let _MIPS_INS_BC1T = 32;; |
| 224 | let _MIPS_INS_BCLRI = 33;; |
| 225 | let _MIPS_INS_BCLR = 34;; |
| 226 | let _MIPS_INS_BEQ = 35;; |
| 227 | let _MIPS_INS_BGEZ = 36;; |
| 228 | let _MIPS_INS_BGEZAL = 37;; |
| 229 | let _MIPS_INS_BGTZ = 38;; |
| 230 | let _MIPS_INS_BINSLI = 39;; |
| 231 | let _MIPS_INS_BINSL = 40;; |
| 232 | let _MIPS_INS_BINSRI = 41;; |
| 233 | let _MIPS_INS_BINSR = 42;; |
| 234 | let _MIPS_INS_BITREV = 43;; |
| 235 | let _MIPS_INS_BLEZ = 44;; |
| 236 | let _MIPS_INS_BLTZ = 45;; |
| 237 | let _MIPS_INS_BLTZAL = 46;; |
| 238 | let _MIPS_INS_BMNZI = 47;; |
| 239 | let _MIPS_INS_BMNZ = 48;; |
| 240 | let _MIPS_INS_BMZI = 49;; |
| 241 | let _MIPS_INS_BMZ = 50;; |
| 242 | let _MIPS_INS_BNE = 51;; |
| 243 | let _MIPS_INS_BNEGI = 52;; |
| 244 | let _MIPS_INS_BNEG = 53;; |
| 245 | let _MIPS_INS_BNZ = 54;; |
| 246 | let _MIPS_INS_BPOSGE32 = 55;; |
| 247 | let _MIPS_INS_BREAK = 56;; |
| 248 | let _MIPS_INS_BSELI = 57;; |
| 249 | let _MIPS_INS_BSEL = 58;; |
| 250 | let _MIPS_INS_BSETI = 59;; |
| 251 | let _MIPS_INS_BSET = 60;; |
| 252 | let _MIPS_INS_BZ = 61;; |
| 253 | let _MIPS_INS_BEQZ = 62;; |
| 254 | let _MIPS_INS_B = 63;; |
| 255 | let _MIPS_INS_BNEZ = 64;; |
| 256 | let _MIPS_INS_BTEQZ = 65;; |
| 257 | let _MIPS_INS_BTNEZ = 66;; |
| 258 | let _MIPS_INS_CEIL = 67;; |
| 259 | let _MIPS_INS_CEQI = 68;; |
| 260 | let _MIPS_INS_CEQ = 69;; |
| 261 | let _MIPS_INS_CFC1 = 70;; |
| 262 | let _MIPS_INS_CFCMSA = 71;; |
| 263 | let _MIPS_INS_CLEI_S = 72;; |
| 264 | let _MIPS_INS_CLEI_U = 73;; |
| 265 | let _MIPS_INS_CLE_S = 74;; |
| 266 | let _MIPS_INS_CLE_U = 75;; |
| 267 | let _MIPS_INS_CLO = 76;; |
| 268 | let _MIPS_INS_CLTI_S = 77;; |
| 269 | let _MIPS_INS_CLTI_U = 78;; |
| 270 | let _MIPS_INS_CLT_S = 79;; |
| 271 | let _MIPS_INS_CLT_U = 80;; |
| 272 | let _MIPS_INS_CLZ = 81;; |
| 273 | let _MIPS_INS_CMPGDU = 82;; |
| 274 | let _MIPS_INS_CMPGU = 83;; |
| 275 | let _MIPS_INS_CMPU = 84;; |
| 276 | let _MIPS_INS_CMP = 85;; |
| 277 | let _MIPS_INS_COPY_S = 86;; |
| 278 | let _MIPS_INS_COPY_U = 87;; |
| 279 | let _MIPS_INS_CTC1 = 88;; |
| 280 | let _MIPS_INS_CTCMSA = 89;; |
| 281 | let _MIPS_INS_CVT = 90;; |
| 282 | let _MIPS_INS_C = 91;; |
| 283 | let _MIPS_INS_CMPI = 92;; |
| 284 | let _MIPS_INS_DADD = 93;; |
| 285 | let _MIPS_INS_DADDI = 94;; |
| 286 | let _MIPS_INS_DADDIU = 95;; |
| 287 | let _MIPS_INS_DADDU = 96;; |
| 288 | let _MIPS_INS_DCLO = 97;; |
| 289 | let _MIPS_INS_DCLZ = 98;; |
| 290 | let _MIPS_INS_DERET = 99;; |
| 291 | let _MIPS_INS_DEXT = 100;; |
| 292 | let _MIPS_INS_DEXTM = 101;; |
| 293 | let _MIPS_INS_DEXTU = 102;; |
| 294 | let _MIPS_INS_DI = 103;; |
| 295 | let _MIPS_INS_DINS = 104;; |
| 296 | let _MIPS_INS_DINSM = 105;; |
| 297 | let _MIPS_INS_DINSU = 106;; |
| 298 | let _MIPS_INS_DIV_S = 107;; |
| 299 | let _MIPS_INS_DIV_U = 108;; |
| 300 | let _MIPS_INS_DMFC0 = 109;; |
| 301 | let _MIPS_INS_DMFC1 = 110;; |
| 302 | let _MIPS_INS_DMFC2 = 111;; |
| 303 | let _MIPS_INS_DMTC0 = 112;; |
| 304 | let _MIPS_INS_DMTC1 = 113;; |
| 305 | let _MIPS_INS_DMTC2 = 114;; |
| 306 | let _MIPS_INS_DMULT = 115;; |
| 307 | let _MIPS_INS_DMULTU = 116;; |
| 308 | let _MIPS_INS_DOTP_S = 117;; |
| 309 | let _MIPS_INS_DOTP_U = 118;; |
| 310 | let _MIPS_INS_DPADD_S = 119;; |
| 311 | let _MIPS_INS_DPADD_U = 120;; |
| 312 | let _MIPS_INS_DPAQX_SA = 121;; |
| 313 | let _MIPS_INS_DPAQX_S = 122;; |
| 314 | let _MIPS_INS_DPAQ_SA = 123;; |
| 315 | let _MIPS_INS_DPAQ_S = 124;; |
| 316 | let _MIPS_INS_DPAU = 125;; |
| 317 | let _MIPS_INS_DPAX = 126;; |
| 318 | let _MIPS_INS_DPA = 127;; |
| 319 | let _MIPS_INS_DPSQX_SA = 128;; |
| 320 | let _MIPS_INS_DPSQX_S = 129;; |
| 321 | let _MIPS_INS_DPSQ_SA = 130;; |
| 322 | let _MIPS_INS_DPSQ_S = 131;; |
| 323 | let _MIPS_INS_DPSUB_S = 132;; |
| 324 | let _MIPS_INS_DPSUB_U = 133;; |
| 325 | let _MIPS_INS_DPSU = 134;; |
| 326 | let _MIPS_INS_DPSX = 135;; |
| 327 | let _MIPS_INS_DPS = 136;; |
| 328 | let _MIPS_INS_DROTR = 137;; |
| 329 | let _MIPS_INS_DROTR32 = 138;; |
| 330 | let _MIPS_INS_DROTRV = 139;; |
| 331 | let _MIPS_INS_DSBH = 140;; |
| 332 | let _MIPS_INS_DDIV = 141;; |
| 333 | let _MIPS_INS_DSHD = 142;; |
| 334 | let _MIPS_INS_DSLL = 143;; |
| 335 | let _MIPS_INS_DSLL32 = 144;; |
| 336 | let _MIPS_INS_DSLLV = 145;; |
| 337 | let _MIPS_INS_DSRA = 146;; |
| 338 | let _MIPS_INS_DSRA32 = 147;; |
| 339 | let _MIPS_INS_DSRAV = 148;; |
| 340 | let _MIPS_INS_DSRL = 149;; |
| 341 | let _MIPS_INS_DSRL32 = 150;; |
| 342 | let _MIPS_INS_DSRLV = 151;; |
| 343 | let _MIPS_INS_DSUBU = 152;; |
| 344 | let _MIPS_INS_DDIVU = 153;; |
| 345 | let _MIPS_INS_DIV = 154;; |
| 346 | let _MIPS_INS_DIVU = 155;; |
| 347 | let _MIPS_INS_EI = 156;; |
| 348 | let _MIPS_INS_ERET = 157;; |
| 349 | let _MIPS_INS_EXT = 158;; |
| 350 | let _MIPS_INS_EXTP = 159;; |
| 351 | let _MIPS_INS_EXTPDP = 160;; |
| 352 | let _MIPS_INS_EXTPDPV = 161;; |
| 353 | let _MIPS_INS_EXTPV = 162;; |
| 354 | let _MIPS_INS_EXTRV_RS = 163;; |
| 355 | let _MIPS_INS_EXTRV_R = 164;; |
| 356 | let _MIPS_INS_EXTRV_S = 165;; |
| 357 | let _MIPS_INS_EXTRV = 166;; |
| 358 | let _MIPS_INS_EXTR_RS = 167;; |
| 359 | let _MIPS_INS_EXTR_R = 168;; |
| 360 | let _MIPS_INS_EXTR_S = 169;; |
| 361 | let _MIPS_INS_EXTR = 170;; |
| 362 | let _MIPS_INS_ABS = 171;; |
| 363 | let _MIPS_INS_FADD = 172;; |
| 364 | let _MIPS_INS_FCAF = 173;; |
| 365 | let _MIPS_INS_FCEQ = 174;; |
| 366 | let _MIPS_INS_FCLASS = 175;; |
| 367 | let _MIPS_INS_FCLE = 176;; |
| 368 | let _MIPS_INS_FCLT = 177;; |
| 369 | let _MIPS_INS_FCNE = 178;; |
| 370 | let _MIPS_INS_FCOR = 179;; |
| 371 | let _MIPS_INS_FCUEQ = 180;; |
| 372 | let _MIPS_INS_FCULE = 181;; |
| 373 | let _MIPS_INS_FCULT = 182;; |
| 374 | let _MIPS_INS_FCUNE = 183;; |
| 375 | let _MIPS_INS_FCUN = 184;; |
| 376 | let _MIPS_INS_FDIV = 185;; |
| 377 | let _MIPS_INS_FEXDO = 186;; |
| 378 | let _MIPS_INS_FEXP2 = 187;; |
| 379 | let _MIPS_INS_FEXUPL = 188;; |
| 380 | let _MIPS_INS_FEXUPR = 189;; |
| 381 | let _MIPS_INS_FFINT_S = 190;; |
| 382 | let _MIPS_INS_FFINT_U = 191;; |
| 383 | let _MIPS_INS_FFQL = 192;; |
| 384 | let _MIPS_INS_FFQR = 193;; |
| 385 | let _MIPS_INS_FILL = 194;; |
| 386 | let _MIPS_INS_FLOG2 = 195;; |
| 387 | let _MIPS_INS_FLOOR = 196;; |
| 388 | let _MIPS_INS_FMADD = 197;; |
| 389 | let _MIPS_INS_FMAX_A = 198;; |
| 390 | let _MIPS_INS_FMAX = 199;; |
| 391 | let _MIPS_INS_FMIN_A = 200;; |
| 392 | let _MIPS_INS_FMIN = 201;; |
| 393 | let _MIPS_INS_MOV = 202;; |
| 394 | let _MIPS_INS_FMSUB = 203;; |
| 395 | let _MIPS_INS_FMUL = 204;; |
| 396 | let _MIPS_INS_MUL = 205;; |
| 397 | let _MIPS_INS_NEG = 206;; |
| 398 | let _MIPS_INS_FRCP = 207;; |
| 399 | let _MIPS_INS_FRINT = 208;; |
| 400 | let _MIPS_INS_FRSQRT = 209;; |
| 401 | let _MIPS_INS_FSAF = 210;; |
| 402 | let _MIPS_INS_FSEQ = 211;; |
| 403 | let _MIPS_INS_FSLE = 212;; |
| 404 | let _MIPS_INS_FSLT = 213;; |
| 405 | let _MIPS_INS_FSNE = 214;; |
| 406 | let _MIPS_INS_FSOR = 215;; |
| 407 | let _MIPS_INS_FSQRT = 216;; |
| 408 | let _MIPS_INS_SQRT = 217;; |
| 409 | let _MIPS_INS_FSUB = 218;; |
| 410 | let _MIPS_INS_SUB = 219;; |
| 411 | let _MIPS_INS_FSUEQ = 220;; |
| 412 | let _MIPS_INS_FSULE = 221;; |
| 413 | let _MIPS_INS_FSULT = 222;; |
| 414 | let _MIPS_INS_FSUNE = 223;; |
| 415 | let _MIPS_INS_FSUN = 224;; |
| 416 | let _MIPS_INS_FTINT_S = 225;; |
| 417 | let _MIPS_INS_FTINT_U = 226;; |
| 418 | let _MIPS_INS_FTQ = 227;; |
| 419 | let _MIPS_INS_FTRUNC_S = 228;; |
| 420 | let _MIPS_INS_FTRUNC_U = 229;; |
| 421 | let _MIPS_INS_HADD_S = 230;; |
| 422 | let _MIPS_INS_HADD_U = 231;; |
| 423 | let _MIPS_INS_HSUB_S = 232;; |
| 424 | let _MIPS_INS_HSUB_U = 233;; |
| 425 | let _MIPS_INS_ILVEV = 234;; |
| 426 | let _MIPS_INS_ILVL = 235;; |
| 427 | let _MIPS_INS_ILVOD = 236;; |
| 428 | let _MIPS_INS_ILVR = 237;; |
| 429 | let _MIPS_INS_INS = 238;; |
| 430 | let _MIPS_INS_INSERT = 239;; |
| 431 | let _MIPS_INS_INSV = 240;; |
| 432 | let _MIPS_INS_INSVE = 241;; |
| 433 | let _MIPS_INS_J = 242;; |
| 434 | let _MIPS_INS_JAL = 243;; |
| 435 | let _MIPS_INS_JALR = 244;; |
| 436 | let _MIPS_INS_JR = 245;; |
| 437 | let _MIPS_INS_JRC = 246;; |
| 438 | let _MIPS_INS_JALRC = 247;; |
| 439 | let _MIPS_INS_LB = 248;; |
| 440 | let _MIPS_INS_LBUX = 249;; |
| 441 | let _MIPS_INS_LBU = 250;; |
| 442 | let _MIPS_INS_LD = 251;; |
| 443 | let _MIPS_INS_LDC1 = 252;; |
| 444 | let _MIPS_INS_LDC2 = 253;; |
| 445 | let _MIPS_INS_LDI = 254;; |
| 446 | let _MIPS_INS_LDL = 255;; |
| 447 | let _MIPS_INS_LDR = 256;; |
| 448 | let _MIPS_INS_LDXC1 = 257;; |
| 449 | let _MIPS_INS_LH = 258;; |
| 450 | let _MIPS_INS_LHX = 259;; |
| 451 | let _MIPS_INS_LHU = 260;; |
| 452 | let _MIPS_INS_LL = 261;; |
| 453 | let _MIPS_INS_LLD = 262;; |
| 454 | let _MIPS_INS_LSA = 263;; |
| 455 | let _MIPS_INS_LUXC1 = 264;; |
| 456 | let _MIPS_INS_LUI = 265;; |
| 457 | let _MIPS_INS_LW = 266;; |
| 458 | let _MIPS_INS_LWC1 = 267;; |
| 459 | let _MIPS_INS_LWC2 = 268;; |
| 460 | let _MIPS_INS_LWL = 269;; |
| 461 | let _MIPS_INS_LWR = 270;; |
| 462 | let _MIPS_INS_LWX = 271;; |
| 463 | let _MIPS_INS_LWXC1 = 272;; |
| 464 | let _MIPS_INS_LWU = 273;; |
| 465 | let _MIPS_INS_LI = 274;; |
| 466 | let _MIPS_INS_MADD = 275;; |
| 467 | let _MIPS_INS_MADDR_Q = 276;; |
| 468 | let _MIPS_INS_MADDU = 277;; |
| 469 | let _MIPS_INS_MADDV = 278;; |
| 470 | let _MIPS_INS_MADD_Q = 279;; |
| 471 | let _MIPS_INS_MAQ_SA = 280;; |
| 472 | let _MIPS_INS_MAQ_S = 281;; |
| 473 | let _MIPS_INS_MAXI_S = 282;; |
| 474 | let _MIPS_INS_MAXI_U = 283;; |
| 475 | let _MIPS_INS_MAX_A = 284;; |
| 476 | let _MIPS_INS_MAX_S = 285;; |
| 477 | let _MIPS_INS_MAX_U = 286;; |
| 478 | let _MIPS_INS_MFC0 = 287;; |
| 479 | let _MIPS_INS_MFC1 = 288;; |
| 480 | let _MIPS_INS_MFC2 = 289;; |
| 481 | let _MIPS_INS_MFHC1 = 290;; |
| 482 | let _MIPS_INS_MFHI = 291;; |
| 483 | let _MIPS_INS_MFLO = 292;; |
| 484 | let _MIPS_INS_MINI_S = 293;; |
| 485 | let _MIPS_INS_MINI_U = 294;; |
| 486 | let _MIPS_INS_MIN_A = 295;; |
| 487 | let _MIPS_INS_MIN_S = 296;; |
| 488 | let _MIPS_INS_MIN_U = 297;; |
| 489 | let _MIPS_INS_MODSUB = 298;; |
| 490 | let _MIPS_INS_MOD_S = 299;; |
| 491 | let _MIPS_INS_MOD_U = 300;; |
| 492 | let _MIPS_INS_MOVE = 301;; |
| 493 | let _MIPS_INS_MOVF = 302;; |
| 494 | let _MIPS_INS_MOVN = 303;; |
| 495 | let _MIPS_INS_MOVT = 304;; |
| 496 | let _MIPS_INS_MOVZ = 305;; |
| 497 | let _MIPS_INS_MSUB = 306;; |
| 498 | let _MIPS_INS_MSUBR_Q = 307;; |
| 499 | let _MIPS_INS_MSUBU = 308;; |
| 500 | let _MIPS_INS_MSUBV = 309;; |
| 501 | let _MIPS_INS_MSUB_Q = 310;; |
| 502 | let _MIPS_INS_MTC0 = 311;; |
| 503 | let _MIPS_INS_MTC1 = 312;; |
| 504 | let _MIPS_INS_MTC2 = 313;; |
| 505 | let _MIPS_INS_MTHC1 = 314;; |
| 506 | let _MIPS_INS_MTHI = 315;; |
| 507 | let _MIPS_INS_MTHLIP = 316;; |
| 508 | let _MIPS_INS_MTLO = 317;; |
| 509 | let _MIPS_INS_MULEQ_S = 318;; |
| 510 | let _MIPS_INS_MULEU_S = 319;; |
| 511 | let _MIPS_INS_MULQ_RS = 320;; |
| 512 | let _MIPS_INS_MULQ_S = 321;; |
| 513 | let _MIPS_INS_MULR_Q = 322;; |
| 514 | let _MIPS_INS_MULSAQ_S = 323;; |
| 515 | let _MIPS_INS_MULSA = 324;; |
| 516 | let _MIPS_INS_MULT = 325;; |
| 517 | let _MIPS_INS_MULTU = 326;; |
| 518 | let _MIPS_INS_MULV = 327;; |
| 519 | let _MIPS_INS_MUL_Q = 328;; |
| 520 | let _MIPS_INS_MUL_S = 329;; |
| 521 | let _MIPS_INS_NLOC = 330;; |
| 522 | let _MIPS_INS_NLZC = 331;; |
| 523 | let _MIPS_INS_NMADD = 332;; |
| 524 | let _MIPS_INS_NMSUB = 333;; |
| 525 | let _MIPS_INS_NOR = 334;; |
| 526 | let _MIPS_INS_NORI = 335;; |
| 527 | let _MIPS_INS_NOT = 336;; |
| 528 | let _MIPS_INS_OR = 337;; |
| 529 | let _MIPS_INS_ORI = 338;; |
| 530 | let _MIPS_INS_PACKRL = 339;; |
| 531 | let _MIPS_INS_PCKEV = 340;; |
| 532 | let _MIPS_INS_PCKOD = 341;; |
| 533 | let _MIPS_INS_PCNT = 342;; |
| 534 | let _MIPS_INS_PICK = 343;; |
| 535 | let _MIPS_INS_PRECEQU = 344;; |
| 536 | let _MIPS_INS_PRECEQ = 345;; |
| 537 | let _MIPS_INS_PRECEU = 346;; |
| 538 | let _MIPS_INS_PRECRQU_S = 347;; |
| 539 | let _MIPS_INS_PRECRQ = 348;; |
| 540 | let _MIPS_INS_PRECRQ_RS = 349;; |
| 541 | let _MIPS_INS_PRECR = 350;; |
| 542 | let _MIPS_INS_PRECR_SRA = 351;; |
| 543 | let _MIPS_INS_PRECR_SRA_R = 352;; |
| 544 | let _MIPS_INS_PREPEND = 353;; |
| 545 | let _MIPS_INS_RADDU = 354;; |
| 546 | let _MIPS_INS_RDDSP = 355;; |
| 547 | let _MIPS_INS_RDHWR = 356;; |
| 548 | let _MIPS_INS_REPLV = 357;; |
| 549 | let _MIPS_INS_REPL = 358;; |
| 550 | let _MIPS_INS_ROTR = 359;; |
| 551 | let _MIPS_INS_ROTRV = 360;; |
| 552 | let _MIPS_INS_ROUND = 361;; |
| 553 | let _MIPS_INS_RESTORE = 362;; |
| 554 | let _MIPS_INS_SAT_S = 363;; |
| 555 | let _MIPS_INS_SAT_U = 364;; |
| 556 | let _MIPS_INS_SB = 365;; |
| 557 | let _MIPS_INS_SC = 366;; |
| 558 | let _MIPS_INS_SCD = 367;; |
| 559 | let _MIPS_INS_SD = 368;; |
| 560 | let _MIPS_INS_SDC1 = 369;; |
| 561 | let _MIPS_INS_SDC2 = 370;; |
| 562 | let _MIPS_INS_SDL = 371;; |
| 563 | let _MIPS_INS_SDR = 372;; |
| 564 | let _MIPS_INS_SDXC1 = 373;; |
| 565 | let _MIPS_INS_SEB = 374;; |
| 566 | let _MIPS_INS_SEH = 375;; |
| 567 | let _MIPS_INS_SH = 376;; |
| 568 | let _MIPS_INS_SHF = 377;; |
| 569 | let _MIPS_INS_SHILO = 378;; |
| 570 | let _MIPS_INS_SHILOV = 379;; |
| 571 | let _MIPS_INS_SHLLV = 380;; |
| 572 | let _MIPS_INS_SHLLV_S = 381;; |
| 573 | let _MIPS_INS_SHLL = 382;; |
| 574 | let _MIPS_INS_SHLL_S = 383;; |
| 575 | let _MIPS_INS_SHRAV = 384;; |
| 576 | let _MIPS_INS_SHRAV_R = 385;; |
| 577 | let _MIPS_INS_SHRA = 386;; |
| 578 | let _MIPS_INS_SHRA_R = 387;; |
| 579 | let _MIPS_INS_SHRLV = 388;; |
| 580 | let _MIPS_INS_SHRL = 389;; |
| 581 | let _MIPS_INS_SLDI = 390;; |
| 582 | let _MIPS_INS_SLD = 391;; |
| 583 | let _MIPS_INS_SLL = 392;; |
| 584 | let _MIPS_INS_SLLI = 393;; |
| 585 | let _MIPS_INS_SLLV = 394;; |
| 586 | let _MIPS_INS_SLT = 395;; |
| 587 | let _MIPS_INS_SLTI = 396;; |
| 588 | let _MIPS_INS_SLTIU = 397;; |
| 589 | let _MIPS_INS_SLTU = 398;; |
| 590 | let _MIPS_INS_SPLATI = 399;; |
| 591 | let _MIPS_INS_SPLAT = 400;; |
| 592 | let _MIPS_INS_SRA = 401;; |
| 593 | let _MIPS_INS_SRAI = 402;; |
| 594 | let _MIPS_INS_SRARI = 403;; |
| 595 | let _MIPS_INS_SRAR = 404;; |
| 596 | let _MIPS_INS_SRAV = 405;; |
| 597 | let _MIPS_INS_SRL = 406;; |
| 598 | let _MIPS_INS_SRLI = 407;; |
| 599 | let _MIPS_INS_SRLRI = 408;; |
| 600 | let _MIPS_INS_SRLR = 409;; |
| 601 | let _MIPS_INS_SRLV = 410;; |
| 602 | let _MIPS_INS_ST = 411;; |
| 603 | let _MIPS_INS_SUBQH = 412;; |
| 604 | let _MIPS_INS_SUBQH_R = 413;; |
| 605 | let _MIPS_INS_SUBQ = 414;; |
| 606 | let _MIPS_INS_SUBQ_S = 415;; |
| 607 | let _MIPS_INS_SUBSUS_U = 416;; |
| 608 | let _MIPS_INS_SUBSUU_S = 417;; |
| 609 | let _MIPS_INS_SUBS_S = 418;; |
| 610 | let _MIPS_INS_SUBS_U = 419;; |
| 611 | let _MIPS_INS_SUBUH = 420;; |
| 612 | let _MIPS_INS_SUBUH_R = 421;; |
| 613 | let _MIPS_INS_SUBU = 422;; |
| 614 | let _MIPS_INS_SUBU_S = 423;; |
| 615 | let _MIPS_INS_SUBVI = 424;; |
| 616 | let _MIPS_INS_SUBV = 425;; |
| 617 | let _MIPS_INS_SUXC1 = 426;; |
| 618 | let _MIPS_INS_SW = 427;; |
| 619 | let _MIPS_INS_SWC1 = 428;; |
| 620 | let _MIPS_INS_SWC2 = 429;; |
| 621 | let _MIPS_INS_SWL = 430;; |
| 622 | let _MIPS_INS_SWR = 431;; |
| 623 | let _MIPS_INS_SWXC1 = 432;; |
| 624 | let _MIPS_INS_SYNC = 433;; |
| 625 | let _MIPS_INS_SYSCALL = 434;; |
| 626 | let _MIPS_INS_SAVE = 435;; |
| 627 | let _MIPS_INS_TEQ = 436;; |
| 628 | let _MIPS_INS_TEQI = 437;; |
| 629 | let _MIPS_INS_TGE = 438;; |
| 630 | let _MIPS_INS_TGEI = 439;; |
| 631 | let _MIPS_INS_TGEIU = 440;; |
| 632 | let _MIPS_INS_TGEU = 441;; |
| 633 | let _MIPS_INS_TLT = 442;; |
| 634 | let _MIPS_INS_TLTI = 443;; |
| 635 | let _MIPS_INS_TLTU = 444;; |
| 636 | let _MIPS_INS_TNE = 445;; |
| 637 | let _MIPS_INS_TNEI = 446;; |
| 638 | let _MIPS_INS_TRUNC = 447;; |
| 639 | let _MIPS_INS_TLTIU = 448;; |
| 640 | let _MIPS_INS_VSHF = 449;; |
| 641 | let _MIPS_INS_WAIT = 450;; |
| 642 | let _MIPS_INS_WRDSP = 451;; |
| 643 | let _MIPS_INS_WSBH = 452;; |
| 644 | let _MIPS_INS_XOR = 453;; |
| 645 | let _MIPS_INS_XORI = 454;; |
| 646 | let _MIPS_INS_NOP = 455;; |
| 647 | let _MIPS_INS_MAX = 456;; |
| 648 | |
| 649 | |
| 650 | (* MIPS group of instructions *) |
| 651 | let _MIPS_GRP_INVALID = 0;; |
| 652 | let _MIPS_GRP_BITCOUNT = 1;; |
| 653 | let _MIPS_GRP_DSP = 2;; |
| 654 | let _MIPS_GRP_DSPR2 = 3;; |
| 655 | let _MIPS_GRP_FPIDX = 4;; |
| 656 | let _MIPS_GRP_MSA = 5;; |
| 657 | let _MIPS_GRP_MIPS32R2 = 6;; |
| 658 | let _MIPS_GRP_MIPS64 = 7;; |
| 659 | let _MIPS_GRP_MIPS64R2 = 8;; |
| 660 | let _MIPS_GRP_SEINREG = 9;; |
| 661 | let _MIPS_GRP_STDENC = 10;; |
| 662 | let _MIPS_GRP_SWAP = 11;; |
| 663 | let _MIPS_GRP_MICROMIPS = 12;; |
| 664 | let _MIPS_GRP_MIPS16MODE = 13;; |
| 665 | let _MIPS_GRP_FP64BIT = 14;; |
| 666 | let _MIPS_GRP_NONANSFPMATH = 15;; |
| 667 | let _MIPS_GRP_NOTFP64BIT = 16;; |
| 668 | let _MIPS_GRP_RELOCSTATIC = 17;; |
| 669 | let _MIPS_GRP_MAX = 18;; |
| 670 | |