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Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +08001#!/usr/bin/env python
2
3# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
fenuks110ab1d2014-04-11 11:00:33 +02004from __future__ import print_function
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +08005from capstone import *
6from capstone.mips import *
Nguyen Anh Quynh10983292014-05-17 09:51:15 +08007from xprint import to_hex, to_x
8
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +08009
fenuks110ab1d2014-04-11 11:00:33 +020010MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
11MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
Nguyen Anh Quynh248519e2014-11-09 14:07:07 +080012MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
13MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080014
15all_tests = (
Nguyen Anh Quynhec58a022014-11-13 11:42:38 +080016 (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
17 (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
Nguyen Anh Quynh7e75ca62014-11-13 11:17:38 +080018 (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"),
19 (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)"),
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080020)
21
Nguyen Anh Quynh10983292014-05-17 09:51:15 +080022
23def print_insn_detail(insn):
24 # print address, mnemonic and operands
25 print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
26
27 # "data" instruction generated by SKIPDATA option has no detail
28 if insn.id == 0:
29 return
30
31 if len(insn.operands) > 0:
32 print("\top_count: %u" % len(insn.operands))
33 c = -1
34 for i in insn.operands:
35 c += 1
36 if i.type == MIPS_OP_REG:
37 print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
38 if i.type == MIPS_OP_IMM:
39 print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
40 if i.type == MIPS_OP_MEM:
41 print("\t\toperands[%u].type: MEM" % c)
42 if i.mem.base != 0:
43 print("\t\t\toperands[%u].mem.base: REG = %s" \
44 % (c, insn.reg_name(i.mem.base)))
45 if i.mem.disp != 0:
46 print("\t\t\toperands[%u].mem.disp: 0x%s" \
47 % (c, to_x(i.mem.disp)))
48
49
fenuks110ab1d2014-04-11 11:00:33 +020050# ## Test class Cs
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080051def test_class():
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080052 for (arch, mode, code, comment) in all_tests:
danghvu1a7c4492013-11-27 22:51:11 -060053 print("*" * 16)
fenuks110ab1d2014-04-11 11:00:33 +020054 print("Platform: %s" % comment)
danghvu1a7c4492013-11-27 22:51:11 -060055 print("Code: %s" % to_hex(code))
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080056 print("Disasm:")
danghvu1a7c4492013-11-27 22:51:11 -060057
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080058 try:
Nguyen Anh Quynh520c3612013-12-06 15:26:07 +080059 md = Cs(arch, mode)
Nguyen Anh Quynh428fdcd2014-01-07 23:39:40 +080060 md.detail = True
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080061 for insn in md.disasm(code, 0x1000):
62 print_insn_detail(insn)
fenuks110ab1d2014-04-11 11:00:33 +020063 print()
danghvu1a7c4492013-11-27 22:51:11 -060064
fenuks110ab1d2014-04-11 11:00:33 +020065 print("0x%x:\n" % (insn.address + insn.size))
Nguyen Anh Quynhf1618bc2013-12-06 20:58:04 +080066 except CsError as e:
fenuks110ab1d2014-04-11 11:00:33 +020067 print("ERROR: %s" % e)
Nguyen Anh Quynh26ee41a2013-11-27 12:11:31 +080068
69
fenuks110ab1d2014-04-11 11:00:33 +020070if __name__ == '__main__':
71 test_class()