Nguyen Anh Quynh | 81a97c6 | 2014-09-26 23:38:53 +0800 | [diff] [blame] | 1 | (* Capstone Disassembly Engine |
| 2 | * By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 *) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 3 | |
| 4 | open Arm |
| 5 | open Arm64 |
| 6 | open Mips |
Guillaume Jeanne | e002ac7 | 2014-06-30 15:46:04 +0200 | [diff] [blame] | 7 | open Ppc |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 8 | open X86 |
Guillaume Jeanne | ae48c97 | 2014-08-19 14:46:06 +0200 | [diff] [blame] | 9 | open Sparc |
| 10 | open Systemz |
| 11 | open Xcore |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 12 | open Printf (* debug *) |
| 13 | |
Nguyen Anh Quynh | 69271dd | 2014-10-31 14:32:34 +0800 | [diff] [blame] | 14 | (* Hardware architectures *) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 15 | type arch = |
| 16 | | CS_ARCH_ARM |
| 17 | | CS_ARCH_ARM64 |
| 18 | | CS_ARCH_MIPS |
| 19 | | CS_ARCH_X86 |
Guillaume Jeanne | ae48c97 | 2014-08-19 14:46:06 +0200 | [diff] [blame] | 20 | | CS_ARCH_PPC |
| 21 | | CS_ARCH_SPARC |
| 22 | | CS_ARCH_SYSZ |
| 23 | | CS_ARCH_XCORE |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 24 | |
Nguyen Anh Quynh | 69271dd | 2014-10-31 14:32:34 +0800 | [diff] [blame] | 25 | (* Hardware modes *) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 26 | type mode = |
| 27 | | CS_MODE_LITTLE_ENDIAN (* little-endian mode (default mode) *) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 28 | | CS_MODE_ARM (* ARM mode *) |
Nguyen Anh Quynh | ff9a574 | 2014-11-13 12:09:49 +0800 | [diff] [blame^] | 29 | | CS_MODE_16 (* 16-bit mode (for X86) *) |
| 30 | | CS_MODE_32 (* 32-bit mode (for X86) *) |
| 31 | | CS_MODE_64 (* 64-bit mode (for X86, PPC) *) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 32 | | CS_MODE_THUMB (* ARM's Thumb mode, including Thumb-2 *) |
Nguyen Anh Quynh | 77d93e9 | 2014-09-25 23:03:36 +0800 | [diff] [blame] | 33 | | CS_MODE_MCLASS (* ARM's MClass mode *) |
Nguyen Anh Quynh | 8e53890 | 2014-11-10 22:06:23 +0800 | [diff] [blame] | 34 | | CS_MODE_V8 (* ARMv8 A32 encodings for ARM *) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 35 | | CS_MODE_MICRO (* MicroMips mode (MIPS architecture) *) |
Nguyen Anh Quynh | 77d93e9 | 2014-09-25 23:03:36 +0800 | [diff] [blame] | 36 | | CS_MODE_MIPS3 (* Mips3 mode (MIPS architecture) *) |
| 37 | | CS_MODE_MIPS32R6 (* Mips32-R6 mode (MIPS architecture) *) |
| 38 | | CS_MODE_MIPSGP64 (* MipsGP64 mode (MIPS architecture) *) |
| 39 | | CS_MODE_V9 (* SparcV9 mode (Sparc architecture) *) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 40 | | CS_MODE_BIG_ENDIAN (* big-endian mode *) |
Nguyen Anh Quynh | ff9a574 | 2014-11-13 12:09:49 +0800 | [diff] [blame^] | 41 | | CS_MODE_MIPS32 (* Mips32 mode (for Mips) *) |
| 42 | | CS_MODE_MIPS64 (* Mips64 mode (for Mips) *) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 43 | |
Guillaume Jeanne | ae48c97 | 2014-08-19 14:46:06 +0200 | [diff] [blame] | 44 | |
Nguyen Anh Quynh | 69271dd | 2014-10-31 14:32:34 +0800 | [diff] [blame] | 45 | (* Runtime option for the disassembled engine *) |
Guillaume Jeanne | ae48c97 | 2014-08-19 14:46:06 +0200 | [diff] [blame] | 46 | type opt_type = |
| 47 | | CS_OPT_SYNTAX (* Asssembly output syntax *) |
| 48 | | CS_OPT_DETAIL (* Break down instruction structure into details *) |
| 49 | | CS_OPT_MODE (* Change engine's mode at run-time *) |
| 50 | | CS_OPT_MEM (* User-defined dynamic memory related functions *) |
| 51 | | CS_OPT_SKIPDATA (* Skip data when disassembling. Then engine is in SKIPDATA mode. *) |
| 52 | | CS_OPT_SKIPDATA_SETUP (* Setup user-defined function for SKIPDATA option *) |
| 53 | |
| 54 | |
Nguyen Anh Quynh | 69271dd | 2014-10-31 14:32:34 +0800 | [diff] [blame] | 55 | (* Runtime option value (associated with option type above) *) |
Nguyen Anh Quynh | fe4822c | 2014-10-04 16:30:02 +0800 | [diff] [blame] | 56 | let _CS_OPT_OFF = 0L;; (* Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA. *) |
| 57 | let _CS_OPT_ON = 3L;; (* Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). *) |
| 58 | let _CS_OPT_SYNTAX_DEFAULT = 0L;; (* Default asm syntax (CS_OPT_SYNTAX). *) |
| 59 | let _CS_OPT_SYNTAX_INTEL = 1L;; (* X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). *) |
| 60 | let _CS_OPT_SYNTAX_ATT = 2L;; (* X86 ATT asm syntax (CS_OPT_SYNTAX). *) |
| 61 | let _CS_OPT_SYNTAX_NOREGNAME = 3L;; (* Prints register name with only number (CS_OPT_SYNTAX) *) |
Guillaume Jeanne | ae48c97 | 2014-08-19 14:46:06 +0200 | [diff] [blame] | 62 | |
Nguyen Anh Quynh | 69271dd | 2014-10-31 14:32:34 +0800 | [diff] [blame] | 63 | (* Common instruction operand types - to be consistent across all architectures. *) |
| 64 | let _CS_OP_INVALID = 0;; (* uninitialized/invalid operand. *) |
| 65 | let _CS_OP_REG = 1;; (* Register operand. *) |
| 66 | let _CS_OP_IMM = 2;; (* Immediate operand. *) |
| 67 | let _CS_OP_MEM = 3;; (* Memory operand. *) |
| 68 | let _CS_OP_FP = 4;; (* Floating-Point operand. *) |
Nguyen Anh Quynh | 82354b6 | 2014-09-28 23:56:02 +0800 | [diff] [blame] | 69 | |
Nguyen Anh Quynh | a65d7ef | 2014-10-31 15:47:17 +0800 | [diff] [blame] | 70 | (* Common instruction groups - to be consistent across all architectures. *) |
| 71 | let _CS_GRP_INVALID = 0;; (* uninitialized/invalid group. *) |
| 72 | let _CS_GRP_JUMP = 1;; (* all jump instructions (conditional+direct+indirect jumps) *) |
| 73 | let _CS_GRP_CALL = 2;; (* all call instructions *) |
| 74 | let _CS_GRP_RET = 3;; (* all return instructions *) |
| 75 | let _CS_GRP_INT = 4;; (* all interrupt instructions (int+syscall) *) |
| 76 | let _CS_GRP_IRET = 5;; (* all interrupt return instructions *) |
| 77 | |
Jay Oster | 79e253c | 2014-10-12 16:03:12 -0700 | [diff] [blame] | 78 | type cs_arch = |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 79 | | CS_INFO_ARM of cs_arm |
| 80 | | CS_INFO_ARM64 of cs_arm64 |
| 81 | | CS_INFO_MIPS of cs_mips |
| 82 | | CS_INFO_X86 of cs_x86 |
Guillaume Jeanne | ae48c97 | 2014-08-19 14:46:06 +0200 | [diff] [blame] | 83 | | CS_INFO_PPC of cs_ppc |
| 84 | | CS_INFO_SPARC of cs_sparc |
| 85 | | CS_INFO_SYSZ of cs_sysz |
| 86 | | CS_INFO_XCORE of cs_xcore |
| 87 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 88 | |
Nguyen Anh Quynh | fe4822c | 2014-10-04 16:30:02 +0800 | [diff] [blame] | 89 | type csh = { |
| 90 | h: Int64.t; |
| 91 | a: arch; |
| 92 | } |
| 93 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 94 | type cs_insn0 = { |
| 95 | id: int; |
| 96 | address: int; |
| 97 | size: int; |
Guillaume Jeanne | cece24e | 2014-06-26 15:35:06 +0200 | [diff] [blame] | 98 | bytes: int array; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 99 | mnemonic: string; |
| 100 | op_str: string; |
| 101 | regs_read: int array; |
| 102 | regs_write: int array; |
| 103 | groups: int array; |
| 104 | arch: cs_arch; |
| 105 | } |
| 106 | |
Nguyen Anh Quynh | fe4822c | 2014-10-04 16:30:02 +0800 | [diff] [blame] | 107 | external _cs_open: arch -> mode list -> Int64.t option = "ocaml_open" |
Nguyen Anh Quynh | 82354b6 | 2014-09-28 23:56:02 +0800 | [diff] [blame] | 108 | external cs_disasm_quick: arch -> mode list -> string -> Int64.t -> Int64.t -> cs_insn0 list = "ocaml_cs_disasm" |
Nguyen Anh Quynh | 77d93e9 | 2014-09-25 23:03:36 +0800 | [diff] [blame] | 109 | external _cs_disasm_internal: arch -> Int64.t -> string -> Int64.t -> Int64.t -> cs_insn0 list = "ocaml_cs_disasm_internal" |
Nguyen Anh Quynh | fe4822c | 2014-10-04 16:30:02 +0800 | [diff] [blame] | 110 | external _cs_reg_name: Int64.t -> int -> string = "ocaml_register_name" |
| 111 | external _cs_insn_name: Int64.t -> int -> string = "ocaml_instruction_name" |
| 112 | external _cs_group_name: Int64.t -> int -> string = "ocaml_group_name" |
Nguyen Anh Quynh | 77d93e9 | 2014-09-25 23:03:36 +0800 | [diff] [blame] | 113 | external cs_version: unit -> int = "ocaml_version" |
Nguyen Anh Quynh | fe4822c | 2014-10-04 16:30:02 +0800 | [diff] [blame] | 114 | external _cs_option: Int64.t -> opt_type -> Int64.t -> int = "ocaml_option" |
| 115 | external _cs_close: Int64.t -> int = "ocaml_close" |
| 116 | |
| 117 | |
| 118 | let cs_open _arch _mode: csh = ( |
| 119 | let _handle = _cs_open _arch _mode in ( |
| 120 | match _handle with |
| 121 | | None -> { h = 0L; a = _arch } |
| 122 | | Some v -> { h = v; a = _arch } |
| 123 | ); |
| 124 | );; |
| 125 | |
| 126 | let cs_close handle = ( |
| 127 | _cs_close handle.h; |
| 128 | ) |
| 129 | |
| 130 | let cs_option handle opt value = ( |
| 131 | _cs_option handle.h opt value; |
| 132 | );; |
| 133 | |
| 134 | let cs_disasm handle code address count = ( |
| 135 | _cs_disasm_internal handle.a handle.h code address count; |
| 136 | );; |
| 137 | |
| 138 | let cs_reg_name handle id = ( |
| 139 | _cs_reg_name handle.h id; |
| 140 | );; |
| 141 | |
| 142 | let cs_insn_name handle id = ( |
| 143 | _cs_insn_name handle.h id; |
| 144 | );; |
| 145 | |
| 146 | let cs_group_name handle id = ( |
| 147 | _cs_group_name handle.h id; |
| 148 | );; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 149 | |
| 150 | class cs_insn c a = |
| 151 | let csh = c in |
Nguyen Anh Quynh | 6dc1dd5 | 2014-09-27 00:40:34 +0800 | [diff] [blame] | 152 | let (id, address, size, bytes, mnemonic, op_str, regs_read, |
| 153 | regs_write, groups, arch) = |
Guillaume Jeanne | cece24e | 2014-06-26 15:35:06 +0200 | [diff] [blame] | 154 | (a.id, a.address, a.size, a.bytes, a.mnemonic, a.op_str, |
Nguyen Anh Quynh | 6dc1dd5 | 2014-09-27 00:40:34 +0800 | [diff] [blame] | 155 | a.regs_read, a.regs_write, a.groups, a.arch) in |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 156 | object |
| 157 | method id = id; |
| 158 | method address = address; |
| 159 | method size = size; |
Guillaume Jeanne | cece24e | 2014-06-26 15:35:06 +0200 | [diff] [blame] | 160 | method bytes = bytes; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 161 | method mnemonic = mnemonic; |
| 162 | method op_str = op_str; |
| 163 | method regs_read = regs_read; |
| 164 | method regs_write = regs_write; |
| 165 | method groups = groups; |
| 166 | method arch = arch; |
Nguyen Anh Quynh | fe4822c | 2014-10-04 16:30:02 +0800 | [diff] [blame] | 167 | method reg_name id = _cs_reg_name csh.h id; |
| 168 | method insn_name id = _cs_insn_name csh.h id; |
| 169 | method group_name id = _cs_group_name csh.h id; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 170 | end;; |
| 171 | |
| 172 | let cs_insn_group handle insn group_id = |
| 173 | List.exists (fun g -> g == group_id) (Array.to_list insn.groups);; |
| 174 | |
| 175 | let cs_reg_read handle insn reg_id = |
| 176 | List.exists (fun g -> g == reg_id) (Array.to_list insn.regs_read);; |
| 177 | |
| 178 | let cs_reg_write handle insn reg_id = |
| 179 | List.exists (fun g -> g == reg_id) (Array.to_list insn.regs_write);; |
| 180 | |
| 181 | |
| 182 | class cs a m = |
| 183 | let mode = m and arch = a in |
Nguyen Anh Quynh | fe4822c | 2014-10-04 16:30:02 +0800 | [diff] [blame] | 184 | let handle = cs_open arch mode in |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 185 | object |
| 186 | method disasm code offset count = |
Nguyen Anh Quynh | fe4822c | 2014-10-04 16:30:02 +0800 | [diff] [blame] | 187 | let insns = (_cs_disasm_internal arch handle.h code offset count) in |
Guillaume Jeanne | cece24e | 2014-06-26 15:35:06 +0200 | [diff] [blame] | 188 | List.map (fun x -> new cs_insn handle x) insns; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 189 | |
| 190 | end;; |