- e0eb06b mips: correct mapping instruction string to instruction ID for alias instructions BAL & BEQZ. bug reported by Pancake by Nguyen Anh Quynh · 10 years ago
- 4f0d704 arm64: vector_index = 0 is valid. this changed invalid value of vector_index to -1 by Nguyen Anh Quynh · 10 years ago
- eda8506 mips: add BC1T & BLTZAL to the list of relative branch instructions. thanks @hlide for the input. by Nguyen Anh Quynh · 10 years ago
- d1a9090 mips: relative branch address calculated current IP added to the relative offset. thanks Pancake, Jay Oster, hlide & jvoisin for helping by Nguyen Anh Quynh · 10 years ago
- 0c07cc9 zero-out instruction details, mnemonic & op_str so cs_insn doesnt have garbage in Diet mode by Nguyen Anh Quynh · 10 years ago
- 934e180 x86: more update to the core by Nguyen Anh Quynh · 10 years ago
- 4c95022 fix warnings on unused variables when compiling in Diet mode by Nguyen Anh Quynh · 10 years ago
- 5426fe0 arm64: change headerguard for AArch64AddressingModes.h by Nguyen Anh Quynh · 10 years ago
- c44aced x86: properly zero-out x86.operands[] by Nguyen Anh Quynh · 10 years ago
- 8a429c2 Merge branch 'v3' of https://github.com/aquynh/capstone into v3 by Nguyen Anh Quynh · 10 years ago
- 9be1f93 fixed warnings in MSVC x64 compilation by Mr. eXoDia · 10 years ago
- 0693809 fixed compile errors on visual studio (variable declarations in C have to be in the top of the function) by Mr. eXoDia · 10 years ago
- 5df81b4 fix a c99 warning by Nguyen Anh Quynh · 10 years ago
- f41dc32 Merge branch 'v3' of https://github.com/aquynh/capstone into v3 by Nguyen Anh Quynh · 10 years ago
- 4b6b15f fix more MSVC warnings by Nguyen Anh Quynh · 10 years ago
- 07c92ec fix warnings reported by MSVC by Nguyen Anh Quynh · 10 years ago
- ed1234a xcore: update core by Nguyen Anh Quynh · 10 years ago
- a7792ae systemz: update core. also update Python & Java bindings by Nguyen Anh Quynh · 10 years ago
- 14b684e last commit missed a check by Nguyen Anh Quynh · 10 years ago
- b1e87e3 arm, mips, ppc, spac, x86: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands by Nguyen Anh Quynh · 10 years ago
- 8027ada arm64: refine output of some instructions to make them match available test suites by Nguyen Anh Quynh · 10 years ago
- 62af137 arm64: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands by Nguyen Anh Quynh · 10 years ago
- c286b34 Merge branch 'arm64' into v3 by Nguyen Anh Quynh · 10 years ago
- 0efef5d solve some conflicts when merging -next into -v3 by Nguyen Anh Quynh · 10 years ago
- 46a74e5 arm64: update core. this added a lot more details to cs_arm64_op struct by Nguyen Anh Quynh · 10 years ago
- ffb6b23 x86: add SMAP group for CLAC/STAC instructions by Nguyen Anh Quynh · 10 years ago
- 6638294 x86: return proper error if cs_option() enables AT&T syntax but AT&T support is opt-out at compile time by Nguyen Anh Quynh · 10 years ago
- a65e77b Merge branch 'no_att' of https://github.com/obs1dium/capstone into next by Nguyen Anh Quynh · 10 years ago
- 1ce5dea ppc: fix an unused variable warning by Nguyen Anh Quynh · 10 years ago
- 2725a3f X86GenInstrInfo size reduction by obs · 10 years ago
- b7e2ff4 x86.operands array wasn't fully cleared by obs · 10 years ago
- 86e8450 renamed CAPSTONE_NO_ATT to CAPSTONE_X86_ATT_DISABLE, added options to makefile, cmake, compile.txt by baguette · 10 years ago
- 4f412c4 Selectively disable AT&T syntax in non-diet mode to reduce library size by baguette · 10 years ago
- a726402 sparc: update core. this added/removed some instructions & groups. updated Python & Java bindings accordingly by Nguyen Anh Quynh · 10 years ago
- 2124b8a mips: indentations by Nguyen Anh Quynh · 10 years ago
- 159ddbd ppc: add new groups to group_name_maps[] by Nguyen Anh Quynh · 10 years ago
- 64f36d9 change '2013>' to 2013-2014 by Nguyen Anh Quynh · 10 years ago
- 91a6477 ppc: fix a mistake on interpreting CR registers by deleting CR8 -> CR31 by Nguyen Anh Quynh · 10 years ago
- dd3deec ppc: update core. this added new instructions, groups & registers. updated Python & Java bindings accordingly by Nguyen Anh Quynh · 10 years ago
- 0f0eb98 mips: update core. this added bunch of new instructions & groups. updated Python & Java bindings accordingly by Nguyen Anh Quynh · 10 years ago
- 7c089fd arm: add new mode CS_MODE_MCLASS for Cortex-M series. updated Python & Java bindings accordingly by Nguyen Anh Quynh · 10 years ago
- b52f11f arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly by Nguyen Anh Quynh · 10 years ago
- 0b69038 x86: update core with upstream. this added bunch of new instructions & groups. also updated Python & Java bindings after the core change by Nguyen Anh Quynh · 10 years ago
- 4db4d9b xcore: fix an warning of unused array when DIET mode is enable by Nguyen Anh Quynh · 10 years ago
- 590f23a arm: do not need to initialize local variable opcode in DecodeRegListOperand() by Nguyen Anh Quynh · 10 years ago
- 0c235e1 arm: some simple improvements & cleanups by Nguyen Anh Quynh · 10 years ago
- 26dfbc6 fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it by Nguyen Anh Quynh · 10 years ago
- 5d80678 Merge branch 'next' of https://github.com/flyingsymbols/capstone into arm by Nguyen Anh Quynh · 10 years ago
- 48eb7a6 x86: INTO is invalid in 64bit mode. bug reported by Pancake & Ange Albertini by Nguyen Anh Quynh · 10 years ago
- 298d413 * added a test file to suite for testing invalid and valid instruction sequences by flyingsymbols · 10 years ago
- 55cd996 sparc: initialize detail->sparc in Sparc_getInstruction. bug reported by Ben Nagy by Nguyen Anh Quynh · 10 years ago
- e1fc8a8 sparc: initialize detail->sparc in Sparc_getInstruction. bug reported by Ben Nagy by Nguyen Anh Quynh · 10 years ago
- 4d2eba7 systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy by Nguyen Anh Quynh · 10 years ago
- 39d6b2f systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy by Nguyen Anh Quynh · 10 years ago
- 650f96c add new API cs_group_name() to return group name in string, given the group id by Nguyen Anh Quynh · 10 years ago
- bb8bbaa x86: test reg, [mem] -> test [mem], reg. bug reported by Gabriel Quadros by Nguyen Anh Quynh · 10 years ago
- dbdb61a x86: regs_write[] of RDTSC & RDTSCP depend on @mode by Nguyen Anh Quynh · 10 years ago
- 9f6ed71 x86: add @rex to cs_x86 struct. updated python & java binding for this change by Nguyen Anh Quynh · 10 years ago
- 32e2c6c x86: address-size prefix should override RIP relative address in x64 mode. bug reported by @hlide by Nguyen Anh Quynh · 10 years ago
- ed6b8c5 x86: address-size prefix should override RIP relative address in x64 mode. bug reported by @hlide by Nguyen Anh Quynh · 10 years ago
- 656ebc9 x86: handle RIP relative addressing in 64bit mode properly. bug reported by @hlide by Nguyen Anh Quynh · 10 years ago
- af6db2a x86: handle RIP relative addressing in 64bit mode properly. bug reported by @hlide by Nguyen Anh Quynh · 10 years ago
- 7ef3700 x86: SHL reg, 1 has one too many operands. bug reported by Sean Heelan by Nguyen Anh Quynh · 10 years ago
- 1a66fec x86: support avx_sae & avx_rm in cs_x86 struct. this also updates Python & Java bindings following the core's change by Nguyen Anh Quynh · 10 years ago
- 12e6e31 x86: rename zero_opmask of cs_x86_op to avx_zero_opmask by Nguyen Anh Quynh · 10 years ago
- 92a3d4c x86: add AVX's zero_opmask to cs_x86_op struct. updated Python & Java bindings for this change by Nguyen Anh Quynh · 10 years ago
- f1ec526 x86: provide size for X86_OP_IMM operand. thank Gabriel Quadros for some suggestions by Nguyen Anh Quynh · 10 years ago
- e1aba17 x86: fix all {cc} instructions to have correct instruction ID by Nguyen Anh Quynh · 10 years ago
- 4c5eabc x86: support SSE_CC & AVX_CC in cs_x86 struct. this also updates Python & Java bindings by Nguyen Anh Quynh · 10 years ago
- 0d71645 x86: add avx_bcast to cs_x86_op to support AVX512 instructions. this also updates Python & Java binding by Nguyen Anh Quynh · 10 years ago
- bb6440c x86: extend cs_x86.opcode to 4 bytes to contain EVEX opcode. this also updates Python binding following this interface change by Nguyen Anh Quynh · 10 years ago
- 15b746f x86: op_addReg() & op_addImm() only work when detail mode is ON by Nguyen Anh Quynh · 10 years ago
- c74ec28 x86: LEA for 16bit register should have pointer size of word, not dword. bug reported by Gabriel Quadros by Nguyen Anh Quynh · 10 years ago
- 14ba46b x86: add segment to x86_op_mem struct. this fixes a bug in generating detail for instructions with segment override. bug reported by Sean Heelan. by Nguyen Anh Quynh · 10 years ago
- eb2f3fb x86: properly reset prefixPresent for prefix0/1 group by Nguyen Anh Quynh · 10 years ago
- 1e688d4 x86: do not use markup in AT&T syntax by Nguyen Anh Quynh · 10 years ago
- 46291c1 Merge branch 'next' into opsize by Nguyen Anh Quynh · 10 years ago
- 44db3c3 x86: support CS_OPT_MODE for dynamically changing mode at run-time by Nguyen Anh Quynh · 10 years ago
- cff0362 arm64: assign NULL to char pointer, not zero. bug reported by Coverity by Nguyen Anh Quynh · 10 years ago
- 1085073 x86: remove disp_size, imm_size, op_size. add size to each operand. thanks Gabriel Quadros for some nice ideas by Nguyen Anh Quynh · 10 years ago
- 73eb5d5 arm: op_addImm() is called only when detail mode is ON by Nguyen Anh Quynh · 10 years ago
- cae09bf replace offset_of with offsetof from stddef.h by Nguyen Anh Quynh · 10 years ago
- ebe2443 arm: some special instructions need to have numerical operand added manually in printInstruction() by Nguyen Anh Quynh · 10 years ago
- eccb9da arm64: zeroout a whole cs_arm64 struct of MCI in *getInstruction(). by Nguyen Anh Quynh · 10 years ago
- 73bbbb3 arm: add ASRS, LSRS, VCLE, VCLT instructions. update Python & Java bindings at the same time by Nguyen Anh Quynh · 10 years ago
- 8693fcd arm: correct operand setup for REG type in printAddrMode3OffsetOperand() by Nguyen Anh Quynh · 10 years ago
- 2a461ed arm: zeroout a whole cs_arm struct in *getInstruction(). this makes sure operand of REG type has shift type = 0 by default by Nguyen Anh Quynh · 10 years ago
- 9cf8811 x86: InternalInstruction@xAcquireRelease should be initialized to 0 (FALSE) by Nguyen Anh Quynh · 10 years ago
- 495295e MCInst_Init() is arch-independent by Nguyen Anh Quynh · 10 years ago
- 215e76b ppc: use MCInst_insert0() instead of MCInst_insert() to avoid malloc/free by Nguyen Anh Quynh · 10 years ago
- d06f3d6 xcore: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free by Nguyen Anh Quynh · 10 years ago
- 88fca42 xcore: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible by Nguyen Anh Quynh · 10 years ago
- 7062988 systemz: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free by Nguyen Anh Quynh · 10 years ago
- bddd215 systemz: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible by Nguyen Anh Quynh · 10 years ago
- 3d3b6ce sparc: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free by Nguyen Anh Quynh · 10 years ago
- 9b91de0 sparc: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible by Nguyen Anh Quynh · 10 years ago
- 7f945d3 ppc: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free by Nguyen Anh Quynh · 10 years ago
- 7f15f67 ppc: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible by Nguyen Anh Quynh · 10 years ago
- f08b83d mips: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free by Nguyen Anh Quynh · 10 years ago
- 0c764d4 mips: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible by Nguyen Anh Quynh · 10 years ago