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Guillaume Chatelet439d3712018-02-01 10:03:09 +01001// Copyright 2017 Google Inc.
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
Guillaume Chatelet8e58ef02018-02-01 10:38:48 +010015#ifndef CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
16#define CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
Guillaume Chatelet439d3712018-02-01 10:03:09 +010017
18#include "cpu_features_macros.h"
19
Guillaume Chatelete4195732018-02-12 16:15:15 +010020CPU_FEATURES_START_CPP_NAMESPACE
Guillaume Chatelet439d3712018-02-01 10:03:09 +010021
22// See https://en.wikipedia.org/wiki/CPUID for a list of x86 cpu features.
Guillaume Chateletd395dfa2019-01-22 13:19:42 +010023// The field names are based on the short name provided in the wikipedia tables.
Guillaume Chatelet439d3712018-02-01 10:03:09 +010024typedef struct {
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020025 int fpu : 1;
26 int tsc : 1;
27 int cx8 : 1;
28 int clfsh : 1;
29 int mmx : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010030 int aes : 1;
31 int erms : 1;
32 int f16c : 1;
33 int fma3 : 1;
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020034 int vaes : 1;
Guillaume Chatelet11e3e202018-02-09 08:55:11 +010035 int vpclmulqdq : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010036 int bmi1 : 1;
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020037 int hle : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010038 int bmi2 : 1;
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020039 int rtm : 1;
40 int rdseed : 1;
41 int clflushopt : 1;
42 int clwb : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010043
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020044 int sse : 1;
45 int sse2 : 1;
46 int sse3 : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010047 int ssse3 : 1;
48 int sse4_1 : 1;
49 int sse4_2 : 1;
50
51 int avx : 1;
52 int avx2 : 1;
53
54 int avx512f : 1;
55 int avx512cd : 1;
56 int avx512er : 1;
57 int avx512pf : 1;
58 int avx512bw : 1;
59 int avx512dq : 1;
60 int avx512vl : 1;
61 int avx512ifma : 1;
62 int avx512vbmi : 1;
63 int avx512vbmi2 : 1;
64 int avx512vnni : 1;
65 int avx512bitalg : 1;
66 int avx512vpopcntdq : 1;
67 int avx512_4vnniw : 1;
68 int avx512_4vbmi2 : 1;
69
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020070 int pclmulqdq : 1;
Patrik Fiedler3ee0d622018-02-13 11:14:32 +010071 int smx : 1;
72 int sgx : 1;
Guillaume Chatelet9b872ce2018-03-13 10:58:42 +010073 int cx16 : 1; // aka. CMPXCHG16B
Guillaume Chateletd395dfa2019-01-22 13:19:42 +010074 int sha : 1;
75 int popcnt : 1;
76 int movbe : 1;
77 int rdrnd : 1;
Patrik Fiedler3ee0d622018-02-13 11:14:32 +010078
Artem Alekseev3ee4a9e2019-06-19 16:06:05 +030079 int dca : 1;
80 int ss : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010081 // Make sure to update X86FeaturesEnum below if you add a field here.
82} X86Features;
83
84typedef struct {
85 X86Features features;
86 int family;
87 int model;
88 int stepping;
89 char vendor[13]; // 0 terminated string
90} X86Info;
91
92// Calls cpuid and returns an initialized X86info.
93// This function is guaranteed to be malloc, memset and memcpy free.
94X86Info GetX86Info(void);
95
96typedef enum {
97 X86_UNKNOWN,
98 INTEL_CORE, // CORE
99 INTEL_PNR, // PENRYN
100 INTEL_NHM, // NEHALEM
101 INTEL_ATOM_BNL, // BONNELL
102 INTEL_WSM, // WESTMERE
103 INTEL_SNB, // SANDYBRIDGE
104 INTEL_IVB, // IVYBRIDGE
105 INTEL_ATOM_SMT, // SILVERMONT
106 INTEL_HSW, // HASWELL
107 INTEL_BDW, // BROADWELL
108 INTEL_SKL, // SKYLAKE
109 INTEL_ATOM_GMT, // GOLDMONT
110 INTEL_KBL, // KABY LAKE
111 INTEL_CFL, // COFFEE LAKE
Brandon Surmanskiefcc49a2018-02-07 11:07:00 -0800112 INTEL_CNL, // CANNON LAKE
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100113 AMD_HAMMER, // K8
114 AMD_K10, // K10
115 AMD_BOBCAT, // K14
116 AMD_BULLDOZER, // K15
117 AMD_JAGUAR, // K16
118 AMD_ZEN, // K17
119} X86Microarchitecture;
120
121// Returns the underlying microarchitecture by looking at X86Info's vendor,
122// family and model.
123X86Microarchitecture GetX86Microarchitecture(const X86Info* info);
124
125// Calls cpuid and fills the brand_string.
126// - brand_string *must* be of size 49 (beware of array decaying).
127// - brand_string will be zero terminated.
128// - This function calls memcpy.
129void FillX86BrandString(char brand_string[49]);
130
131////////////////////////////////////////////////////////////////////////////////
132// Introspection functions
133
134typedef enum {
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200135 X86_FPU,
136 X86_TSC,
137 X86_CX8,
138 X86_CLFSH,
139 X86_MMX,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100140 X86_AES,
141 X86_ERMS,
142 X86_F16C,
143 X86_FMA3,
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200144 X86_VAES,
Guillaume Chatelet11e3e202018-02-09 08:55:11 +0100145 X86_VPCLMULQDQ,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100146 X86_BMI1,
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200147 X86_HLE,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100148 X86_BMI2,
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200149 X86_RTM,
150 X86_RDSEED,
151 X86_CLFLUSHOPT,
152 X86_CLWB,
153 X86_SSE,
154 X86_SSE2,
155 X86_SSE3,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100156 X86_SSSE3,
157 X86_SSE4_1,
158 X86_SSE4_2,
159 X86_AVX,
160 X86_AVX2,
161 X86_AVX512F,
162 X86_AVX512CD,
163 X86_AVX512ER,
164 X86_AVX512PF,
165 X86_AVX512BW,
166 X86_AVX512DQ,
167 X86_AVX512VL,
168 X86_AVX512IFMA,
169 X86_AVX512VBMI,
170 X86_AVX512VBMI2,
171 X86_AVX512VNNI,
172 X86_AVX512BITALG,
173 X86_AVX512VPOPCNTDQ,
174 X86_AVX512_4VNNIW,
175 X86_AVX512_4VBMI2,
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200176 X86_PCLMULQDQ,
Patrik Fiedler3ee0d622018-02-13 11:14:32 +0100177 X86_SMX,
178 X86_SGX,
Guillaume Chatelet9b872ce2018-03-13 10:58:42 +0100179 X86_CX16,
Guillaume Chateletd395dfa2019-01-22 13:19:42 +0100180 X86_SHA,
181 X86_POPCNT,
182 X86_MOVBE,
183 X86_RDRND,
Artem Alekseev3ee4a9e2019-06-19 16:06:05 +0300184 X86_DCA,
185 X86_SS,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100186 X86_LAST_,
187} X86FeaturesEnum;
188
189int GetX86FeaturesEnumValue(const X86Features* features, X86FeaturesEnum value);
190
191const char* GetX86FeaturesEnumName(X86FeaturesEnum);
192
193const char* GetX86MicroarchitectureName(X86Microarchitecture);
194
Guillaume Chatelete4195732018-02-12 16:15:15 +0100195CPU_FEATURES_END_CPP_NAMESPACE
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100196
Guillaume Chatelet4155ee72019-01-18 13:38:22 +0100197#if !defined(CPU_FEATURES_ARCH_X86)
198#error "Including cpuinfo_x86.h from a non-x86 target."
199#endif
200
Guillaume Chatelet8e58ef02018-02-01 10:38:48 +0100201#endif // CPU_FEATURES_INCLUDE_CPUINFO_X86_H_