Guillaume Chatelet | dfdac6a | 2019-01-17 18:00:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010 The Android Open Source Project |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in |
| 12 | * the documentation and/or other materials provided with the |
| 13 | * distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 18 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 19 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 21 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 22 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 23 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 24 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 25 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 26 | * SUCH DAMAGE. |
| 27 | */ |
| 28 | #ifndef GOOGLE_CPU_FEATURES_H |
| 29 | #define GOOGLE_CPU_FEATURES_H |
| 30 | #include <stdint.h> |
| 31 | #include <sys/cdefs.h> |
| 32 | |
| 33 | __BEGIN_DECLS |
| 34 | |
| 35 | /* A list of valid values returned by android_getCpuFamily(). |
| 36 | * They describe the CPU Architecture of the current process. |
| 37 | */ |
| 38 | typedef enum { |
| 39 | ANDROID_CPU_FAMILY_UNKNOWN = 0, |
| 40 | ANDROID_CPU_FAMILY_ARM, |
| 41 | ANDROID_CPU_FAMILY_X86, |
| 42 | ANDROID_CPU_FAMILY_MIPS, |
| 43 | ANDROID_CPU_FAMILY_ARM64, |
| 44 | ANDROID_CPU_FAMILY_X86_64, |
| 45 | ANDROID_CPU_FAMILY_MIPS64, |
| 46 | ANDROID_CPU_FAMILY_MAX /* do not remove */ |
| 47 | } AndroidCpuFamily; |
| 48 | |
| 49 | /* Return the CPU family of the current process. |
| 50 | * |
| 51 | * Note that this matches the bitness of the current process. I.e. when |
| 52 | * running a 32-bit binary on a 64-bit capable CPU, this will return the |
| 53 | * 32-bit CPU family value. |
| 54 | */ |
| 55 | extern AndroidCpuFamily android_getCpuFamily(void); |
| 56 | |
| 57 | /* Return a bitmap describing a set of optional CPU features that are |
| 58 | * supported by the current device's CPU. The exact bit-flags returned |
| 59 | * depend on the value returned by android_getCpuFamily(). See the |
| 60 | * documentation for the ANDROID_CPU_*_FEATURE_* flags below for details. |
| 61 | */ |
| 62 | extern uint64_t android_getCpuFeatures(void); |
| 63 | |
| 64 | /* The list of feature flags for ANDROID_CPU_FAMILY_ARM that can be |
| 65 | * recognized by the library (see note below for 64-bit ARM). Value details |
| 66 | * are: |
| 67 | * |
| 68 | * VFPv2: |
| 69 | * CPU supports the VFPv2 instruction set. Many, but not all, ARMv6 CPUs |
| 70 | * support these instructions. VFPv2 is a subset of VFPv3 so this will |
| 71 | * be set whenever VFPv3 is set too. |
| 72 | * |
| 73 | * ARMv7: |
| 74 | * CPU supports the ARMv7-A basic instruction set. |
| 75 | * This feature is mandated by the 'armeabi-v7a' ABI. |
| 76 | * |
| 77 | * VFPv3: |
| 78 | * CPU supports the VFPv3-D16 instruction set, providing hardware FPU |
| 79 | * support for single and double precision floating point registers. |
| 80 | * Note that only 16 FPU registers are available by default, unless |
| 81 | * the D32 bit is set too. This feature is also mandated by the |
| 82 | * 'armeabi-v7a' ABI. |
| 83 | * |
| 84 | * VFP_D32: |
| 85 | * CPU VFP optional extension that provides 32 FPU registers, |
| 86 | * instead of 16. Note that ARM mandates this feature is the 'NEON' |
| 87 | * feature is implemented by the CPU. |
| 88 | * |
| 89 | * NEON: |
| 90 | * CPU FPU supports "ARM Advanced SIMD" instructions, also known as |
| 91 | * NEON. Note that this mandates the VFP_D32 feature as well, per the |
| 92 | * ARM Architecture specification. |
| 93 | * |
| 94 | * VFP_FP16: |
| 95 | * Half-width floating precision VFP extension. If set, the CPU |
| 96 | * supports instructions to perform floating-point operations on |
| 97 | * 16-bit registers. This is part of the VFPv4 specification, but |
| 98 | * not mandated by any Android ABI. |
| 99 | * |
| 100 | * VFP_FMA: |
| 101 | * Fused multiply-accumulate VFP instructions extension. Also part of |
| 102 | * the VFPv4 specification, but not mandated by any Android ABI. |
| 103 | * |
| 104 | * NEON_FMA: |
| 105 | * Fused multiply-accumulate NEON instructions extension. Optional |
| 106 | * extension from the VFPv4 specification, but not mandated by any |
| 107 | * Android ABI. |
| 108 | * |
| 109 | * IDIV_ARM: |
| 110 | * Integer division available in ARM mode. Only available |
| 111 | * on recent CPUs (e.g. Cortex-A15). |
| 112 | * |
| 113 | * IDIV_THUMB2: |
| 114 | * Integer division available in Thumb-2 mode. Only available |
| 115 | * on recent CPUs (e.g. Cortex-A15). |
| 116 | * |
| 117 | * iWMMXt: |
| 118 | * Optional extension that adds MMX registers and operations to an |
| 119 | * ARM CPU. This is only available on a few XScale-based CPU designs |
| 120 | * sold by Marvell. Pretty rare in practice. |
| 121 | * |
| 122 | * AES: |
| 123 | * CPU supports AES instructions. These instructions are only |
| 124 | * available for 32-bit applications running on ARMv8 CPU. |
| 125 | * |
| 126 | * CRC32: |
| 127 | * CPU supports CRC32 instructions. These instructions are only |
| 128 | * available for 32-bit applications running on ARMv8 CPU. |
| 129 | * |
| 130 | * SHA2: |
| 131 | * CPU supports SHA2 instructions. These instructions are only |
| 132 | * available for 32-bit applications running on ARMv8 CPU. |
| 133 | * |
| 134 | * SHA1: |
| 135 | * CPU supports SHA1 instructions. These instructions are only |
| 136 | * available for 32-bit applications running on ARMv8 CPU. |
| 137 | * |
| 138 | * PMULL: |
| 139 | * CPU supports 64-bit PMULL and PMULL2 instructions. These |
| 140 | * instructions are only available for 32-bit applications |
| 141 | * running on ARMv8 CPU. |
| 142 | * |
| 143 | * If you want to tell the compiler to generate code that targets one of |
| 144 | * the feature set above, you should probably use one of the following |
| 145 | * flags (for more details, see technical note at the end of this file): |
| 146 | * |
| 147 | * -mfpu=vfp |
| 148 | * -mfpu=vfpv2 |
| 149 | * These are equivalent and tell GCC to use VFPv2 instructions for |
| 150 | * floating-point operations. Use this if you want your code to |
| 151 | * run on *some* ARMv6 devices, and any ARMv7-A device supported |
| 152 | * by Android. |
| 153 | * |
| 154 | * Generated code requires VFPv2 feature. |
| 155 | * |
| 156 | * -mfpu=vfpv3-d16 |
| 157 | * Tell GCC to use VFPv3 instructions (using only 16 FPU registers). |
| 158 | * This should be generic code that runs on any CPU that supports the |
| 159 | * 'armeabi-v7a' Android ABI. Note that no ARMv6 CPU supports this. |
| 160 | * |
| 161 | * Generated code requires VFPv3 feature. |
| 162 | * |
| 163 | * -mfpu=vfpv3 |
| 164 | * Tell GCC to use VFPv3 instructions with 32 FPU registers. |
| 165 | * Generated code requires VFPv3|VFP_D32 features. |
| 166 | * |
| 167 | * -mfpu=neon |
| 168 | * Tell GCC to use VFPv3 instructions with 32 FPU registers, and |
| 169 | * also support NEON intrinsics (see <arm_neon.h>). |
| 170 | * Generated code requires VFPv3|VFP_D32|NEON features. |
| 171 | * |
| 172 | * -mfpu=vfpv4-d16 |
| 173 | * Generated code requires VFPv3|VFP_FP16|VFP_FMA features. |
| 174 | * |
| 175 | * -mfpu=vfpv4 |
| 176 | * Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32 features. |
| 177 | * |
| 178 | * -mfpu=neon-vfpv4 |
| 179 | * Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32|NEON|NEON_FMA |
| 180 | * features. |
| 181 | * |
| 182 | * -mcpu=cortex-a7 |
| 183 | * -mcpu=cortex-a15 |
| 184 | * Generated code requires VFPv3|VFP_FP16|VFP_FMA|VFP_D32| |
| 185 | * NEON|NEON_FMA|IDIV_ARM|IDIV_THUMB2 |
| 186 | * This flag implies -mfpu=neon-vfpv4. |
| 187 | * |
| 188 | * -mcpu=iwmmxt |
| 189 | * Allows the use of iWMMXt instrinsics with GCC. |
| 190 | * |
| 191 | * IMPORTANT NOTE: These flags should only be tested when |
| 192 | * android_getCpuFamily() returns ANDROID_CPU_FAMILY_ARM, i.e. this is a |
| 193 | * 32-bit process. |
| 194 | * |
| 195 | * When running a 64-bit ARM process on an ARMv8 CPU, |
| 196 | * android_getCpuFeatures() will return a different set of bitflags |
| 197 | */ |
| 198 | enum { |
| 199 | ANDROID_CPU_ARM_FEATURE_ARMv7 = (1 << 0), |
| 200 | ANDROID_CPU_ARM_FEATURE_VFPv3 = (1 << 1), |
| 201 | ANDROID_CPU_ARM_FEATURE_NEON = (1 << 2), |
| 202 | ANDROID_CPU_ARM_FEATURE_LDREX_STREX = (1 << 3), |
| 203 | ANDROID_CPU_ARM_FEATURE_VFPv2 = (1 << 4), |
| 204 | ANDROID_CPU_ARM_FEATURE_VFP_D32 = (1 << 5), |
| 205 | ANDROID_CPU_ARM_FEATURE_VFP_FP16 = (1 << 6), |
| 206 | ANDROID_CPU_ARM_FEATURE_VFP_FMA = (1 << 7), |
| 207 | ANDROID_CPU_ARM_FEATURE_NEON_FMA = (1 << 8), |
| 208 | ANDROID_CPU_ARM_FEATURE_IDIV_ARM = (1 << 9), |
| 209 | ANDROID_CPU_ARM_FEATURE_IDIV_THUMB2 = (1 << 10), |
| 210 | ANDROID_CPU_ARM_FEATURE_iWMMXt = (1 << 11), |
| 211 | ANDROID_CPU_ARM_FEATURE_AES = (1 << 12), |
| 212 | ANDROID_CPU_ARM_FEATURE_PMULL = (1 << 13), |
| 213 | ANDROID_CPU_ARM_FEATURE_SHA1 = (1 << 14), |
| 214 | ANDROID_CPU_ARM_FEATURE_SHA2 = (1 << 15), |
| 215 | ANDROID_CPU_ARM_FEATURE_CRC32 = (1 << 16), |
| 216 | }; |
| 217 | |
| 218 | /* The bit flags corresponding to the output of android_getCpuFeatures() |
| 219 | * when android_getCpuFamily() returns ANDROID_CPU_FAMILY_ARM64. Value details |
| 220 | * are: |
| 221 | * |
| 222 | * FP: |
| 223 | * CPU has Floating-point unit. |
| 224 | * |
| 225 | * ASIMD: |
| 226 | * CPU has Advanced SIMD unit. |
| 227 | * |
| 228 | * AES: |
| 229 | * CPU supports AES instructions. |
| 230 | * |
| 231 | * CRC32: |
| 232 | * CPU supports CRC32 instructions. |
| 233 | * |
| 234 | * SHA2: |
| 235 | * CPU supports SHA2 instructions. |
| 236 | * |
| 237 | * SHA1: |
| 238 | * CPU supports SHA1 instructions. |
| 239 | * |
| 240 | * PMULL: |
| 241 | * CPU supports 64-bit PMULL and PMULL2 instructions. |
| 242 | */ |
| 243 | enum { |
| 244 | ANDROID_CPU_ARM64_FEATURE_FP = (1 << 0), |
| 245 | ANDROID_CPU_ARM64_FEATURE_ASIMD = (1 << 1), |
| 246 | ANDROID_CPU_ARM64_FEATURE_AES = (1 << 2), |
| 247 | ANDROID_CPU_ARM64_FEATURE_PMULL = (1 << 3), |
| 248 | ANDROID_CPU_ARM64_FEATURE_SHA1 = (1 << 4), |
| 249 | ANDROID_CPU_ARM64_FEATURE_SHA2 = (1 << 5), |
| 250 | ANDROID_CPU_ARM64_FEATURE_CRC32 = (1 << 6), |
| 251 | }; |
| 252 | |
| 253 | /* The bit flags corresponding to the output of android_getCpuFeatures() |
| 254 | * when android_getCpuFamily() returns ANDROID_CPU_FAMILY_X86 or |
| 255 | * ANDROID_CPU_FAMILY_X86_64. |
| 256 | */ |
| 257 | enum { |
| 258 | ANDROID_CPU_X86_FEATURE_SSSE3 = (1 << 0), |
| 259 | ANDROID_CPU_X86_FEATURE_POPCNT = (1 << 1), |
| 260 | ANDROID_CPU_X86_FEATURE_MOVBE = (1 << 2), |
| 261 | ANDROID_CPU_X86_FEATURE_SSE4_1 = (1 << 3), |
| 262 | ANDROID_CPU_X86_FEATURE_SSE4_2 = (1 << 4), |
| 263 | ANDROID_CPU_X86_FEATURE_AES_NI = (1 << 5), |
| 264 | ANDROID_CPU_X86_FEATURE_AVX = (1 << 6), |
| 265 | ANDROID_CPU_X86_FEATURE_RDRAND = (1 << 7), |
| 266 | ANDROID_CPU_X86_FEATURE_AVX2 = (1 << 8), |
| 267 | ANDROID_CPU_X86_FEATURE_SHA_NI = (1 << 9), |
| 268 | }; |
| 269 | |
| 270 | /* The bit flags corresponding to the output of android_getCpuFeatures() |
| 271 | * when android_getCpuFamily() returns ANDROID_CPU_FAMILY_MIPS |
| 272 | * or ANDROID_CPU_FAMILY_MIPS64. Values are: |
| 273 | * |
| 274 | * R6: |
| 275 | * CPU executes MIPS Release 6 instructions natively, and |
| 276 | * supports obsoleted R1..R5 instructions only via kernel traps. |
| 277 | * |
| 278 | * MSA: |
| 279 | * CPU supports Mips SIMD Architecture instructions. |
| 280 | */ |
| 281 | enum { |
| 282 | ANDROID_CPU_MIPS_FEATURE_R6 = (1 << 0), |
| 283 | ANDROID_CPU_MIPS_FEATURE_MSA = (1 << 1), |
| 284 | }; |
| 285 | |
Guillaume Chatelet | 20fa92a | 2019-01-23 12:59:46 +0100 | [diff] [blame] | 286 | /* Return the number of CPU cores detected on this device. |
| 287 | * Please note the current implementation supports up to 32 cpus. |
| 288 | */ |
Guillaume Chatelet | dfdac6a | 2019-01-17 18:00:21 +0100 | [diff] [blame] | 289 | extern int android_getCpuCount(void); |
| 290 | |
| 291 | /* The following is used to force the CPU count and features |
| 292 | * mask in sandboxed processes. Under 4.1 and higher, these processes |
| 293 | * cannot access /proc, which is the only way to get information from |
| 294 | * the kernel about the current hardware (at least on ARM). |
| 295 | * |
| 296 | * It _must_ be called only once, and before any android_getCpuXXX |
| 297 | * function, any other case will fail. |
| 298 | * |
| 299 | * This function return 1 on success, and 0 on failure. |
| 300 | */ |
| 301 | extern int android_setCpu(int cpu_count, uint64_t cpu_features); |
| 302 | |
| 303 | #ifdef __arm__ |
| 304 | |
| 305 | /* Retrieve the ARM 32-bit CPUID value from the kernel. |
| 306 | * Note that this cannot work on sandboxed processes under 4.1 and |
| 307 | * higher, unless you called android_setCpuArm() before. |
| 308 | */ |
| 309 | extern uint32_t android_getCpuIdArm(void); |
| 310 | |
| 311 | /* An ARM-specific variant of android_setCpu() that also allows you |
| 312 | * to set the ARM CPUID field. |
| 313 | */ |
| 314 | extern int android_setCpuArm(int cpu_count, uint64_t cpu_features, |
| 315 | uint32_t cpu_id); |
| 316 | |
| 317 | #endif |
| 318 | |
| 319 | __END_DECLS |
| 320 | #endif /* GOOGLE_CPU_FEATURES_H */ |