Rashmica Gupta | 3adafbf | 2018-04-23 10:46:47 +1000 | [diff] [blame] | 1 | // Copyright 2018 IBM |
| 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | // you may not use this file except in compliance with the License. |
| 5 | // You may obtain a copy of the License at |
| 6 | // |
| 7 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | // See the License for the specific language governing permissions and |
| 13 | // limitations under the License. |
| 14 | |
| 15 | #ifndef CPU_FEATURES_INCLUDE_CPUINFO_PPC_H_ |
| 16 | #define CPU_FEATURES_INCLUDE_CPUINFO_PPC_H_ |
| 17 | |
Artem Alekseev | 653d581 | 2019-07-02 17:52:25 +0300 | [diff] [blame] | 18 | #include "cpu_features_cache_info.h" |
Guillaume Chatelet | 22a5362 | 2020-09-23 11:52:20 +0200 | [diff] [blame] | 19 | #include "cpu_features_macros.h" |
Rashmica Gupta | c45e32f | 2018-05-02 14:30:25 +1000 | [diff] [blame] | 20 | #include "internal/hwcaps.h" |
Rashmica Gupta | 3adafbf | 2018-04-23 10:46:47 +1000 | [diff] [blame] | 21 | |
| 22 | CPU_FEATURES_START_CPP_NAMESPACE |
| 23 | |
| 24 | typedef struct { |
| 25 | int ppc32 : 1; |
| 26 | int ppc64 : 1; |
| 27 | int ppc601 : 1; |
| 28 | int altivec : 1; |
| 29 | int fpu : 1; |
| 30 | int mmu : 1; |
| 31 | int mac_4xx : 1; |
| 32 | int unifiedcache : 1; |
| 33 | int spe : 1; |
| 34 | int efpsingle : 1; |
| 35 | int efpdouble : 1; |
| 36 | int no_tb : 1; |
| 37 | int power4 : 1; |
| 38 | int power5 : 1; |
| 39 | int power5plus : 1; |
| 40 | int cell : 1; |
| 41 | int booke : 1; |
| 42 | int smt : 1; |
| 43 | int icachesnoop : 1; |
| 44 | int arch205 : 1; |
| 45 | int pa6t : 1; |
| 46 | int dfp : 1; |
| 47 | int power6ext : 1; |
| 48 | int arch206 : 1; |
| 49 | int vsx : 1; |
| 50 | int pseries_perfmon_compat : 1; |
| 51 | int truele : 1; |
| 52 | int ppcle : 1; |
| 53 | int arch207 : 1; |
| 54 | int htm : 1; |
| 55 | int dscr : 1; |
| 56 | int ebb : 1; |
| 57 | int isel : 1; |
| 58 | int tar : 1; |
| 59 | int vcrypto : 1; |
| 60 | int htm_nosc : 1; |
| 61 | int arch300 : 1; |
| 62 | int ieee128 : 1; |
| 63 | int darn : 1; |
| 64 | int scv : 1; |
| 65 | int htm_no_suspend : 1; |
| 66 | |
| 67 | // Make sure to update PPCFeaturesEnum below if you add a field here. |
| 68 | } PPCFeatures; |
| 69 | |
| 70 | typedef struct { |
| 71 | PPCFeatures features; |
| 72 | } PPCInfo; |
| 73 | |
| 74 | // This function is guaranteed to be malloc, memset and memcpy free. |
| 75 | PPCInfo GetPPCInfo(void); |
| 76 | |
| 77 | typedef struct { |
| 78 | char platform[64]; // 0 terminated string |
| 79 | char model[64]; // 0 terminated string |
| 80 | char machine[64]; // 0 terminated string |
| 81 | char cpu[64]; // 0 terminated string |
Rashmica Gupta | c45e32f | 2018-05-02 14:30:25 +1000 | [diff] [blame] | 82 | PlatformType type; |
Rashmica Gupta | 3adafbf | 2018-04-23 10:46:47 +1000 | [diff] [blame] | 83 | } PPCPlatformStrings; |
| 84 | |
| 85 | PPCPlatformStrings GetPPCPlatformStrings(void); |
| 86 | |
| 87 | //////////////////////////////////////////////////////////////////////////////// |
| 88 | // Introspection functions |
| 89 | |
| 90 | typedef enum { |
| 91 | PPC_32, /* 32 bit mode execution */ |
| 92 | PPC_64, /* 64 bit mode execution */ |
| 93 | PPC_601_INSTR, /* Old POWER ISA */ |
| 94 | PPC_HAS_ALTIVEC, /* SIMD Unit*/ |
| 95 | PPC_HAS_FPU, /* Floating Point Unit */ |
| 96 | PPC_HAS_MMU, /* Memory management unit */ |
| 97 | PPC_HAS_4xxMAC, |
| 98 | PPC_UNIFIED_CACHE, /* Unified instruction and data cache */ |
| 99 | PPC_HAS_SPE, /* Signal processing extention unit */ |
| 100 | PPC_HAS_EFP_SINGLE, /* SPE single precision fpu */ |
| 101 | PPC_HAS_EFP_DOUBLE, /* SPE double precision fpu */ |
| 102 | PPC_NO_TB, /* No timebase */ |
| 103 | PPC_POWER4, |
| 104 | PPC_POWER5, |
| 105 | PPC_POWER5_PLUS, |
| 106 | PPC_CELL, /* Cell broadband engine */ |
| 107 | PPC_BOOKE, /* Embedded ISA */ |
| 108 | PPC_SMT, /* Simultaneous multi-threading */ |
| 109 | PPC_ICACHE_SNOOP, |
| 110 | PPC_ARCH_2_05, /* ISA 2.05 - POWER6 */ |
| 111 | PPC_PA6T, /* PA Semi 6T core ISA */ |
| 112 | PPC_HAS_DFP, /* Decimal floating point unit */ |
| 113 | PPC_POWER6_EXT, |
| 114 | PPC_ARCH_2_06, /* ISA 2.06 - POWER7 */ |
| 115 | PPC_HAS_VSX, /* Vector-scalar extension */ |
| 116 | PPC_PSERIES_PERFMON_COMPAT, /* Set of backwards compatibile performance |
| 117 | monitoring events */ |
| 118 | PPC_TRUE_LE, |
| 119 | PPC_PPC_LE, |
| 120 | PPC_ARCH_2_07, /* ISA 2.07 - POWER8 */ |
| 121 | PPC_HTM, /* Hardware Transactional Memory */ |
| 122 | PPC_DSCR, /* Data stream control register */ |
| 123 | PPC_EBB, /* Event base branching */ |
| 124 | PPC_ISEL, /* Integer select instructions */ |
| 125 | PPC_TAR, /* Target address register */ |
| 126 | PPC_VEC_CRYPTO, /* Vector cryptography instructions */ |
| 127 | PPC_HTM_NOSC, /* Transactions aborted when syscall made*/ |
| 128 | PPC_ARCH_3_00, /* ISA 3.00 - POWER9 */ |
| 129 | PPC_HAS_IEEE128, /* VSX IEEE Binary Float 128-bit */ |
| 130 | PPC_DARN, /* Deliver a random number instruction */ |
| 131 | PPC_SCV, /* scv syscall */ |
| 132 | PPC_HTM_NO_SUSPEND, /* TM w/out suspended state */ |
| 133 | PPC_LAST_, |
| 134 | } PPCFeaturesEnum; |
| 135 | |
| 136 | int GetPPCFeaturesEnumValue(const PPCFeatures* features, PPCFeaturesEnum value); |
| 137 | |
| 138 | const char* GetPPCFeaturesEnumName(PPCFeaturesEnum); |
| 139 | |
| 140 | CPU_FEATURES_END_CPP_NAMESPACE |
| 141 | |
Guillaume Chatelet | 4155ee7 | 2019-01-18 13:38:22 +0100 | [diff] [blame] | 142 | #if !defined(CPU_FEATURES_ARCH_PPC) |
| 143 | #error "Including cpuinfo_ppc.h from a non-ppc target." |
| 144 | #endif |
| 145 | |
Rashmica Gupta | 3adafbf | 2018-04-23 10:46:47 +1000 | [diff] [blame] | 146 | #endif // CPU_FEATURES_INCLUDE_CPUINFO_PPC_H_ |