Marat Dukhan | 006461a | 2017-08-24 16:10:46 -0700 | [diff] [blame^] | 1 | #include <stdbool.h> |
| 2 | #include <stdint.h> |
| 3 | #include <stdio.h> |
| 4 | #include <string.h> |
| 5 | |
| 6 | #include <arm/android/api.h> |
| 7 | #include <log.h> |
| 8 | |
| 9 | |
| 10 | #define CPUINFO_COUNT_OF(x) (sizeof(x) / sizeof(0[x])) |
| 11 | |
| 12 | |
| 13 | static inline bool is_ascii_whitespace(char c) { |
| 14 | switch (c) { |
| 15 | case ' ': |
| 16 | case '\t': |
| 17 | case '\r': |
| 18 | case '\n': |
| 19 | return true; |
| 20 | default: |
| 21 | return false; |
| 22 | } |
| 23 | } |
| 24 | |
| 25 | static inline bool is_ascii_alphabetic(char c) { |
| 26 | const char lower_c = c | '\x20'; |
| 27 | return (uint8_t) (lower_c - 'a') <= (uint8_t) ('z' - 'a'); |
| 28 | } |
| 29 | |
| 30 | static inline bool is_ascii_alphabetic_uppercase(char c) { |
| 31 | return (uint8_t) (c - 'A') <= (uint8_t) ('Z' - 'A'); |
| 32 | } |
| 33 | |
| 34 | static inline bool is_ascii_numeric(char c) { |
| 35 | return (uint8_t) (c - '0') < 10; |
| 36 | } |
| 37 | |
| 38 | static inline bool is_ascii_alphanumeric(char c) { |
| 39 | return is_ascii_alphabetic(c) || is_ascii_numeric(c); |
| 40 | } |
| 41 | |
| 42 | static inline uint16_t load_u16le(const void* ptr) { |
| 43 | #if defined(__ARM_ARCH_7A__) || defined(__aarch64__) |
| 44 | return *((const uint16_t*) ptr); |
| 45 | #else |
| 46 | const uint8_t* byte_ptr = (const uint8_t*) ptr; |
| 47 | return ((uint16_t) byte_ptr[1] << 8) | (uint16_t) byte_ptr[0]; |
| 48 | #endif |
| 49 | } |
| 50 | |
| 51 | static inline uint32_t load_u24le(const void* ptr) { |
| 52 | #if defined(__ARM_ARCH_7A__) || defined(__aarch64__) |
| 53 | return ((uint32_t) ((const uint8_t*) ptr)[2] << 16) | ((uint32_t) *((const uint16_t*) ptr)); |
| 54 | #else |
| 55 | const uint8_t* byte_ptr = (const uint8_t*) ptr; |
| 56 | return ((uint32_t) byte_ptr[2] << 16) | ((uint32_t) byte_ptr[1] << 8) | (uint32_t) byte_ptr[0]; |
| 57 | #endif |
| 58 | } |
| 59 | |
| 60 | static inline uint32_t load_u32le(const void* ptr) { |
| 61 | #if defined(__ARM_ARCH_7A__) || defined(__aarch64__) |
| 62 | return *((const uint32_t*) ptr); |
| 63 | #else |
| 64 | return ((uint32_t) ((const uint8_t*) ptr)[3] << 24) | load_u24le(ptr); |
| 65 | #endif |
| 66 | } |
| 67 | |
| 68 | /* |
| 69 | * Map from ARM chipset series ID to ARM chipset vendor ID. |
| 70 | * This map is used to avoid storing vendor IDs in tables. |
| 71 | */ |
| 72 | static enum cpuinfo_arm_chipset_vendor chipset_series_vendor[cpuinfo_arm_chipset_series_max] = { |
| 73 | [cpuinfo_arm_chipset_series_unknown] = cpuinfo_arm_chipset_vendor_unknown, |
| 74 | [cpuinfo_arm_chipset_series_qualcomm_qsd] = cpuinfo_arm_chipset_vendor_qualcomm, |
| 75 | [cpuinfo_arm_chipset_series_qualcomm_msm] = cpuinfo_arm_chipset_vendor_qualcomm, |
| 76 | [cpuinfo_arm_chipset_series_qualcomm_apq] = cpuinfo_arm_chipset_vendor_qualcomm, |
| 77 | [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = cpuinfo_arm_chipset_vendor_qualcomm, |
| 78 | [cpuinfo_arm_chipset_series_mediatek_mt] = cpuinfo_arm_chipset_vendor_mediatek, |
| 79 | [cpuinfo_arm_chipset_series_samsung_exynos] = cpuinfo_arm_chipset_vendor_samsung, |
| 80 | [cpuinfo_arm_chipset_series_hisilicon_k3v] = cpuinfo_arm_chipset_vendor_hisilicon, |
| 81 | [cpuinfo_arm_chipset_series_hisilicon_hi] = cpuinfo_arm_chipset_vendor_hisilicon, |
| 82 | [cpuinfo_arm_chipset_series_hisilicon_kirin] = cpuinfo_arm_chipset_vendor_hisilicon, |
| 83 | [cpuinfo_arm_chipset_series_actions_atm] = cpuinfo_arm_chipset_vendor_actions, |
| 84 | [cpuinfo_arm_chipset_series_allwinner_a] = cpuinfo_arm_chipset_vendor_allwinner, |
| 85 | [cpuinfo_arm_chipset_series_amlogic_aml] = cpuinfo_arm_chipset_vendor_amlogic, |
| 86 | [cpuinfo_arm_chipset_series_amlogic_s] = cpuinfo_arm_chipset_vendor_amlogic, |
| 87 | [cpuinfo_arm_chipset_series_broadcom_bcm] = cpuinfo_arm_chipset_vendor_broadcom, |
| 88 | [cpuinfo_arm_chipset_series_lg_nuclun] = cpuinfo_arm_chipset_vendor_lg, |
| 89 | [cpuinfo_arm_chipset_series_leadcore_lc] = cpuinfo_arm_chipset_vendor_leadcore, |
| 90 | [cpuinfo_arm_chipset_series_marvell_pxa] = cpuinfo_arm_chipset_vendor_marvell, |
| 91 | [cpuinfo_arm_chipset_series_mstar_6a] = cpuinfo_arm_chipset_vendor_mstar, |
| 92 | [cpuinfo_arm_chipset_series_novathor_u] = cpuinfo_arm_chipset_vendor_novathor, |
| 93 | [cpuinfo_arm_chipset_series_nvidia_tegra_t] = cpuinfo_arm_chipset_vendor_nvidia, |
| 94 | [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = cpuinfo_arm_chipset_vendor_nvidia, |
| 95 | [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = cpuinfo_arm_chipset_vendor_nvidia, |
| 96 | [cpuinfo_arm_chipset_series_pinecone_surge_s] = cpuinfo_arm_chipset_vendor_pinecone, |
| 97 | [cpuinfo_arm_chipset_series_renesas_mp] = cpuinfo_arm_chipset_vendor_renesas, |
| 98 | [cpuinfo_arm_chipset_series_rockchip_rk] = cpuinfo_arm_chipset_vendor_rockchip, |
| 99 | [cpuinfo_arm_chipset_series_spreadtrum_sc] = cpuinfo_arm_chipset_vendor_spreadtrum, |
| 100 | [cpuinfo_arm_chipset_series_telechips_tcc] = cpuinfo_arm_chipset_vendor_telechips, |
| 101 | [cpuinfo_arm_chipset_series_texas_instruments_omap] = cpuinfo_arm_chipset_vendor_texas_instruments, |
| 102 | [cpuinfo_arm_chipset_series_wondermedia_wm] = cpuinfo_arm_chipset_vendor_wondermedia, |
| 103 | }; |
| 104 | |
| 105 | /** |
| 106 | * Tries to match /(MSM|APQ)\d{4}([A-Z\-]*)/ signature (case-insensitive) for Qualcomm MSM and APQ chipsets. |
| 107 | * If match successful, extracts model information into \p chipset argument. |
| 108 | * |
| 109 | * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform |
| 110 | * or ro.chipname) to match. |
| 111 | * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform or |
| 112 | * ro.chipname) to match. |
| 113 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 114 | * |
| 115 | * @returns true if signature matched, false otherwise. |
| 116 | */ |
| 117 | static bool match_msm_apq( |
| 118 | const char* start, const char* end, |
| 119 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 120 | { |
| 121 | /* Expect at least 7 symbols: 3 symbols "MSM" or "APQ" + 4 digits */ |
| 122 | if (start + 7 > end) { |
| 123 | return false; |
| 124 | } |
| 125 | |
| 126 | /* Check that string starts with "MSM" or "APQ", case-insensitive. |
| 127 | * The first three characters are loaded as 24-bit little endian word, binary ORed with 0x20 to convert to lower |
| 128 | * case, and compared to "MSM" and "APQ" strings as integers. |
| 129 | */ |
| 130 | const uint32_t series_signature = UINT32_C(0x00202020) | load_u24le(start); |
| 131 | enum cpuinfo_arm_chipset_series series; |
| 132 | switch (series_signature) { |
| 133 | case UINT32_C(0x6D736D): /* "msm" = reverse("msm") */ |
| 134 | series = cpuinfo_arm_chipset_series_qualcomm_msm; |
| 135 | break; |
| 136 | case UINT32_C(0x717061): /* "qpa" = reverse("apq") */ |
| 137 | series = cpuinfo_arm_chipset_series_qualcomm_apq; |
| 138 | break; |
| 139 | default: |
| 140 | return false; |
| 141 | } |
| 142 | |
| 143 | /* Sometimes there is a space ' ' following the MSM/APQ series */ |
| 144 | const char* pos = start + 3; |
| 145 | if (*pos == ' ') { |
| 146 | pos++; |
| 147 | |
| 148 | /* Expect at least 4 more symbols (4-digit model number) */ |
| 149 | if (pos + 4 > end) { |
| 150 | return false; |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | /* Validate and parse 4-digit model number */ |
| 155 | uint32_t model = 0; |
| 156 | for (uint32_t i = 0; i < 4; i++) { |
| 157 | const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; |
| 158 | if (digit >= 10) { |
| 159 | /* Not really a digit */ |
| 160 | return false; |
| 161 | } |
| 162 | model = model * 10 + digit; |
| 163 | } |
| 164 | |
| 165 | /* Suffix is optional, so if we got to this point, parsing is successful. Commit parsed chipset. */ |
| 166 | *chipset = (struct cpuinfo_arm_chipset) { |
| 167 | .vendor = cpuinfo_arm_chipset_vendor_qualcomm, |
| 168 | .series = series, |
| 169 | .model = model, |
| 170 | }; |
| 171 | |
| 172 | /* Parse as many suffix characters as match the pattern [A-Za-z\-] */ |
| 173 | for (uint32_t i = 0; i < CPUINFO_ARM_CHIPSET_SUFFIX_MAX; i++) { |
| 174 | if (pos + i == end) { |
| 175 | break; |
| 176 | } |
| 177 | |
| 178 | const char c = pos[i]; |
| 179 | if (is_ascii_alphabetic(c)) { |
| 180 | /* Matched a letter [A-Za-z] */ |
| 181 | chipset->suffix[i] = c & '\xDF'; |
| 182 | } else if (c == '-') { |
| 183 | /* Matched a dash '-' */ |
| 184 | chipset->suffix[i] = c; |
| 185 | } else { |
| 186 | /* Neither of [A-Za-z\-] */ |
| 187 | break; |
| 188 | } |
| 189 | } |
| 190 | return true; |
| 191 | } |
| 192 | |
| 193 | /** |
| 194 | * Tries to match /SDM\d{3}$/ signature for Qualcomm Snapdragon chipsets. |
| 195 | * If match successful, extracts model information into \p chipset argument. |
| 196 | * |
| 197 | * @param start - start of the /proc/cpuinfo Hardware string to match. |
| 198 | * @param end - end of the /proc/cpuinfo Hardware string to match. |
| 199 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 200 | * |
| 201 | * @returns true if signature matched, false otherwise. |
| 202 | */ |
| 203 | static bool match_sdm( |
| 204 | const char* start, const char* end, |
| 205 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 206 | { |
| 207 | /* Expect exactly 6 symbols: 3 symbols "SDM" + 3 digits */ |
| 208 | if (start + 6 != end) { |
| 209 | return false; |
| 210 | } |
| 211 | |
| 212 | /* Check that string starts with "SDM". |
| 213 | * The first three characters are loaded and compared as 24-bit little endian word. |
| 214 | */ |
| 215 | const uint32_t expected_sdm = load_u24le(start); |
| 216 | if (expected_sdm != UINT32_C(0x004D4453) /* "MDS" = reverse("SDM") */) { |
| 217 | return false; |
| 218 | } |
| 219 | |
| 220 | /* Validate and parse 3-digit model number */ |
| 221 | uint32_t model = 0; |
| 222 | for (uint32_t i = 3; i < 6; i++) { |
| 223 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 224 | if (digit >= 10) { |
| 225 | /* Not really a digit */ |
| 226 | return false; |
| 227 | } |
| 228 | model = model * 10 + digit; |
| 229 | } |
| 230 | |
| 231 | /* Return parsed chipset. */ |
| 232 | *chipset = (struct cpuinfo_arm_chipset) { |
| 233 | .vendor = cpuinfo_arm_chipset_vendor_qualcomm, |
| 234 | .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, |
| 235 | .model = model, |
| 236 | }; |
| 237 | return true; |
| 238 | } |
| 239 | |
| 240 | /** |
| 241 | * Tries to match /Samsung Exynos\d{4}$/ signature (case-insensitive) for Samsung Exynos chipsets. |
| 242 | * If match successful, extracts model information into \p chipset argument. |
| 243 | * |
| 244 | * @param start - start of the /proc/cpuinfo Hardware string to match. |
| 245 | * @param end - end of the /proc/cpuinfo Hardware string to match. |
| 246 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 247 | * |
| 248 | * @returns true if signature matched, false otherwise. |
| 249 | */ |
| 250 | static bool match_samsung_exynos( |
| 251 | const char* start, const char* end, |
| 252 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 253 | { |
| 254 | /* |
| 255 | * Expect at 18-19 symbols: |
| 256 | * - "Samsung" (7 symbols) + space + "Exynos" (6 symbols) + optional space 4-digit model number |
| 257 | */ |
| 258 | const size_t length = end - start; |
| 259 | switch (length) { |
| 260 | case 18: |
| 261 | case 19: |
| 262 | break; |
| 263 | default: |
| 264 | return false; |
| 265 | } |
| 266 | |
| 267 | /* |
| 268 | * Check that the string starts with "samsung exynos", case-insensitive. |
| 269 | * Blocks of 4 characters are loaded and compared as little-endian 32-bit word. |
| 270 | * Case-insensitive characters are binary ORed with 0x20 to convert them to lowercase. |
| 271 | */ |
| 272 | const uint32_t expected_sams = UINT32_C(0x20202000) | load_u32le(start); |
| 273 | if (expected_sams != UINT32_C(0x736D6153) /* "smaS" = reverse("Sams") */) { |
| 274 | return false; |
| 275 | } |
| 276 | const uint32_t expected_ung = UINT32_C(0x00202020) | load_u32le(start + 4); |
| 277 | if (expected_ung != UINT32_C(0x20676E75) /* " ung" = reverse("ung ") */) { |
| 278 | return false; |
| 279 | } |
| 280 | const uint32_t expected_exyn = UINT32_C(0x20202000) | load_u32le(start + 8); |
| 281 | if (expected_exyn != UINT32_C(0x6E797845) /* "nyxE" = reverse("Exyn") */) { |
| 282 | return false; |
| 283 | } |
| 284 | const uint16_t expected_os = UINT16_C(0x2020) | load_u16le(start + 12); |
| 285 | if (expected_os != UINT16_C(0x736F) /* "so" = reverse("os") */) { |
| 286 | return false; |
| 287 | } |
| 288 | |
| 289 | const char* pos = start + 14; |
| 290 | |
| 291 | /* There can be a space ' ' following the "Exynos" string */ |
| 292 | if (*pos == ' ') { |
| 293 | pos++; |
| 294 | |
| 295 | /* If optional space if present, we expect exactly 19 characters */ |
| 296 | if (length != 19) { |
| 297 | return false; |
| 298 | } |
| 299 | } |
| 300 | |
| 301 | /* Validate and parse 4-digit model number */ |
| 302 | uint32_t model = 0; |
| 303 | for (uint32_t i = 0; i < 4; i++) { |
| 304 | const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; |
| 305 | if (digit >= 10) { |
| 306 | /* Not really a digit */ |
| 307 | return start; |
| 308 | } |
| 309 | model = model * 10 + digit; |
| 310 | } |
| 311 | |
| 312 | /* Return parsed chipset */ |
| 313 | *chipset = (struct cpuinfo_arm_chipset) { |
| 314 | .vendor = cpuinfo_arm_chipset_vendor_samsung, |
| 315 | .series = cpuinfo_arm_chipset_series_samsung_exynos, |
| 316 | .model = model, |
| 317 | }; |
| 318 | return pos; |
| 319 | } |
| 320 | |
| 321 | /** |
| 322 | * Tries to match /exynos\d{4}$/ signature for Samsung Exynos chipsets. |
| 323 | * If match successful, extracts model information into \p chipset argument. |
| 324 | * |
| 325 | * @param start - start of the platform identifier (ro.board.platform or ro.chipname) to match. |
| 326 | * @param end - end of the platform identifier (ro.board.platform or ro.chipname) to match. |
| 327 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 328 | * |
| 329 | * @returns true if signature matched, false otherwise. |
| 330 | */ |
| 331 | static bool match_exynos( |
| 332 | const char* start, const char* end, |
| 333 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 334 | { |
| 335 | /* Expect exactly 10 symbols: "exynos" (6 symbols) + 4-digit model number */ |
| 336 | if (start + 10 != end) { |
| 337 | return false; |
| 338 | } |
| 339 | |
| 340 | /* Load first 4 bytes as little endian 32-bit word */ |
| 341 | const uint32_t expected_exyn = load_u32le(start); |
| 342 | if (expected_exyn != UINT32_C(0x6E797865) /* "nyxe" = reverse("exyn") */ ) { |
| 343 | return false; |
| 344 | } |
| 345 | |
| 346 | /* Load next 2 bytes as little endian 16-bit word */ |
| 347 | const uint16_t expected_os = load_u16le(start + 4); |
| 348 | if (expected_os != UINT16_C(0x736F) /* "so" = reverse("os") */ ) { |
| 349 | return false; |
| 350 | } |
| 351 | |
| 352 | /* Check and parse 4-digit model number */ |
| 353 | uint32_t model = 0; |
| 354 | for (uint32_t i = 6; i < 10; i++) { |
| 355 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 356 | if (digit >= 10) { |
| 357 | /* Not really a digit */ |
| 358 | return false; |
| 359 | } |
| 360 | model = model * 10 + digit; |
| 361 | } |
| 362 | |
| 363 | /* Return parsed chipset. */ |
| 364 | *chipset = (struct cpuinfo_arm_chipset) { |
| 365 | .vendor = cpuinfo_arm_chipset_vendor_samsung, |
| 366 | .series = cpuinfo_arm_chipset_series_samsung_exynos, |
| 367 | .model = model, |
| 368 | }; |
| 369 | return true; |
| 370 | } |
| 371 | |
| 372 | /** |
| 373 | * Tries to match /universal\d{4}$/ signature for Samsung Exynos chipsets. |
| 374 | * If match successful, extracts model information into \p chipset argument. |
| 375 | * |
| 376 | * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) |
| 377 | * to match. |
| 378 | * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) |
| 379 | * to match. |
| 380 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 381 | * |
| 382 | * @returns true if signature matched, false otherwise. |
| 383 | */ |
| 384 | static bool match_universal( |
| 385 | const char* start, const char* end, |
| 386 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 387 | { |
| 388 | /* Expect exactly 13 symbols: "universal" (9 symbols) + 4-digit model number */ |
| 389 | if (start + 13 != end) { |
| 390 | return false; |
| 391 | } |
| 392 | |
| 393 | /* |
| 394 | * Check that the string starts with "universal". |
| 395 | * Blocks of 4 characters are loaded and compared as little-endian 32-bit word. |
| 396 | * Case-insensitive characters are binary ORed with 0x20 to convert them to lowercase. |
| 397 | */ |
| 398 | const uint8_t expected_u = UINT8_C(0x20) | (uint8_t) start[0]; |
| 399 | if (expected_u != UINT8_C(0x75) /* "u" */) { |
| 400 | return false; |
| 401 | } |
| 402 | const uint32_t expected_nive = UINT32_C(0x20202020) | load_u32le(start + 1); |
| 403 | if (expected_nive != UINT32_C(0x6576696E) /* "evin" = reverse("nive") */ ) { |
| 404 | return false; |
| 405 | } |
| 406 | const uint32_t expected_ersa = UINT32_C(0x20202020) | load_u32le(start + 5); |
| 407 | if (expected_ersa != UINT32_C(0x6C617372) /* "lasr" = reverse("rsal") */) { |
| 408 | return false; |
| 409 | } |
| 410 | |
| 411 | /* Validate and parse 4-digit model number */ |
| 412 | uint32_t model = 0; |
| 413 | for (uint32_t i = 9; i < 13; i++) { |
| 414 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 415 | if (digit >= 10) { |
| 416 | /* Not really a digit */ |
| 417 | return false; |
| 418 | } |
| 419 | model = model * 10 + digit; |
| 420 | } |
| 421 | |
| 422 | /* Return parsed chipset. */ |
| 423 | *chipset = (struct cpuinfo_arm_chipset) { |
| 424 | .vendor = cpuinfo_arm_chipset_vendor_samsung, |
| 425 | .series = cpuinfo_arm_chipset_series_samsung_exynos, |
| 426 | .model = model, |
| 427 | }; |
| 428 | return true; |
| 429 | } |
| 430 | |
| 431 | /** |
| 432 | * Compares, case insensitively, a string to known values "SMDK4210" and "SMDK4x12" for Samsung Exynos chipsets. |
| 433 | * If platform identifier matches one of the SMDK* values, extracts model information into \p chipset argument. |
| 434 | * For "SMDK4x12" match, decodes the chipset name using number of cores. |
| 435 | * |
| 436 | * @param start - start of the platform identifier (/proc/cpuinfo Hardware string or ro.product.board) to match. |
| 437 | * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or ro.product.board) to match. |
| 438 | * @param cores - number of cores in the chipset. |
| 439 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 440 | * |
| 441 | * @returns true if signature matched, false otherwise. |
| 442 | */ |
| 443 | static bool match_and_parse_smdk( |
| 444 | const char* start, const char* end, uint32_t cores, |
| 445 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 446 | { |
| 447 | /* Expect exactly 8 symbols: "SMDK" (4 symbols) + 4-digit model number */ |
| 448 | if (start + 8 != end) { |
| 449 | return false; |
| 450 | } |
| 451 | |
| 452 | /* |
| 453 | * Check that string starts with "MT" (case-insensitive). |
| 454 | * The first four characters are loaded as a 32-bit little endian word and converted to lowercase. |
| 455 | */ |
| 456 | const uint32_t expected_smdk = UINT32_C(0x20202020) | load_u32le(start); |
| 457 | if (expected_smdk != UINT32_C(0x6B646D73) /* "kdms" = reverse("smdk") */) { |
| 458 | return false; |
| 459 | } |
| 460 | |
| 461 | /* |
| 462 | * Check that string ends with "4210" or "4x12". |
| 463 | * The last four characters are loaded and compared as a 32-bit little endian word. |
| 464 | */ |
| 465 | uint32_t model = 0; |
| 466 | const uint32_t expected_model = load_u32le(start + 4); |
| 467 | switch (expected_model) { |
| 468 | case UINT32_C(0x30313234): /* "0124" = reverse("4210") */ |
| 469 | model = 4210; |
| 470 | break; |
| 471 | case UINT32_C(0x32317834): /* "21x4" = reverse("4x12") */ |
| 472 | switch (cores) { |
| 473 | case 2: |
| 474 | model = 4212; |
| 475 | break; |
| 476 | case 4: |
| 477 | model = 4412; |
| 478 | break; |
| 479 | default: |
| 480 | cpuinfo_log_warning("system reported invalid %"PRIu32"-core Exynos 4x12 chipset", cores); |
| 481 | } |
| 482 | } |
| 483 | |
| 484 | if (model == 0) { |
| 485 | return false; |
| 486 | } |
| 487 | |
| 488 | *chipset = (struct cpuinfo_arm_chipset) { |
| 489 | .vendor = cpuinfo_arm_chipset_vendor_samsung, |
| 490 | .series = cpuinfo_arm_chipset_series_samsung_exynos, |
| 491 | .model = model, |
| 492 | }; |
| 493 | return true; |
| 494 | } |
| 495 | |
| 496 | /** |
| 497 | * Tries to match /MTK?\d{4}[A-Z]*$/ signature for MediaTek MT chipsets. |
| 498 | * If match successful, extracts model information into \p chipset argument. |
| 499 | * |
| 500 | * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform, |
| 501 | * ro.mediatek.platform, or ro.chipname) to match. |
| 502 | * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform, |
| 503 | * ro.mediatek.platform, or ro.chipname) to match. |
| 504 | * @param match_end - indicates if the function should attempt to match through the end of the string and fail if there |
| 505 | * are unparsed characters in the end, or match only MTK signature, model number, and some of the |
| 506 | * suffix characters (the ones that pass validation). |
| 507 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 508 | * |
| 509 | * @returns true if signature matched, false otherwise. |
| 510 | */ |
| 511 | static bool match_mt( |
| 512 | const char* start, const char* end, bool match_end, |
| 513 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 514 | { |
| 515 | /* Expect at least 6 symbols: "MT" (2 symbols) + 4-digit model number */ |
| 516 | if (start + 6 > end) { |
| 517 | return false; |
| 518 | } |
| 519 | |
| 520 | /* |
| 521 | * Check that string starts with "MT" (case-insensitive). |
| 522 | * The first two characters are loaded as 16-bit little endian word and converted to lowercase. |
| 523 | */ |
| 524 | const uint16_t mt = UINT16_C(0x2020) | load_u16le(start); |
| 525 | if (mt != UINT16_C(0x746D) /* "tm" */) { |
| 526 | return false; |
| 527 | } |
| 528 | |
| 529 | |
| 530 | /* Some images report "MTK" rather than "MT" */ |
| 531 | const char* pos = start + 2; |
| 532 | if (((uint8_t) *pos | UINT8_C(0x20)) == (uint8_t) 'k') { |
| 533 | pos++; |
| 534 | |
| 535 | /* Expect 4 more symbols after "MTK" (4-digit model number) */ |
| 536 | if (pos + 4 > end) { |
| 537 | return false; |
| 538 | } |
| 539 | } |
| 540 | |
| 541 | /* Validate and parse 4-digit model number */ |
| 542 | uint32_t model = 0; |
| 543 | for (uint32_t i = 0; i < 4; i++) { |
| 544 | const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; |
| 545 | if (digit >= 10) { |
| 546 | /* Not really a digit */ |
| 547 | return false; |
| 548 | } |
| 549 | model = model * 10 + digit; |
| 550 | } |
| 551 | |
| 552 | /* Record parsed chipset. This implicitly zeroes-out suffix, which will be parsed later. */ |
| 553 | *chipset = (struct cpuinfo_arm_chipset) { |
| 554 | .vendor = cpuinfo_arm_chipset_vendor_mediatek, |
| 555 | .series = cpuinfo_arm_chipset_series_mediatek_mt, |
| 556 | .model = model, |
| 557 | }; |
| 558 | |
| 559 | if (match_end) { |
| 560 | /* Check that the potential suffix does not exceed maximum length */ |
| 561 | const size_t suffix_length = end - pos; |
| 562 | if (suffix_length > CPUINFO_ARM_CHIPSET_SUFFIX_MAX) { |
| 563 | return false; |
| 564 | } |
| 565 | |
| 566 | /* Validate suffix characters and copy them to chipset structure */ |
| 567 | for (size_t i = 0; i < suffix_length; i++) { |
| 568 | const char c = (*pos++); |
| 569 | if (is_ascii_alphabetic(c)) { |
| 570 | /* Matched a letter [A-Za-z], convert to uppercase */ |
| 571 | chipset->suffix[i] = c & '\xDF'; |
| 572 | } else if (c == '/') { |
| 573 | /* Matched a slash '/' */ |
| 574 | chipset->suffix[i] = c; |
| 575 | } else { |
| 576 | /* Invalid suffix character (neither of [A-Za-z/]) */ |
| 577 | return false; |
| 578 | } |
| 579 | } |
| 580 | } else { |
| 581 | /* Validate and parse as many suffix characters as we can */ |
| 582 | for (size_t i = 0; i < CPUINFO_ARM_CHIPSET_SUFFIX_MAX; i++) { |
| 583 | if (pos + i == end) { |
| 584 | break; |
| 585 | } |
| 586 | |
| 587 | const char c = pos[i]; |
| 588 | if (is_ascii_alphabetic(c)) { |
| 589 | /* Matched a letter [A-Za-z], convert to uppercase */ |
| 590 | chipset->suffix[i] = c & '\xDF'; |
| 591 | } else if (c == '/') { |
| 592 | /* Matched a slash '/' */ |
| 593 | chipset->suffix[i] = c; |
| 594 | } else { |
| 595 | /* Invalid suffix character (neither of [A-Za-z/]). This marks the end of the suffix. */ |
| 596 | break; |
| 597 | } |
| 598 | } |
| 599 | } |
| 600 | /* All suffix characters successfully validated and copied to chipset data */ |
| 601 | return true; |
| 602 | } |
| 603 | |
| 604 | /** |
| 605 | * Tries to match /Kirin\s?\d{3}$/ signature for HiSilicon Kirin chipsets. |
| 606 | * If match successful, extracts model information into \p chipset argument. |
| 607 | * |
| 608 | * @param start - start of the /proc/cpuinfo Hardware string to match. |
| 609 | * @param end - end of the /proc/cpuinfo Hardware string to match. |
| 610 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 611 | * |
| 612 | * @returns true if signature matched, false otherwise. |
| 613 | */ |
| 614 | static bool match_kirin( |
| 615 | const char* start, const char* end, |
| 616 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 617 | { |
| 618 | /* Expect 8-9 symbols: "Kirin" (5 symbols) + optional whitespace (1 symbol) + 3-digit model number */ |
| 619 | const size_t length = end - start; |
| 620 | switch (length) { |
| 621 | case 8: |
| 622 | case 9: |
| 623 | break; |
| 624 | default: |
| 625 | return false; |
| 626 | } |
| 627 | |
| 628 | /* Check that the string starts with "Kirin". Symbols 1-5 are loaded and compared as little-endian 32-bit word. */ |
| 629 | if (start[0] != 'K') { |
| 630 | return false; |
| 631 | } |
| 632 | const uint32_t irin = load_u32le(start + 1); |
| 633 | if (irin != UINT32_C(0x6E697269) /* "niri" = reverse("irin") */) { |
| 634 | return false; |
| 635 | } |
| 636 | |
| 637 | /* Check for optional whitespace after "Kirin" */ |
| 638 | if (is_ascii_whitespace(start[5])) { |
| 639 | /* When whitespace is present after "Kirin", expect 9 symbols total */ |
| 640 | if (length != 9) { |
| 641 | return false; |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | /* Validate and parse 3-digit model number */ |
| 646 | uint32_t model = 0; |
| 647 | for (int32_t i = 0; i < 3; i++) { |
| 648 | const uint32_t digit = (uint32_t) (uint8_t) end[i - 3] - '0'; |
| 649 | if (digit >= 10) { |
| 650 | /* Not really a digit */ |
| 651 | return start; |
| 652 | } |
| 653 | model = model * 10 + digit; |
| 654 | } |
| 655 | |
| 656 | /* |
| 657 | * Thats it, return parsed chipset. |
| 658 | * Technically, Kirin 910T has a suffix, but it never appears in the form of "910T" string. |
| 659 | * Instead, Kirin 910T devices report "hi6620oem" string (handled outside of this function). |
| 660 | */ |
| 661 | *chipset = (struct cpuinfo_arm_chipset) { |
| 662 | .vendor = cpuinfo_arm_chipset_vendor_hisilicon, |
| 663 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 664 | .model = model, |
| 665 | }; |
| 666 | return true; |
| 667 | } |
| 668 | |
| 669 | /** |
| 670 | * Tries to match /rk\d{4}[a-z]?$/ signature for Rockchip RK chipsets. |
| 671 | * If match successful, extracts model information into \p chipset argument. |
| 672 | * |
| 673 | * @param start - start of the platform identifier (/proc/cpuinfo Hardware string or ro.board.platform) to match. |
| 674 | * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or ro.board.platform) to match. |
| 675 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 676 | * |
| 677 | * @returns true if signature matched, false otherwise. |
| 678 | */ |
| 679 | static bool match_rk( |
| 680 | const char* start, const char* end, |
| 681 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 682 | { |
| 683 | /* Expect 6-7 symbols: "RK" (2 symbols) + 4-digit model number + optional 1-letter suffix */ |
| 684 | const size_t length = end - start; |
| 685 | switch (length) { |
| 686 | case 6: |
| 687 | case 7: |
| 688 | break; |
| 689 | default: |
| 690 | return false; |
| 691 | } |
| 692 | |
| 693 | /* |
| 694 | * Check that string starts with "RK" (case-insensitive). |
| 695 | * The first two characters are loaded as 16-bit little endian word and converted to lowercase. |
| 696 | */ |
| 697 | const uint16_t expected_rk = UINT16_C(0x2020) | load_u16le(start); |
| 698 | if (expected_rk != UINT16_C(0x6B72) /* "kr" = reverse("rk") */) { |
| 699 | return false; |
| 700 | } |
| 701 | |
| 702 | /* Validate and parse 4-digit model number */ |
| 703 | uint32_t model = 0; |
| 704 | for (uint32_t i = 2; i < 6; i++) { |
| 705 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 706 | if (digit >= 10) { |
| 707 | /* Not really a digit */ |
| 708 | return start; |
| 709 | } |
| 710 | model = model * 10 + digit; |
| 711 | } |
| 712 | |
| 713 | /* Parse optional suffix */ |
| 714 | char suffix = 0; |
| 715 | if (length == 7) { |
| 716 | /* Parse the suffix letter */ |
| 717 | const char c = start[6]; |
| 718 | if (is_ascii_alphabetic(c)) { |
| 719 | /* Convert to upper case */ |
| 720 | suffix = c & '\xDF'; |
| 721 | } else { |
| 722 | /* Invalid suffix character */ |
| 723 | return false; |
| 724 | } |
| 725 | } |
| 726 | |
| 727 | /* Return parsed chipset */ |
| 728 | *chipset = (struct cpuinfo_arm_chipset) { |
| 729 | .vendor = cpuinfo_arm_chipset_vendor_rockchip, |
| 730 | .series = cpuinfo_arm_chipset_series_rockchip_rk, |
| 731 | .model = model, |
| 732 | .suffix = { |
| 733 | [0] = suffix, |
| 734 | }, |
| 735 | }; |
| 736 | return true; |
| 737 | } |
| 738 | |
| 739 | /** |
| 740 | * Tries to match, case-insentitively, /sc\d{4}[a-z]*|scx15$/ signature for Spreadtrum SC chipsets. |
| 741 | * If match successful, extracts model information into \p chipset argument. |
| 742 | * |
| 743 | * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, |
| 744 | * ro.board.platform, or ro.chipname) to match. |
| 745 | * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, |
| 746 | * ro.board.platform, or ro.chipname) to match. |
| 747 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 748 | * |
| 749 | * @returns true if signature matched, false otherwise. |
| 750 | */ |
| 751 | static bool match_sc( |
| 752 | const char* start, const char* end, |
| 753 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 754 | { |
| 755 | /* Expect at least 5 symbols: "scx15" */ |
| 756 | if (start + 5 > end) { |
| 757 | return false; |
| 758 | } |
| 759 | |
| 760 | /* |
| 761 | * Check that string starts with "SC" (case-insensitive). |
| 762 | * The first two characters are loaded as 16-bit little endian word and converted to lowercase. |
| 763 | */ |
| 764 | const uint16_t expected_sc = UINT16_C(0x2020) | load_u16le(start); |
| 765 | if (expected_sc != UINT16_C(0x6373) /* "cs" = reverse("sc") */) { |
| 766 | return false; |
| 767 | } |
| 768 | |
| 769 | /* Special case: "scx" prefix (SC7715 reported as "scx15") */ |
| 770 | if ((start[2] | '\x20') == 'x') { |
| 771 | /* Expect exactly 5 characters: "scx15" */ |
| 772 | if (start + 5 != end) { |
| 773 | return false; |
| 774 | } |
| 775 | |
| 776 | /* Check that string ends with "15" */ |
| 777 | const uint16_t expected_15 = load_u16le(start + 3); |
| 778 | if (expected_15 != UINT16_C(0x3531) /* "51" = reverse("15") */ ) { |
| 779 | return false; |
| 780 | } |
| 781 | |
| 782 | *chipset = (struct cpuinfo_arm_chipset) { |
| 783 | .vendor = cpuinfo_arm_chipset_vendor_spreadtrum, |
| 784 | .series = cpuinfo_arm_chipset_series_spreadtrum_sc, |
| 785 | .model = 7715, |
| 786 | }; |
| 787 | return true; |
| 788 | } |
| 789 | |
| 790 | /* Expect at least 6 symbols: "SC" (2 symbols) + 4-digit model number */ |
| 791 | if (start + 6 > end) { |
| 792 | return false; |
| 793 | } |
| 794 | |
| 795 | /* Validate and parse 4-digit model number */ |
| 796 | uint32_t model = 0; |
| 797 | for (uint32_t i = 2; i < 6; i++) { |
| 798 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 799 | if (digit >= 10) { |
| 800 | /* Not really a digit */ |
| 801 | return false; |
| 802 | } |
| 803 | model = model * 10 + digit; |
| 804 | } |
| 805 | |
| 806 | /* Write parsed chipset */ |
| 807 | *chipset = (struct cpuinfo_arm_chipset) { |
| 808 | .vendor = cpuinfo_arm_chipset_vendor_spreadtrum, |
| 809 | .series = cpuinfo_arm_chipset_series_spreadtrum_sc, |
| 810 | .model = model, |
| 811 | }; |
| 812 | |
| 813 | /* Validate and copy suffix letters. If suffix is too long, truncate at CPUINFO_ARM_CHIPSET_SUFFIX_MAX letters. */ |
| 814 | const char* suffix = start + 6; |
| 815 | for (size_t i = 0; i < CPUINFO_ARM_CHIPSET_SUFFIX_MAX; i++) { |
| 816 | if (suffix + i == end) { |
| 817 | break; |
| 818 | } |
| 819 | |
| 820 | const char c = suffix[i]; |
| 821 | if (!is_ascii_alphabetic(c)) { |
| 822 | /* Invalid suffix character */ |
| 823 | return false; |
| 824 | } |
| 825 | /* Convert suffix letter to uppercase */ |
| 826 | chipset->suffix[i] = c & '\xDF'; |
| 827 | } |
| 828 | return true; |
| 829 | } |
| 830 | |
| 831 | /** |
| 832 | * Tries to match /lc\d{4}[a-z]?$/ signature for Leadcore LC chipsets. |
| 833 | * If match successful, extracts model information into \p chipset argument. |
| 834 | * |
| 835 | * @param start - start of the platform identifier (ro.product.board or ro.board.platform) to match. |
| 836 | * @param end - end of the platform identifier (ro.product.board or ro.board.platform) to match. |
| 837 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 838 | * |
| 839 | * @returns true if signature matched, false otherwise. |
| 840 | */ |
| 841 | static bool match_lc( |
| 842 | const char* start, const char* end, |
| 843 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 844 | { |
| 845 | /* Expect at 6-7 symbols: "lc" (2 symbols) + 4-digit model number + optional 1-letter suffix */ |
| 846 | const size_t length = end - start; |
| 847 | switch (length) { |
| 848 | case 6: |
| 849 | case 7: |
| 850 | break; |
| 851 | default: |
| 852 | return false; |
| 853 | } |
| 854 | |
| 855 | /* Check that string starts with "lc". The first two characters are loaded as 16-bit little endian word */ |
| 856 | const uint16_t expected_lc = load_u16le(start); |
| 857 | if (expected_lc != UINT16_C(0x636C) /* "cl" = reverse("lc") */) { |
| 858 | return false; |
| 859 | } |
| 860 | |
| 861 | /* Validate and parse 4-digit model number */ |
| 862 | uint32_t model = 0; |
| 863 | for (uint32_t i = 2; i < 6; i++) { |
| 864 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 865 | if (digit >= 10) { |
| 866 | /* Not really a digit */ |
| 867 | return false; |
| 868 | } |
| 869 | model = model * 10 + digit; |
| 870 | } |
| 871 | |
| 872 | /* Parse optional suffix letter */ |
| 873 | char suffix = 0; |
| 874 | if (length == 7) { |
| 875 | const char c = start[6]; |
| 876 | if (is_ascii_alphabetic(c)) { |
| 877 | /* Convert to uppercase */ |
| 878 | chipset->suffix[0] = c & '\xDF'; |
| 879 | } else { |
| 880 | /* Invalid suffix character */ |
| 881 | return false; |
| 882 | } |
| 883 | } |
| 884 | |
| 885 | /* Return parsed chipset */ |
| 886 | *chipset = (struct cpuinfo_arm_chipset) { |
| 887 | .vendor = cpuinfo_arm_chipset_vendor_leadcore, |
| 888 | .series = cpuinfo_arm_chipset_series_leadcore_lc, |
| 889 | .model = model, |
| 890 | .suffix = { |
| 891 | [0] = suffix, |
| 892 | }, |
| 893 | }; |
| 894 | return true; |
| 895 | } |
| 896 | |
| 897 | /** |
| 898 | * Tries to match /PXA(\d{3,4}|1L88)$/ signature for Marvell PXA chipsets. |
| 899 | * If match successful, extracts model information into \p chipset argument. |
| 900 | * |
| 901 | * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) |
| 902 | * to match. |
| 903 | * @param end - end of the platform identifier (/proc/cpuinfo Hardaware string, ro.product.board or ro.chipname) to |
| 904 | * match. |
| 905 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 906 | * |
| 907 | * @returns true if signature matched, false otherwise. |
| 908 | */ |
| 909 | static bool match_pxa( |
| 910 | const char* start, const char* end, |
| 911 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 912 | { |
| 913 | /* Expect 6-7 symbols: "PXA" (3 symbols) + 3-4 digit model number */ |
| 914 | const size_t length = end - start; |
| 915 | switch (length) { |
| 916 | case 6: |
| 917 | case 7: |
| 918 | break; |
| 919 | default: |
| 920 | return false; |
| 921 | } |
| 922 | |
| 923 | /* Check that the string starts with "PXA". Symbols 1-3 are loaded and compared as little-endian 16-bit word. */ |
| 924 | if (start[0] != 'P') { |
| 925 | return false; |
| 926 | } |
| 927 | const uint16_t expected_xa = load_u16le(start + 1); |
| 928 | if (expected_xa != UINT16_C(0x4158) /* "AX" = reverse("XA") */) { |
| 929 | return false; |
| 930 | } |
| 931 | |
| 932 | uint32_t model = 0; |
| 933 | |
| 934 | |
| 935 | /* Check for a very common typo: "PXA1L88" for "PXA1088" */ |
| 936 | if (length == 7) { |
| 937 | /* Load 4 model "number" symbols as a little endian 32-bit word and compare to "1L88" */ |
| 938 | const uint32_t expected_1L88 = load_u32le(start + 3); |
| 939 | if (expected_1L88 == UINT32_C(0x38384C31) /* "88L1" = reverse("1L88") */) { |
| 940 | model = 1088; |
| 941 | goto write_chipset; |
| 942 | } |
| 943 | } |
| 944 | |
| 945 | /* Check and parse 3-4 digit model number */ |
| 946 | for (uint32_t i = 3; i < length; i++) { |
| 947 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 948 | if (digit >= 10) { |
| 949 | /* Not really a digit */ |
| 950 | return false; |
| 951 | } |
| 952 | model = model * 10 + digit; |
| 953 | } |
| 954 | |
| 955 | /* Return parsed chipset. */ |
| 956 | write_chipset: |
| 957 | *chipset = (struct cpuinfo_arm_chipset) { |
| 958 | .vendor = cpuinfo_arm_chipset_vendor_marvell, |
| 959 | .series = cpuinfo_arm_chipset_series_marvell_pxa, |
| 960 | .model = model, |
| 961 | }; |
| 962 | return true; |
| 963 | } |
| 964 | |
| 965 | /** |
| 966 | * Tries to match /OMAP\d{4}$/ signature for Texas Instruments OMAP chipsets. |
| 967 | * If match successful, extracts model information into \p chipset argument. |
| 968 | * |
| 969 | * @param start - start of the /proc/cpuinfo Hardware string to match. |
| 970 | * @param end - end of the /proc/cpuinfo Hardaware string to match. |
| 971 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 972 | * |
| 973 | * @returns true if signature matched, false otherwise. |
| 974 | */ |
| 975 | static bool match_omap( |
| 976 | const char* start, const char* end, |
| 977 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 978 | { |
| 979 | /* Expect exactly 8 symbols: "OMAP" (4 symbols) + 4-digit model number */ |
| 980 | if (start + 8 != end) { |
| 981 | return false; |
| 982 | } |
| 983 | |
| 984 | /* Check that the string starts with "OMAP". Symbols 0-4 are loaded and compared as little-endian 32-bit word. */ |
| 985 | const uint32_t expected_omap = load_u32le(start); |
| 986 | if (expected_omap != UINT32_C(0x50414D4F) /* "PAMO" = reverse("OMAP") */) { |
| 987 | return false; |
| 988 | } |
| 989 | |
| 990 | /* Validate and parse 4-digit model number */ |
| 991 | uint32_t model = 0; |
| 992 | for (uint32_t i = 4; i < 8; i++) { |
| 993 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 994 | if (digit >= 10) { |
| 995 | /* Not really a digit */ |
| 996 | return false; |
| 997 | } |
| 998 | model = model * 10 + digit; |
| 999 | } |
| 1000 | |
| 1001 | /* Return parsed chipset. */ |
| 1002 | *chipset = (struct cpuinfo_arm_chipset) { |
| 1003 | .vendor = cpuinfo_arm_chipset_vendor_texas_instruments, |
| 1004 | .series = cpuinfo_arm_chipset_series_texas_instruments_omap, |
| 1005 | .model = model, |
| 1006 | }; |
| 1007 | return true; |
| 1008 | } |
| 1009 | |
| 1010 | /** |
| 1011 | * Compares platform identifier string to known values for Broadcom chipsets. |
| 1012 | * If the string matches one of the known values, the function decodes Broadcom chipset from frequency and number of |
| 1013 | * cores into \p chipset argument. |
| 1014 | * |
| 1015 | * @param start - start of the platform identifier (ro.product.board or ro.board.platform) to match. |
| 1016 | * @param end - end of the platform identifier (ro.product.board or ro.board.platform) to match. |
| 1017 | * @param cores - number of cores in the chipset. |
| 1018 | * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu<number>/cpofreq/cpu_freq_max values. |
| 1019 | * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. |
| 1020 | * |
| 1021 | * @returns true if signature matched (even if exact model can't be decoded), false otherwise. |
| 1022 | */ |
| 1023 | static bool match_and_parse_broadcom( |
| 1024 | const char* start, const char* end, uint32_t cores, uint32_t max_cpu_freq_max, |
| 1025 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 1026 | { |
| 1027 | /* Expect 4-6 symbols: "java" (4 symbols), "rhea" (4 symbols), "capri" (5 symbols), or "hawaii" (6 symbols) */ |
| 1028 | const size_t length = end - start; |
| 1029 | switch (length) { |
| 1030 | case 4: |
| 1031 | case 5: |
| 1032 | case 6: |
| 1033 | break; |
| 1034 | default: |
| 1035 | return false; |
| 1036 | } |
| 1037 | |
| 1038 | /* |
| 1039 | * Compare the platform identifier to known values for Broadcom chipsets: |
| 1040 | * - "rhea" |
| 1041 | * - "java" |
| 1042 | * - "capri" |
| 1043 | * - "hawaii" |
| 1044 | * Upon a successful match, decode chipset name from frequency and number of cores. |
| 1045 | */ |
| 1046 | uint32_t model = 0; |
| 1047 | char suffix = 0; |
| 1048 | const uint32_t expected_platform = load_u32le(start); |
| 1049 | switch (expected_platform) { |
| 1050 | case UINT32_C(0x61656872): /* "aehr" = reverse("rhea") */ |
| 1051 | if (length == 4) { |
| 1052 | /* |
| 1053 | * Detected "rhea" platform: |
| 1054 | * - 1 core @ 849999 KHz -> BCM21654 |
| 1055 | * - 1 core @ 999999 KHz -> BCM21654G |
| 1056 | */ |
| 1057 | if (cores == 1) { |
| 1058 | model = 21654; |
| 1059 | if (max_cpu_freq_max >= 999999) { |
| 1060 | suffix = 'G'; |
| 1061 | } |
| 1062 | } |
| 1063 | } |
| 1064 | break; |
| 1065 | case UINT32_C(0x6176616A): /* "avaj" = reverse("java") */ |
| 1066 | if (length == 4) { |
| 1067 | /* |
| 1068 | * Detected "java" platform: |
| 1069 | * - 4 cores -> BCM23550 |
| 1070 | */ |
| 1071 | if (cores == 4) { |
| 1072 | model = 23550; |
| 1073 | } |
| 1074 | } |
| 1075 | break; |
| 1076 | case UINT32_C(0x61776168): /* "awah" = reverse("hawa") */ |
| 1077 | if (length == 6) { |
| 1078 | /* Check that string equals "hawaii" */ |
| 1079 | const uint16_t expected_ii = load_u16le(start + 4); |
| 1080 | if (expected_ii == UINT16_C(0x6969) /* "ii" */ ) { |
| 1081 | /* |
| 1082 | * Detected "hawaii" platform: |
| 1083 | * - 1 core -> BCM21663 |
| 1084 | * - 2 cores @ 999999 KHz -> BCM21664 |
| 1085 | * - 2 cores @ 1200000 KHz -> BCM21664T |
| 1086 | */ |
| 1087 | switch (cores) { |
| 1088 | case 1: |
| 1089 | model = 21663; |
| 1090 | break; |
| 1091 | case 2: |
| 1092 | model = 21664; |
| 1093 | if (max_cpu_freq_max >= 1200000) { |
| 1094 | suffix = 'T'; |
| 1095 | } |
| 1096 | break; |
| 1097 | } |
| 1098 | } |
| 1099 | } |
| 1100 | break; |
| 1101 | case UINT32_C(0x72706163): /* "rpac" = reverse("capr") */ |
| 1102 | if (length == 5) { |
| 1103 | /* Check that string equals "capri" */ |
| 1104 | if (start[4] == 'i') { |
| 1105 | /* |
| 1106 | * Detected "capri" platform: |
| 1107 | * - 2 cores -> BCM28155 |
| 1108 | */ |
| 1109 | if (cores == 2) { |
| 1110 | model = 28155; |
| 1111 | } |
| 1112 | } |
| 1113 | } |
| 1114 | break; |
| 1115 | } |
| 1116 | |
| 1117 | if (model != 0) { |
| 1118 | /* Chipset was successfully decoded */ |
| 1119 | *chipset = (struct cpuinfo_arm_chipset) { |
| 1120 | .vendor = cpuinfo_arm_chipset_vendor_broadcom, |
| 1121 | .series = cpuinfo_arm_chipset_series_broadcom_bcm, |
| 1122 | .model = model, |
| 1123 | .suffix = { |
| 1124 | [0] = suffix, |
| 1125 | }, |
| 1126 | }; |
| 1127 | } |
| 1128 | return model != 0; |
| 1129 | } |
| 1130 | |
| 1131 | struct sunxi_map_entry { |
| 1132 | uint8_t sunxi; |
| 1133 | uint8_t cores; |
| 1134 | uint8_t model; |
| 1135 | char suffix; |
| 1136 | }; |
| 1137 | |
| 1138 | static const struct sunxi_map_entry sunxi_map_entries[] = { |
| 1139 | { |
| 1140 | /* ("sun4i", 1) -> "A10" */ |
| 1141 | .sunxi = 4, |
| 1142 | .cores = 1, |
| 1143 | .model = 10, |
| 1144 | }, |
| 1145 | { |
| 1146 | /* ("sun5i", 1) -> "A13" */ |
| 1147 | .sunxi = 5, |
| 1148 | .cores = 1, |
| 1149 | .model = 13, |
| 1150 | }, |
| 1151 | { |
| 1152 | /* ("sun6i", 4) -> "A31" */ |
| 1153 | .sunxi = 6, |
| 1154 | .cores = 4, |
| 1155 | .model = 31, |
| 1156 | }, |
| 1157 | { |
| 1158 | /* ("sun7i", 2) -> "A20" */ |
| 1159 | .sunxi = 7, |
| 1160 | .cores = 2, |
| 1161 | .model = 20, |
| 1162 | |
| 1163 | }, |
| 1164 | { |
| 1165 | /* ("sun8i", 2) -> "A23" */ |
| 1166 | .sunxi = 8, |
| 1167 | .cores = 2, |
| 1168 | .model = 23, |
| 1169 | }, |
| 1170 | { |
| 1171 | /* ("sun8i", 4) -> "A33" */ |
| 1172 | .sunxi = 8, |
| 1173 | .cores = 4, |
| 1174 | .model = 33, |
| 1175 | }, |
| 1176 | { |
| 1177 | /* ("sun8i", 8) -> "A83T" */ |
| 1178 | .sunxi = 8, |
| 1179 | .cores = 8, |
| 1180 | .model = 83, |
| 1181 | .suffix = 'T', |
| 1182 | }, |
| 1183 | { |
| 1184 | /* ("sun9i", 8) -> "A80" */ |
| 1185 | .sunxi = 9, |
| 1186 | .cores = 8, |
| 1187 | .model = 80, |
| 1188 | }, |
| 1189 | { |
| 1190 | /* ("sun50i", 4) -> "A64" */ |
| 1191 | .sunxi = 50, |
| 1192 | .cores = 4, |
| 1193 | .model = 64, |
| 1194 | }, |
| 1195 | }; |
| 1196 | |
| 1197 | /** |
| 1198 | * Tries to match /proc/cpuinfo Hardware string to Allwinner /sun\d+i/ signature. |
| 1199 | * If the string matches signature, the function decodes Allwinner chipset from the number in the signature and the |
| 1200 | * number of cores, and stores it in \p chipset argument. |
| 1201 | * |
| 1202 | * @param start - start of the /proc/cpuinfo Hardware string to match. |
| 1203 | * @param end - end of the /proc/cpuinfo Hardware string to match. |
| 1204 | * @param cores - number of cores in the chipset. |
| 1205 | * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. |
| 1206 | * |
| 1207 | * @returns true if signature matched (even if exact model can't be decoded), false otherwise. |
| 1208 | */ |
| 1209 | static bool match_and_parse_sunxi( |
| 1210 | const char* start, const char* end, uint32_t cores, |
| 1211 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 1212 | { |
| 1213 | /* Expect at least 5 symbols: "sun" (3 symbols) + platform id (1-2 digits) + "i" (1 symbol) */ |
| 1214 | if (start + 5 > end) { |
| 1215 | return false; |
| 1216 | } |
| 1217 | |
| 1218 | /* Compare the first 3 characters to "sun" */ |
| 1219 | if (start[0] != 's') { |
| 1220 | return false; |
| 1221 | } |
| 1222 | const uint16_t expected_un = load_u16le(start + 1); |
| 1223 | if (expected_un != UINT16_C(0x6E75) /* "nu" = reverse("un") */) { |
| 1224 | return false; |
| 1225 | } |
| 1226 | |
| 1227 | /* Check and parse the first (required) digit of the sunXi platform id */ |
| 1228 | uint32_t sunxi_platform = 0; |
| 1229 | { |
| 1230 | const uint32_t digit = (uint32_t) (uint8_t) start[3] - '0'; |
| 1231 | if (digit >= 10) { |
| 1232 | /* Not really a digit */ |
| 1233 | return false; |
| 1234 | } |
| 1235 | sunxi_platform = digit; |
| 1236 | } |
| 1237 | |
| 1238 | /* Parse optional second digit of the sunXi platform id */ |
| 1239 | const char* pos = start + 4; |
| 1240 | { |
| 1241 | const uint32_t digit = (uint32_t) (uint8_t) (*pos) - '0'; |
| 1242 | if (digit < 10) { |
| 1243 | sunxi_platform = sunxi_platform * 10 + digit; |
| 1244 | if (++pos == end) { |
| 1245 | /* Expected one more character, final 'i' letter */ |
| 1246 | return false; |
| 1247 | } |
| 1248 | } |
| 1249 | } |
| 1250 | |
| 1251 | /* Validate the final 'i' letter */ |
| 1252 | if (*pos != 'i') { |
| 1253 | return false; |
| 1254 | } |
| 1255 | |
| 1256 | /* Compare sunXi platform id and number of cores to tabluted values to decode chipset name */ |
| 1257 | uint32_t model = 0; |
| 1258 | char suffix = 0; |
| 1259 | for (size_t i = 0; i < CPUINFO_COUNT_OF(sunxi_map_entries); i++) { |
| 1260 | if (sunxi_platform == sunxi_map_entries[i].sunxi && cores == sunxi_map_entries[i].cores) { |
| 1261 | model = sunxi_map_entries[i].model; |
| 1262 | suffix = sunxi_map_entries[i].suffix; |
| 1263 | break; |
| 1264 | } |
| 1265 | } |
| 1266 | |
| 1267 | if (model == 0) { |
| 1268 | cpuinfo_log_info("unrecognized %"PRIu32"-core Allwinner sun%"PRIu32" platform", cores, sunxi_platform); |
| 1269 | } |
| 1270 | /* Create chipset name from decoded data */ |
| 1271 | *chipset = (struct cpuinfo_arm_chipset) { |
| 1272 | .vendor = cpuinfo_arm_chipset_vendor_allwinner, |
| 1273 | .series = cpuinfo_arm_chipset_series_allwinner_a, |
| 1274 | .model = model, |
| 1275 | .suffix = { |
| 1276 | [0] = suffix, |
| 1277 | }, |
| 1278 | }; |
| 1279 | return true; |
| 1280 | } |
| 1281 | |
| 1282 | /** |
| 1283 | * Compares /proc/cpuinfo Hardware string to "WMT" signature. |
| 1284 | * If the string matches signature, the function decodes WonderMedia chipset from frequency and number of cores into |
| 1285 | * \p chipset argument. |
| 1286 | * |
| 1287 | * @param start - start of the /proc/cpuinfo Hardware string to match. |
| 1288 | * @param end - end of the /proc/cpuinfo Hardware string to match. |
| 1289 | * @param cores - number of cores in the chipset. |
| 1290 | * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu<number>/cpofreq/cpu_freq_max values. |
| 1291 | * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. |
| 1292 | * |
| 1293 | * @returns true if signature matched (even if exact model can't be decoded), false otherwise. |
| 1294 | */ |
| 1295 | static bool match_and_parse_wmt( |
| 1296 | const char* start, const char* end, uint32_t cores, uint32_t max_cpu_freq_max, |
| 1297 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 1298 | { |
| 1299 | /* Expected 3 symbols: "WMT" */ |
| 1300 | if (start + 3 != end) { |
| 1301 | return false; |
| 1302 | } |
| 1303 | |
| 1304 | /* Compare string to "WMT" */ |
| 1305 | if (start[0] != 'W') { |
| 1306 | return false; |
| 1307 | } |
| 1308 | const uint16_t expected_mt = load_u16le(start + 1); |
| 1309 | if (expected_mt != UINT16_C(0x544D) /* "TM" = reverse("MT") */) { |
| 1310 | return false; |
| 1311 | } |
| 1312 | |
| 1313 | /* Decode chipset name from frequency and number of cores */ |
| 1314 | uint32_t model = 0; |
| 1315 | switch (cores) { |
| 1316 | case 1: |
| 1317 | switch (max_cpu_freq_max) { |
| 1318 | case 1008000: |
| 1319 | /* 1 core @ 1008000 KHz -> WM8950 */ |
| 1320 | model = 8950; |
| 1321 | break; |
| 1322 | case 1200000: |
| 1323 | /* 1 core @ 1200000 KHz -> WM8850 */ |
| 1324 | model = 8850; |
| 1325 | break; |
| 1326 | } |
| 1327 | break; |
| 1328 | case 2: |
| 1329 | if (max_cpu_freq_max == 1500000) { |
| 1330 | /* 2 cores @ 1500000 KHz -> WM8880 */ |
| 1331 | model = 8880; |
| 1332 | } |
| 1333 | break; |
| 1334 | } |
| 1335 | |
| 1336 | if (model == 0) { |
| 1337 | cpuinfo_log_info("unrecognized WonderMedia platform with %"PRIu32" cores at %"PRIu32" KHz", |
| 1338 | cores, max_cpu_freq_max); |
| 1339 | } |
| 1340 | *chipset = (struct cpuinfo_arm_chipset) { |
| 1341 | .vendor = cpuinfo_arm_chipset_vendor_wondermedia, |
| 1342 | .series = cpuinfo_arm_chipset_series_wondermedia_wm, |
| 1343 | .model = model, |
| 1344 | }; |
| 1345 | return true; |
| 1346 | } |
| 1347 | |
| 1348 | struct huawei_map_entry { |
| 1349 | uint32_t platform; |
| 1350 | uint32_t model; |
| 1351 | }; |
| 1352 | |
| 1353 | static const struct huawei_map_entry huawei_platform_map[] = { |
| 1354 | { |
| 1355 | /* "BAC" -> Kirin 659 */ |
| 1356 | .platform = UINT32_C(0x00434142), /* "\0CAB" = reverse("BAC\0") */ |
| 1357 | .model = 659, |
| 1358 | }, |
| 1359 | { |
| 1360 | /* "DUK" -> Kirin 960 */ |
| 1361 | .platform = UINT32_C(0x004B5544), /* "\0KUD" = reverse("DUK\0") */ |
| 1362 | .model = 960, |
| 1363 | }, |
| 1364 | { |
| 1365 | /* "EVA" -> Kirin 955 */ |
| 1366 | .platform = UINT32_C(0x00415645), /* "\0AVE" = reverse("EVA\0") */ |
| 1367 | .model = 955, |
| 1368 | }, |
| 1369 | { |
| 1370 | /* "FRD" -> Kirin 950 */ |
| 1371 | .platform = UINT32_C(0x00445246), /* "\0DRF" = reverse("FRD\0") */ |
| 1372 | .model = 950, |
| 1373 | }, |
| 1374 | { |
| 1375 | /* "KNT" -> Kirin 950 */ |
| 1376 | .platform = UINT32_C(0x00544E4B), /* "\0TNK" = reverse("KNT\0") */ |
| 1377 | .model = 950, |
| 1378 | }, |
| 1379 | { |
| 1380 | /* "LON" -> Kirin 960 */ |
| 1381 | .platform = UINT32_C(0x004E4F4C), /* "\0NOL" = reverse("LON\0") */ |
| 1382 | .model = 960, |
| 1383 | }, |
| 1384 | { |
| 1385 | /* "MHA" -> Kirin 960 */ |
| 1386 | .platform = UINT32_C(0x0041484D), /* "\0AHM" = reverse("MHA\0") */ |
| 1387 | .model = 960, |
| 1388 | }, |
| 1389 | { |
| 1390 | /* "NXT" -> Kirin 950 */ |
| 1391 | .platform = UINT32_C(0x0054584E), /* "\0TXN" = reverse("NXT\0") */ |
| 1392 | .model = 950, |
| 1393 | }, |
| 1394 | { |
| 1395 | /* "STF" -> Kirin 960 */ |
| 1396 | .platform = UINT32_C(0x00465453), /* "\0FTS" = reverse("STF\0") */ |
| 1397 | .model = 960, |
| 1398 | }, |
| 1399 | { |
| 1400 | /* "VIE" -> Kirin 955 */ |
| 1401 | .platform = UINT32_C(0x00454956), /* "\0EIV" = reverse("VIE\0") */ |
| 1402 | .model = 955, |
| 1403 | }, |
| 1404 | { |
| 1405 | /* "VKY" -> Kirin 960 */ |
| 1406 | .platform = UINT32_C(0x00594B56), /* "\0YKV" = reverse("VKY\0") */ |
| 1407 | .model = 960, |
| 1408 | }, |
| 1409 | { |
| 1410 | /* "VTR" -> Kirin 960 */ |
| 1411 | .platform = UINT32_C(0x00525456), /* "\0RTV" = reverse("VTR\0") */ |
| 1412 | .model = 960, |
| 1413 | }, |
| 1414 | }; |
| 1415 | |
| 1416 | /** |
| 1417 | * Tries to match ro.product.board string to Huawei /([A-Z]{3})(\-[A-Z]?L\d{2})$/ signature where \1 is one of the |
| 1418 | * known values for Huawei devices, which do not report chipset name elsewhere. |
| 1419 | * If the string matches signature, the function decodes chipset (always HiSilicon Kirin for matched devices) from |
| 1420 | * the number in the signature and stores it in \p chipset argument. |
| 1421 | * |
| 1422 | * @param start - start of the ro.product.board string to match. |
| 1423 | * @param end - end of the ro.product.board string to match. |
| 1424 | * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. |
| 1425 | * |
| 1426 | * @returns true if signature matched, false otherwise. |
| 1427 | */ |
| 1428 | static bool match_and_parse_huawei( |
| 1429 | const char* start, const char* end, |
| 1430 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 1431 | { |
| 1432 | /* |
| 1433 | * Expect length of either 3, 7 or 8, exactly: |
| 1434 | * - 3-letter platform identifier (see huawei_platform_map) |
| 1435 | * - 3-letter platform identifier + '-' + 'L' + two digits |
| 1436 | * - 3-letter platform identifier + '-' + capital letter + 'L' + two digits |
| 1437 | */ |
| 1438 | const size_t length = end - start; |
| 1439 | switch (length) { |
| 1440 | case 3: |
| 1441 | case 7: |
| 1442 | case 8: |
| 1443 | break; |
| 1444 | default: |
| 1445 | return false; |
| 1446 | } |
| 1447 | |
| 1448 | /* |
| 1449 | * Try to find the first three-letter substring in among the tabulated entries for Huawei devices. |
| 1450 | * The first three letters are loaded and compared as a little-endian 24-bit word. |
| 1451 | */ |
| 1452 | uint32_t model = 0; |
| 1453 | const uint32_t target_platform_id = load_u24le(start); |
| 1454 | for (uint32_t i = 0; i < CPUINFO_COUNT_OF(huawei_platform_map); i++) { |
| 1455 | if (huawei_platform_map[i].platform == target_platform_id) { |
| 1456 | model = huawei_platform_map[i].model; |
| 1457 | break; |
| 1458 | } |
| 1459 | } |
| 1460 | |
| 1461 | if (model == 0) { |
| 1462 | /* Platform does not match the tabulated Huawei entries */ |
| 1463 | return false; |
| 1464 | } |
| 1465 | |
| 1466 | if (length > 3) { |
| 1467 | /* |
| 1468 | * Check that: |
| 1469 | * - The symbol after platform id is a dash |
| 1470 | * - The symbol after it is an uppercase letter. For 7-symbol strings, the symbol is just 'L'. |
| 1471 | */ |
| 1472 | if (start[3] != '-' || !is_ascii_alphabetic_uppercase(start[4])) { |
| 1473 | return false; |
| 1474 | } |
| 1475 | |
| 1476 | /* Check that the last 3 entries are /L\d\d/ */ |
| 1477 | if (end[-3] != 'L' || !is_ascii_numeric(end[-2]) || !is_ascii_numeric(end[-1])) { |
| 1478 | return false; |
| 1479 | } |
| 1480 | } |
| 1481 | |
| 1482 | /* All checks succeeded, commit chipset name */ |
| 1483 | *chipset = (struct cpuinfo_arm_chipset) { |
| 1484 | .vendor = cpuinfo_arm_chipset_vendor_hisilicon, |
| 1485 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 1486 | .model = model, |
| 1487 | }; |
| 1488 | return true; |
| 1489 | } |
| 1490 | |
| 1491 | /** |
| 1492 | * Tries to match /tcc\d{3}x$/ signature for Telechips TCCXXXx chipsets. |
| 1493 | * If match successful, extracts model information into \p chipset argument. |
| 1494 | * |
| 1495 | * @param start - start of the /proc/cpuinfo Hardware string to match. |
| 1496 | * @param end - end of the /proc/cpuinfo Hardware string to match. |
| 1497 | * @param[out] chipset - location where chipset information will be stored upon a successful match. |
| 1498 | * |
| 1499 | * @returns true if signature matched, false otherwise. |
| 1500 | */ |
| 1501 | static bool match_tcc( |
| 1502 | const char* start, const char* end, |
| 1503 | struct cpuinfo_arm_chipset chipset[restrict static 1]) |
| 1504 | { |
| 1505 | /* Expect exactly 7 symbols: "tcc" (3 symbols) + 3-digit model number + fixed "x" suffix */ |
| 1506 | if (start + 7 != end) { |
| 1507 | return false; |
| 1508 | } |
| 1509 | |
| 1510 | /* Quick check for the first character */ |
| 1511 | if (start[0] != 't') { |
| 1512 | return false; |
| 1513 | } |
| 1514 | |
| 1515 | /* Load the next 2 bytes as little endian 16-bit word */ |
| 1516 | const uint16_t expected_cc = load_u16le(start + 1); |
| 1517 | if (expected_cc != UINT16_C(0x6363) /* "cc" */ ) { |
| 1518 | return false; |
| 1519 | } |
| 1520 | |
| 1521 | /* Check and parse 3-digit model number */ |
| 1522 | uint32_t model = 0; |
| 1523 | for (uint32_t i = 3; i < 6; i++) { |
| 1524 | const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; |
| 1525 | if (digit >= 10) { |
| 1526 | /* Not really a digit */ |
| 1527 | return false; |
| 1528 | } |
| 1529 | model = model * 10 + digit; |
| 1530 | } |
| 1531 | |
| 1532 | /* Check the fixed 'x' suffix in the end */ |
| 1533 | if (start[6] != 'x') { |
| 1534 | return false; |
| 1535 | } |
| 1536 | |
| 1537 | /* Commit parsed chipset. */ |
| 1538 | *chipset = (struct cpuinfo_arm_chipset) { |
| 1539 | .vendor = cpuinfo_arm_chipset_vendor_telechips, |
| 1540 | .series = cpuinfo_arm_chipset_series_telechips_tcc, |
| 1541 | .model = model, |
| 1542 | .suffix = 'X', |
| 1543 | }; |
| 1544 | return true; |
| 1545 | } |
| 1546 | |
| 1547 | /* |
| 1548 | * Compares ro.board.platform string to nVidia Tegra signatures ("tegra" and "tegra3") |
| 1549 | * This check has effect on how /proc/cpuinfo Hardware string is interpreted. |
| 1550 | * |
| 1551 | * @param start - start of the ro.board.platform string to check. |
| 1552 | * @param end - end of the ro.board.platform string to check. |
| 1553 | * |
| 1554 | * @returns true if the string matches an nVidia Tegra signature, and false otherwise |
| 1555 | */ |
| 1556 | static bool is_tegra(const char* start, const char* end) { |
| 1557 | /* Expect 5 ("tegra") or 6 ("tegra3") symbols */ |
| 1558 | const size_t length = end - start; |
| 1559 | switch (length) { |
| 1560 | case 5: |
| 1561 | case 6: |
| 1562 | break; |
| 1563 | default: |
| 1564 | return false; |
| 1565 | } |
| 1566 | |
| 1567 | /* Check that the first 5 characters match "tegra" */ |
| 1568 | if (start[0] != 't') { |
| 1569 | return false; |
| 1570 | } |
| 1571 | const uint32_t expected_egra = load_u32le(start + 1); |
| 1572 | if (expected_egra != UINT32_C(0x61726765) /* "arge" = reverse("egra") */) { |
| 1573 | return false; |
| 1574 | } |
| 1575 | |
| 1576 | /* Check if the string is either "tegra" (length = 5) or "tegra3" (length != 5) and last character is '3' */ |
| 1577 | return (length == 5 || start[5] == '3'); |
| 1578 | } |
| 1579 | |
| 1580 | struct special_map_entry { |
| 1581 | const char* platform; |
| 1582 | uint16_t model; |
| 1583 | uint8_t series; |
| 1584 | char suffix; |
| 1585 | }; |
| 1586 | |
| 1587 | static const struct special_map_entry special_hardware_map_entries[] = { |
| 1588 | { |
| 1589 | /* "k3v2oem1" -> HiSilicon K3V2 */ |
| 1590 | .platform = "k3v2oem1", |
| 1591 | .series = cpuinfo_arm_chipset_series_hisilicon_k3v, |
| 1592 | .model = 2, |
| 1593 | }, |
| 1594 | { |
| 1595 | /* "hi6620oem" -> HiSilicon Kirin 910T */ |
| 1596 | .platform = "hi6620oem", |
| 1597 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 1598 | .model = 910, |
| 1599 | .suffix = 'T' |
| 1600 | }, |
| 1601 | { |
| 1602 | /* "hi6250" -> HiSilicon Kirin 650 */ |
| 1603 | .platform = "hi6250", |
| 1604 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 1605 | .model = 650, |
| 1606 | }, |
| 1607 | { |
| 1608 | /* "hi6210sft" -> HiSilicon Kirin 620 */ |
| 1609 | .platform = "hi6210sft", |
| 1610 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 1611 | .model = 620, |
| 1612 | }, |
| 1613 | { |
| 1614 | /* "hi3751" -> HiSilicon Hi3751 */ |
| 1615 | .platform = "hi3751", |
| 1616 | .series = cpuinfo_arm_chipset_series_hisilicon_hi, |
| 1617 | .model = 3751, |
| 1618 | }, |
| 1619 | { |
| 1620 | /* "hi3635" -> HiSilicon Kirin 930 */ |
| 1621 | .platform = "hi3635", |
| 1622 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 1623 | .model = 930, |
| 1624 | }, |
| 1625 | { |
| 1626 | /* "hi3630" -> HiSilicon Kirin 920 */ |
| 1627 | .platform = "hi3630", |
| 1628 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 1629 | .model = 920, |
| 1630 | }, |
| 1631 | { |
| 1632 | /* "gs705a" -> Actions ATM7059A */ |
| 1633 | .platform = "gs705a", |
| 1634 | .series = cpuinfo_arm_chipset_series_actions_atm, |
| 1635 | .model = 7059, |
| 1636 | .suffix = 'A', |
| 1637 | }, |
| 1638 | { |
| 1639 | /* "gs702a" -> Actions ATM7029 */ |
| 1640 | .platform = "gs702a", |
| 1641 | .series = cpuinfo_arm_chipset_series_actions_atm, |
| 1642 | .model = 7029, |
| 1643 | }, |
| 1644 | { |
| 1645 | /* "gs702c" -> Actions ATM7029B */ |
| 1646 | .platform = "gs702c", |
| 1647 | .series = cpuinfo_arm_chipset_series_actions_atm, |
| 1648 | .model = 7029, |
| 1649 | .suffix = 'B' |
| 1650 | }, |
| 1651 | { |
| 1652 | /* "Amlogic Meson8" -> Amlogic S812 */ |
| 1653 | .platform = "Amlogic Meson8", |
| 1654 | .series = cpuinfo_arm_chipset_series_amlogic_s, |
| 1655 | .model = 812, |
| 1656 | }, |
| 1657 | { |
| 1658 | /* "Amlogic Meson8B" -> Amlogic S805 */ |
| 1659 | .platform = "Amlogic Meson8B", |
| 1660 | .series = cpuinfo_arm_chipset_series_amlogic_s, |
| 1661 | .model = 805, |
| 1662 | }, |
| 1663 | { |
| 1664 | /* "mapphone_CDMA" -> Texas Instruments OMAP4430 */ |
| 1665 | .platform = "mapphone_CDMA", |
| 1666 | .series = cpuinfo_arm_chipset_series_texas_instruments_omap, |
| 1667 | .model = 4430, |
| 1668 | }, |
| 1669 | { |
| 1670 | /* "Tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 */ |
| 1671 | .platform = "Tuna", |
| 1672 | .series = cpuinfo_arm_chipset_series_texas_instruments_omap, |
| 1673 | .model = 4460, |
| 1674 | }, |
| 1675 | { |
| 1676 | /* "Manta" (Samsung Nexus 10) -> Samsung Exynos 5250 */ |
| 1677 | .platform = "Manta", |
| 1678 | .series = cpuinfo_arm_chipset_series_samsung_exynos, |
| 1679 | .model = 5250, |
| 1680 | }, |
| 1681 | { |
| 1682 | /* "Odin" -> LG Nuclun 7111 */ |
| 1683 | .platform = "Odin", |
| 1684 | .series = cpuinfo_arm_chipset_series_lg_nuclun, |
| 1685 | .model = 7111, |
| 1686 | }, |
| 1687 | { |
| 1688 | /* "Madison" -> MStar 6A338 */ |
| 1689 | .platform = "Madison", |
| 1690 | .series = cpuinfo_arm_chipset_series_mstar_6a, |
| 1691 | .model = 338, |
| 1692 | }, |
| 1693 | }; |
| 1694 | |
| 1695 | static const struct special_map_entry tegra_hardware_map_entries[] = { |
| 1696 | { |
| 1697 | /* "cardhu" (nVidia Cardhu developer tablet) -> Tegra T30 */ |
| 1698 | .platform = "cardhu", |
| 1699 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1700 | .model = 30, |
| 1701 | }, |
| 1702 | { |
| 1703 | /* "p3" (Samsung Galaxy Tab 8.9) -> Tegra T20 */ |
| 1704 | .platform = "p3", |
| 1705 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1706 | .model = 20, |
| 1707 | }, |
| 1708 | { |
| 1709 | /* "endeavoru" (HTC One X) -> Tegra AP33 */ |
| 1710 | .platform = "endeavoru", |
| 1711 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, |
| 1712 | .model = 33, |
| 1713 | }, |
| 1714 | { |
| 1715 | /* "evitareul" (HTC One X+) -> Tegra T33 */ |
| 1716 | .platform = "evitareul", |
| 1717 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1718 | .model = 33, |
| 1719 | }, |
| 1720 | { |
| 1721 | /* "enrc2b" (HTC One X+) -> Tegra T33 */ |
| 1722 | .platform = "enrc2b", |
| 1723 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1724 | .model = 33, |
| 1725 | }, |
| 1726 | { |
| 1727 | /* "mozart" (Asus Transformer Pad TF701T) -> Tegra T114 */ |
| 1728 | .platform = "mozart", |
| 1729 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1730 | .model = 114, |
| 1731 | }, |
| 1732 | { |
| 1733 | /* "tn8" (nVidia Shield Tablet K1) -> Tegra T124 */ |
| 1734 | .platform = "tn8", |
| 1735 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1736 | .model = 124, |
| 1737 | }, |
| 1738 | { |
| 1739 | /* "mocha" (Xiaomi Mi Pad) -> Tegra T124 */ |
| 1740 | .platform = "mocha", |
| 1741 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1742 | .model = 124, |
| 1743 | }, |
| 1744 | { |
| 1745 | /* "stingray" (Motorola XOOM) -> Tegra AP20H */ |
| 1746 | .platform = "stingray", |
| 1747 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, |
| 1748 | .model = 20, |
| 1749 | .suffix = 'H', |
| 1750 | }, |
| 1751 | { |
| 1752 | /* "Ceres" (Wiko Highway 4G) -> Tegra SL460N */ |
| 1753 | .platform = "Ceres", |
| 1754 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, |
| 1755 | .model = 460, |
| 1756 | .suffix = 'N', |
| 1757 | }, |
| 1758 | { |
| 1759 | /* "chagall" (Fujitsu Stylistic M532) -> Tegra T30 */ |
| 1760 | .platform = "chagall", |
| 1761 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1762 | .model = 30, |
| 1763 | }, |
| 1764 | { |
| 1765 | /* "ventana" (Asus Transformer TF101) -> Tegra T20 */ |
| 1766 | .platform = "ventana", |
| 1767 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1768 | .model = 20, |
| 1769 | }, |
| 1770 | { |
| 1771 | /* "bobsleigh" (Fujitsu Arrows Tab F-05E) -> Tegra T33 */ |
| 1772 | .platform = "bobsleigh", |
| 1773 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1774 | .model = 33, |
| 1775 | }, |
| 1776 | { |
| 1777 | /* "tegra_fjdev103" (Fujitsu Arrows V F-04E) -> Tegra T33 */ |
| 1778 | .platform = "tegra_fjdev103", |
| 1779 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1780 | .model = 33, |
| 1781 | }, |
| 1782 | { |
| 1783 | /* "nbx03" (Sony Tablet S) -> Tegra T20 */ |
| 1784 | .platform = "nbx03", |
| 1785 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1786 | .model = 20, |
| 1787 | }, |
| 1788 | { |
| 1789 | /* "txs03" (Sony Xperia Tablet S) -> Tegra T30L */ |
| 1790 | .platform = "txs03", |
| 1791 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1792 | .model = 30, |
| 1793 | .suffix = 'L', |
| 1794 | }, |
| 1795 | { |
| 1796 | /* "x3" (LG Optimus 4X HD P880) -> Tegra AP33 */ |
| 1797 | .platform = "x3", |
| 1798 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, |
| 1799 | .model = 33, |
| 1800 | }, |
| 1801 | { |
| 1802 | /* "BIRCH" (HP Slate 7 Plus) -> Tegra T30L */ |
| 1803 | .platform = "BIRCH", |
| 1804 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1805 | .model = 30, |
| 1806 | .suffix = 'L', |
| 1807 | }, |
| 1808 | { |
| 1809 | /* "macallan" (HP Slate 8 Pro) -> Tegra T114 */ |
| 1810 | .platform = "macallan", |
| 1811 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1812 | .model = 114, |
| 1813 | }, |
| 1814 | { |
| 1815 | /* "tostab12BL" (Toshiba AT10-A "Excite Pure") -> Tegra T30L */ |
| 1816 | .platform = "tostab12BL", |
| 1817 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1818 | .model = 30, |
| 1819 | .suffix = 'L', |
| 1820 | }, |
| 1821 | { |
| 1822 | /* "tostab12BA" (Toshiba AT10-LE-A "Excite Pro") -> Tegra T114 */ |
| 1823 | .platform = "tostab12BA", |
| 1824 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1825 | .model = 114, |
| 1826 | }, |
| 1827 | { |
| 1828 | /* "picasso" (Acer Iconia Tab A500) -> Tegra AP20H */ |
| 1829 | .platform = "picasso", |
| 1830 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, |
| 1831 | .model = 20, |
| 1832 | .suffix = 'H', |
| 1833 | }, |
| 1834 | { |
| 1835 | /* "picasso_e" (Acer Iconia Tab A200) -> Tegra AP20H */ |
| 1836 | .platform = "picasso_e", |
| 1837 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, |
| 1838 | .model = 20, |
| 1839 | .suffix = 'H', |
| 1840 | }, |
| 1841 | { |
| 1842 | /* "picasso_e2" (Acer Iconia Tab A210) -> Tegra T30L */ |
| 1843 | .platform = "picasso_e2", |
| 1844 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1845 | .model = 30, |
| 1846 | .suffix = 'L', |
| 1847 | }, |
| 1848 | { |
| 1849 | /* "picasso_m" (Acer Iconia Tab A510) -> Tegra T30 */ |
| 1850 | .platform = "picasso_m", |
| 1851 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1852 | .model = 30, |
| 1853 | }, |
| 1854 | { |
| 1855 | /* "picasso_mf" (Acer Iconia Tab A700) -> Tegra T30 */ |
| 1856 | .platform = "picasso_mf", |
| 1857 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1858 | .model = 30, |
| 1859 | }, |
| 1860 | { |
| 1861 | /* "avalon" (Toshiba AT300 "Excite 10") -> Tegra T30L */ |
| 1862 | .platform = "avalon", |
| 1863 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1864 | .model = 30, |
| 1865 | .suffix = 'L', |
| 1866 | }, |
| 1867 | { |
| 1868 | /* "NS_14T004" (iRiver NS-14T004) -> Tegra T30L */ |
| 1869 | .platform = "NS_14T004", |
| 1870 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 1871 | .model = 30, |
| 1872 | .suffix = 'L', |
| 1873 | }, |
| 1874 | }; |
| 1875 | |
| 1876 | /* |
| 1877 | * Decodes chipset name from /proc/cpuinfo Hardware string. |
| 1878 | * For some chipsets, the function relies frequency and on number of cores for chipset detection. |
| 1879 | * |
| 1880 | * @param[in] platform - /proc/cpuinfo Hardware string. |
| 1881 | * @param cores - number of cores in the chipset. |
| 1882 | * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu<number>/cpofreq/cpu_freq_max values. |
| 1883 | * |
| 1884 | * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor |
| 1885 | * and series identifiers. |
| 1886 | */ |
| 1887 | struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_proc_cpuinfo_hardware( |
| 1888 | const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], |
| 1889 | uint32_t cores, uint32_t max_cpu_freq_max, bool is_tegra) |
| 1890 | { |
| 1891 | struct cpuinfo_arm_chipset chipset; |
| 1892 | const size_t hardware_length = strnlen(hardware, CPUINFO_HARDWARE_VALUE_MAX); |
| 1893 | const char* hardware_end = hardware + hardware_length; |
| 1894 | |
| 1895 | if (is_tegra) { |
| 1896 | /* |
| 1897 | * nVidia Tegra-specific path: compare /proc/cpuinfo Hardware string to |
| 1898 | * tabulated Hardware values for popular chipsets/devices with Tegra chipsets. |
| 1899 | * This path is only used when ro.board.platform indicates a Tegra chipset |
| 1900 | * (albeit does not indicate which exactly Tegra chipset). |
| 1901 | */ |
| 1902 | for (size_t i = 0; i < CPUINFO_COUNT_OF(tegra_hardware_map_entries); i++) { |
| 1903 | if (strncmp(tegra_hardware_map_entries[i].platform, hardware, hardware_length) == 0 && |
| 1904 | tegra_hardware_map_entries[i].platform[hardware_length] == 0) |
| 1905 | { |
| 1906 | cpuinfo_log_debug( |
| 1907 | "found /proc/cpuinfo Hardware string \"%.*s\" in nVidia Tegra chipset table", |
| 1908 | (int) hardware_length, hardware); |
| 1909 | /* Create chipset name from entry */ |
| 1910 | return (struct cpuinfo_arm_chipset) { |
| 1911 | .vendor = chipset_series_vendor[tegra_hardware_map_entries[i].series], |
| 1912 | .series = (enum cpuinfo_arm_chipset_series) tegra_hardware_map_entries[i].series, |
| 1913 | .model = tegra_hardware_map_entries[i].model, |
| 1914 | .suffix = { |
| 1915 | [0] = tegra_hardware_map_entries[i].suffix, |
| 1916 | }, |
| 1917 | }; |
| 1918 | } |
| 1919 | } |
| 1920 | } else { |
| 1921 | /* Generic path: consider all other vendors */ |
| 1922 | |
| 1923 | bool word_start = true; |
| 1924 | for (const char* pos = hardware; pos != hardware_end; pos++) { |
| 1925 | const char c = *pos; |
| 1926 | switch (c) { |
| 1927 | case ' ': |
| 1928 | case '\t': |
| 1929 | case ',': |
| 1930 | word_start = true; |
| 1931 | break; |
| 1932 | default: |
| 1933 | if (word_start && is_ascii_alphabetic(c)) { |
| 1934 | /* Check Qualcomm MSM/APQ signature */ |
| 1935 | if (match_msm_apq(pos, hardware_end, &chipset)) { |
| 1936 | cpuinfo_log_debug( |
| 1937 | "matched Qualcomm MSM/APQ signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 1938 | (int) hardware_length, hardware); |
| 1939 | return chipset; |
| 1940 | } |
| 1941 | |
| 1942 | /* Check SDMxxx (Qualcomm Snapdragon) signature */ |
| 1943 | if (match_sdm(pos, hardware_end, &chipset)) { |
| 1944 | cpuinfo_log_debug( |
| 1945 | "matched Qualcomm SDM signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 1946 | (int) hardware_length, hardware); |
| 1947 | return chipset; |
| 1948 | } |
| 1949 | |
| 1950 | /* Check MediaTek MT signature */ |
| 1951 | if (match_mt(pos, hardware_end, true, &chipset)) { |
| 1952 | cpuinfo_log_debug( |
| 1953 | "matched MediaTek MT signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 1954 | (int) hardware_length, hardware); |
| 1955 | return chipset; |
| 1956 | } |
| 1957 | |
| 1958 | /* Check HiSilicon Kirin signature */ |
| 1959 | if (match_kirin(pos, hardware_end, &chipset)) { |
| 1960 | cpuinfo_log_debug( |
| 1961 | "matched HiSilicon Kirin signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 1962 | (int) hardware_length, hardware); |
| 1963 | return chipset; |
| 1964 | } |
| 1965 | |
| 1966 | /* Check Rockchip RK signature */ |
| 1967 | if (match_rk(pos, hardware_end, &chipset)) { |
| 1968 | cpuinfo_log_debug( |
| 1969 | "matched Rockchip RK signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 1970 | (int) hardware_length, hardware); |
| 1971 | return chipset; |
| 1972 | } |
| 1973 | } |
| 1974 | word_start = false; |
| 1975 | break; |
| 1976 | } |
| 1977 | } |
| 1978 | |
| 1979 | /* Check Samsung Exynos signature */ |
| 1980 | if (match_samsung_exynos(hardware, hardware_end, &chipset)) { |
| 1981 | cpuinfo_log_debug( |
| 1982 | "matched Samsung Exynos signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 1983 | (int) hardware_length, hardware); |
| 1984 | return chipset; |
| 1985 | } |
| 1986 | |
| 1987 | /* Check universalXXXX (Samsung Exynos) signature */ |
| 1988 | if (match_universal(hardware, hardware_end, &chipset)) { |
| 1989 | cpuinfo_log_debug( |
| 1990 | "matched UNIVERSAL (Samsung Exynos) signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 1991 | (int) hardware_length, hardware); |
| 1992 | return chipset; |
| 1993 | } |
| 1994 | |
| 1995 | /* Match /SMDK(4410|4x12)$/ */ |
| 1996 | if (match_and_parse_smdk(hardware, hardware_end, cores, &chipset)) { |
| 1997 | cpuinfo_log_debug( |
| 1998 | "matched SMDK (Samsung Exynos) signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 1999 | (int) hardware_length, hardware); |
| 2000 | return chipset; |
| 2001 | } |
| 2002 | |
| 2003 | /* Check Spreadtrum SC signature */ |
| 2004 | if (match_sc(hardware, hardware_end, &chipset)) { |
| 2005 | cpuinfo_log_debug( |
| 2006 | "matched Spreadtrum SC signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 2007 | (int) hardware_length, hardware); |
| 2008 | return chipset; |
| 2009 | } |
| 2010 | |
| 2011 | /* Check Marvell PXA signature */ |
| 2012 | if (match_pxa(hardware, hardware_end, &chipset)) { |
| 2013 | cpuinfo_log_debug( |
| 2014 | "matched Marvell PXA signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 2015 | (int) hardware_length, hardware); |
| 2016 | return chipset; |
| 2017 | } |
| 2018 | |
| 2019 | /* Match /sun\d+i/ signature and map to Allwinner chipset name */ |
| 2020 | if (match_and_parse_sunxi(hardware, hardware_end, cores, &chipset)) { |
| 2021 | cpuinfo_log_debug( |
| 2022 | "matched sunxi (Allwinner Ax) signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 2023 | (int) hardware_length, hardware); |
| 2024 | return chipset; |
| 2025 | } |
| 2026 | |
| 2027 | /* Check Texas Instruments OMAP signature */ |
| 2028 | if (match_omap(hardware, hardware_end, &chipset)) { |
| 2029 | cpuinfo_log_debug( |
| 2030 | "matched Texas Instruments OMAP signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 2031 | (int) hardware_length, hardware); |
| 2032 | return chipset; |
| 2033 | } |
| 2034 | |
| 2035 | /* Check WonderMedia WMT signature and decode chipset from frequency and number of cores */ |
| 2036 | if (match_and_parse_wmt(hardware, hardware_end, cores, max_cpu_freq_max, &chipset)) { |
| 2037 | cpuinfo_log_debug( |
| 2038 | "matched WonderMedia WMT signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 2039 | (int) hardware_length, hardware); |
| 2040 | return chipset; |
| 2041 | } |
| 2042 | |
| 2043 | /* Check Telechips TCC signature */ |
| 2044 | if (match_tcc(hardware, hardware_end, &chipset)) { |
| 2045 | cpuinfo_log_debug( |
| 2046 | "matched Telechips TCC signature in /proc/cpuinfo Hardware string \"%.*s\"", |
| 2047 | (int) hardware_length, hardware); |
| 2048 | return chipset; |
| 2049 | } |
| 2050 | |
| 2051 | /* Compare to tabulated Hardware values for popular chipsets/devices which can't be otherwise detected */ |
| 2052 | for (size_t i = 0; i < CPUINFO_COUNT_OF(special_hardware_map_entries); i++) { |
| 2053 | if (strncmp(special_hardware_map_entries[i].platform, hardware, hardware_length) == 0 && |
| 2054 | special_hardware_map_entries[i].platform[hardware_length] == 0) |
| 2055 | { |
| 2056 | cpuinfo_log_debug( |
| 2057 | "found /proc/cpuinfo Hardware string \"%.*s\" in special chipset table", |
| 2058 | (int) hardware_length, hardware); |
| 2059 | /* Create chipset name from entry */ |
| 2060 | return (struct cpuinfo_arm_chipset) { |
| 2061 | .vendor = chipset_series_vendor[special_hardware_map_entries[i].series], |
| 2062 | .series = (enum cpuinfo_arm_chipset_series) special_hardware_map_entries[i].series, |
| 2063 | .model = special_hardware_map_entries[i].model, |
| 2064 | .suffix = { |
| 2065 | [0] = special_hardware_map_entries[i].suffix, |
| 2066 | }, |
| 2067 | }; |
| 2068 | } |
| 2069 | } |
| 2070 | } |
| 2071 | |
| 2072 | return (struct cpuinfo_arm_chipset) { |
| 2073 | .vendor = cpuinfo_arm_chipset_vendor_unknown, |
| 2074 | .series = cpuinfo_arm_chipset_series_unknown, |
| 2075 | }; |
| 2076 | } |
| 2077 | |
| 2078 | static const struct special_map_entry special_board_map_entries[] = { |
| 2079 | { |
| 2080 | /* "hi6250" -> HiSilicon Kirin 650 */ |
| 2081 | .platform = "hi6250", |
| 2082 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2083 | .model = 650, |
| 2084 | }, |
| 2085 | { |
| 2086 | /* "hi6210sft" -> HiSilicon Kirin 620 */ |
| 2087 | .platform = "hi6210sft", |
| 2088 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2089 | .model = 620, |
| 2090 | }, |
| 2091 | { |
| 2092 | /* "hi3650" -> HiSilicon Kirin 950 */ |
| 2093 | .platform = "hi3650", |
| 2094 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2095 | .model = 950, |
| 2096 | }, |
| 2097 | { |
| 2098 | /* "hi3635" -> HiSilicon Kirin 930 */ |
| 2099 | .platform = "hi3635", |
| 2100 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2101 | .model = 930, |
| 2102 | }, |
| 2103 | { |
| 2104 | /* "hi3630" -> HiSilicon Kirin 920 */ |
| 2105 | .platform = "hi3630", |
| 2106 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2107 | .model = 920, |
| 2108 | }, |
| 2109 | { |
| 2110 | /* "mp523x" -> Renesas MP5232 */ |
| 2111 | .platform = "mp523x", |
| 2112 | .series = cpuinfo_arm_chipset_series_renesas_mp, |
| 2113 | .model = 5232, |
| 2114 | }, |
| 2115 | { |
| 2116 | /* "piranha" -> Texas Instruments OMAP4430 */ |
| 2117 | .platform = "piranha", |
| 2118 | .series = cpuinfo_arm_chipset_series_texas_instruments_omap, |
| 2119 | .model = 4430, |
| 2120 | }, |
| 2121 | { |
| 2122 | /* "BEETHOVEN" (Huawei MadiaPad M3) -> HiSilicon Kirin 950 */ |
| 2123 | .platform = "BEETHOVEN", |
| 2124 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2125 | .model = 950, |
| 2126 | }, |
| 2127 | { |
| 2128 | /* "hws7701u" (Huawei MediaPad 7 Youth) -> Rockchip RK3168 */ |
| 2129 | .platform = "hws7701u", |
| 2130 | .series = cpuinfo_arm_chipset_series_rockchip_rk, |
| 2131 | .model = 3168, |
| 2132 | }, |
| 2133 | { |
| 2134 | /* "g2mv" (LG G2 mini LTE) -> nVidia Tegra SL460N */ |
| 2135 | .platform = "g2mv", |
| 2136 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, |
| 2137 | .model = 460, |
| 2138 | .suffix = 'N', |
| 2139 | }, |
| 2140 | { |
| 2141 | /* "K00F" (Asus MeMO Pad 10) -> Rockchip RK3188 */ |
| 2142 | .platform = "K00F", |
| 2143 | .series = cpuinfo_arm_chipset_series_rockchip_rk, |
| 2144 | .model = 3188, |
| 2145 | }, |
| 2146 | { |
| 2147 | /* "T7H" (HP Slate 7) -> Rockchip RK3066 */ |
| 2148 | .platform = "T7H", |
| 2149 | .series = cpuinfo_arm_chipset_series_rockchip_rk, |
| 2150 | .model = 3066, |
| 2151 | }, |
| 2152 | { |
| 2153 | /* "tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 */ |
| 2154 | .platform = "tuna", |
| 2155 | .series = cpuinfo_arm_chipset_series_texas_instruments_omap, |
| 2156 | .model = 4460, |
| 2157 | }, |
| 2158 | { |
| 2159 | /* "grouper" (Asus Nexus 7 2012) -> nVidia Tegra T30L */ |
| 2160 | .platform = "grouper", |
| 2161 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 2162 | .model = 30, |
| 2163 | .suffix = 'L', |
| 2164 | }, |
| 2165 | { |
| 2166 | /* "flounder" (HTC Nexus 9) -> nVidia Tegra T132 */ |
| 2167 | .platform = "flounder", |
| 2168 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 2169 | .model = 132, |
| 2170 | }, |
| 2171 | { |
| 2172 | /* "dragon" (Google Pixel C) -> nVidia Tegra T210 */ |
| 2173 | .platform = "dragon", |
| 2174 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 2175 | .model = 210, |
| 2176 | }, |
| 2177 | { |
| 2178 | /* "sailfish" (Google Pixel) -> Qualcomm MSM8996PRO */ |
| 2179 | .platform = "sailfish", |
| 2180 | .series = cpuinfo_arm_chipset_series_qualcomm_msm, |
| 2181 | .model = 8996, |
| 2182 | .suffix = 'P', |
| 2183 | }, |
| 2184 | { |
| 2185 | /* "marlin" (Google Pixel XL) -> Qualcomm MSM8996PRO */ |
| 2186 | .platform = "marlin", |
| 2187 | .series = cpuinfo_arm_chipset_series_qualcomm_msm, |
| 2188 | .model = 8996, |
| 2189 | .suffix = 'P', |
| 2190 | }, |
| 2191 | }; |
| 2192 | |
| 2193 | /* |
| 2194 | * Decodes chipset name from ro.product.board Android system property. |
| 2195 | * For some chipsets, the function relies frequency and on number of cores for chipset detection. |
| 2196 | * |
| 2197 | * @param[in] platform - ro.product.board value. |
| 2198 | * @param cores - number of cores in the chipset. |
| 2199 | * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu<number>/cpofreq/cpu_freq_max values. |
| 2200 | * |
| 2201 | * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor |
| 2202 | * and series identifiers. |
| 2203 | */ |
| 2204 | struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_board( |
| 2205 | const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], |
| 2206 | uint32_t cores, uint32_t max_cpu_freq_max) |
| 2207 | { |
| 2208 | struct cpuinfo_arm_chipset chipset; |
| 2209 | const char* board = ro_product_board; |
| 2210 | const size_t board_length = strnlen(ro_product_board, CPUINFO_BUILD_PROP_VALUE_MAX); |
| 2211 | const char* board_end = ro_product_board + board_length; |
| 2212 | |
| 2213 | /* Check Qualcomm MSM/APQ signature */ |
| 2214 | if (match_msm_apq(board, board_end, &chipset)) { |
| 2215 | cpuinfo_log_debug( |
| 2216 | "matched Qualcomm MSM/APQ signature in ro.product.board string \"%.*s\"", (int) board_length, board); |
| 2217 | return chipset; |
| 2218 | } |
| 2219 | |
| 2220 | /* Check universaXXXX (Samsung Exynos) signature */ |
| 2221 | if (match_universal(board, board_end, &chipset)) { |
| 2222 | cpuinfo_log_debug( |
| 2223 | "matched UNIVERSAL (Samsung Exynos) signature in ro.product.board string \"%.*s\"", |
| 2224 | (int) board_length, board); |
| 2225 | return chipset; |
| 2226 | } |
| 2227 | |
| 2228 | /* Check SMDK (Samsung Exynos) signature */ |
| 2229 | if (match_and_parse_smdk(board, board_end, cores, &chipset)) { |
| 2230 | cpuinfo_log_debug( |
| 2231 | "matched SMDK (Samsung Exynos) signature in ro.product.board string \"%.*s\"", |
| 2232 | (int) board_length, board); |
| 2233 | return chipset; |
| 2234 | } |
| 2235 | |
| 2236 | /* Check MediaTek MT signature */ |
| 2237 | if (match_mt(board, board_end, true, &chipset)) { |
| 2238 | cpuinfo_log_debug( |
| 2239 | "matched MediaTek MT signature in ro.product.board string \"%.*s\"", |
| 2240 | (int) board_length, board); |
| 2241 | return chipset; |
| 2242 | } |
| 2243 | |
| 2244 | /* Check Spreadtrum SC signature */ |
| 2245 | if (match_sc(board, board_end, &chipset)) { |
| 2246 | cpuinfo_log_debug( |
| 2247 | "matched Spreadtrum SC signature in ro.product.board string \"%.*s\"", |
| 2248 | (int) board_length, board); |
| 2249 | return chipset; |
| 2250 | } |
| 2251 | |
| 2252 | /* Check Marvell PXA signature */ |
| 2253 | if (match_pxa(board, board_end, &chipset)) { |
| 2254 | cpuinfo_log_debug( |
| 2255 | "matched Marvell PXA signature in ro.product.board string \"%.*s\"", |
| 2256 | (int) board_length, board); |
| 2257 | return chipset; |
| 2258 | } |
| 2259 | |
| 2260 | /* Check Leadcore LCxxxx signature */ |
| 2261 | if (match_lc(board, board_end, &chipset)) { |
| 2262 | cpuinfo_log_debug( |
| 2263 | "matched Leadcore LC signature in ro.product.board string \"%.*s\"", |
| 2264 | (int) board_length, board); |
| 2265 | return chipset; |
| 2266 | } |
| 2267 | |
| 2268 | /* |
| 2269 | * Compare to tabulated ro.product.board values for Broadcom chipsets and decode chipset from frequency and |
| 2270 | * number of cores. |
| 2271 | */ |
| 2272 | if (match_and_parse_broadcom(board, board_end, cores, max_cpu_freq_max, &chipset)) { |
| 2273 | cpuinfo_log_debug( |
| 2274 | "found ro.product.board string \"%.*s\" in Broadcom chipset table", |
| 2275 | (int) board_length, board); |
| 2276 | return chipset; |
| 2277 | } |
| 2278 | |
| 2279 | /* Compare to tabulated ro.product.board values for Huawei devices which don't report chipset elsewhere */ |
| 2280 | if (match_and_parse_huawei(board, board_end, &chipset)) { |
| 2281 | cpuinfo_log_debug( |
| 2282 | "found ro.product.board string \"%.*s\" in Huawei chipset table", |
| 2283 | (int) board_length, board); |
| 2284 | return chipset; |
| 2285 | } |
| 2286 | |
| 2287 | /* Compare to tabulated ro.product.board values for popular chipsets/devices which can't be otherwise detected */ |
| 2288 | for (size_t i = 0; i < CPUINFO_COUNT_OF(special_board_map_entries); i++) { |
| 2289 | if (strncmp(special_board_map_entries[i].platform, board, board_length) == 0 && |
| 2290 | special_board_map_entries[i].platform[board_length] == 0) |
| 2291 | { |
| 2292 | cpuinfo_log_debug( |
| 2293 | "found ro.product.board string \"%.*s\" in special chipset table", |
| 2294 | (int) board_length, board); |
| 2295 | /* Create chipset name from entry */ |
| 2296 | return (struct cpuinfo_arm_chipset) { |
| 2297 | .vendor = chipset_series_vendor[special_board_map_entries[i].series], |
| 2298 | .series = (enum cpuinfo_arm_chipset_series) special_board_map_entries[i].series, |
| 2299 | .model = special_board_map_entries[i].model, |
| 2300 | .suffix = { |
| 2301 | [0] = special_board_map_entries[i].suffix, |
| 2302 | /* The suffix of MSM8996PRO is truncated at the first letter, reconstruct it here. */ |
| 2303 | [1] = special_board_map_entries[i].suffix == 'P' ? 'R' : 0, |
| 2304 | [2] = special_board_map_entries[i].suffix == 'P' ? 'O' : 0, |
| 2305 | }, |
| 2306 | }; |
| 2307 | } |
| 2308 | } |
| 2309 | |
| 2310 | return (struct cpuinfo_arm_chipset) { |
| 2311 | .vendor = cpuinfo_arm_chipset_vendor_unknown, |
| 2312 | .series = cpuinfo_arm_chipset_series_unknown, |
| 2313 | }; |
| 2314 | } |
| 2315 | |
| 2316 | struct amlogic_map_entry { |
| 2317 | char ro_board_platform[6]; |
| 2318 | uint16_t model; |
| 2319 | uint8_t series; |
| 2320 | char suffix[3]; |
| 2321 | }; |
| 2322 | |
| 2323 | static const struct amlogic_map_entry amlogic_map_entries[] = { |
| 2324 | { |
| 2325 | /* "meson3" -> Amlogic AML8726-M */ |
| 2326 | .ro_board_platform = "meson3", |
| 2327 | .series = cpuinfo_arm_chipset_series_amlogic_aml, |
| 2328 | .model = 8726, |
| 2329 | .suffix = "-M", |
| 2330 | }, |
| 2331 | { |
| 2332 | /* "meson6" -> Amlogic AML8726-MX */ |
| 2333 | .ro_board_platform = "meson6", |
| 2334 | .series = cpuinfo_arm_chipset_series_amlogic_aml, |
| 2335 | .model = 8726, |
| 2336 | .suffix = "-MX", |
| 2337 | }, |
| 2338 | { |
| 2339 | /* "meson8" -> Amlogic S805 */ |
| 2340 | .ro_board_platform = "meson8", |
| 2341 | .series = cpuinfo_arm_chipset_series_amlogic_s, |
| 2342 | .model = 805, |
| 2343 | }, |
| 2344 | { |
| 2345 | /* "gxbaby" -> Amlogic S905 */ |
| 2346 | .ro_board_platform = "gxbaby", |
| 2347 | .series = cpuinfo_arm_chipset_series_amlogic_s, |
| 2348 | .model = 905, |
| 2349 | }, |
| 2350 | { |
| 2351 | /* "gxl" -> Amlogic S905X */ |
| 2352 | .ro_board_platform = "gxl", |
| 2353 | .series = cpuinfo_arm_chipset_series_amlogic_s, |
| 2354 | .model = 905, |
| 2355 | .suffix = "X", |
| 2356 | }, |
| 2357 | { |
| 2358 | /* "gxm" -> Amlogic S912 */ |
| 2359 | .ro_board_platform = "gxm", |
| 2360 | .series = cpuinfo_arm_chipset_series_amlogic_s, |
| 2361 | .model = 912, |
| 2362 | }, |
| 2363 | }; |
| 2364 | |
| 2365 | static const struct special_map_entry special_platform_map_entries[] = { |
| 2366 | { |
| 2367 | /* "hi6620oem" -> HiSilicon Kirin 910T */ |
| 2368 | .platform = "hi6620oem", |
| 2369 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2370 | .model = 910, |
| 2371 | .suffix = 'T', |
| 2372 | }, |
| 2373 | { |
| 2374 | /* "hi6250" -> HiSilicon Kirin 650 */ |
| 2375 | .platform = "hi6250", |
| 2376 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2377 | .model = 650, |
| 2378 | }, |
| 2379 | { |
| 2380 | /* "hi6210sft" -> HiSilicon Kirin 620 */ |
| 2381 | .platform = "hi6210sft", |
| 2382 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2383 | .model = 620, |
| 2384 | }, |
| 2385 | { |
| 2386 | /* "hi3650" -> HiSilicon Kirin 950 */ |
| 2387 | .platform = "hi3650", |
| 2388 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2389 | .model = 950, |
| 2390 | }, |
| 2391 | { |
| 2392 | /* "hi3635" -> HiSilicon Kirin 930 */ |
| 2393 | .platform = "hi3635", |
| 2394 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2395 | .model = 930, |
| 2396 | }, |
| 2397 | { |
| 2398 | /* "hi3630" -> HiSilicon Kirin 920 */ |
| 2399 | .platform = "hi3630", |
| 2400 | .series = cpuinfo_arm_chipset_series_hisilicon_kirin, |
| 2401 | .model = 920, |
| 2402 | }, |
| 2403 | { |
| 2404 | /* "k3v2oem1" -> HiSilicon K3V2 */ |
| 2405 | .platform = "k3v2oem1", |
| 2406 | .series = cpuinfo_arm_chipset_series_hisilicon_k3v, |
| 2407 | .model = 2, |
| 2408 | }, |
| 2409 | { |
| 2410 | /* "k3v200" -> HiSilicon K3V2 */ |
| 2411 | .platform = "k3v200", |
| 2412 | .series = cpuinfo_arm_chipset_series_hisilicon_k3v, |
| 2413 | .model = 2, |
| 2414 | }, |
| 2415 | { |
| 2416 | /* "montblanc" -> NovaThor U8500 */ |
| 2417 | .platform = "montblanc", |
| 2418 | .series = cpuinfo_arm_chipset_series_novathor_u, |
| 2419 | .model = 8500, |
| 2420 | }, |
| 2421 | { |
| 2422 | /* "song" -> Pinecone Surge S1 */ |
| 2423 | .platform = "song", |
| 2424 | .series = cpuinfo_arm_chipset_series_pinecone_surge_s, |
| 2425 | .model = 1, |
| 2426 | }, |
| 2427 | { |
| 2428 | /* "tegra132" -> nVidia Tegra T132 */ |
| 2429 | .platform = "tegra132", |
| 2430 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 2431 | .model = 132, |
| 2432 | }, |
| 2433 | { |
| 2434 | /* "tegra210_dragon" -> nVidia Tegra T210 */ |
| 2435 | .platform = "tegra210_dragon", |
| 2436 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 2437 | .model = 210, |
| 2438 | }, |
| 2439 | { |
| 2440 | /* "tegra4" -> nVidia Tegra T114 */ |
| 2441 | .platform = "tegra4", |
| 2442 | .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, |
| 2443 | .model = 114, |
| 2444 | }, |
| 2445 | { |
| 2446 | /* "s5pc100" -> Samsung Exynos 3110 */ |
| 2447 | .platform = "s5pc100", |
| 2448 | .series = cpuinfo_arm_chipset_series_samsung_exynos, |
| 2449 | .model = 3110, |
| 2450 | }, |
| 2451 | }; |
| 2452 | |
| 2453 | /* |
| 2454 | * Decodes chipset name from ro.board.platform Android system property. |
| 2455 | * For some chipsets, the function relies frequency and on number of cores for chipset detection. |
| 2456 | * |
| 2457 | * @param[in] platform - ro.board.platform value. |
| 2458 | * @param cores - number of cores in the chipset. |
| 2459 | * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu<number>/cpofreq/cpu_freq_max values. |
| 2460 | * |
| 2461 | * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor |
| 2462 | * and series identifiers. |
| 2463 | */ |
| 2464 | struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_board_platform( |
| 2465 | const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], |
| 2466 | uint32_t cores, uint32_t max_cpu_freq_max) |
| 2467 | { |
| 2468 | struct cpuinfo_arm_chipset chipset; |
| 2469 | const size_t platform_length = strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); |
| 2470 | const char* platform_end = platform + platform_length; |
| 2471 | |
| 2472 | /* Check Qualcomm MSM/APQ signature */ |
| 2473 | if (match_msm_apq(platform, platform_end, &chipset)) { |
| 2474 | cpuinfo_log_debug( |
| 2475 | "matched Qualcomm MSM/APQ signature in ro.board.platform string \"%.*s\"", |
| 2476 | (int) platform_length, platform); |
| 2477 | return chipset; |
| 2478 | } |
| 2479 | |
| 2480 | /* Check exynosXXXX (Samsung Exynos) signature */ |
| 2481 | if (match_exynos(platform, platform_end, &chipset)) { |
| 2482 | cpuinfo_log_debug( |
| 2483 | "matched exynosXXXX (Samsung Exynos) signature in ro.board.platform string \"%.*s\"", |
| 2484 | (int) platform_length, platform); |
| 2485 | return chipset; |
| 2486 | } |
| 2487 | |
| 2488 | /* Check MediaTek MT signature */ |
| 2489 | if (match_mt(platform, platform_end, true, &chipset)) { |
| 2490 | cpuinfo_log_debug( |
| 2491 | "matched MediaTek MT signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); |
| 2492 | return chipset; |
| 2493 | } |
| 2494 | |
| 2495 | /* Check Spreadtrum SC signature */ |
| 2496 | if (match_sc(platform, platform_end, &chipset)) { |
| 2497 | cpuinfo_log_debug( |
| 2498 | "matched Spreadtrum SC signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); |
| 2499 | return chipset; |
| 2500 | } |
| 2501 | |
| 2502 | /* Check Rockchip RK signature */ |
| 2503 | if (match_rk(platform, platform_end, &chipset)) { |
| 2504 | cpuinfo_log_debug( |
| 2505 | "matched Rockchip RK signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); |
| 2506 | return chipset; |
| 2507 | } |
| 2508 | |
| 2509 | /* Check Leadcore LCxxxx signature */ |
| 2510 | if (match_lc(platform, platform_end, &chipset)) { |
| 2511 | cpuinfo_log_debug( |
| 2512 | "matched Leadcore LC signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); |
| 2513 | return chipset; |
| 2514 | } |
| 2515 | |
| 2516 | /* Compare to tabulated ro.board.platform values for Huawei devices which don't report chipset elsewhere */ |
| 2517 | if (match_and_parse_huawei(platform, platform_end, &chipset)) { |
| 2518 | cpuinfo_log_debug( |
| 2519 | "found ro.board.platform string \"%.*s\" in Huawei chipset table", |
| 2520 | (int) platform_length, platform); |
| 2521 | return chipset; |
| 2522 | } |
| 2523 | |
| 2524 | /* |
| 2525 | * Compare to known ro.board.platform values for Broadcom devices and |
| 2526 | * detect chipset from frequency and number of cores |
| 2527 | */ |
| 2528 | if (match_and_parse_broadcom(platform, platform_end, cores, max_cpu_freq_max, &chipset)) { |
| 2529 | cpuinfo_log_debug( |
| 2530 | "found ro.board.platform string \"%.*s\" in Broadcom chipset table", |
| 2531 | (int) platform_length, platform); |
| 2532 | return chipset; |
| 2533 | } |
| 2534 | |
| 2535 | /* |
| 2536 | * Compare to ro.board.platform value ("omap4") for OMAP4xxx chipsets. |
| 2537 | * Upon successful match, detect OMAP4430 from frequency and number of cores. |
| 2538 | */ |
| 2539 | if (platform_length == 5 && cores == 2 && max_cpu_freq_max == 1008000 && memcmp(platform, "omap4", 5) == 0) { |
| 2540 | cpuinfo_log_debug( |
| 2541 | "matched Texas Instruments OMAP4 signature in ro.board.platform string \"%.*s\"", |
| 2542 | (int) platform_length, platform); |
| 2543 | |
| 2544 | return (struct cpuinfo_arm_chipset) { |
| 2545 | .vendor = cpuinfo_arm_chipset_vendor_texas_instruments, |
| 2546 | .series = cpuinfo_arm_chipset_series_texas_instruments_omap, |
| 2547 | .model = 4430, |
| 2548 | }; |
| 2549 | } |
| 2550 | |
| 2551 | /* |
| 2552 | * Compare to tabulated ro.board.platform values for Amlogic chipsets/devices which can't be otherwise detected. |
| 2553 | * The tabulated Amlogic ro.board.platform values have not more than 6 characters. |
| 2554 | */ |
| 2555 | if (platform_length <= 6) { |
| 2556 | for (size_t i = 0; i < CPUINFO_COUNT_OF(amlogic_map_entries); i++) { |
| 2557 | if (strncmp(amlogic_map_entries[i].ro_board_platform, platform, 6) == 0) { |
| 2558 | cpuinfo_log_debug( |
| 2559 | "found ro.board.platform string \"%.*s\" in Amlogic chipset table", |
| 2560 | (int) platform_length, platform); |
| 2561 | /* Create chipset name from entry */ |
| 2562 | return (struct cpuinfo_arm_chipset) { |
| 2563 | .vendor = cpuinfo_arm_chipset_vendor_amlogic, |
| 2564 | .series = (enum cpuinfo_arm_chipset_series) amlogic_map_entries[i].series, |
| 2565 | .model = amlogic_map_entries[i].model, |
| 2566 | .suffix = { |
| 2567 | [0] = amlogic_map_entries[i].suffix[0], |
| 2568 | [1] = amlogic_map_entries[i].suffix[1], |
| 2569 | [2] = amlogic_map_entries[i].suffix[2], |
| 2570 | }, |
| 2571 | }; |
| 2572 | } |
| 2573 | } |
| 2574 | } |
| 2575 | |
| 2576 | /* Compare to tabulated ro.board.platform values for popular chipsets/devices which can't be otherwise detected */ |
| 2577 | for (size_t i = 0; i < CPUINFO_COUNT_OF(special_platform_map_entries); i++) { |
| 2578 | if (strncmp(special_platform_map_entries[i].platform, platform, platform_length) == 0 && |
| 2579 | special_platform_map_entries[i].platform[platform_length] == 0) |
| 2580 | { |
| 2581 | /* Create chipset name from entry */ |
| 2582 | cpuinfo_log_debug( |
| 2583 | "found ro.board.platform string \"%.*s\" in special chipset table", (int) platform_length, platform); |
| 2584 | return (struct cpuinfo_arm_chipset) { |
| 2585 | .vendor = chipset_series_vendor[special_platform_map_entries[i].series], |
| 2586 | .series = (enum cpuinfo_arm_chipset_series) special_platform_map_entries[i].series, |
| 2587 | .model = special_platform_map_entries[i].model, |
| 2588 | .suffix = { |
| 2589 | [0] = special_platform_map_entries[i].suffix, |
| 2590 | }, |
| 2591 | }; |
| 2592 | } |
| 2593 | } |
| 2594 | |
| 2595 | /* None of the ro.board.platform signatures matched, indicate unknown chipset */ |
| 2596 | return (struct cpuinfo_arm_chipset) { |
| 2597 | .vendor = cpuinfo_arm_chipset_vendor_unknown, |
| 2598 | .series = cpuinfo_arm_chipset_series_unknown, |
| 2599 | }; |
| 2600 | } |
| 2601 | |
| 2602 | /* |
| 2603 | * Decodes chipset name from ro.mediatek.platform Android system property. |
| 2604 | * |
| 2605 | * @param[in] platform - ro.mediatek.platform value. |
| 2606 | * |
| 2607 | * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor |
| 2608 | * and series identifiers. |
| 2609 | */ |
| 2610 | struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( |
| 2611 | const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) |
| 2612 | { |
| 2613 | struct cpuinfo_arm_chipset chipset; |
| 2614 | const char* platform_end = platform + strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX);; |
| 2615 | |
| 2616 | /* Check MediaTek MT signature */ |
| 2617 | if (match_mt(platform, platform_end, false, &chipset)) { |
| 2618 | return chipset; |
| 2619 | } |
| 2620 | |
| 2621 | return (struct cpuinfo_arm_chipset) { |
| 2622 | .vendor = cpuinfo_arm_chipset_vendor_unknown, |
| 2623 | .series = cpuinfo_arm_chipset_series_unknown, |
| 2624 | }; |
| 2625 | } |
| 2626 | |
| 2627 | /* |
| 2628 | * Decodes chipset name from ro.chipname Android system property. |
| 2629 | * |
| 2630 | * @param[in] chipname - ro.chipname value. |
| 2631 | * |
| 2632 | * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor |
| 2633 | * and series identifiers. |
| 2634 | */ |
| 2635 | struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_chipname( |
| 2636 | const char chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) |
| 2637 | { |
| 2638 | struct cpuinfo_arm_chipset chipset; |
| 2639 | const size_t chipname_length = strnlen(chipname, CPUINFO_BUILD_PROP_VALUE_MAX); |
| 2640 | const char* chipname_end = chipname + chipname_length; |
| 2641 | |
| 2642 | /* Check Qualcomm MSM/APQ signatures */ |
| 2643 | if (match_msm_apq(chipname, chipname_end, &chipset)) { |
| 2644 | cpuinfo_log_debug( |
| 2645 | "matched Qualcomm MSM/APQ signature in ro.chipname string \"%.*s\"", |
| 2646 | (int) chipname_length, chipname); |
| 2647 | return chipset; |
| 2648 | } |
| 2649 | |
| 2650 | /* Check exynosXXXX (Samsung Exynos) signature */ |
| 2651 | if (match_exynos(chipname, chipname_end, &chipset)) { |
| 2652 | cpuinfo_log_debug( |
| 2653 | "matched exynosXXXX (Samsung Exynos) signature in ro.chipname string \"%.*s\"", |
| 2654 | (int) chipname_length, chipname); |
| 2655 | return chipset; |
| 2656 | } |
| 2657 | |
| 2658 | /* Check universalXXXX (Samsung Exynos) signature */ |
| 2659 | if (match_universal(chipname, chipname_end, &chipset)) { |
| 2660 | cpuinfo_log_debug( |
| 2661 | "matched UNIVERSAL (Samsung Exynos) signature in ro.chipname Hardware string \"%.*s\"", |
| 2662 | (int) chipname_length, chipname); |
| 2663 | return chipset; |
| 2664 | } |
| 2665 | |
| 2666 | /* Check MediaTek MT signature */ |
| 2667 | if (match_mt(chipname, chipname_end, true, &chipset)) { |
| 2668 | cpuinfo_log_debug( |
| 2669 | "matched MediaTek MT signature in ro.chipname string \"%.*s\"", |
| 2670 | (int) chipname_length, chipname); |
| 2671 | return chipset; |
| 2672 | } |
| 2673 | |
| 2674 | /* Check Spreadtrum SC signature */ |
| 2675 | if (match_sc(chipname, chipname_end, &chipset)) { |
| 2676 | cpuinfo_log_debug( |
| 2677 | "matched Spreadtrum SC signature in ro.chipname string \"%.*s\"", |
| 2678 | (int) chipname_length, chipname); |
| 2679 | return chipset; |
| 2680 | } |
| 2681 | |
| 2682 | /* Check Marvell PXA signature */ |
| 2683 | if (match_pxa(chipname, chipname_end, &chipset)) { |
| 2684 | cpuinfo_log_debug( |
| 2685 | "matched Marvell PXA signature in ro.chipname string \"%.*s\"", |
| 2686 | (int) chipname_length, chipname); |
| 2687 | return chipset; |
| 2688 | } |
| 2689 | |
| 2690 | /* Compare to ro.chipname value ("mp523x") for Renesas MP5232 which can't be otherwise detected */ |
| 2691 | if (chipname_length == 6 && memcmp(chipname, "mp523x", 6) == 0) { |
| 2692 | cpuinfo_log_debug( |
| 2693 | "matched Renesas MP5232 signature in ro.chipname string \"%.*s\"", |
| 2694 | (int) chipname_length, chipname); |
| 2695 | |
| 2696 | return (struct cpuinfo_arm_chipset) { |
| 2697 | .vendor = cpuinfo_arm_chipset_vendor_renesas, |
| 2698 | .series = cpuinfo_arm_chipset_series_renesas_mp, |
| 2699 | .model = 5232, |
| 2700 | }; |
| 2701 | } |
| 2702 | |
| 2703 | return (struct cpuinfo_arm_chipset) { |
| 2704 | .vendor = cpuinfo_arm_chipset_vendor_unknown, |
| 2705 | .series = cpuinfo_arm_chipset_series_unknown, |
| 2706 | }; |
| 2707 | } |
| 2708 | |
| 2709 | /* |
| 2710 | * Fix common bugs, typos, and renames in chipset name. |
| 2711 | * |
| 2712 | * @param[in,out] chipset - chipset name to fix. |
| 2713 | * @param cores - number of cores in the chipset. |
| 2714 | * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu<number>/cpofreq/cpu_freq_max values. |
| 2715 | */ |
| 2716 | void cpuinfo_arm_fixup_chipset( |
| 2717 | struct cpuinfo_arm_chipset chipset[restrict static 1], uint32_t cores, uint32_t max_cpu_freq_max) |
| 2718 | { |
| 2719 | switch (chipset->series) { |
| 2720 | case cpuinfo_arm_chipset_series_qualcomm_msm: |
| 2721 | /* Check if there is suffix */ |
| 2722 | if (chipset->suffix[0] == 0) { |
| 2723 | /* No suffix, but the model may be misreported */ |
| 2724 | switch (chipset->model) { |
| 2725 | case 8216: |
| 2726 | /* MSM8216 was renamed to MSM8916 */ |
| 2727 | cpuinfo_log_info("reinterpreted MSM8216 chipset as MSM8916"); |
| 2728 | chipset->model = 8916; |
| 2729 | break; |
| 2730 | case 8916: |
| 2731 | /* Common bug: MSM8939 (Octa-core) reported as MSM8916 (Quad-core) */ |
| 2732 | switch (cores) { |
| 2733 | case 4: |
| 2734 | break; |
| 2735 | case 8: |
| 2736 | cpuinfo_log_info("reinterpreted MSM8916 chipset with 8 cores as MSM8939"); |
| 2737 | chipset->model = 8939; |
| 2738 | break; |
| 2739 | default: |
| 2740 | cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", |
| 2741 | cores, chipset->model); |
| 2742 | chipset->model = 0; |
| 2743 | } |
| 2744 | break; |
| 2745 | case 8937: |
| 2746 | /* Common bug: MSM8917 (Quad-core) reported as MSM8937 (Octa-core) */ |
| 2747 | switch (cores) { |
| 2748 | case 4: |
| 2749 | cpuinfo_log_info("reinterpreted MSM8937 chipset with 4 cores as MSM8917"); |
| 2750 | chipset->model = 8917; |
| 2751 | break; |
| 2752 | case 8: |
| 2753 | break; |
| 2754 | default: |
| 2755 | cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", |
| 2756 | cores, chipset->model); |
| 2757 | chipset->model = 0; |
| 2758 | } |
| 2759 | break; |
| 2760 | case 8960: |
| 2761 | /* Common bug: APQ8064 (Quad-core) reported as MSM8960 (Dual-core) */ |
| 2762 | switch (cores) { |
| 2763 | case 2: |
| 2764 | break; |
| 2765 | case 4: |
| 2766 | cpuinfo_log_info("reinterpreted MSM8960 chipset with 4 cores as APQ8064"); |
| 2767 | chipset->series = cpuinfo_arm_chipset_series_qualcomm_apq; |
| 2768 | chipset->model = 8064; |
| 2769 | break; |
| 2770 | default: |
| 2771 | cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", |
| 2772 | cores, chipset->model); |
| 2773 | chipset->model = 0; |
| 2774 | } |
| 2775 | break; |
| 2776 | case 8996: |
| 2777 | /* Common bug: MSM8994 (Octa-core) reported as MSM8996 (Quad-core) */ |
| 2778 | switch (cores) { |
| 2779 | case 4: |
| 2780 | break; |
| 2781 | case 8: |
| 2782 | cpuinfo_log_info("reinterpreted MSM8996 chipset with 8 cores as MSM8994"); |
| 2783 | chipset->model = 8994; |
| 2784 | break; |
| 2785 | default: |
| 2786 | cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", |
| 2787 | cores, chipset->model); |
| 2788 | chipset->model = 0; |
| 2789 | } |
| 2790 | break; |
| 2791 | case 8610: |
| 2792 | /* Common bug: MSM8212 (Quad-core) reported as MSM8610 (Dual-core) */ |
| 2793 | switch (cores) { |
| 2794 | case 2: |
| 2795 | break; |
| 2796 | case 4: |
| 2797 | cpuinfo_log_info("reinterpreted MSM8610 chipset with 4 cores as MSM8212"); |
| 2798 | chipset->model = 8212; |
| 2799 | break; |
| 2800 | default: |
| 2801 | cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", |
| 2802 | cores, chipset->model); |
| 2803 | chipset->model = 0; |
| 2804 | } |
| 2805 | break; |
| 2806 | } |
| 2807 | } else { |
| 2808 | /* Suffix may need correction */ |
| 2809 | const uint32_t suffix_word = load_u32le(chipset->suffix); |
| 2810 | if (suffix_word == UINT32_C(0x004D534D) /* "\0MSM" = reverse("MSM\0") */) { |
| 2811 | /* |
| 2812 | * Common bug: model name repeated twice, e.g. "MSM8916MSM8916" |
| 2813 | * In this case, model matching code parses the second "MSM" as a suffix |
| 2814 | */ |
| 2815 | chipset->suffix[0] = 0; |
| 2816 | chipset->suffix[1] = 0; |
| 2817 | chipset->suffix[2] = 0; |
| 2818 | } else { |
| 2819 | switch (chipset->model) { |
| 2820 | case 8976: |
| 2821 | /* MSM8976SG -> MSM8976PRO */ |
| 2822 | if (suffix_word == UINT32_C(0x00004753) /* "\0\0GS" = reverse("SG\0\0") */ ) { |
| 2823 | chipset->suffix[0] = 'P'; |
| 2824 | chipset->suffix[1] = 'R'; |
| 2825 | chipset->suffix[2] = 'O'; |
| 2826 | } |
| 2827 | break; |
| 2828 | case 8996: |
| 2829 | /* MSM8996PRO -> MSM8996PRO-AB or MSM8996PRO-AC */ |
| 2830 | if (suffix_word == UINT32_C(0x004F5250) /* "\0ORP" = reverse("PRO\0") */ ) { |
| 2831 | chipset->suffix[3] = '-'; |
| 2832 | chipset->suffix[4] = 'A'; |
| 2833 | chipset->suffix[5] = 'B' + (char) (max_cpu_freq_max >= 2188800); |
| 2834 | } |
| 2835 | break; |
| 2836 | } |
| 2837 | } |
| 2838 | } |
| 2839 | break; |
| 2840 | case cpuinfo_arm_chipset_series_qualcomm_apq: |
| 2841 | { |
| 2842 | /* Suffix may need correction */ |
| 2843 | const uint32_t expected_apq = load_u32le(chipset->suffix); |
| 2844 | if (expected_apq == UINT32_C(0x00515041) /* "\0QPA" = reverse("APQ\0") */) { |
| 2845 | /* |
| 2846 | * Common bug: model name repeated twice, e.g. "APQ8016APQ8016" |
| 2847 | * In this case, model matching code parses the second "APQ" as a suffix |
| 2848 | */ |
| 2849 | chipset->suffix[0] = 0; |
| 2850 | chipset->suffix[1] = 0; |
| 2851 | chipset->suffix[2] = 0; |
| 2852 | } |
| 2853 | break; |
| 2854 | } |
| 2855 | case cpuinfo_arm_chipset_series_samsung_exynos: |
| 2856 | if (chipset->model == 7580) { |
| 2857 | /* Common bug: Exynos 7578 (Quad-core) reported as Exynos 7580 (Octa-core) */ |
| 2858 | switch (cores) { |
| 2859 | case 4: |
| 2860 | cpuinfo_log_info("reinterpreted Exynos 7580 chipset with 4 cores as Exynos 7578"); |
| 2861 | chipset->model = 7578; |
| 2862 | break; |
| 2863 | case 8: |
| 2864 | break; |
| 2865 | default: |
| 2866 | cpuinfo_log_warning("system reported invalid %"PRIu32"-core Exynos 7580 chipset", cores); |
| 2867 | chipset->model = 0; |
| 2868 | } |
| 2869 | } |
| 2870 | break; |
| 2871 | case cpuinfo_arm_chipset_series_mediatek_mt: |
| 2872 | if (chipset->model == 6752) { |
| 2873 | /* Common bug: MT6732 (Quad-core) reported as MT6752 (Octa-core) */ |
| 2874 | switch (cores) { |
| 2875 | case 4: |
| 2876 | cpuinfo_log_info("reinterpreted MT6752 chipset with 4 cores as MT6732"); |
| 2877 | chipset->model = 6732; |
| 2878 | break; |
| 2879 | case 8: |
| 2880 | break; |
| 2881 | default: |
| 2882 | cpuinfo_log_warning("system reported invalid %"PRIu32"-core MT6752 chipset", cores); |
| 2883 | chipset->model = 0; |
| 2884 | } |
| 2885 | } |
| 2886 | if (chipset->suffix[0] == 'T') { |
| 2887 | /* Normalization: "TURBO" and "TRUBO" (apparently a typo) -> "T" */ |
| 2888 | const uint32_t suffix_word = load_u32le(chipset->suffix + 1); |
| 2889 | switch (suffix_word) { |
| 2890 | case UINT32_C(0x4F425255): /* "OBRU" = reverse("URBO") */ |
| 2891 | case UINT32_C(0x4F425552): /* "OBUR" = reverse("RUBO") */ |
| 2892 | if (chipset->suffix[5] == 0) { |
| 2893 | chipset->suffix[1] = 0; |
| 2894 | chipset->suffix[2] = 0; |
| 2895 | chipset->suffix[3] = 0; |
| 2896 | chipset->suffix[4] = 0; |
| 2897 | } |
| 2898 | break; |
| 2899 | } |
| 2900 | } |
| 2901 | break; |
| 2902 | default: |
| 2903 | break; |
| 2904 | } |
| 2905 | } |
| 2906 | |
| 2907 | /* Map from ARM chipset vendor ID to its string representation */ |
| 2908 | static const char* chipset_vendor_string[cpuinfo_arm_chipset_vendor_max] = { |
| 2909 | [cpuinfo_arm_chipset_vendor_unknown] = "Unknown", |
| 2910 | [cpuinfo_arm_chipset_vendor_qualcomm] = "Qualcomm", |
| 2911 | [cpuinfo_arm_chipset_vendor_mediatek] = "MediaTek", |
| 2912 | [cpuinfo_arm_chipset_vendor_samsung] = "Samsung", |
| 2913 | [cpuinfo_arm_chipset_vendor_hisilicon] = "HiSilicon", |
| 2914 | [cpuinfo_arm_chipset_vendor_actions] = "Actions", |
| 2915 | [cpuinfo_arm_chipset_vendor_allwinner] = "Allwinner", |
| 2916 | [cpuinfo_arm_chipset_vendor_amlogic] = "Amlogic", |
| 2917 | [cpuinfo_arm_chipset_vendor_broadcom] = "Broadcom", |
| 2918 | [cpuinfo_arm_chipset_vendor_lg] = "LG", |
| 2919 | [cpuinfo_arm_chipset_vendor_leadcore] = "Leadcore", |
| 2920 | [cpuinfo_arm_chipset_vendor_marvell] = "Marvell", |
| 2921 | [cpuinfo_arm_chipset_vendor_mstar] = "MStar", |
| 2922 | [cpuinfo_arm_chipset_vendor_novathor] = "NovaThor", |
| 2923 | [cpuinfo_arm_chipset_vendor_nvidia] = "nVidia", |
| 2924 | [cpuinfo_arm_chipset_vendor_pinecone] = "Pinecone", |
| 2925 | [cpuinfo_arm_chipset_vendor_renesas] = "Renesas", |
| 2926 | [cpuinfo_arm_chipset_vendor_rockchip] = "Rockchip", |
| 2927 | [cpuinfo_arm_chipset_vendor_spreadtrum] = "Spreadtrum", |
| 2928 | [cpuinfo_arm_chipset_vendor_telechips] = "Telechips", |
| 2929 | [cpuinfo_arm_chipset_vendor_texas_instruments] = "Texas Instruments", |
| 2930 | [cpuinfo_arm_chipset_vendor_wondermedia] = "WonderMedia", |
| 2931 | }; |
| 2932 | |
| 2933 | /* Map from ARM chipset series ID to its string representation */ |
| 2934 | static const char* chipset_series_string[cpuinfo_arm_chipset_series_max] = { |
| 2935 | [cpuinfo_arm_chipset_series_unknown] = NULL, |
| 2936 | [cpuinfo_arm_chipset_series_qualcomm_qsd] = "QSD", |
| 2937 | [cpuinfo_arm_chipset_series_qualcomm_msm] = "MSM", |
| 2938 | [cpuinfo_arm_chipset_series_qualcomm_apq] = "APQ", |
| 2939 | [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = "Snapdragon ", |
| 2940 | [cpuinfo_arm_chipset_series_mediatek_mt] = "MT", |
| 2941 | [cpuinfo_arm_chipset_series_samsung_exynos] = "Exynos ", |
| 2942 | [cpuinfo_arm_chipset_series_hisilicon_k3v] = "K3V", |
| 2943 | [cpuinfo_arm_chipset_series_hisilicon_hi] = "Hi", |
| 2944 | [cpuinfo_arm_chipset_series_hisilicon_kirin] = "Kirin ", |
| 2945 | [cpuinfo_arm_chipset_series_actions_atm] = "ATM", |
| 2946 | [cpuinfo_arm_chipset_series_allwinner_a] = "A", |
| 2947 | [cpuinfo_arm_chipset_series_amlogic_aml] = "AML", |
| 2948 | [cpuinfo_arm_chipset_series_amlogic_s] = "S", |
| 2949 | [cpuinfo_arm_chipset_series_broadcom_bcm] = "BCM", |
| 2950 | [cpuinfo_arm_chipset_series_lg_nuclun] = "Nuclun ", |
| 2951 | [cpuinfo_arm_chipset_series_leadcore_lc] = "LC", |
| 2952 | [cpuinfo_arm_chipset_series_marvell_pxa] = "PXA", |
| 2953 | [cpuinfo_arm_chipset_series_mstar_6a] = "6A", |
| 2954 | [cpuinfo_arm_chipset_series_novathor_u] = "U", |
| 2955 | [cpuinfo_arm_chipset_series_nvidia_tegra_t] = "Tegra T", |
| 2956 | [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = "Tegra AP", |
| 2957 | [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = "Tegra SL", |
| 2958 | [cpuinfo_arm_chipset_series_pinecone_surge_s] = "Surge S", |
| 2959 | [cpuinfo_arm_chipset_series_renesas_mp] = "MP", |
| 2960 | [cpuinfo_arm_chipset_series_rockchip_rk] = "RK", |
| 2961 | [cpuinfo_arm_chipset_series_spreadtrum_sc] = "SC", |
| 2962 | [cpuinfo_arm_chipset_series_telechips_tcc] = "TCC", |
| 2963 | [cpuinfo_arm_chipset_series_texas_instruments_omap] = "OMAP", |
| 2964 | [cpuinfo_arm_chipset_series_wondermedia_wm] = "WM", |
| 2965 | }; |
| 2966 | |
| 2967 | /* Convert chipset name represented by cpuinfo_arm_chipset structure to a string representation */ |
| 2968 | void cpuinfo_arm_chipset_to_string( |
| 2969 | const struct cpuinfo_arm_chipset chipset[restrict static 1], |
| 2970 | char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]) |
| 2971 | { |
| 2972 | enum cpuinfo_arm_chipset_vendor vendor = chipset->vendor; |
| 2973 | if (vendor >= cpuinfo_arm_chipset_vendor_max) { |
| 2974 | vendor = cpuinfo_arm_chipset_vendor_unknown; |
| 2975 | } |
| 2976 | enum cpuinfo_arm_chipset_series series = chipset->series; |
| 2977 | if (series >= cpuinfo_arm_chipset_series_max) { |
| 2978 | series = cpuinfo_arm_chipset_series_unknown; |
| 2979 | } |
| 2980 | const char* vendor_string = chipset_vendor_string[vendor]; |
| 2981 | const char* series_string = chipset_series_string[series]; |
| 2982 | const uint32_t model = chipset->model; |
| 2983 | if (model == 0) { |
| 2984 | if (series == cpuinfo_arm_chipset_series_unknown) { |
| 2985 | strncpy(name, vendor_string, CPUINFO_ARM_CHIPSET_NAME_MAX); |
| 2986 | } else { |
| 2987 | snprintf(name, CPUINFO_ARM_CHIPSET_NAME_MAX, |
| 2988 | "%s %s", vendor_string, series_string); |
| 2989 | } |
| 2990 | } else { |
| 2991 | const size_t suffix_length = strnlen(chipset->suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); |
| 2992 | snprintf(name, CPUINFO_ARM_CHIPSET_NAME_MAX, |
| 2993 | "%s %s%"PRIu32"%.*s", vendor_string, series_string, model, (int) suffix_length, chipset->suffix); |
| 2994 | } |
| 2995 | } |
| 2996 | |
| 2997 | static inline struct cpuinfo_arm_chipset disambiguate_qualcomm_chipset( |
| 2998 | const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], |
| 2999 | const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], |
| 3000 | const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], |
| 3001 | const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) |
| 3002 | { |
| 3003 | if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3004 | return *ro_chipname_chipset; |
| 3005 | } |
| 3006 | if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3007 | return *proc_cpuinfo_hardware_chipset; |
| 3008 | } |
| 3009 | if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3010 | return *ro_product_board_chipset; |
| 3011 | } |
| 3012 | return *ro_board_platform_chipset; |
| 3013 | } |
| 3014 | |
| 3015 | static inline struct cpuinfo_arm_chipset disambiguate_mediatek_chipset( |
| 3016 | const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], |
| 3017 | const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], |
| 3018 | const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], |
| 3019 | const struct cpuinfo_arm_chipset ro_mediatek_platform_chipset[restrict static 1], |
| 3020 | const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) |
| 3021 | { |
| 3022 | if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3023 | return *ro_chipname_chipset; |
| 3024 | } |
| 3025 | if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3026 | return *proc_cpuinfo_hardware_chipset; |
| 3027 | } |
| 3028 | if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3029 | return *ro_product_board_chipset; |
| 3030 | } |
| 3031 | if (ro_board_platform_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3032 | return *ro_board_platform_chipset; |
| 3033 | } |
| 3034 | return *ro_mediatek_platform_chipset; |
| 3035 | } |
| 3036 | |
| 3037 | static inline struct cpuinfo_arm_chipset disambiguate_hisilicon_chipset( |
| 3038 | const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], |
| 3039 | const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], |
| 3040 | const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) |
| 3041 | { |
| 3042 | if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3043 | return *proc_cpuinfo_hardware_chipset; |
| 3044 | } |
| 3045 | if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3046 | return *ro_product_board_chipset; |
| 3047 | } |
| 3048 | return *ro_board_platform_chipset; |
| 3049 | } |
| 3050 | |
| 3051 | static inline struct cpuinfo_arm_chipset disambiguate_amlogic_chipset( |
| 3052 | const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], |
| 3053 | const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) |
| 3054 | { |
| 3055 | if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3056 | return *proc_cpuinfo_hardware_chipset; |
| 3057 | } |
| 3058 | return *ro_board_platform_chipset; |
| 3059 | } |
| 3060 | |
| 3061 | static inline struct cpuinfo_arm_chipset disambiguate_marvell_chipset( |
| 3062 | const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], |
| 3063 | const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], |
| 3064 | const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) |
| 3065 | { |
| 3066 | if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3067 | return *ro_chipname_chipset; |
| 3068 | } |
| 3069 | if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3070 | return *ro_product_board_chipset; |
| 3071 | } |
| 3072 | return *proc_cpuinfo_hardware_chipset; |
| 3073 | } |
| 3074 | |
| 3075 | static inline struct cpuinfo_arm_chipset disambiguate_rockchip_chipset( |
| 3076 | const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], |
| 3077 | const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], |
| 3078 | const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) |
| 3079 | { |
| 3080 | if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3081 | return *ro_product_board_chipset; |
| 3082 | } |
| 3083 | if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3084 | return *proc_cpuinfo_hardware_chipset; |
| 3085 | } |
| 3086 | return *ro_board_platform_chipset; |
| 3087 | } |
| 3088 | |
| 3089 | static inline struct cpuinfo_arm_chipset disambiguate_spreadtrum_chipset( |
| 3090 | const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], |
| 3091 | const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], |
| 3092 | const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], |
| 3093 | const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) |
| 3094 | { |
| 3095 | if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3096 | return *ro_chipname_chipset; |
| 3097 | } |
| 3098 | if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3099 | return *ro_product_board_chipset; |
| 3100 | } |
| 3101 | if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { |
| 3102 | return *proc_cpuinfo_hardware_chipset; |
| 3103 | } |
| 3104 | return *ro_board_platform_chipset; |
| 3105 | } |
| 3106 | |
| 3107 | /* |
| 3108 | * Decodes chipset name from Android system properties: |
| 3109 | * - /proc/cpuinfo Hardware string |
| 3110 | * - ro.product.board |
| 3111 | * - ro.board.platform |
| 3112 | * - ro.mediatek.platform |
| 3113 | * - ro.chipname |
| 3114 | * For some chipsets, the function relies frequency and on number of cores for chipset detection. |
| 3115 | * |
| 3116 | * @param[in] properties - structure with the Android system properties described above. |
| 3117 | * @param cores - number of cores in the chipset. |
| 3118 | * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu<number>/cpofreq/cpu_freq_max values. |
| 3119 | * |
| 3120 | * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor |
| 3121 | * and series identifiers. |
| 3122 | */ |
| 3123 | struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( |
| 3124 | const struct cpuinfo_android_properties properties[restrict static 1], |
| 3125 | uint32_t cores, |
| 3126 | uint32_t max_cpu_freq_max) |
| 3127 | { |
| 3128 | struct cpuinfo_arm_chipset chipset = { |
| 3129 | .vendor = cpuinfo_arm_chipset_vendor_unknown, |
| 3130 | .series = cpuinfo_arm_chipset_series_unknown, |
| 3131 | }; |
| 3132 | |
| 3133 | const bool tegra_platform = is_tegra( |
| 3134 | properties->ro_board_platform, |
| 3135 | properties->ro_board_platform + strnlen(properties->ro_board_platform, CPUINFO_BUILD_PROP_VALUE_MAX)); |
| 3136 | |
| 3137 | struct cpuinfo_arm_chipset chipsets[cpuinfo_android_chipset_property_max] = { |
| 3138 | [cpuinfo_android_chipset_property_proc_cpuinfo_hardware] = |
| 3139 | cpuinfo_arm_android_decode_chipset_from_proc_cpuinfo_hardware( |
| 3140 | properties->proc_cpuinfo_hardware, cores, max_cpu_freq_max, tegra_platform), |
| 3141 | [cpuinfo_android_chipset_property_ro_product_board] = |
| 3142 | cpuinfo_arm_android_decode_chipset_from_ro_product_board( |
| 3143 | properties->ro_product_board, cores, max_cpu_freq_max), |
| 3144 | [cpuinfo_android_chipset_property_ro_board_platform] = |
| 3145 | cpuinfo_arm_android_decode_chipset_from_ro_board_platform( |
| 3146 | properties->ro_board_platform, cores, max_cpu_freq_max), |
| 3147 | [cpuinfo_android_chipset_property_ro_mediatek_platform] = |
| 3148 | cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform(properties->ro_mediatek_platform), |
| 3149 | [cpuinfo_android_chipset_property_ro_chipname] = |
| 3150 | cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_chipname), |
| 3151 | }; |
| 3152 | enum cpuinfo_arm_chipset_vendor vendor = cpuinfo_arm_chipset_vendor_unknown; |
| 3153 | for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { |
| 3154 | const enum cpuinfo_arm_chipset_vendor decoded_vendor = chipsets[i].vendor; |
| 3155 | if (decoded_vendor != cpuinfo_arm_chipset_vendor_unknown) { |
| 3156 | if (vendor == cpuinfo_arm_chipset_vendor_unknown) { |
| 3157 | vendor = decoded_vendor; |
| 3158 | } else if (vendor != decoded_vendor) { |
| 3159 | /* Parsing different system properties produces different chipset vendors. This situation is rare. */ |
| 3160 | cpuinfo_log_error( |
| 3161 | "chipset detection failed: different chipset vendors reported in different system properties"); |
| 3162 | goto finish; |
| 3163 | } |
| 3164 | } |
| 3165 | } |
| 3166 | if (vendor == cpuinfo_arm_chipset_vendor_unknown) { |
| 3167 | cpuinfo_log_warning( |
| 3168 | "chipset detection failed: none of the system properties matched known signatures"); |
| 3169 | goto finish; |
| 3170 | } |
| 3171 | |
| 3172 | /* Fix common bugs in reported chipsets */ |
| 3173 | for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { |
| 3174 | cpuinfo_arm_fixup_chipset(&chipsets[i], cores, max_cpu_freq_max); |
| 3175 | } |
| 3176 | |
| 3177 | /* |
| 3178 | * Propagate suffixes: consider all pairs of chipsets, if both chipsets in the pair are from the same series, |
| 3179 | * and one's suffix is a prefix of another's chipset suffix, use the longest suffix. |
| 3180 | */ |
| 3181 | for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { |
| 3182 | const size_t chipset_i_suffix_length = strnlen(chipsets[i].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); |
| 3183 | for (size_t j = 0; j < i; j++) { |
| 3184 | if (chipsets[i].series == chipsets[j].series) { |
| 3185 | const size_t chipset_j_suffix_length = strnlen(chipsets[j].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); |
| 3186 | if (chipset_i_suffix_length != chipset_j_suffix_length) { |
| 3187 | const size_t common_prefix_length = (chipset_i_suffix_length < chipset_j_suffix_length) ? |
| 3188 | chipset_i_suffix_length : chipset_j_suffix_length; |
| 3189 | if (common_prefix_length == 0 || |
| 3190 | memcmp(chipsets[i].suffix, chipsets[j].suffix, common_prefix_length) == 0) |
| 3191 | { |
| 3192 | if (chipset_i_suffix_length > chipset_j_suffix_length) { |
| 3193 | memcpy(chipsets[j].suffix, chipsets[i].suffix, chipset_i_suffix_length); |
| 3194 | } else { |
| 3195 | memcpy(chipsets[i].suffix, chipsets[j].suffix, chipset_j_suffix_length); |
| 3196 | } |
| 3197 | } |
| 3198 | } |
| 3199 | } |
| 3200 | } |
| 3201 | } |
| 3202 | |
| 3203 | for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { |
| 3204 | if (chipsets[i].series != cpuinfo_arm_chipset_series_unknown) { |
| 3205 | if (chipset.series == cpuinfo_arm_chipset_series_unknown) { |
| 3206 | chipset = chipsets[i]; |
| 3207 | } else if (chipsets[i].series != chipset.series || chipsets[i].model != chipset.model || |
| 3208 | strncmp(chipsets[i].suffix, chipset.suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX) != 0) |
| 3209 | { |
| 3210 | cpuinfo_log_info( |
| 3211 | "different chipsets reported in different system properties; " |
| 3212 | "vendor-specific disambiguation heuristic would be used"); |
| 3213 | switch (vendor) { |
| 3214 | case cpuinfo_arm_chipset_vendor_qualcomm: |
| 3215 | return disambiguate_qualcomm_chipset( |
| 3216 | &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], |
| 3217 | &chipsets[cpuinfo_android_chipset_property_ro_product_board], |
| 3218 | &chipsets[cpuinfo_android_chipset_property_ro_board_platform], |
| 3219 | &chipsets[cpuinfo_android_chipset_property_ro_chipname]); |
| 3220 | case cpuinfo_arm_chipset_vendor_mediatek: |
| 3221 | return disambiguate_mediatek_chipset( |
| 3222 | &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], |
| 3223 | &chipsets[cpuinfo_android_chipset_property_ro_product_board], |
| 3224 | &chipsets[cpuinfo_android_chipset_property_ro_board_platform], |
| 3225 | &chipsets[cpuinfo_android_chipset_property_ro_mediatek_platform], |
| 3226 | &chipsets[cpuinfo_android_chipset_property_ro_chipname]); |
| 3227 | case cpuinfo_arm_chipset_vendor_hisilicon: |
| 3228 | return disambiguate_hisilicon_chipset( |
| 3229 | &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], |
| 3230 | &chipsets[cpuinfo_android_chipset_property_ro_product_board], |
| 3231 | &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); |
| 3232 | case cpuinfo_arm_chipset_vendor_amlogic: |
| 3233 | return disambiguate_amlogic_chipset( |
| 3234 | &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], |
| 3235 | &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); |
| 3236 | case cpuinfo_arm_chipset_vendor_marvell: |
| 3237 | return disambiguate_marvell_chipset( |
| 3238 | &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], |
| 3239 | &chipsets[cpuinfo_android_chipset_property_ro_product_board], |
| 3240 | &chipsets[cpuinfo_android_chipset_property_ro_chipname]); |
| 3241 | case cpuinfo_arm_chipset_vendor_rockchip: |
| 3242 | return disambiguate_rockchip_chipset( |
| 3243 | &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], |
| 3244 | &chipsets[cpuinfo_android_chipset_property_ro_product_board], |
| 3245 | &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); |
| 3246 | case cpuinfo_arm_chipset_vendor_spreadtrum: |
| 3247 | return disambiguate_spreadtrum_chipset( |
| 3248 | &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], |
| 3249 | &chipsets[cpuinfo_android_chipset_property_ro_product_board], |
| 3250 | &chipsets[cpuinfo_android_chipset_property_ro_board_platform], |
| 3251 | &chipsets[cpuinfo_android_chipset_property_ro_chipname]); |
| 3252 | default: |
| 3253 | cpuinfo_log_error( |
| 3254 | "chipset detection failed: " |
| 3255 | "could not disambiguate different chipsets reported in different system properties"); |
| 3256 | /* chipset variable contains valid, but inconsistent chipset information, overwrite it */ |
| 3257 | chipset = (struct cpuinfo_arm_chipset) { |
| 3258 | .vendor = cpuinfo_arm_chipset_vendor_unknown, |
| 3259 | .series = cpuinfo_arm_chipset_series_unknown, |
| 3260 | }; |
| 3261 | goto finish; |
| 3262 | } |
| 3263 | } |
| 3264 | } |
| 3265 | } |
| 3266 | |
| 3267 | finish: |
| 3268 | return chipset; |
| 3269 | } |