blob: 99739f0566d5467075c30d7db6f1db41fc33cc15 [file] [log] [blame]
Marat Dukhan2e00fed2017-08-10 17:23:43 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
Marat Dukhan30401972017-09-26 18:35:52 -07008 ASSERT_EQ(8, cpuinfo_get_processors_count());
Marat Dukhan2e00fed2017-08-10 17:23:43 -07009}
10
11TEST(PROCESSORS, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070012 ASSERT_TRUE(cpuinfo_get_processors());
Marat Dukhan2e00fed2017-08-10 17:23:43 -070013}
14
Marat Dukhan2d37dc42017-09-25 01:32:37 -070015TEST(PROCESSORS, smt_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070016 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
Marat Dukhan2e00fed2017-08-10 17:23:43 -070018 }
19}
20
Marat Dukhan2d37dc42017-09-25 01:32:37 -070021TEST(PROCESSORS, core) {
Marat Dukhan30401972017-09-26 18:35:52 -070022 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070024 }
25}
26
27TEST(PROCESSORS, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070028 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
Marat Dukhan2e00fed2017-08-10 17:23:43 -070030 }
31}
32
Marat Dukhan846c1782017-09-13 09:47:26 -070033TEST(PROCESSORS, linux_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070034 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan846c1782017-09-13 09:47:26 -070035 switch (i) {
36 case 0:
37 case 1:
38 case 2:
39 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -070040 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070041 break;
42 case 4:
43 case 5:
44 case 6:
45 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -070046 ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070047 break;
48 }
49 }
50}
51
Marat Dukhan2d37dc42017-09-25 01:32:37 -070052TEST(PROCESSORS, l1i) {
Marat Dukhan30401972017-09-26 18:35:52 -070053 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
54 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070055 }
56}
57
58TEST(PROCESSORS, l1d) {
Marat Dukhan30401972017-09-26 18:35:52 -070059 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
60 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070061 }
62}
63
64TEST(PROCESSORS, l2) {
Marat Dukhan30401972017-09-26 18:35:52 -070065 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -070066 switch (i) {
67 case 0:
68 case 1:
69 case 2:
70 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -070071 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070072 break;
73 case 4:
74 case 5:
75 case 6:
76 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -070077 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070078 break;
79 }
80 }
81}
82
83TEST(PROCESSORS, l3) {
Marat Dukhan30401972017-09-26 18:35:52 -070084 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
85 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070086 }
87}
88
89TEST(PROCESSORS, l4) {
Marat Dukhan30401972017-09-26 18:35:52 -070090 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
91 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070092 }
93}
94
Marat Dukhan7073e832017-09-24 22:23:55 -070095TEST(CORES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -070096 ASSERT_EQ(8, cpuinfo_get_cores_count());
Marat Dukhan7073e832017-09-24 22:23:55 -070097}
98
Marat Dukhan2d37dc42017-09-25 01:32:37 -070099TEST(CORES, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700100 ASSERT_TRUE(cpuinfo_get_cores());
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700101}
102
Marat Dukhan7073e832017-09-24 22:23:55 -0700103TEST(CORES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700104 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
105 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
Marat Dukhan7073e832017-09-24 22:23:55 -0700106 }
107}
108
109TEST(CORES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700110 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
111 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
Marat Dukhan7073e832017-09-24 22:23:55 -0700112 }
113}
114
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700115TEST(CORES, core_id) {
Marat Dukhan30401972017-09-26 18:35:52 -0700116 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
117 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700118 }
119}
120
121TEST(CORES, package) {
Marat Dukhan30401972017-09-26 18:35:52 -0700122 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
123 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700124 }
125}
126
127TEST(CORES, vendor) {
Marat Dukhan30401972017-09-26 18:35:52 -0700128 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700129 switch (i) {
130 case 0:
131 case 1:
132 case 2:
133 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -0700134 ASSERT_EQ(cpuinfo_vendor_samsung, cpuinfo_get_core(i)->vendor);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700135 break;
136 case 4:
137 case 5:
138 case 6:
139 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -0700140 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700141 break;
142 }
143 }
144}
145
146TEST(CORES, uarch) {
Marat Dukhan30401972017-09-26 18:35:52 -0700147 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700148 switch (i) {
149 case 0:
150 case 1:
151 case 2:
152 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -0700153 ASSERT_EQ(cpuinfo_uarch_mongoose, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700154 break;
155 case 4:
156 case 5:
157 case 6:
158 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -0700159 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700160 break;
161 }
162 }
163}
164
165TEST(CORES, midr) {
Marat Dukhan30401972017-09-26 18:35:52 -0700166 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700167 switch (i) {
168 case 0:
169 case 1:
170 case 2:
171 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -0700172 ASSERT_EQ(UINT32_C(0x531F0011), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700173 break;
174 case 4:
175 case 5:
176 case 6:
177 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -0700178 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700179 break;
180 }
181 }
182}
183
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700184TEST(PACKAGES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700185 ASSERT_EQ(1, cpuinfo_get_packages_count());
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700186}
187
188TEST(PACKAGES, name) {
Marat Dukhan30401972017-09-26 18:35:52 -0700189 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700190 ASSERT_EQ("Samsung Exynos 8890",
Marat Dukhan30401972017-09-26 18:35:52 -0700191 std::string(cpuinfo_get_package(i)->name,
192 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700193 }
194}
195
196TEST(PACKAGES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700197 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
198 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700199 }
200}
201
202TEST(PACKAGES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700203 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
204 ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700205 }
206}
207
208TEST(PACKAGES, core_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700209 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
210 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700211 }
212}
213
214TEST(PACKAGES, core_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700215 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
216 ASSERT_EQ(8, cpuinfo_get_package(i)->core_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700217 }
218}
219
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700220TEST(ISA, thumb) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700221 #if CPUINFO_ARCH_ARM
222 ASSERT_TRUE(cpuinfo_has_arm_thumb());
223 #elif CPUINFO_ARCH_ARM64
224 ASSERT_FALSE(cpuinfo_has_arm_thumb());
225 #endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700226}
227
228TEST(ISA, thumb2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700229 #if CPUINFO_ARCH_ARM
230 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
231 #elif CPUINFO_ARCH_ARM64
232 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
233 #endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700234}
235
236TEST(ISA, armv5e) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700237 #if CPUINFO_ARCH_ARM
238 ASSERT_TRUE(cpuinfo_has_arm_v5e());
239 #elif CPUINFO_ARCH_ARM64
240 ASSERT_FALSE(cpuinfo_has_arm_v5e());
241 #endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700242}
243
244TEST(ISA, armv6) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700245 #if CPUINFO_ARCH_ARM
246 ASSERT_TRUE(cpuinfo_has_arm_v6());
247 #elif CPUINFO_ARCH_ARM64
248 ASSERT_FALSE(cpuinfo_has_arm_v6());
249 #endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700250}
251
252TEST(ISA, armv6k) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700253 #if CPUINFO_ARCH_ARM
254 ASSERT_TRUE(cpuinfo_has_arm_v6k());
255 #elif CPUINFO_ARCH_ARM64
256 ASSERT_FALSE(cpuinfo_has_arm_v6k());
257 #endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700258}
259
260TEST(ISA, armv7) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700261 #if CPUINFO_ARCH_ARM
262 ASSERT_TRUE(cpuinfo_has_arm_v7());
263 #elif CPUINFO_ARCH_ARM64
264 ASSERT_FALSE(cpuinfo_has_arm_v7());
265 #endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700266}
267
268TEST(ISA, armv7mp) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700269 #if CPUINFO_ARCH_ARM
270 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
271 #elif CPUINFO_ARCH_ARM64
272 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
273 #endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700274}
275
276TEST(ISA, idiv) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700277 ASSERT_TRUE(cpuinfo_has_arm_idiv());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700278}
279
280TEST(ISA, vfpv2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700281 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700282}
283
284TEST(ISA, vfpv3) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700285 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700286}
287
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700288TEST(ISA, vfpv3_d32) {
289 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700290}
291
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700292TEST(ISA, vfpv3_fp16) {
293 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700294}
295
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700296TEST(ISA, vfpv3_fp16_d32) {
297 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
298}
299
300TEST(ISA, vfpv4) {
301 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
302}
303
304TEST(ISA, vfpv4_d32) {
305 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700306}
307
308TEST(ISA, wmmx) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700309 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700310}
311
312TEST(ISA, wmmx2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700313 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700314}
315
316TEST(ISA, neon) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700317 ASSERT_TRUE(cpuinfo_has_arm_neon());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700318}
319
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700320TEST(ISA, neon_fp16) {
321 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700322}
323
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700324TEST(ISA, neon_fma) {
325 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700326}
327
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700328TEST(ISA, atomics) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700329 ASSERT_FALSE(cpuinfo_has_arm_atomics());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700330}
331
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700332TEST(ISA, neon_rdm) {
333 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700334}
335
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700336TEST(ISA, fp16_arith) {
337 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700338}
339
340TEST(ISA, jscvt) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700341 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700342}
343
344TEST(ISA, fcma) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700345 ASSERT_FALSE(cpuinfo_has_arm_fcma());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700346}
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700347
348TEST(ISA, aes) {
349 ASSERT_TRUE(cpuinfo_has_arm_aes());
350}
351
352TEST(ISA, sha1) {
353 ASSERT_TRUE(cpuinfo_has_arm_sha1());
354}
355
356TEST(ISA, sha2) {
357 ASSERT_TRUE(cpuinfo_has_arm_sha2());
358}
359
360TEST(ISA, pmull) {
361 ASSERT_TRUE(cpuinfo_has_arm_pmull());
362}
363
364TEST(ISA, crc32) {
365 ASSERT_TRUE(cpuinfo_has_arm_crc32());
366}
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700367
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700368TEST(L1I, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700369 ASSERT_EQ(8, cpuinfo_get_l1i_caches_count());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700370}
371
372TEST(L1I, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700373 ASSERT_TRUE(cpuinfo_get_l1i_caches());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700374}
375
376TEST(L1I, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700377 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
378 switch (i) {
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700379 case 0:
380 case 1:
381 case 2:
382 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -0700383 ASSERT_EQ(64 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700384 break;
385 case 4:
386 case 5:
387 case 6:
388 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -0700389 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700390 break;
391 }
392 }
393}
394
395TEST(L1I, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700396 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
397 switch (i) {
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700398 case 0:
399 case 1:
400 case 2:
401 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -0700402 ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700403 break;
404 case 4:
405 case 5:
406 case 6:
407 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -0700408 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700409 break;
410 }
411 }
412}
413
414TEST(L1I, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700415 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
416 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
417 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700418 }
419}
420
421TEST(L1I, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700422 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
423 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700424 }
425}
426
427TEST(L1I, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700428 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
429 switch (i) {
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700430 case 0:
431 case 1:
432 case 2:
433 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -0700434 ASSERT_EQ(128, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700435 break;
436 case 4:
437 case 5:
438 case 6:
439 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -0700440 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700441 break;
442 }
443 }
444}
445
446TEST(L1I, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700447 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
448 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700449 }
450}
451
452TEST(L1I, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700453 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
454 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
455 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700456 }
457}
458
459TEST(L1D, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700460 ASSERT_EQ(8, cpuinfo_get_l1d_caches_count());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700461}
462
463TEST(L1D, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700464 ASSERT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700465}
466
467TEST(L1D, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700468 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
469 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700470 }
471}
472
473TEST(L1D, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700474 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
475 switch (i) {
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700476 case 0:
477 case 1:
478 case 2:
479 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -0700480 ASSERT_EQ(8, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700481 break;
482 case 4:
483 case 5:
484 case 6:
485 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -0700486 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700487 break;
488 }
489 }
490}
491
492TEST(L1D, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700493 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
494 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
495 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700496 }
497}
498
499TEST(L1D, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700500 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
501 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700502 }
503}
504
505TEST(L1D, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700506 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
507 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700508 }
509}
510
511TEST(L1D, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700512 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
513 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700514 }
515}
516
517TEST(L1D, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700518 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
519 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
520 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700521 }
522}
523
524TEST(L2, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700525 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700526}
527
528TEST(L2, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700529 ASSERT_TRUE(cpuinfo_get_l2_caches());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700530}
531
532TEST(L2, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700533 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
534 switch (i) {
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700535 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700536 ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700537 break;
538 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700539 ASSERT_EQ(256 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700540 break;
541 }
542 }
543}
544
545TEST(L2, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700546 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
547 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700548 }
549}
550
551TEST(L2, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700552 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
553 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
554 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700555 }
556}
557
558TEST(L2, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700559 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
560 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700561 }
562}
563
564TEST(L2, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700565 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
566 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700567 }
568}
569
570TEST(L2, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700571 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
572 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700573 }
574}
575
576TEST(L2, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700577 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
578 switch (i) {
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700579 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700580 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
581 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700582 break;
583 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700584 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_start);
585 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700586 break;
587 }
588 }
589}
590
591TEST(L3, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700592 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
593 ASSERT_FALSE(cpuinfo_get_l3_caches());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700594}
595
596TEST(L4, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700597 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
598 ASSERT_FALSE(cpuinfo_get_l4_caches());
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700599}
600
601#include <galaxy-s7-global.h>
602
603int main(int argc, char* argv[]) {
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800604#if CPUINFO_ARCH_ARM
605 cpuinfo_set_hwcap(UINT32_C(0x0037B0D6));
606 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
607#elif CPUINFO_ARCH_ARM64
608 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
609#endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700610 cpuinfo_mock_filesystem(filesystem);
Marat Dukhana2658a62017-09-17 11:14:51 -0700611#ifdef __ANDROID__
612 cpuinfo_mock_android_properties(properties);
613#endif
Marat Dukhan2e00fed2017-08-10 17:23:43 -0700614 cpuinfo_initialize();
615 ::testing::InitGoogleTest(&argc, argv);
616 return RUN_ALL_TESTS();
Marat Dukhan30401972017-09-26 18:35:52 -0700617}