blob: 9ab392fb2618dfb8899c58bd357080f347b7a8ce [file] [log] [blame]
Marat Dukhand51d3952018-03-17 19:18:06 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
8 ASSERT_EQ(8, cpuinfo_get_processors_count());
9}
10
11TEST(PROCESSORS, non_null) {
12 ASSERT_TRUE(cpuinfo_get_processors());
13}
14
15TEST(PROCESSORS, smt_id) {
16 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
18 }
19}
20
21TEST(PROCESSORS, core) {
22 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
24 }
25}
26
Marat Dukhan2b307932018-03-18 16:15:36 -070027TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 switch (i) {
30 case 0:
31 case 1:
32 case 2:
33 case 3:
34 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
35 break;
36 case 4:
37 case 5:
38 case 6:
39 case 7:
40 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
41 break;
42 }
43 }
44}
45
Marat Dukhand51d3952018-03-17 19:18:06 -070046TEST(PROCESSORS, package) {
47 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
48 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
49 }
50}
51
52TEST(PROCESSORS, linux_id) {
53 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
54 switch (i) {
55 case 0:
56 case 1:
57 case 2:
58 case 3:
59 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
60 break;
61 case 4:
62 case 5:
63 case 6:
64 case 7:
65 ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id);
66 break;
67 }
68 }
69}
70
71TEST(PROCESSORS, l1i) {
72 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
73 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
74 }
75}
76
77TEST(PROCESSORS, l1d) {
78 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
79 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
80 }
81}
82
Marat Dukhan2b307932018-03-18 16:15:36 -070083TEST(PROCESSORS, DISABLED_l2) {
Marat Dukhand51d3952018-03-17 19:18:06 -070084 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2b307932018-03-18 16:15:36 -070085 ASSERT_EQ(cpuinfo_get_l2_cache(i), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhand51d3952018-03-17 19:18:06 -070086 }
87}
88
Marat Dukhan2b307932018-03-18 16:15:36 -070089TEST(PROCESSORS, DISABLED_l3) {
Marat Dukhand51d3952018-03-17 19:18:06 -070090 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2b307932018-03-18 16:15:36 -070091 ASSERT_EQ(cpuinfo_get_l3_cache(0), cpuinfo_get_processor(i)->cache.l3);
Marat Dukhand51d3952018-03-17 19:18:06 -070092 }
93}
94
95TEST(PROCESSORS, l4) {
96 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
97 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
98 }
99}
100
101TEST(CORES, count) {
102 ASSERT_EQ(8, cpuinfo_get_cores_count());
103}
104
105TEST(CORES, non_null) {
106 ASSERT_TRUE(cpuinfo_get_cores());
107}
108
109TEST(CORES, processor_start) {
110 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
111 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
112 }
113}
114
115TEST(CORES, processor_count) {
116 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
117 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
118 }
119}
120
121TEST(CORES, core_id) {
122 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
123 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
124 }
125}
126
Marat Dukhan2b307932018-03-18 16:15:36 -0700127TEST(CORES, cluster) {
128 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
129 switch (i) {
130 case 0:
131 case 1:
132 case 2:
133 case 3:
134 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
135 break;
136 case 4:
137 case 5:
138 case 6:
139 case 7:
140 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
141 break;
142 }
143 }
144}
145
Marat Dukhand51d3952018-03-17 19:18:06 -0700146TEST(CORES, package) {
147 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
148 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
149 }
150}
151
152TEST(CORES, vendor) {
153 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
154 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
155 }
156}
157
158TEST(CORES, uarch) {
159 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
160 switch (i) {
161 case 0:
162 case 1:
163 case 2:
164 case 3:
165 ASSERT_EQ(cpuinfo_uarch_cortex_a75, cpuinfo_get_core(i)->uarch);
166 break;
167 case 4:
168 case 5:
169 case 6:
170 case 7:
171 ASSERT_EQ(cpuinfo_uarch_cortex_a55, cpuinfo_get_core(i)->uarch);
172 break;
173 }
174 }
175}
176
177TEST(CORES, midr) {
178 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
179 switch (i) {
180 case 0:
181 case 1:
182 case 2:
183 case 3:
184 ASSERT_EQ(UINT32_C(0x516F802D), cpuinfo_get_core(i)->midr);
185 break;
186 case 4:
187 case 5:
188 case 6:
189 case 7:
190 ASSERT_EQ(UINT32_C(0x517F803C), cpuinfo_get_core(i)->midr);
191 break;
192 }
193 }
194}
195
196TEST(CORES, DISABLED_frequency) {
197 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
198 switch (i) {
199 case 0:
200 case 1:
201 case 2:
202 case 3:
203 ASSERT_EQ(UINT64_C(2803200000), cpuinfo_get_core(i)->frequency);
204 break;
205 case 4:
206 case 5:
207 case 6:
208 case 7:
209 ASSERT_EQ(UINT64_C(1766400000), cpuinfo_get_core(i)->frequency);
210 break;
211 }
212 }
213}
214
215TEST(PACKAGES, count) {
216 ASSERT_EQ(1, cpuinfo_get_packages_count());
217}
218
219TEST(PACKAGES, name) {
220 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
221 ASSERT_EQ("Qualcomm Snapdragon 845",
222 std::string(cpuinfo_get_package(i)->name,
223 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
224 }
225}
226
227TEST(PACKAGES, gpu_name) {
228 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
229 ASSERT_EQ("Qualcomm Adreno 630",
230 std::string(cpuinfo_get_package(i)->gpu_name,
231 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
232 }
233}
234
235TEST(PACKAGES, processor_start) {
236 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
237 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
238 }
239}
240
241TEST(PACKAGES, processor_count) {
242 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
243 ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count);
244 }
245}
246
247TEST(PACKAGES, core_start) {
248 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
249 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
250 }
251}
252
253TEST(PACKAGES, core_count) {
254 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
255 ASSERT_EQ(8, cpuinfo_get_package(i)->core_count);
256 }
257}
258
Marat Dukhan2b307932018-03-18 16:15:36 -0700259TEST(PACKAGES, cluster_start) {
260 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
261 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
262 }
263}
264
265TEST(PACKAGES, cluster_count) {
266 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
267 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
268 }
269}
270
Marat Dukhand51d3952018-03-17 19:18:06 -0700271TEST(ISA, thumb) {
272 #if CPUINFO_ARCH_ARM
273 ASSERT_TRUE(cpuinfo_has_arm_thumb());
274 #elif CPUINFO_ARCH_ARM64
275 ASSERT_FALSE(cpuinfo_has_arm_thumb());
276 #endif
277}
278
279TEST(ISA, thumb2) {
280 #if CPUINFO_ARCH_ARM
281 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
282 #elif CPUINFO_ARCH_ARM64
283 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
284 #endif
285}
286
287TEST(ISA, armv5e) {
288 #if CPUINFO_ARCH_ARM
289 ASSERT_TRUE(cpuinfo_has_arm_v5e());
290 #elif CPUINFO_ARCH_ARM64
291 ASSERT_FALSE(cpuinfo_has_arm_v5e());
292 #endif
293}
294
295TEST(ISA, armv6) {
296 #if CPUINFO_ARCH_ARM
297 ASSERT_TRUE(cpuinfo_has_arm_v6());
298 #elif CPUINFO_ARCH_ARM64
299 ASSERT_FALSE(cpuinfo_has_arm_v6());
300 #endif
301}
302
303TEST(ISA, armv6k) {
304 #if CPUINFO_ARCH_ARM
305 ASSERT_TRUE(cpuinfo_has_arm_v6k());
306 #elif CPUINFO_ARCH_ARM64
307 ASSERT_FALSE(cpuinfo_has_arm_v6k());
308 #endif
309}
310
311TEST(ISA, armv7) {
312 #if CPUINFO_ARCH_ARM
313 ASSERT_TRUE(cpuinfo_has_arm_v7());
314 #elif CPUINFO_ARCH_ARM64
315 ASSERT_FALSE(cpuinfo_has_arm_v7());
316 #endif
317}
318
319TEST(ISA, armv7mp) {
320 #if CPUINFO_ARCH_ARM
321 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
322 #elif CPUINFO_ARCH_ARM64
323 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
324 #endif
325}
326
327TEST(ISA, idiv) {
328 ASSERT_TRUE(cpuinfo_has_arm_idiv());
329}
330
331TEST(ISA, vfpv2) {
332 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
333}
334
335TEST(ISA, vfpv3) {
336 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
337}
338
339TEST(ISA, vfpv3_d32) {
340 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
341}
342
343TEST(ISA, vfpv3_fp16) {
344 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
345}
346
347TEST(ISA, vfpv3_fp16_d32) {
348 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
349}
350
351TEST(ISA, vfpv4) {
352 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
353}
354
355TEST(ISA, vfpv4_d32) {
356 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
357}
358
359TEST(ISA, wmmx) {
360 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
361}
362
363TEST(ISA, wmmx2) {
364 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
365}
366
367TEST(ISA, neon) {
368 ASSERT_TRUE(cpuinfo_has_arm_neon());
369}
370
371TEST(ISA, neon_fp16) {
372 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
373}
374
375TEST(ISA, neon_fma) {
376 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
377}
378
379TEST(ISA, atomics) {
380 #if CPUINFO_ARCH_ARM
381 ASSERT_FALSE(cpuinfo_has_arm_atomics());
382 #elif CPUINFO_ARCH_ARM64
383 ASSERT_TRUE(cpuinfo_has_arm_atomics());
384 #endif
385}
386
387TEST(ISA, neon_rdm) {
388 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
389}
390
391TEST(ISA, fp16_arith) {
392 #if CPUINFO_ARCH_ARM
393 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
394 #elif CPUINFO_ARCH_ARM64
395 ASSERT_TRUE(cpuinfo_has_arm_fp16_arith());
396 #endif
397}
398
399TEST(ISA, jscvt) {
400 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
401}
402
403TEST(ISA, fcma) {
404 ASSERT_FALSE(cpuinfo_has_arm_fcma());
405}
406
407TEST(ISA, aes) {
408 ASSERT_TRUE(cpuinfo_has_arm_aes());
409}
410
411TEST(ISA, sha1) {
412 ASSERT_TRUE(cpuinfo_has_arm_sha1());
413}
414
415TEST(ISA, sha2) {
416 ASSERT_TRUE(cpuinfo_has_arm_sha2());
417}
418
419TEST(ISA, pmull) {
420 ASSERT_TRUE(cpuinfo_has_arm_pmull());
421}
422
423TEST(ISA, crc32) {
424 ASSERT_TRUE(cpuinfo_has_arm_crc32());
425}
426
427TEST(L1I, count) {
428 ASSERT_EQ(8, cpuinfo_get_l1i_caches_count());
429}
430
431TEST(L1I, non_null) {
432 ASSERT_TRUE(cpuinfo_get_l1i_caches());
433}
434
435TEST(L1I, DISABLED_size) {
436 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
437 switch (i) {
438 case 0:
439 case 1:
440 case 2:
441 case 3:
442 ASSERT_EQ(64 * 1024, cpuinfo_get_l1i_cache(i)->size);
443 break;
444 case 4:
445 case 5:
446 case 6:
447 case 7:
448 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
449 break;
450 }
451 }
452}
453
454TEST(L1I, DISABLED_associativity) {
455 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
456 ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity);
457 }
458}
459
460TEST(L1I, sets) {
461 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
462 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
463 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
464 }
465}
466
467TEST(L1I, partitions) {
468 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
469 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
470 }
471}
472
473TEST(L1I, line_size) {
474 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
475 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
476 }
477}
478
479TEST(L1I, flags) {
480 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
481 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
482 }
483}
484
485TEST(L1I, processors) {
486 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
487 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
488 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
489 }
490}
491
492TEST(L1D, count) {
493 ASSERT_EQ(8, cpuinfo_get_l1d_caches_count());
494}
495
496TEST(L1D, non_null) {
497 ASSERT_TRUE(cpuinfo_get_l1d_caches());
498}
499
500TEST(L1D, DISABLED_size) {
501 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
502 switch (i) {
503 case 0:
504 case 1:
505 case 2:
506 case 3:
507 ASSERT_EQ(64 * 1024, cpuinfo_get_l1d_cache(i)->size);
508 break;
509 case 4:
510 case 5:
511 case 6:
512 case 7:
513 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
514 break;
515 }
516 }
517}
518
519TEST(L1D, DISABLED_associativity) {
520 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
521 switch (i) {
522 case 0:
523 case 1:
524 case 2:
525 case 3:
526 ASSERT_EQ(16, cpuinfo_get_l1d_cache(i)->associativity);
527 break;
528 case 4:
529 case 5:
530 case 6:
531 case 7:
532 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
533 break;
534 }
535 }
536}
537
538TEST(L1D, sets) {
539 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
540 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
541 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
542 }
543}
544
545TEST(L1D, partitions) {
546 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
547 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
548 }
549}
550
551TEST(L1D, line_size) {
552 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
553 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
554 }
555}
556
557TEST(L1D, flags) {
558 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
559 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
560 }
561}
562
563TEST(L1D, processors) {
564 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
565 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
566 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
567 }
568}
569
570TEST(L2, DISABLED_count) {
571 ASSERT_EQ(8, cpuinfo_get_l2_caches_count());
572}
573
574TEST(L2, non_null) {
575 ASSERT_TRUE(cpuinfo_get_l2_caches());
576}
577
578TEST(L2, DISABLED_size) {
579 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
580 switch (i) {
581 case 0:
582 case 1:
583 case 2:
584 case 3:
585 ASSERT_EQ(128 * 1024, cpuinfo_get_l2_cache(i)->size);
586 break;
587 case 4:
588 case 5:
589 case 6:
590 case 7:
591 ASSERT_EQ(256 * 1024, cpuinfo_get_l2_cache(i)->size);
592 break;
593 }
594 }
595}
596
597TEST(L2, DISABLED_associativity) {
598 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
599 switch (i) {
600 case 0:
601 case 1:
602 case 2:
603 case 3:
604 ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity);
605 break;
606 case 4:
607 case 5:
608 case 6:
609 case 7:
610 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->associativity);
611 break;
612 }
613 }
614}
615
616TEST(L2, sets) {
617 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
618 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
619 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
620 }
621}
622
623TEST(L2, partitions) {
624 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
625 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
626 }
627}
628
629TEST(L2, line_size) {
630 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
631 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
632 }
633}
634
635TEST(L2, DISABLED_flags) {
636 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
637 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
638 }
639}
640
641TEST(L2, DISABLED_processors) {
642 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
643 ASSERT_EQ(i, cpuinfo_get_l2_cache(i)->processor_start);
644 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->processor_count);
645 }
646}
647
648TEST(L3, DISABLED_count) {
649 ASSERT_EQ(1, cpuinfo_get_l3_caches_count());
650}
651
652TEST(L3, DISABLED_non_null) {
653 ASSERT_TRUE(cpuinfo_get_l3_caches());
654}
655
656TEST(L3, DISABLED_size) {
657 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
658 ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l3_cache(i)->size);
659 }
660}
661
662TEST(L3, DISABLED_associativity) {
663 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
664 ASSERT_EQ(8, cpuinfo_get_l3_cache(i)->associativity);
665 }
666}
667
668TEST(L3, sets) {
669 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
670 ASSERT_EQ(cpuinfo_get_l3_cache(i)->size,
671 cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity);
672 }
673}
674
675TEST(L3, partitions) {
676 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
677 ASSERT_EQ(1, cpuinfo_get_l3_cache(i)->partitions);
678 }
679}
680
681TEST(L3, line_size) {
682 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
683 ASSERT_EQ(64, cpuinfo_get_l3_cache(i)->line_size);
684 }
685}
686
687TEST(L3, DISABLED_flags) {
688 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
689 ASSERT_EQ(0, cpuinfo_get_l3_cache(i)->flags);
690 }
691}
692
693TEST(L3, processors) {
694 for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) {
695 ASSERT_EQ(0, cpuinfo_get_l3_cache(i)->processor_start);
696 ASSERT_EQ(8, cpuinfo_get_l3_cache(i)->processor_count);
697 }
698}
699
700TEST(L4, none) {
701 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
702 ASSERT_FALSE(cpuinfo_get_l4_caches());
703}
704
705#include <galaxy-s9-us.h>
706
707int main(int argc, char* argv[]) {
708#if CPUINFO_ARCH_ARM
709 cpuinfo_set_hwcap(UINT32_C(0x0037B0D6));
710 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
711#elif CPUINFO_ARCH_ARM64
712 cpuinfo_set_hwcap(UINT32_C(0x000007FF));
713#endif
714 cpuinfo_mock_filesystem(filesystem);
715#ifdef __ANDROID__
716 cpuinfo_mock_android_properties(properties);
717 cpuinfo_mock_gl_renderer("Adreno (TM) 630");
718#endif
719 cpuinfo_initialize();
720 ::testing::InitGoogleTest(&argc, argv);
721 return RUN_ALL_TESTS();
722}