blob: 99c2752266ac04679034df6ac3cfd38095338afe [file] [log] [blame]
Marat Dukhan65b05d22017-08-11 00:53:02 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
Marat Dukhan30401972017-09-26 18:35:52 -07008 ASSERT_EQ(6, cpuinfo_get_processors_count());
Marat Dukhan65b05d22017-08-11 00:53:02 -07009}
10
11TEST(PROCESSORS, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070012 ASSERT_TRUE(cpuinfo_get_processors());
Marat Dukhan65b05d22017-08-11 00:53:02 -070013}
14
Marat Dukhan2d37dc42017-09-25 01:32:37 -070015TEST(PROCESSORS, smt_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070016 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
Marat Dukhan65b05d22017-08-11 00:53:02 -070018 }
19}
20
Marat Dukhan2d37dc42017-09-25 01:32:37 -070021TEST(PROCESSORS, core) {
Marat Dukhan30401972017-09-26 18:35:52 -070022 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070024 }
25}
26
Marat Dukhan2b307932018-03-18 16:15:36 -070027TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 switch (i) {
30 case 0:
31 case 1:
32 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
33 break;
34 case 2:
35 case 3:
36 case 4:
37 case 5:
38 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
39 break;
40 }
41 }
42}
43
Marat Dukhan2d37dc42017-09-25 01:32:37 -070044TEST(PROCESSORS, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070045 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
46 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
Marat Dukhan65b05d22017-08-11 00:53:02 -070047 }
48}
49
Marat Dukhan846c1782017-09-13 09:47:26 -070050TEST(PROCESSORS, linux_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070051 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan846c1782017-09-13 09:47:26 -070052 switch (i) {
53 case 0:
54 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -070055 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070056 break;
57 case 2:
58 case 3:
59 case 4:
60 case 5:
Marat Dukhan30401972017-09-26 18:35:52 -070061 ASSERT_EQ(i - 2, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070062 break;
63 }
64 }
65}
66
Marat Dukhan2d37dc42017-09-25 01:32:37 -070067TEST(PROCESSORS, l1i) {
Marat Dukhan30401972017-09-26 18:35:52 -070068 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
69 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070070 }
71}
72
73TEST(PROCESSORS, l1d) {
Marat Dukhan30401972017-09-26 18:35:52 -070074 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
75 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070076 }
77}
78
79TEST(PROCESSORS, l2) {
Marat Dukhan30401972017-09-26 18:35:52 -070080 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -070081 switch (i) {
82 case 0:
83 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -070084 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070085 break;
86 case 2:
87 case 3:
88 case 4:
89 case 5:
Marat Dukhan30401972017-09-26 18:35:52 -070090 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070091 break;
92 }
93 }
94}
95
96TEST(PROCESSORS, l3) {
Marat Dukhan30401972017-09-26 18:35:52 -070097 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
98 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070099 }
100}
101
102TEST(PROCESSORS, l4) {
Marat Dukhan30401972017-09-26 18:35:52 -0700103 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
104 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700105 }
106}
107
Marat Dukhan7073e832017-09-24 22:23:55 -0700108TEST(CORES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700109 ASSERT_EQ(6, cpuinfo_get_cores_count());
Marat Dukhan7073e832017-09-24 22:23:55 -0700110}
111
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700112TEST(CORES, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700113 ASSERT_TRUE(cpuinfo_get_cores());
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700114}
115
Marat Dukhan7073e832017-09-24 22:23:55 -0700116TEST(CORES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700117 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
118 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
Marat Dukhan7073e832017-09-24 22:23:55 -0700119 }
120}
121
122TEST(CORES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700123 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
124 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
Marat Dukhan7073e832017-09-24 22:23:55 -0700125 }
126}
127
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700128TEST(CORES, core_id) {
Marat Dukhan30401972017-09-26 18:35:52 -0700129 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
130 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700131 }
132}
133
Marat Dukhan2b307932018-03-18 16:15:36 -0700134TEST(CORES, cluster) {
135 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
136 switch (i) {
137 case 0:
138 case 1:
139 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
140 break;
141 case 2:
142 case 3:
143 case 4:
144 case 5:
145 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
146 break;
147 }
148 }
149}
150
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700151TEST(CORES, package) {
Marat Dukhan30401972017-09-26 18:35:52 -0700152 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
153 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700154 }
155}
156
157TEST(CORES, vendor) {
Marat Dukhan30401972017-09-26 18:35:52 -0700158 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
159 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700160 }
161}
162
163TEST(CORES, uarch) {
Marat Dukhan30401972017-09-26 18:35:52 -0700164 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700165 switch (i) {
166 case 0:
167 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700168 ASSERT_EQ(cpuinfo_uarch_cortex_a57, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700169 break;
170 case 2:
171 case 3:
172 case 4:
173 case 5:
Marat Dukhan30401972017-09-26 18:35:52 -0700174 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700175 break;
176 }
177 }
178}
179
180TEST(CORES, midr) {
Marat Dukhan30401972017-09-26 18:35:52 -0700181 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700182 switch (i) {
183 case 0:
184 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700185 ASSERT_EQ(UINT32_C(0x411FD072), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700186 break;
187 case 2:
188 case 3:
189 case 4:
190 case 5:
Marat Dukhan30401972017-09-26 18:35:52 -0700191 ASSERT_EQ(UINT32_C(0x410FD033), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700192 break;
193 }
194 }
195}
196
Marat Dukhan575a6302018-03-10 14:38:49 -0800197TEST(CORES, DISABLED_frequency) {
198 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
199 switch (i) {
200 case 0:
201 case 1:
202 ASSERT_EQ(UINT64_C(1824000000), cpuinfo_get_core(i)->frequency);
203 break;
204 case 2:
205 case 3:
206 case 4:
207 case 5:
208 ASSERT_EQ(UINT64_C(1440000000), cpuinfo_get_core(i)->frequency);
209 break;
210 }
211 }
212}
213
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700214TEST(PACKAGES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700215 ASSERT_EQ(1, cpuinfo_get_packages_count());
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700216}
217
218TEST(PACKAGES, name) {
Marat Dukhan30401972017-09-26 18:35:52 -0700219 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700220 ASSERT_EQ("Qualcomm MSM8992",
Marat Dukhan30401972017-09-26 18:35:52 -0700221 std::string(cpuinfo_get_package(i)->name,
222 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700223 }
224}
225
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800226TEST(PACKAGES, gpu_name) {
227 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
228 ASSERT_EQ("Qualcomm Adreno 418",
229 std::string(cpuinfo_get_package(i)->gpu_name,
230 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
231 }
232}
233
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700234TEST(PACKAGES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700235 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
236 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700237 }
238}
239
240TEST(PACKAGES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700241 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
242 ASSERT_EQ(6, cpuinfo_get_package(i)->processor_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700243 }
244}
245
246TEST(PACKAGES, core_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700247 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
248 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700249 }
250}
251
252TEST(PACKAGES, core_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700253 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
254 ASSERT_EQ(6, cpuinfo_get_package(i)->core_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700255 }
256}
257
Marat Dukhan2b307932018-03-18 16:15:36 -0700258TEST(PACKAGES, cluster_start) {
259 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
260 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
261 }
262}
263
264TEST(PACKAGES, cluster_count) {
265 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
266 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
267 }
268}
269
Marat Dukhan65b05d22017-08-11 00:53:02 -0700270TEST(ISA, thumb) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700271 #if CPUINFO_ARCH_ARM
272 ASSERT_TRUE(cpuinfo_has_arm_thumb());
273 #elif CPUINFO_ARCH_ARM64
274 ASSERT_FALSE(cpuinfo_has_arm_thumb());
275 #endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700276}
277
278TEST(ISA, thumb2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700279 #if CPUINFO_ARCH_ARM
280 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
281 #elif CPUINFO_ARCH_ARM64
282 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
283 #endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700284}
285
286TEST(ISA, armv5e) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700287 #if CPUINFO_ARCH_ARM
288 ASSERT_TRUE(cpuinfo_has_arm_v5e());
289 #elif CPUINFO_ARCH_ARM64
290 ASSERT_FALSE(cpuinfo_has_arm_v5e());
291 #endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700292}
293
294TEST(ISA, armv6) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700295 #if CPUINFO_ARCH_ARM
296 ASSERT_TRUE(cpuinfo_has_arm_v6());
297 #elif CPUINFO_ARCH_ARM64
298 ASSERT_FALSE(cpuinfo_has_arm_v6());
299 #endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700300}
301
302TEST(ISA, armv6k) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700303 #if CPUINFO_ARCH_ARM
304 ASSERT_TRUE(cpuinfo_has_arm_v6k());
305 #elif CPUINFO_ARCH_ARM64
306 ASSERT_FALSE(cpuinfo_has_arm_v6k());
307 #endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700308}
309
310TEST(ISA, armv7) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700311 #if CPUINFO_ARCH_ARM
312 ASSERT_TRUE(cpuinfo_has_arm_v7());
313 #elif CPUINFO_ARCH_ARM64
314 ASSERT_FALSE(cpuinfo_has_arm_v7());
315 #endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700316}
317
318TEST(ISA, armv7mp) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700319 #if CPUINFO_ARCH_ARM
320 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
321 #elif CPUINFO_ARCH_ARM64
322 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
323 #endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700324}
325
326TEST(ISA, idiv) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700327 ASSERT_TRUE(cpuinfo_has_arm_idiv());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700328}
329
330TEST(ISA, vfpv2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700331 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700332}
333
334TEST(ISA, vfpv3) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700335 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700336}
337
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700338TEST(ISA, vfpv3_d32) {
339 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700340}
341
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700342TEST(ISA, vfpv3_fp16) {
343 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700344}
345
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700346TEST(ISA, vfpv3_fp16_d32) {
347 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
348}
349
350TEST(ISA, vfpv4) {
351 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
352}
353
354TEST(ISA, vfpv4_d32) {
355 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700356}
357
358TEST(ISA, wmmx) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700359 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700360}
361
362TEST(ISA, wmmx2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700363 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700364}
365
366TEST(ISA, neon) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700367 ASSERT_TRUE(cpuinfo_has_arm_neon());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700368}
369
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700370TEST(ISA, neon_fp16) {
371 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700372}
373
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700374TEST(ISA, neon_fma) {
375 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700376}
377
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700378TEST(ISA, atomics) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700379 ASSERT_FALSE(cpuinfo_has_arm_atomics());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700380}
381
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700382TEST(ISA, neon_rdm) {
383 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700384}
385
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700386TEST(ISA, fp16_arith) {
387 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700388}
389
390TEST(ISA, jscvt) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700391 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700392}
393
394TEST(ISA, fcma) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700395 ASSERT_FALSE(cpuinfo_has_arm_fcma());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700396}
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700397
398TEST(ISA, aes) {
399 ASSERT_TRUE(cpuinfo_has_arm_aes());
400}
401
402TEST(ISA, sha1) {
403 ASSERT_TRUE(cpuinfo_has_arm_sha1());
404}
405
406TEST(ISA, sha2) {
407 ASSERT_TRUE(cpuinfo_has_arm_sha2());
408}
409
410TEST(ISA, pmull) {
411 ASSERT_TRUE(cpuinfo_has_arm_pmull());
412}
413
414TEST(ISA, crc32) {
415 ASSERT_TRUE(cpuinfo_has_arm_crc32());
416}
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700417
Marat Dukhan65b05d22017-08-11 00:53:02 -0700418TEST(L1I, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700419 ASSERT_EQ(6, cpuinfo_get_l1i_caches_count());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700420}
421
422TEST(L1I, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700423 ASSERT_TRUE(cpuinfo_get_l1i_caches());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700424}
425
426TEST(L1I, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700427 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
428 switch (i) {
Marat Dukhan65b05d22017-08-11 00:53:02 -0700429 case 0:
430 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700431 ASSERT_EQ(48 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700432 break;
433 case 2:
434 case 3:
435 case 4:
436 case 5:
Marat Dukhan30401972017-09-26 18:35:52 -0700437 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700438 break;
439 }
440 }
441}
442
443TEST(L1I, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700444 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
445 switch (i) {
Marat Dukhan65b05d22017-08-11 00:53:02 -0700446 case 0:
447 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700448 ASSERT_EQ(3, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700449 break;
450 case 2:
451 case 3:
452 case 4:
453 case 5:
Marat Dukhan30401972017-09-26 18:35:52 -0700454 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700455 break;
456 }
457 }
458}
459
460TEST(L1I, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700461 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
462 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
463 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700464 }
465}
466
467TEST(L1I, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700468 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
469 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700470 }
471}
472
473TEST(L1I, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700474 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
475 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700476 }
477}
478
479TEST(L1I, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700480 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
481 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700482 }
483}
484
485TEST(L1I, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700486 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
487 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
488 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700489 }
490}
491
492TEST(L1D, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700493 ASSERT_EQ(6, cpuinfo_get_l1d_caches_count());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700494}
495
496TEST(L1D, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700497 ASSERT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700498}
499
500TEST(L1D, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700501 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
502 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700503 }
504}
505
506TEST(L1D, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700507 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
508 switch (i) {
Marat Dukhan65b05d22017-08-11 00:53:02 -0700509 case 0:
510 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700511 ASSERT_EQ(2, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700512 break;
513 case 2:
514 case 3:
515 case 4:
516 case 5:
Marat Dukhan30401972017-09-26 18:35:52 -0700517 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700518 break;
519 }
520 }
521}
522
523TEST(L1D, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700524 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
525 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
526 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700527 }
528}
529
530TEST(L1D, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700531 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
532 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700533 }
534}
535
536TEST(L1D, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700537 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
538 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700539 }
540}
541
542TEST(L1D, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700543 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
544 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700545 }
546}
547
548TEST(L1D, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700549 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
550 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
551 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700552 }
553}
554
555TEST(L2, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700556 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700557}
558
559TEST(L2, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700560 ASSERT_TRUE(cpuinfo_get_l2_caches());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700561}
562
563TEST(L2, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700564 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
565 switch (i) {
Marat Dukhan65b05d22017-08-11 00:53:02 -0700566 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700567 ASSERT_EQ(1 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700568 break;
569 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700570 ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700571 break;
572 }
573 }
574}
575
576TEST(L2, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700577 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
578 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700579 }
580}
581
582TEST(L2, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700583 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
584 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
585 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700586 }
587}
588
589TEST(L2, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700590 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
591 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700592 }
593}
594
595TEST(L2, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700596 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
597 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700598 }
599}
600
601TEST(L2, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700602 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
603 switch (i) {
Marat Dukhanb33716e2017-08-31 12:50:10 -0700604 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700605 ASSERT_EQ(CPUINFO_CACHE_INCLUSIVE, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhanb33716e2017-08-31 12:50:10 -0700606 break;
607 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700608 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhanb33716e2017-08-31 12:50:10 -0700609 break;
610 }
Marat Dukhan65b05d22017-08-11 00:53:02 -0700611 }
612}
613
614TEST(L2, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700615 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
616 switch (i) {
Marat Dukhan65b05d22017-08-11 00:53:02 -0700617 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700618 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
619 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700620 break;
621 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700622 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_start);
623 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan65b05d22017-08-11 00:53:02 -0700624 break;
625 }
626 }
627}
628
629TEST(L3, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700630 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
631 ASSERT_FALSE(cpuinfo_get_l3_caches());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700632}
633
634TEST(L4, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700635 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
636 ASSERT_FALSE(cpuinfo_get_l4_caches());
Marat Dukhan65b05d22017-08-11 00:53:02 -0700637}
638
639#include <nexus5x.h>
640
641int main(int argc, char* argv[]) {
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800642#if CPUINFO_ARCH_ARM
643 cpuinfo_set_hwcap(UINT32_C(0x0027B0D6));
644 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
645#elif CPUINFO_ARCH_ARM64
646 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
647#endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700648 cpuinfo_mock_filesystem(filesystem);
Marat Dukhan5659d292017-09-12 23:21:03 -0700649#ifdef __ANDROID__
650 cpuinfo_mock_android_properties(properties);
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800651 cpuinfo_mock_gl_renderer("Adreno (TM) 418");
Marat Dukhan5659d292017-09-12 23:21:03 -0700652#endif
Marat Dukhan65b05d22017-08-11 00:53:02 -0700653 cpuinfo_initialize();
654 ::testing::InitGoogleTest(&argc, argv);
655 return RUN_ALL_TESTS();
Marat Dukhan30401972017-09-26 18:35:52 -0700656}