blob: 9b2bb276d0c47f246ef90f2ae4cc3216e89f7e6a [file] [log] [blame]
Marat Dukhanac576322017-05-08 13:08:25 +00001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
Marat Dukhan30401972017-09-26 18:35:52 -07008 ASSERT_EQ(4, cpuinfo_get_processors_count());
Marat Dukhanac576322017-05-08 13:08:25 +00009}
10
11TEST(PROCESSORS, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070012 ASSERT_TRUE(cpuinfo_get_processors());
Marat Dukhanac576322017-05-08 13:08:25 +000013}
14
Marat Dukhan2d37dc42017-09-25 01:32:37 -070015TEST(PROCESSORS, smt_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070016 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
Marat Dukhanac576322017-05-08 13:08:25 +000018 }
19}
20
Marat Dukhan2d37dc42017-09-25 01:32:37 -070021TEST(PROCESSORS, core) {
Marat Dukhan30401972017-09-26 18:35:52 -070022 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070024 }
25}
26
27TEST(PROCESSORS, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070028 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
Marat Dukhanac576322017-05-08 13:08:25 +000030 }
31}
32
Marat Dukhan846c1782017-09-13 09:47:26 -070033TEST(PROCESSORS, linux_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070034 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
35 ASSERT_EQ(i, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070036 }
37}
38
Marat Dukhan2d37dc42017-09-25 01:32:37 -070039TEST(PROCESSORS, l1i) {
Marat Dukhan30401972017-09-26 18:35:52 -070040 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
41 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070042 }
43}
44
45TEST(PROCESSORS, l1d) {
Marat Dukhan30401972017-09-26 18:35:52 -070046 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
47 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070048 }
49}
50
51TEST(PROCESSORS, l2) {
Marat Dukhan30401972017-09-26 18:35:52 -070052 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
53 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070054 }
55}
56
57TEST(PROCESSORS, l3) {
Marat Dukhan30401972017-09-26 18:35:52 -070058 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
59 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070060 }
61}
62
63TEST(PROCESSORS, l4) {
Marat Dukhan30401972017-09-26 18:35:52 -070064 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
65 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070066 }
67}
68
Marat Dukhan7073e832017-09-24 22:23:55 -070069TEST(CORES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -070070 ASSERT_EQ(4, cpuinfo_get_cores_count());
Marat Dukhan7073e832017-09-24 22:23:55 -070071}
72
Marat Dukhan2d37dc42017-09-25 01:32:37 -070073TEST(CORES, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070074 ASSERT_TRUE(cpuinfo_get_cores());
Marat Dukhan2d37dc42017-09-25 01:32:37 -070075}
76
Marat Dukhan7073e832017-09-24 22:23:55 -070077TEST(CORES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -070078 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
79 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
Marat Dukhan7073e832017-09-24 22:23:55 -070080 }
81}
82
83TEST(CORES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -070084 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
85 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
Marat Dukhan7073e832017-09-24 22:23:55 -070086 }
87}
88
Marat Dukhan2d37dc42017-09-25 01:32:37 -070089TEST(CORES, core_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070090 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
91 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070092 }
93}
94
95TEST(CORES, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070096 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
97 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070098 }
99}
100
101TEST(CORES, vendor) {
Marat Dukhan30401972017-09-26 18:35:52 -0700102 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
103 ASSERT_EQ(cpuinfo_vendor_qualcomm, cpuinfo_get_core(i)->vendor);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700104 }
105}
106
107TEST(CORES, uarch) {
Marat Dukhan30401972017-09-26 18:35:52 -0700108 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
109 ASSERT_EQ(cpuinfo_uarch_krait, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700110 }
111}
112
113TEST(CORES, midr) {
Marat Dukhan30401972017-09-26 18:35:52 -0700114 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
115 ASSERT_EQ(UINT32_C(0x510F06F2), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700116 }
117}
118
Marat Dukhan575a6302018-03-10 14:38:49 -0800119TEST(CORES, DISABLED_frequency) {
120 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
121 ASSERT_EQ(UINT64_C(1512000000), cpuinfo_get_core(i)->frequency);
122 }
123}
124
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700125TEST(PACKAGES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700126 ASSERT_EQ(1, cpuinfo_get_packages_count());
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700127}
128
129TEST(PACKAGES, name) {
Marat Dukhan30401972017-09-26 18:35:52 -0700130 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700131 ASSERT_EQ("Qualcomm APQ8064",
Marat Dukhan30401972017-09-26 18:35:52 -0700132 std::string(cpuinfo_get_package(i)->name,
133 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700134 }
135}
136
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800137TEST(PACKAGES, gpu_name) {
138 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
139 ASSERT_EQ("Qualcomm Adreno 320",
140 std::string(cpuinfo_get_package(i)->gpu_name,
141 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
142 }
143}
144
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700145TEST(PACKAGES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700146 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
147 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700148 }
149}
150
151TEST(PACKAGES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700152 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
153 ASSERT_EQ(4, cpuinfo_get_package(i)->processor_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700154 }
155}
156
157TEST(PACKAGES, core_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700158 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
159 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700160 }
161}
162
163TEST(PACKAGES, core_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700164 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
165 ASSERT_EQ(4, cpuinfo_get_package(i)->core_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700166 }
167}
168
Marat Dukhanac576322017-05-08 13:08:25 +0000169TEST(ISA, thumb) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700170 ASSERT_TRUE(cpuinfo_has_arm_thumb());
Marat Dukhanac576322017-05-08 13:08:25 +0000171}
172
173TEST(ISA, thumb2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700174 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
Marat Dukhanac576322017-05-08 13:08:25 +0000175}
176
177TEST(ISA, armv5e) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700178 ASSERT_TRUE(cpuinfo_has_arm_v5e());
Marat Dukhanac576322017-05-08 13:08:25 +0000179}
180
181TEST(ISA, armv6) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700182 ASSERT_TRUE(cpuinfo_has_arm_v6());
Marat Dukhanac576322017-05-08 13:08:25 +0000183}
184
185TEST(ISA, armv6k) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700186 ASSERT_TRUE(cpuinfo_has_arm_v6k());
Marat Dukhanac576322017-05-08 13:08:25 +0000187}
188
189TEST(ISA, armv7) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700190 ASSERT_TRUE(cpuinfo_has_arm_v7());
Marat Dukhanac576322017-05-08 13:08:25 +0000191}
192
193TEST(ISA, armv7mp) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700194 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
Marat Dukhanac576322017-05-08 13:08:25 +0000195}
196
197TEST(ISA, idiv) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700198 ASSERT_TRUE(cpuinfo_has_arm_idiv());
Marat Dukhanac576322017-05-08 13:08:25 +0000199}
200
201TEST(ISA, vfpv2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700202 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
Marat Dukhanac576322017-05-08 13:08:25 +0000203}
204
205TEST(ISA, vfpv3) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700206 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
Marat Dukhanac576322017-05-08 13:08:25 +0000207}
208
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700209TEST(ISA, vfpv3_d32) {
210 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
Marat Dukhanac576322017-05-08 13:08:25 +0000211}
212
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700213TEST(ISA, vfpv3_fp16) {
214 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
Marat Dukhanac576322017-05-08 13:08:25 +0000215}
216
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700217TEST(ISA, vfpv3_fp16_d32) {
218 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
219}
220
221TEST(ISA, vfpv4) {
222 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
223}
224
225TEST(ISA, vfpv4_d32) {
226 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
Marat Dukhanac576322017-05-08 13:08:25 +0000227}
228
229TEST(ISA, wmmx) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700230 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
Marat Dukhanac576322017-05-08 13:08:25 +0000231}
232
233TEST(ISA, wmmx2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700234 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
Marat Dukhanac576322017-05-08 13:08:25 +0000235}
236
237TEST(ISA, neon) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700238 ASSERT_TRUE(cpuinfo_has_arm_neon());
239}
240
241TEST(ISA, neon_fp16) {
242 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
243}
244
245TEST(ISA, neon_fma) {
246 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
247}
248
249TEST(ISA, atomics) {
250 ASSERT_FALSE(cpuinfo_has_arm_atomics());
251}
252
253TEST(ISA, neon_rdm) {
254 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
255}
256
257TEST(ISA, fp16_arith) {
258 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
259}
260
261TEST(ISA, jscvt) {
262 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
263}
264
265TEST(ISA, fcma) {
266 ASSERT_FALSE(cpuinfo_has_arm_fcma());
Marat Dukhanac576322017-05-08 13:08:25 +0000267}
268
269TEST(ISA, aes) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700270 ASSERT_FALSE(cpuinfo_has_arm_aes());
Marat Dukhanac576322017-05-08 13:08:25 +0000271}
272
273TEST(ISA, sha1) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700274 ASSERT_FALSE(cpuinfo_has_arm_sha1());
Marat Dukhanac576322017-05-08 13:08:25 +0000275}
276
277TEST(ISA, sha2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700278 ASSERT_FALSE(cpuinfo_has_arm_sha2());
Marat Dukhanac576322017-05-08 13:08:25 +0000279}
280
281TEST(ISA, pmull) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700282 ASSERT_FALSE(cpuinfo_has_arm_pmull());
Marat Dukhanac576322017-05-08 13:08:25 +0000283}
284
285TEST(ISA, crc32) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700286 ASSERT_FALSE(cpuinfo_has_arm_crc32());
Marat Dukhanac576322017-05-08 13:08:25 +0000287}
288
289TEST(L1I, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700290 ASSERT_EQ(4, cpuinfo_get_l1i_caches_count());
Marat Dukhanac576322017-05-08 13:08:25 +0000291}
292
293TEST(L1I, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700294 ASSERT_TRUE(cpuinfo_get_l1i_caches());
Marat Dukhanac576322017-05-08 13:08:25 +0000295}
296
297TEST(L1I, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700298 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
299 ASSERT_EQ(16 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhanac576322017-05-08 13:08:25 +0000300 }
301}
302
303TEST(L1I, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700304 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
305 ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhanac576322017-05-08 13:08:25 +0000306 }
307}
308
309TEST(L1I, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700310 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
311 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
312 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhanac576322017-05-08 13:08:25 +0000313 }
314}
315
316TEST(L1I, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700317 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
318 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
Marat Dukhanac576322017-05-08 13:08:25 +0000319 }
320}
321
322TEST(L1I, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700323 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
324 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhanac576322017-05-08 13:08:25 +0000325 }
326}
327
328TEST(L1I, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700329 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
330 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
Marat Dukhanac576322017-05-08 13:08:25 +0000331 }
332}
333
334TEST(L1I, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700335 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
336 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
337 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
Marat Dukhanac576322017-05-08 13:08:25 +0000338 }
339}
340
341TEST(L1D, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700342 ASSERT_EQ(4, cpuinfo_get_l1d_caches_count());
Marat Dukhanac576322017-05-08 13:08:25 +0000343}
344
345TEST(L1D, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700346 ASSERT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhanac576322017-05-08 13:08:25 +0000347}
348
349TEST(L1D, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700350 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
351 ASSERT_EQ(16 * 1024, cpuinfo_get_l1d_cache(i)->size);
Marat Dukhanac576322017-05-08 13:08:25 +0000352 }
353}
354
355TEST(L1D, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700356 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
357 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhanac576322017-05-08 13:08:25 +0000358 }
359}
360
361TEST(L1D, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700362 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
363 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
364 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhanac576322017-05-08 13:08:25 +0000365 }
366}
367
368TEST(L1D, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700369 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
370 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
Marat Dukhanac576322017-05-08 13:08:25 +0000371 }
372}
373
374TEST(L1D, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700375 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
376 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
Marat Dukhanac576322017-05-08 13:08:25 +0000377 }
378}
379
380TEST(L1D, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700381 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
382 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
Marat Dukhanac576322017-05-08 13:08:25 +0000383 }
384}
385
386TEST(L1D, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700387 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
388 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
389 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
Marat Dukhanac576322017-05-08 13:08:25 +0000390 }
391}
392
393TEST(L2, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700394 ASSERT_EQ(1, cpuinfo_get_l2_caches_count());
Marat Dukhanac576322017-05-08 13:08:25 +0000395}
396
397TEST(L2, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700398 ASSERT_TRUE(cpuinfo_get_l2_caches());
Marat Dukhanac576322017-05-08 13:08:25 +0000399}
400
401TEST(L2, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700402 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
403 ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhanac576322017-05-08 13:08:25 +0000404 }
405}
406
407TEST(L2, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700408 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
409 ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhanac576322017-05-08 13:08:25 +0000410 }
411}
412
413TEST(L2, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700414 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
415 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
416 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhanac576322017-05-08 13:08:25 +0000417 }
418}
419
420TEST(L2, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700421 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
422 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
Marat Dukhanac576322017-05-08 13:08:25 +0000423 }
424}
425
426TEST(L2, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700427 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
428 ASSERT_EQ(128, cpuinfo_get_l2_cache(i)->line_size);
Marat Dukhanac576322017-05-08 13:08:25 +0000429 }
430}
431
432TEST(L2, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700433 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
434 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhanac576322017-05-08 13:08:25 +0000435 }
436}
437
438TEST(L2, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700439 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
440 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
441 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhanac576322017-05-08 13:08:25 +0000442 }
443}
444
445TEST(L3, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700446 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
447 ASSERT_FALSE(cpuinfo_get_l3_caches());
Marat Dukhanac576322017-05-08 13:08:25 +0000448}
449
450TEST(L4, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700451 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
452 ASSERT_FALSE(cpuinfo_get_l4_caches());
Marat Dukhanac576322017-05-08 13:08:25 +0000453}
454
Marat Dukhan079ccbd2017-08-09 17:00:32 -0700455#include <nexus4.h>
456
Marat Dukhanac576322017-05-08 13:08:25 +0000457int main(int argc, char* argv[]) {
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800458#if CPUINFO_ARCH_ARM
459 cpuinfo_set_hwcap(UINT32_C(0x0001B0D7));
460#endif
Marat Dukhan079ccbd2017-08-09 17:00:32 -0700461 cpuinfo_mock_filesystem(filesystem);
Marat Dukhan5659d292017-09-12 23:21:03 -0700462#ifdef __ANDROID__
463 cpuinfo_mock_android_properties(properties);
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800464 cpuinfo_mock_gl_renderer("Adreno (TM) 320");
Marat Dukhan5659d292017-09-12 23:21:03 -0700465#endif
Marat Dukhanac576322017-05-08 13:08:25 +0000466 cpuinfo_initialize();
467 ::testing::InitGoogleTest(&argc, argv);
468 return RUN_ALL_TESTS();
Marat Dukhan30401972017-09-26 18:35:52 -0700469}