Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 1 | #pragma once |
| 2 | #ifndef CPUINFO_H |
| 3 | #define CPUINFO_H |
| 4 | |
| 5 | #ifndef __cplusplus |
| 6 | #include <stdbool.h> |
| 7 | #endif |
| 8 | |
Hao Lu | 3617d5b | 2017-10-23 15:16:50 -0700 | [diff] [blame] | 9 | #ifdef __APPLE__ |
| 10 | #include <TargetConditionals.h> |
| 11 | #endif |
| 12 | |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 13 | #include <stdint.h> |
| 14 | |
| 15 | /* Identify architecture and define corresponding macro */ |
| 16 | |
| 17 | #if defined(__i386__) || defined(__i486__) || defined(__i586__) || defined(__i686__) || defined(_M_IX86) |
| 18 | #define CPUINFO_ARCH_X86 1 |
| 19 | #endif |
| 20 | |
| 21 | #if defined(__x86_64__) || defined(__x86_64) || defined(_M_X64) || defined(_M_AMD64) |
| 22 | #define CPUINFO_ARCH_X86_64 1 |
| 23 | #endif |
| 24 | |
| 25 | #if defined(__arm__) || defined(_M_ARM) |
| 26 | #define CPUINFO_ARCH_ARM 1 |
| 27 | #endif |
| 28 | |
| 29 | #if defined(__aarch64__) || defined(_M_ARM64) |
| 30 | #define CPUINFO_ARCH_ARM64 1 |
| 31 | #endif |
| 32 | |
| 33 | #if defined(__PPC64__) || defined(__powerpc64__) || defined(_ARCH_PPC64) |
| 34 | #define CPUINFO_ARCH_PPC64 1 |
| 35 | #endif |
| 36 | |
| 37 | #if defined(__pnacl__) |
| 38 | #define CPUINFO_ARCH_PNACL 1 |
| 39 | #endif |
| 40 | |
| 41 | #if defined(EMSCRIPTEN) |
| 42 | #define CPUINFO_ARCH_ASMJS 1 |
| 43 | #endif |
| 44 | |
| 45 | #if CPUINFO_ARCH_X86 && defined(_MSC_VER) |
| 46 | #define CPUINFO_ABI __cdecl |
| 47 | #elif CPUINFO_ARCH_X86 && defined(__GNUC__) |
| 48 | #define CPUINFO_ABI __attribute__((__cdecl__)) |
| 49 | #else |
| 50 | #define CPUINFO_ABI |
| 51 | #endif |
| 52 | |
| 53 | /* Define other architecture-specific macros as 0 */ |
| 54 | |
| 55 | #ifndef CPUINFO_ARCH_X86 |
| 56 | #define CPUINFO_ARCH_X86 0 |
| 57 | #endif |
| 58 | |
| 59 | #ifndef CPUINFO_ARCH_X86_64 |
| 60 | #define CPUINFO_ARCH_X86_64 0 |
| 61 | #endif |
| 62 | |
| 63 | #ifndef CPUINFO_ARCH_ARM |
| 64 | #define CPUINFO_ARCH_ARM 0 |
| 65 | #endif |
| 66 | |
| 67 | #ifndef CPUINFO_ARCH_ARM64 |
| 68 | #define CPUINFO_ARCH_ARM64 0 |
| 69 | #endif |
| 70 | |
| 71 | #ifndef CPUINFO_ARCH_PPC64 |
| 72 | #define CPUINFO_ARCH_PPC64 0 |
| 73 | #endif |
| 74 | |
| 75 | #ifndef CPUINFO_ARCH_PNACL |
| 76 | #define CPUINFO_ARCH_PNACL 0 |
| 77 | #endif |
| 78 | |
| 79 | #ifndef CPUINFO_ARCH_ASMJS |
| 80 | #define CPUINFO_ARCH_ASMJS 0 |
| 81 | #endif |
| 82 | |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 83 | #define CPUINFO_CACHE_UNIFIED 0x00000001 |
| 84 | #define CPUINFO_CACHE_INCLUSIVE 0x00000002 |
| 85 | #define CPUINFO_CACHE_COMPLEX_INDEXING 0x00000004 |
| 86 | |
| 87 | struct cpuinfo_cache { |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 88 | /** Cache size in bytes */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 89 | uint32_t size; |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 90 | /** Number of ways of associativity */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 91 | uint32_t associativity; |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 92 | /** Number of sets */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 93 | uint32_t sets; |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 94 | /** Number of partitions */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 95 | uint32_t partitions; |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 96 | /** Line size in bytes */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 97 | uint32_t line_size; |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 98 | /** |
| 99 | * Binary characteristics of the cache (unified cache, inclusive cache, cache with complex indexing). |
| 100 | * |
| 101 | * @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE, CPUINFO_CACHE_COMPLEX_INDEXING |
| 102 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 103 | uint32_t flags; |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 104 | /** Index of the first logical processor that shares this cache */ |
Marat Dukhan | ab3a127 | 2017-08-25 23:20:07 -0700 | [diff] [blame] | 105 | uint32_t processor_start; |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 106 | /** Number of logical processors that share this cache */ |
Marat Dukhan | ab3a127 | 2017-08-25 23:20:07 -0700 | [diff] [blame] | 107 | uint32_t processor_count; |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 108 | }; |
| 109 | |
| 110 | struct cpuinfo_trace_cache { |
| 111 | uint32_t uops; |
| 112 | uint32_t associativity; |
| 113 | }; |
| 114 | |
| 115 | #define CPUINFO_PAGE_SIZE_4KB 0x1000 |
| 116 | #define CPUINFO_PAGE_SIZE_1MB 0x100000 |
| 117 | #define CPUINFO_PAGE_SIZE_2MB 0x200000 |
| 118 | #define CPUINFO_PAGE_SIZE_4MB 0x400000 |
| 119 | #define CPUINFO_PAGE_SIZE_16MB 0x1000000 |
| 120 | #define CPUINFO_PAGE_SIZE_1GB 0x40000000 |
| 121 | |
| 122 | struct cpuinfo_tlb { |
| 123 | uint32_t entries; |
| 124 | uint32_t associativity; |
| 125 | uint64_t pages; |
| 126 | }; |
| 127 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 128 | /** Vendor of processor core design */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 129 | enum cpuinfo_vendor { |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 130 | /** Processor vendor is not known to the library, or the library failed to get vendor information from the OS. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 131 | cpuinfo_vendor_unknown = 0, |
Marat Dukhan | b92e2ed | 2017-09-26 19:26:41 -0700 | [diff] [blame] | 132 | |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 133 | /* Active vendors of modern CPUs */ |
| 134 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 135 | /** |
| 136 | * Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor microarchitectures. |
| 137 | * |
| 138 | * Sold its ARM design subsidiary in 2006. The last ARM processor design was released in 2004. |
| 139 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 140 | cpuinfo_vendor_intel = 1, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 141 | /** Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 142 | cpuinfo_vendor_amd = 2, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 143 | /** ARM Holdings plc. Vendor of ARM and ARM64 processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 144 | cpuinfo_vendor_arm = 3, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 145 | /** Qualcomm Incorporated. Vendor of ARM and ARM64 processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 146 | cpuinfo_vendor_qualcomm = 4, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 147 | /** Apple Inc. Vendor of ARM and ARM64 processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 148 | cpuinfo_vendor_apple = 5, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 149 | /** Samsung Electronics Co., Ltd. Vendir if ARM64 processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 150 | cpuinfo_vendor_samsung = 6, |
Marat Dukhan | 93982f2 | 2017-10-20 13:10:23 -0700 | [diff] [blame] | 151 | /** Nvidia Corporation. Vendor of ARM64-compatible processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 152 | cpuinfo_vendor_nvidia = 7, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 153 | /** MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 154 | cpuinfo_vendor_mips = 8, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 155 | /** International Business Machines Corporation. Vendor of PowerPC processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 156 | cpuinfo_vendor_ibm = 9, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 157 | /** Ingenic Semiconductor. Vendor of MIPS processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 158 | cpuinfo_vendor_ingenic = 10, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 159 | /** |
| 160 | * VIA Technologies, Inc. Vendor of x86 and x86-64 processor microarchitectures. |
| 161 | * |
| 162 | * Processors are designed by Centaur Technology, a subsidiary of VIA Technologies. |
| 163 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 164 | cpuinfo_vendor_via = 11, |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 165 | /** Cavium, Inc. Vendor of ARM64 processor microarchitectures. */ |
| 166 | cpuinfo_vendor_cavium = 12, |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 167 | |
| 168 | /* Active vendors of embedded CPUs */ |
| 169 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 170 | /** Texas Instruments Inc. Vendor of ARM processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 171 | cpuinfo_vendor_texas_instruments = 30, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 172 | /** Marvell Technology Group Ltd. Vendor of ARM processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 173 | cpuinfo_vendor_marvell = 31, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 174 | /** RDC Semiconductor Co., Ltd. Vendor of x86 processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 175 | cpuinfo_vendor_rdc = 32, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 176 | /** DM&P Electronics Inc. Vendor of x86 processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 177 | cpuinfo_vendor_dmp = 33, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 178 | /** Motorola, Inc. Vendor of PowerPC and ARM processor microarchitectures. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 179 | cpuinfo_vendor_motorola = 34, |
| 180 | |
| 181 | /* Defunct CPU vendors */ |
Marat Dukhan | b92e2ed | 2017-09-26 19:26:41 -0700 | [diff] [blame] | 182 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 183 | /** |
| 184 | * Transmeta Corporation. Vendor of x86 processor microarchitectures. |
| 185 | * |
| 186 | * Now defunct. The last processor design was released in 2004. |
| 187 | * Transmeta processors implemented VLIW ISA and used binary translation to execute x86 code. |
| 188 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 189 | cpuinfo_vendor_transmeta = 50, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 190 | /** |
| 191 | * Cyrix Corporation. Vendor of x86 processor microarchitectures. |
| 192 | * |
| 193 | * Now defunct. The last processor design was released in 1996. |
| 194 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 195 | cpuinfo_vendor_cyrix = 51, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 196 | /** |
| 197 | * Rise Technology. Vendor of x86 processor microarchitectures. |
| 198 | * |
| 199 | * Now defunct. The last processor design was released in 1999. |
| 200 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 201 | cpuinfo_vendor_rise = 52, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 202 | /** |
| 203 | * National Semiconductor. Vendor of x86 processor microarchitectures. |
| 204 | * |
| 205 | * Sold its x86 design subsidiary in 1999. The last processor design was released in 1998. |
| 206 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 207 | cpuinfo_vendor_nsc = 53, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 208 | /** |
| 209 | * Silicon Integrated Systems. Vendor of x86 processor microarchitectures. |
| 210 | * |
| 211 | * Sold its x86 design subsidiary in 2001. The last processor design was released in 2001. |
| 212 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 213 | cpuinfo_vendor_sis = 54, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 214 | /** |
| 215 | * NexGen. Vendor of x86 processor microarchitectures. |
| 216 | * |
| 217 | * Now defunct. The last processor design was released in 1994. |
| 218 | * NexGen designed the first x86 microarchitecture which decomposed x86 instructions into simple microoperations. |
| 219 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 220 | cpuinfo_vendor_nexgen = 55, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 221 | /** |
| 222 | * United Microelectronics Corporation. Vendor of x86 processor microarchitectures. |
| 223 | * |
| 224 | * Ceased x86 in the early 1990s. The last processor design was released in 1991. |
| 225 | * Designed U5C and U5D processors. Both are 486 level. |
| 226 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 227 | cpuinfo_vendor_umc = 56, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 228 | /** |
| 229 | * Digital Equipment Corporation. Vendor of ARM processor microarchitecture. |
| 230 | * |
| 231 | * Sold its ARM designs in 1997. The last processor design was released in 1997. |
| 232 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 233 | cpuinfo_vendor_dec = 57, |
| 234 | }; |
| 235 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 236 | /** |
| 237 | * Processor microarchitecture |
| 238 | * |
| 239 | * Processors with different microarchitectures often have different instruction performance characteristics, |
| 240 | * and may have dramatically different pipeline organization. |
| 241 | */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 242 | enum cpuinfo_uarch { |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 243 | /** Microarchitecture is unknown, or the library failed to get information about the microarchitecture from OS */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 244 | cpuinfo_uarch_unknown = 0, |
| 245 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 246 | /** Pentium and Pentium MMX microarchitecture. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 247 | cpuinfo_uarch_p5 = 0x00100100, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 248 | /** Intel Quark microarchitecture. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 249 | cpuinfo_uarch_quark = 0x00100101, |
| 250 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 251 | /** Pentium Pro, Pentium II, and Pentium III. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 252 | cpuinfo_uarch_p6 = 0x00100200, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 253 | /** Pentium M. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 254 | cpuinfo_uarch_dothan = 0x00100201, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 255 | /** Intel Core microarchitecture. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 256 | cpuinfo_uarch_yonah = 0x00100202, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 257 | /** Intel Core 2 microarchitecture on 65 nm process. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 258 | cpuinfo_uarch_conroe = 0x00100203, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 259 | /** Intel Core 2 microarchitecture on 45 nm process. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 260 | cpuinfo_uarch_penryn = 0x00100204, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 261 | /** Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st gen). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 262 | cpuinfo_uarch_nehalem = 0x00100205, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 263 | /** Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 264 | cpuinfo_uarch_sandy_bridge = 0x00100206, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 265 | /** Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 266 | cpuinfo_uarch_ivy_bridge = 0x00100207, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 267 | /** Intel Haswell microarchitecture (Core i3/i5/i7 4th gen). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 268 | cpuinfo_uarch_haswell = 0x00100208, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 269 | /** Intel Broadwell microarchitecture. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 270 | cpuinfo_uarch_broadwell = 0x00100209, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 271 | /** Intel Sky Lake microarchitecture. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 272 | cpuinfo_uarch_sky_lake = 0x0010020A, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 273 | /** Intel Kaby Lake microarchitecture. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 274 | cpuinfo_uarch_kaby_lake = 0x0010020B, |
| 275 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 276 | /** Pentium 4 with Willamette, Northwood, or Foster cores. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 277 | cpuinfo_uarch_willamette = 0x00100300, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 278 | /** Pentium 4 with Prescott and later cores. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 279 | cpuinfo_uarch_prescott = 0x00100301, |
| 280 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 281 | /** Intel Atom on 45 nm process. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 282 | cpuinfo_uarch_bonnell = 0x00100400, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 283 | /** Intel Atom on 32 nm process. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 284 | cpuinfo_uarch_saltwell = 0x00100401, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 285 | /** Intel Silvermont microarchitecture (22 nm out-of-order Atom). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 286 | cpuinfo_uarch_silvermont = 0x00100402, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 287 | /** Intel Airmont microarchitecture (14 nm out-of-order Atom). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 288 | cpuinfo_uarch_airmont = 0x00100403, |
| 289 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 290 | /** Intel Knights Ferry HPC boards. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 291 | cpuinfo_uarch_knights_ferry = 0x00100500, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 292 | /** Intel Knights Corner HPC boards (aka Xeon Phi). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 293 | cpuinfo_uarch_knights_corner = 0x00100501, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 294 | /** Intel Knights Landing microarchitecture (second-gen MIC). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 295 | cpuinfo_uarch_knights_landing = 0x00100502, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 296 | /** Intel Knights Hill microarchitecture (third-gen MIC). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 297 | cpuinfo_uarch_knights_hill = 0x00100503, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 298 | /** Intel Knights Mill Xeon Phi. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 299 | cpuinfo_uarch_knights_mill = 0x00100504, |
| 300 | |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 301 | /** Intel/Marvell XScale series. */ |
| 302 | cpuinfo_uarch_xscale = 0x00100600, |
| 303 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 304 | /** AMD K5. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 305 | cpuinfo_uarch_k5 = 0x00200100, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 306 | /** AMD K6 and alike. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 307 | cpuinfo_uarch_k6 = 0x00200101, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 308 | /** AMD Athlon and Duron. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 309 | cpuinfo_uarch_k7 = 0x00200102, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 310 | /** AMD Athlon 64, Opteron 64. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 311 | cpuinfo_uarch_k8 = 0x00200103, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 312 | /** AMD Family 10h (Barcelona, Istambul, Magny-Cours). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 313 | cpuinfo_uarch_k10 = 0x00200104, |
| 314 | /** |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 315 | * AMD Bulldozer microarchitecture |
| 316 | * Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs. |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 317 | */ |
| 318 | cpuinfo_uarch_bulldozer = 0x00200105, |
| 319 | /** |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 320 | * AMD Piledriver microarchitecture |
| 321 | * Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu Dhabi Opteron CPUs. |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 322 | */ |
| 323 | cpuinfo_uarch_piledriver = 0x00200106, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 324 | /** AMD Steamroller microarchitecture (Kaveri APUs). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 325 | cpuinfo_uarch_steamroller = 0x00200107, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 326 | /** AMD Excavator microarchitecture (Carizzo APUs). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 327 | cpuinfo_uarch_excavator = 0x00200108, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 328 | /** AMD Zen microarchitecture (Ryzen CPUs). */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 329 | cpuinfo_uarch_zen = 0x00200109, |
| 330 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 331 | /** NSC Geode and AMD Geode GX and LX. */ |
Marat Dukhan | e25187d | 2017-04-16 05:03:07 -0400 | [diff] [blame] | 332 | cpuinfo_uarch_geode = 0x00200200, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 333 | /** AMD Bobcat mobile microarchitecture. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 334 | cpuinfo_uarch_bobcat = 0x00200201, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 335 | /** AMD Jaguar mobile microarchitecture. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 336 | cpuinfo_uarch_jaguar = 0x00200202, |
Marat Dukhan | b92e2ed | 2017-09-26 19:26:41 -0700 | [diff] [blame] | 337 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 338 | /** ARM7 series. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 339 | cpuinfo_uarch_arm7 = 0x00300100, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 340 | /** ARM9 series. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 341 | cpuinfo_uarch_arm9 = 0x00300101, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 342 | /** ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 343 | cpuinfo_uarch_arm11 = 0x00300102, |
| 344 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 345 | /** ARM Cortex-A5. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 346 | cpuinfo_uarch_cortex_a5 = 0x00300205, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 347 | /** ARM Cortex-A7. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 348 | cpuinfo_uarch_cortex_a7 = 0x00300207, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 349 | /** ARM Cortex-A8. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 350 | cpuinfo_uarch_cortex_a8 = 0x00300208, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 351 | /** ARM Cortex-A9. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 352 | cpuinfo_uarch_cortex_a9 = 0x00300209, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 353 | /** ARM Cortex-A12. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 354 | cpuinfo_uarch_cortex_a12 = 0x00300212, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 355 | /** ARM Cortex-A15. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 356 | cpuinfo_uarch_cortex_a15 = 0x00300215, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 357 | /** ARM Cortex-A17. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 358 | cpuinfo_uarch_cortex_a17 = 0x00300217, |
| 359 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 360 | /** ARM Cortex-A32. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 361 | cpuinfo_uarch_cortex_a32 = 0x00300332, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 362 | /** ARM Cortex-A35. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 363 | cpuinfo_uarch_cortex_a35 = 0x00300335, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 364 | /** ARM Cortex-A53. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 365 | cpuinfo_uarch_cortex_a53 = 0x00300353, |
Marat Dukhan | a8fb3dd | 2017-08-09 13:49:39 -0700 | [diff] [blame] | 366 | /** ARM Cortex-A55. */ |
| 367 | cpuinfo_uarch_cortex_a55 = 0x00300355, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 368 | /** ARM Cortex-A57. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 369 | cpuinfo_uarch_cortex_a57 = 0x00300357, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 370 | /** ARM Cortex-A72. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 371 | cpuinfo_uarch_cortex_a72 = 0x00300372, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 372 | /** ARM Cortex-A73. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 373 | cpuinfo_uarch_cortex_a73 = 0x00300373, |
Marat Dukhan | a8fb3dd | 2017-08-09 13:49:39 -0700 | [diff] [blame] | 374 | /** ARM Cortex-A75. */ |
| 375 | cpuinfo_uarch_cortex_a75 = 0x00300375, |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 376 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 377 | /** Qualcomm Scorpion. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 378 | cpuinfo_uarch_scorpion = 0x00400100, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 379 | /** Qualcomm Krait. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 380 | cpuinfo_uarch_krait = 0x00400101, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 381 | /** Qualcomm Kryo. */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 382 | cpuinfo_uarch_kryo = 0x00400102, |
| 383 | |
Marat Dukhan | 93982f2 | 2017-10-20 13:10:23 -0700 | [diff] [blame] | 384 | /** Nvidia Denver. */ |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 385 | cpuinfo_uarch_denver = 0x00500100, |
| 386 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 387 | /** Samsung Mongoose. */ |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 388 | cpuinfo_uarch_mongoose = 0x00600100, |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 389 | |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 390 | /** Apple A6 and A6X processors. */ |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 391 | cpuinfo_uarch_swift = 0x00700100, |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 392 | /** Apple A7 processor. */ |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 393 | cpuinfo_uarch_cyclone = 0x00700101, |
Hao Lu | 922070c | 2017-10-18 16:29:02 -0700 | [diff] [blame] | 394 | /** Apple A8 and A8X processor. */ |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 395 | cpuinfo_uarch_typhoon = 0x00700102, |
Hao Lu | 922070c | 2017-10-18 16:29:02 -0700 | [diff] [blame] | 396 | /** Apple A9 and A9X processor. */ |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 397 | cpuinfo_uarch_twister = 0x00700103, |
Hao Lu | 922070c | 2017-10-18 16:29:02 -0700 | [diff] [blame] | 398 | /** Apple A10 and A10X processor. */ |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 399 | cpuinfo_uarch_hurricane = 0x00700104, |
Hao Lu | 922070c | 2017-10-18 16:29:02 -0700 | [diff] [blame] | 400 | /** Apple A11 processor (big cores). */ |
| 401 | cpuinfo_uarch_monsoon = 0x00700105, |
| 402 | /** Apple A11 processor (little cores). */ |
| 403 | cpuinfo_uarch_mistral = 0x00700106, |
Marat Dukhan | 92dae31 | 2017-05-09 14:10:17 +0000 | [diff] [blame] | 404 | |
| 405 | /** Cavium ThunderX. */ |
| 406 | cpuinfo_uarch_thunderx = 0x00800100, |
Marat Dukhan | 8871832 | 2017-08-24 10:12:20 -0700 | [diff] [blame] | 407 | |
| 408 | /** Marvell PJ4. */ |
| 409 | cpuinfo_uarch_pj4 = 0x00900100, |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 410 | }; |
| 411 | |
| 412 | struct cpuinfo_processor { |
Marat Dukhan | 2d37dc4 | 2017-09-25 01:32:37 -0700 | [diff] [blame] | 413 | /** SMT (hyperthread) ID within a core */ |
| 414 | uint32_t smt_id; |
| 415 | /** Core containing this logical processor */ |
| 416 | const struct cpuinfo_core* core; |
| 417 | /** Physical package containing this logical processor */ |
| 418 | const struct cpuinfo_package* package; |
Marat Dukhan | 15e1df9 | 2017-09-13 11:10:10 -0700 | [diff] [blame] | 419 | #if defined(__linux__) |
Marat Dukhan | 2d37dc4 | 2017-09-25 01:32:37 -0700 | [diff] [blame] | 420 | /** |
| 421 | * Linux-specific ID for the logical processor: |
| 422 | * - Linux kernel exposes information about this logical processor in /sys/devices/system/cpu/cpu<linux_id>/ |
| 423 | * - Bit <linux_id> in the cpu_set_t identifies this logical processor |
| 424 | */ |
Marat Dukhan | 15e1df9 | 2017-09-13 11:10:10 -0700 | [diff] [blame] | 425 | int linux_id; |
| 426 | #endif |
Marat Dukhan | 2d37dc4 | 2017-09-25 01:32:37 -0700 | [diff] [blame] | 427 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 428 | /** APIC ID (unique x86-specific ID of the logical processor) */ |
| 429 | uint32_t apic_id; |
| 430 | #endif |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 431 | struct { |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 432 | /** Level 1 instruction cache */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 433 | const struct cpuinfo_cache* l1i; |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 434 | /** Level 1 data cache */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 435 | const struct cpuinfo_cache* l1d; |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 436 | /** Level 2 unified or data cache */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 437 | const struct cpuinfo_cache* l2; |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 438 | /** Level 3 unified or data cache */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 439 | const struct cpuinfo_cache* l3; |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 440 | /** Level 4 unified or data cache */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 441 | const struct cpuinfo_cache* l4; |
| 442 | } cache; |
| 443 | }; |
| 444 | |
| 445 | struct cpuinfo_core { |
Marat Dukhan | 2d37dc4 | 2017-09-25 01:32:37 -0700 | [diff] [blame] | 446 | /** Index of the first logical processor on this core */ |
Marat Dukhan | ab3a127 | 2017-08-25 23:20:07 -0700 | [diff] [blame] | 447 | uint32_t processor_start; |
Marat Dukhan | 2d37dc4 | 2017-09-25 01:32:37 -0700 | [diff] [blame] | 448 | /** Number of logical processors on this core */ |
Marat Dukhan | ab3a127 | 2017-08-25 23:20:07 -0700 | [diff] [blame] | 449 | uint32_t processor_count; |
Marat Dukhan | 2d37dc4 | 2017-09-25 01:32:37 -0700 | [diff] [blame] | 450 | /** Core ID within a package */ |
| 451 | uint32_t core_id; |
| 452 | /** Physical package containing this core */ |
| 453 | const struct cpuinfo_package* package; |
| 454 | /** Vendor of the CPU microarchitecture for this core */ |
| 455 | enum cpuinfo_vendor vendor; |
| 456 | /** CPU microarchitecture for this core */ |
| 457 | enum cpuinfo_uarch uarch; |
| 458 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 459 | /** Value of CPUID leaf 1 EAX register for this core */ |
| 460 | uint32_t cpuid; |
| 461 | #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
| 462 | /** Value of Main ID Register (MIDR) for this core */ |
| 463 | uint32_t midr; |
| 464 | #endif |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 465 | }; |
| 466 | |
Marat Dukhan | fb4fbe0 | 2017-09-13 00:51:05 -0700 | [diff] [blame] | 467 | #define CPUINFO_PACKAGE_NAME_MAX 48 |
Marat Dukhan | c40c731 | 2017-09-21 16:08:18 -0700 | [diff] [blame] | 468 | #define CPUINFO_GPU_NAME_MAX 64 |
Marat Dukhan | fb4fbe0 | 2017-09-13 00:51:05 -0700 | [diff] [blame] | 469 | |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 470 | struct cpuinfo_package { |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 471 | /** SoC or processor chip model name */ |
Marat Dukhan | fb4fbe0 | 2017-09-13 00:51:05 -0700 | [diff] [blame] | 472 | char name[CPUINFO_PACKAGE_NAME_MAX]; |
Hao Lu | 3617d5b | 2017-10-23 15:16:50 -0700 | [diff] [blame] | 473 | #if defined(__ANDROID__) || (defined(__APPLE__) && TARGET_OS_IPHONE) |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 474 | /** Integrated GPU model name */ |
| 475 | char gpu_name[CPUINFO_GPU_NAME_MAX]; |
| 476 | #endif |
| 477 | /** Index of the first logical processor on this physical package */ |
Marat Dukhan | ab3a127 | 2017-08-25 23:20:07 -0700 | [diff] [blame] | 478 | uint32_t processor_start; |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 479 | /** Number of logical processors on this physical package */ |
Marat Dukhan | ab3a127 | 2017-08-25 23:20:07 -0700 | [diff] [blame] | 480 | uint32_t processor_count; |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 481 | /** Index of the first core on this physical package */ |
Marat Dukhan | fb4fbe0 | 2017-09-13 00:51:05 -0700 | [diff] [blame] | 482 | uint32_t core_start; |
Marat Dukhan | 8f79efb | 2017-09-25 11:17:21 -0700 | [diff] [blame] | 483 | /** Number of cores on this physical package */ |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 484 | uint32_t core_count; |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 485 | }; |
| 486 | |
| 487 | #ifdef __cplusplus |
| 488 | extern "C" { |
| 489 | #endif |
| 490 | |
| 491 | void CPUINFO_ABI cpuinfo_initialize(void); |
| 492 | |
| 493 | void CPUINFO_ABI cpuinfo_deinitialize(void); |
| 494 | |
| 495 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 496 | /* This structure is not a part of stable API. Use cpuinfo_has_x86_* functions instead. */ |
| 497 | struct cpuinfo_x86_isa { |
| 498 | #if CPUINFO_ARCH_X86 |
| 499 | bool rdtsc; |
| 500 | #endif |
| 501 | bool rdtscp; |
| 502 | bool rdpid; |
| 503 | bool sysenter; |
| 504 | #if CPUINFO_ARCH_X86 |
| 505 | bool syscall; |
| 506 | #endif |
| 507 | bool msr; |
| 508 | bool clzero; |
| 509 | bool clflush; |
| 510 | bool clflushopt; |
| 511 | bool mwait; |
| 512 | bool mwaitx; |
| 513 | #if CPUINFO_ARCH_X86 |
| 514 | bool emmx; |
| 515 | #endif |
| 516 | bool fxsave; |
| 517 | bool xsave; |
| 518 | #if CPUINFO_ARCH_X86 |
| 519 | bool fpu; |
| 520 | bool mmx; |
| 521 | bool mmx_plus; |
| 522 | #endif |
| 523 | bool three_d_now; |
| 524 | bool three_d_now_plus; |
| 525 | #if CPUINFO_ARCH_X86 |
| 526 | bool three_d_now_geode; |
| 527 | #endif |
| 528 | bool prefetch; |
| 529 | bool prefetchw; |
| 530 | bool prefetchwt1; |
| 531 | #if CPUINFO_ARCH_X86 |
| 532 | bool daz; |
| 533 | bool sse; |
| 534 | bool sse2; |
| 535 | #endif |
| 536 | bool sse3; |
| 537 | bool ssse3; |
| 538 | bool sse4_1; |
| 539 | bool sse4_2; |
| 540 | bool sse4a; |
| 541 | bool misaligned_sse; |
| 542 | bool avx; |
| 543 | bool fma3; |
| 544 | bool fma4; |
| 545 | bool xop; |
| 546 | bool f16c; |
| 547 | bool avx2; |
| 548 | bool avx512f; |
| 549 | bool avx512pf; |
| 550 | bool avx512er; |
| 551 | bool avx512cd; |
| 552 | bool avx512dq; |
| 553 | bool avx512bw; |
| 554 | bool avx512vl; |
| 555 | bool avx512ifma; |
| 556 | bool avx512vbmi; |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 557 | bool avx512vbmi2; |
| 558 | bool avx512bitalg; |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 559 | bool avx512vpopcntdq; |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 560 | bool avx512vnni; |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 561 | bool avx512_4vnniw; |
| 562 | bool avx512_4fmaps; |
| 563 | bool hle; |
| 564 | bool rtm; |
| 565 | bool xtest; |
| 566 | bool mpx; |
| 567 | #if CPUINFO_ARCH_X86 |
| 568 | bool cmov; |
| 569 | bool cmpxchg8b; |
| 570 | #endif |
| 571 | bool cmpxchg16b; |
| 572 | bool clwb; |
| 573 | bool movbe; |
| 574 | #if CPUINFO_ARCH_X86_64 |
| 575 | bool lahf_sahf; |
| 576 | #endif |
| 577 | bool fs_gs_base; |
| 578 | bool lzcnt; |
| 579 | bool popcnt; |
| 580 | bool tbm; |
| 581 | bool bmi; |
| 582 | bool bmi2; |
| 583 | bool adx; |
| 584 | bool aes; |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 585 | bool vaes; |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 586 | bool pclmulqdq; |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 587 | bool vpclmulqdq; |
| 588 | bool gfni; |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 589 | bool rdrand; |
| 590 | bool rdseed; |
| 591 | bool sha; |
| 592 | bool rng; |
| 593 | bool ace; |
| 594 | bool ace2; |
| 595 | bool phe; |
| 596 | bool pmm; |
| 597 | bool lwp; |
| 598 | }; |
| 599 | |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 600 | extern struct cpuinfo_x86_isa cpuinfo_isa; |
| 601 | #endif |
| 602 | |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 603 | static inline bool cpuinfo_has_x86_rdtsc(void) { |
| 604 | #if CPUINFO_ARCH_X86_64 |
| 605 | return true; |
| 606 | #elif CPUINFO_ARCH_X86 |
| 607 | #if defined(__ANDROID__) |
| 608 | return true; |
| 609 | #else |
| 610 | return cpuinfo_isa.rdtsc; |
| 611 | #endif |
| 612 | #else |
| 613 | return false; |
| 614 | #endif |
| 615 | } |
| 616 | |
| 617 | static inline bool cpuinfo_has_x86_rdtscp(void) { |
| 618 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 619 | return cpuinfo_isa.rdtscp; |
| 620 | #else |
| 621 | return false; |
| 622 | #endif |
| 623 | } |
| 624 | |
| 625 | static inline bool cpuinfo_has_x86_rdpid(void) { |
| 626 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 627 | return cpuinfo_isa.rdpid; |
| 628 | #else |
| 629 | return false; |
| 630 | #endif |
| 631 | } |
| 632 | |
| 633 | static inline bool cpuinfo_has_x86_clzero(void) { |
| 634 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 635 | return cpuinfo_isa.clzero; |
| 636 | #else |
| 637 | return false; |
| 638 | #endif |
| 639 | } |
| 640 | |
| 641 | static inline bool cpuinfo_has_x86_mwait(void) { |
| 642 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 643 | return cpuinfo_isa.mwait; |
| 644 | #else |
| 645 | return false; |
| 646 | #endif |
| 647 | } |
| 648 | |
| 649 | static inline bool cpuinfo_has_x86_mwaitx(void) { |
| 650 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 651 | return cpuinfo_isa.mwaitx; |
| 652 | #else |
| 653 | return false; |
| 654 | #endif |
| 655 | } |
| 656 | |
| 657 | static inline bool cpuinfo_has_x86_fxsave(void) { |
| 658 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 659 | return cpuinfo_isa.fxsave; |
| 660 | #else |
| 661 | return false; |
| 662 | #endif |
| 663 | } |
| 664 | |
| 665 | static inline bool cpuinfo_has_x86_xsave(void) { |
| 666 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 667 | return cpuinfo_isa.xsave; |
| 668 | #else |
| 669 | return false; |
| 670 | #endif |
| 671 | } |
| 672 | |
| 673 | static inline bool cpuinfo_has_x86_fpu(void) { |
| 674 | #if CPUINFO_ARCH_X86_64 |
| 675 | return true; |
| 676 | #elif CPUINFO_ARCH_X86 |
| 677 | #if defined(__ANDROID__) |
| 678 | return true; |
| 679 | #else |
| 680 | return cpuinfo_isa.fpu; |
| 681 | #endif |
| 682 | #else |
| 683 | return false; |
| 684 | #endif |
| 685 | } |
| 686 | |
| 687 | static inline bool cpuinfo_has_x86_mmx(void) { |
| 688 | #if CPUINFO_ARCH_X86_64 |
| 689 | return true; |
| 690 | #elif CPUINFO_ARCH_X86 |
| 691 | #if defined(__ANDROID__) |
| 692 | return true; |
| 693 | #else |
| 694 | return cpuinfo_isa.mmx; |
| 695 | #endif |
| 696 | #else |
| 697 | return false; |
| 698 | #endif |
| 699 | } |
| 700 | |
| 701 | static inline bool cpuinfo_has_x86_mmx_plus(void) { |
| 702 | #if CPUINFO_ARCH_X86_64 |
| 703 | return true; |
| 704 | #elif CPUINFO_ARCH_X86 |
| 705 | #if defined(__ANDROID__) |
| 706 | return true; |
| 707 | #else |
| 708 | return cpuinfo_isa.mmx_plus; |
| 709 | #endif |
| 710 | #else |
| 711 | return false; |
| 712 | #endif |
| 713 | } |
| 714 | |
| 715 | static inline bool cpuinfo_has_x86_3dnow(void) { |
| 716 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 717 | return cpuinfo_isa.three_d_now; |
| 718 | #else |
| 719 | return false; |
| 720 | #endif |
| 721 | } |
| 722 | |
| 723 | static inline bool cpuinfo_has_x86_3dnow_plus(void) { |
| 724 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 725 | return cpuinfo_isa.three_d_now_plus; |
| 726 | #else |
| 727 | return false; |
| 728 | #endif |
| 729 | } |
| 730 | |
| 731 | static inline bool cpuinfo_has_x86_3dnow_geode(void) { |
| 732 | #if CPUINFO_ARCH_X86_64 |
| 733 | return false; |
| 734 | #elif CPUINFO_ARCH_X86 |
| 735 | #if defined(__ANDROID__) |
| 736 | return false; |
| 737 | #else |
| 738 | return cpuinfo_isa.three_d_now_geode; |
| 739 | #endif |
| 740 | #else |
| 741 | return false; |
| 742 | #endif |
| 743 | } |
| 744 | |
| 745 | static inline bool cpuinfo_has_x86_prefetch(void) { |
| 746 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 747 | return cpuinfo_isa.prefetch; |
| 748 | #else |
| 749 | return false; |
| 750 | #endif |
| 751 | } |
| 752 | |
| 753 | static inline bool cpuinfo_has_x86_prefetchw(void) { |
| 754 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 755 | return cpuinfo_isa.prefetchw; |
| 756 | #else |
| 757 | return false; |
| 758 | #endif |
| 759 | } |
| 760 | |
| 761 | static inline bool cpuinfo_has_x86_prefetchwt1(void) { |
| 762 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
Marat Dukhan | 6022f80 | 2017-09-26 11:56:36 -0700 | [diff] [blame] | 763 | return cpuinfo_isa.prefetchwt1; |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 764 | #else |
| 765 | return false; |
| 766 | #endif |
| 767 | } |
| 768 | |
| 769 | static inline bool cpuinfo_has_x86_daz(void) { |
| 770 | #if CPUINFO_ARCH_X86_64 |
| 771 | return true; |
| 772 | #elif CPUINFO_ARCH_X86 |
| 773 | #if defined(__ANDROID__) |
| 774 | return true; |
| 775 | #else |
| 776 | return cpuinfo_isa.daz; |
| 777 | #endif |
| 778 | #else |
| 779 | return false; |
| 780 | #endif |
| 781 | } |
| 782 | |
Marat Dukhan | 9da4c91 | 2017-09-26 10:53:28 -0700 | [diff] [blame] | 783 | static inline bool cpuinfo_has_x86_sse(void) { |
| 784 | #if CPUINFO_ARCH_X86_64 |
| 785 | return true; |
| 786 | #elif CPUINFO_ARCH_X86 |
| 787 | #if defined(__ANDROID__) |
| 788 | return true; |
| 789 | #else |
| 790 | return cpuinfo_isa.sse; |
| 791 | #endif |
| 792 | #else |
| 793 | return false; |
| 794 | #endif |
| 795 | } |
| 796 | |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 797 | static inline bool cpuinfo_has_x86_sse2(void) { |
| 798 | #if CPUINFO_ARCH_X86_64 |
| 799 | return true; |
| 800 | #elif CPUINFO_ARCH_X86 |
| 801 | #if defined(__ANDROID__) |
| 802 | return true; |
| 803 | #else |
| 804 | return cpuinfo_isa.sse2; |
| 805 | #endif |
| 806 | #else |
| 807 | return false; |
| 808 | #endif |
| 809 | } |
| 810 | |
| 811 | static inline bool cpuinfo_has_x86_sse3(void) { |
| 812 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 813 | #if defined(__ANDROID__) |
| 814 | return true; |
| 815 | #else |
| 816 | return cpuinfo_isa.sse3; |
| 817 | #endif |
| 818 | #else |
| 819 | return false; |
| 820 | #endif |
| 821 | } |
| 822 | |
| 823 | static inline bool cpuinfo_has_x86_ssse3(void) { |
| 824 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 825 | #if defined(__ANDROID__) |
| 826 | return true; |
| 827 | #else |
| 828 | return cpuinfo_isa.ssse3; |
| 829 | #endif |
| 830 | #else |
| 831 | return false; |
| 832 | #endif |
| 833 | } |
| 834 | |
| 835 | static inline bool cpuinfo_has_x86_sse4_1(void) { |
| 836 | #if CPUINFO_ARCH_X86_64 |
| 837 | #if defined(__ANDROID__) |
| 838 | return true; |
| 839 | #else |
| 840 | return cpuinfo_isa.sse4_1; |
| 841 | #endif |
| 842 | #elif CPUINFO_ARCH_X86 |
| 843 | return cpuinfo_isa.sse4_1; |
| 844 | #else |
| 845 | return false; |
| 846 | #endif |
| 847 | } |
| 848 | |
| 849 | static inline bool cpuinfo_has_x86_sse4_2(void) { |
| 850 | #if CPUINFO_ARCH_X86_64 |
| 851 | #if defined(__ANDROID__) |
| 852 | return true; |
| 853 | #else |
| 854 | return cpuinfo_isa.sse4_2; |
| 855 | #endif |
| 856 | #elif CPUINFO_ARCH_X86 |
| 857 | return cpuinfo_isa.sse4_2; |
| 858 | #else |
| 859 | return false; |
| 860 | #endif |
| 861 | } |
| 862 | |
| 863 | static inline bool cpuinfo_has_x86_sse4a(void) { |
| 864 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 865 | return cpuinfo_isa.sse4a; |
| 866 | #else |
| 867 | return false; |
| 868 | #endif |
| 869 | } |
| 870 | |
| 871 | static inline bool cpuinfo_has_x86_misaligned_sse(void) { |
| 872 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 873 | return cpuinfo_isa.misaligned_sse; |
| 874 | #else |
| 875 | return false; |
| 876 | #endif |
| 877 | } |
| 878 | |
| 879 | static inline bool cpuinfo_has_x86_avx(void) { |
| 880 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 881 | return cpuinfo_isa.avx; |
| 882 | #else |
| 883 | return false; |
| 884 | #endif |
| 885 | } |
| 886 | |
| 887 | static inline bool cpuinfo_has_x86_fma3(void) { |
| 888 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 889 | return cpuinfo_isa.fma3; |
| 890 | #else |
| 891 | return false; |
| 892 | #endif |
| 893 | } |
| 894 | |
| 895 | static inline bool cpuinfo_has_x86_fma4(void) { |
| 896 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 897 | return cpuinfo_isa.fma4; |
| 898 | #else |
| 899 | return false; |
| 900 | #endif |
| 901 | } |
| 902 | |
| 903 | static inline bool cpuinfo_has_x86_xop(void) { |
| 904 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 905 | return cpuinfo_isa.xop; |
| 906 | #else |
| 907 | return false; |
| 908 | #endif |
| 909 | } |
| 910 | |
| 911 | static inline bool cpuinfo_has_x86_f16c(void) { |
| 912 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 913 | return cpuinfo_isa.f16c; |
| 914 | #else |
| 915 | return false; |
| 916 | #endif |
| 917 | } |
| 918 | |
| 919 | static inline bool cpuinfo_has_x86_avx2(void) { |
| 920 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 921 | return cpuinfo_isa.avx2; |
| 922 | #else |
| 923 | return false; |
| 924 | #endif |
| 925 | } |
| 926 | |
| 927 | static inline bool cpuinfo_has_x86_avx512f(void) { |
| 928 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 929 | return cpuinfo_isa.avx512f; |
| 930 | #else |
| 931 | return false; |
| 932 | #endif |
| 933 | } |
| 934 | |
| 935 | static inline bool cpuinfo_has_x86_avx512pf(void) { |
| 936 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 937 | return cpuinfo_isa.avx512pf; |
| 938 | #else |
| 939 | return false; |
| 940 | #endif |
| 941 | } |
| 942 | |
| 943 | static inline bool cpuinfo_has_x86_avx512er(void) { |
| 944 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 945 | return cpuinfo_isa.avx512er; |
| 946 | #else |
| 947 | return false; |
| 948 | #endif |
| 949 | } |
| 950 | |
| 951 | static inline bool cpuinfo_has_x86_avx512cd(void) { |
| 952 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 953 | return cpuinfo_isa.avx512cd; |
| 954 | #else |
| 955 | return false; |
| 956 | #endif |
| 957 | } |
| 958 | |
| 959 | static inline bool cpuinfo_has_x86_avx512dq(void) { |
| 960 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 961 | return cpuinfo_isa.avx512dq; |
| 962 | #else |
| 963 | return false; |
| 964 | #endif |
| 965 | } |
| 966 | |
| 967 | static inline bool cpuinfo_has_x86_avx512bw(void) { |
| 968 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 969 | return cpuinfo_isa.avx512bw; |
| 970 | #else |
| 971 | return false; |
| 972 | #endif |
| 973 | } |
| 974 | |
| 975 | static inline bool cpuinfo_has_x86_avx512vl(void) { |
| 976 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 977 | return cpuinfo_isa.avx512vl; |
| 978 | #else |
| 979 | return false; |
| 980 | #endif |
| 981 | } |
| 982 | |
| 983 | static inline bool cpuinfo_has_x86_avx512ifma(void) { |
| 984 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 985 | return cpuinfo_isa.avx512ifma; |
| 986 | #else |
| 987 | return false; |
| 988 | #endif |
| 989 | } |
| 990 | |
| 991 | static inline bool cpuinfo_has_x86_avx512vbmi(void) { |
| 992 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 993 | return cpuinfo_isa.avx512vbmi; |
| 994 | #else |
| 995 | return false; |
| 996 | #endif |
| 997 | } |
| 998 | |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 999 | static inline bool cpuinfo_has_x86_avx512vbmi2(void) { |
| 1000 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1001 | return cpuinfo_isa.avx512vbmi2; |
| 1002 | #else |
| 1003 | return false; |
| 1004 | #endif |
| 1005 | } |
| 1006 | |
| 1007 | static inline bool cpuinfo_has_x86_avx512bitalg(void) { |
| 1008 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1009 | return cpuinfo_isa.avx512bitalg; |
| 1010 | #else |
| 1011 | return false; |
| 1012 | #endif |
| 1013 | } |
| 1014 | |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1015 | static inline bool cpuinfo_has_x86_avx512vpopcntdq(void) { |
| 1016 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1017 | return cpuinfo_isa.avx512vpopcntdq; |
| 1018 | #else |
| 1019 | return false; |
| 1020 | #endif |
| 1021 | } |
| 1022 | |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 1023 | static inline bool cpuinfo_has_x86_avx512vnni(void) { |
Marat Dukhan | 6b33b23 | 2017-10-13 09:36:52 -0700 | [diff] [blame] | 1024 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 1025 | return cpuinfo_isa.avx512vnni; |
| 1026 | #else |
| 1027 | return false; |
| 1028 | #endif |
| 1029 | } |
| 1030 | |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1031 | static inline bool cpuinfo_has_x86_avx512_4vnniw(void) { |
| 1032 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1033 | return cpuinfo_isa.avx512_4vnniw; |
| 1034 | #else |
| 1035 | return false; |
| 1036 | #endif |
| 1037 | } |
| 1038 | |
| 1039 | static inline bool cpuinfo_has_x86_avx512_4fmaps(void) { |
| 1040 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1041 | return cpuinfo_isa.avx512_4fmaps; |
| 1042 | #else |
| 1043 | return false; |
| 1044 | #endif |
| 1045 | } |
| 1046 | |
Marat Dukhan | 9e32e8d | 2017-09-26 11:02:37 -0700 | [diff] [blame] | 1047 | static inline bool cpuinfo_has_x86_hle(void) { |
| 1048 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1049 | return cpuinfo_isa.hle; |
| 1050 | #else |
| 1051 | return false; |
| 1052 | #endif |
| 1053 | } |
| 1054 | |
| 1055 | static inline bool cpuinfo_has_x86_rtm(void) { |
| 1056 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1057 | return cpuinfo_isa.rtm; |
| 1058 | #else |
| 1059 | return false; |
| 1060 | #endif |
| 1061 | } |
| 1062 | |
| 1063 | static inline bool cpuinfo_has_x86_xtest(void) { |
| 1064 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1065 | return cpuinfo_isa.xtest; |
| 1066 | #else |
| 1067 | return false; |
| 1068 | #endif |
| 1069 | } |
| 1070 | |
| 1071 | static inline bool cpuinfo_has_x86_mpx(void) { |
| 1072 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1073 | return cpuinfo_isa.mpx; |
| 1074 | #else |
| 1075 | return false; |
| 1076 | #endif |
| 1077 | } |
| 1078 | |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1079 | static inline bool cpuinfo_has_x86_cmov(void) { |
| 1080 | #if CPUINFO_ARCH_X86_64 |
| 1081 | return true; |
| 1082 | #elif CPUINFO_ARCH_X86 |
| 1083 | return cpuinfo_isa.cmov; |
| 1084 | #else |
| 1085 | return false; |
| 1086 | #endif |
| 1087 | } |
| 1088 | |
| 1089 | static inline bool cpuinfo_has_x86_cmpxchg8b(void) { |
| 1090 | #if CPUINFO_ARCH_X86_64 |
| 1091 | return true; |
| 1092 | #elif CPUINFO_ARCH_X86 |
| 1093 | return cpuinfo_isa.cmpxchg8b; |
| 1094 | #else |
| 1095 | return false; |
| 1096 | #endif |
| 1097 | } |
| 1098 | |
| 1099 | static inline bool cpuinfo_has_x86_cmpxchg16b(void) { |
| 1100 | #if CPUINFO_ARCH_X86_64 |
| 1101 | return cpuinfo_isa.cmpxchg16b; |
| 1102 | #else |
| 1103 | return false; |
| 1104 | #endif |
| 1105 | } |
| 1106 | |
| 1107 | static inline bool cpuinfo_has_x86_clwb(void) { |
| 1108 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1109 | return cpuinfo_isa.clwb; |
| 1110 | #else |
| 1111 | return false; |
| 1112 | #endif |
| 1113 | } |
| 1114 | |
| 1115 | static inline bool cpuinfo_has_x86_movbe(void) { |
Marat Dukhan | 6022f80 | 2017-09-26 11:56:36 -0700 | [diff] [blame] | 1116 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1117 | return cpuinfo_isa.movbe; |
| 1118 | #else |
| 1119 | return false; |
| 1120 | #endif |
| 1121 | } |
| 1122 | |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 1123 | static inline bool cpuinfo_has_x86_lahf_sahf(void) { |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1124 | #if CPUINFO_ARCH_X86 |
| 1125 | return true; |
| 1126 | #elif CPUINFO_ARCH_X86_64 |
| 1127 | return cpuinfo_isa.lahf_sahf; |
| 1128 | #else |
| 1129 | return false; |
| 1130 | #endif |
| 1131 | } |
| 1132 | |
| 1133 | static inline bool cpuinfo_has_x86_lzcnt(void) { |
| 1134 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1135 | return cpuinfo_isa.lzcnt; |
| 1136 | #else |
| 1137 | return false; |
| 1138 | #endif |
| 1139 | } |
| 1140 | |
| 1141 | static inline bool cpuinfo_has_x86_popcnt(void) { |
| 1142 | #if CPUINFO_ARCH_X86_64 |
| 1143 | #if defined(__ANDROID__) |
| 1144 | return true; |
| 1145 | #else |
| 1146 | return cpuinfo_isa.popcnt; |
| 1147 | #endif |
| 1148 | #elif CPUINFO_ARCH_X86 |
| 1149 | return cpuinfo_isa.popcnt; |
| 1150 | #else |
| 1151 | return false; |
| 1152 | #endif |
| 1153 | } |
| 1154 | |
| 1155 | static inline bool cpuinfo_has_x86_tbm(void) { |
| 1156 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1157 | return cpuinfo_isa.tbm; |
| 1158 | #else |
| 1159 | return false; |
| 1160 | #endif |
| 1161 | } |
| 1162 | |
| 1163 | static inline bool cpuinfo_has_x86_bmi(void) { |
| 1164 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1165 | return cpuinfo_isa.bmi; |
| 1166 | #else |
| 1167 | return false; |
| 1168 | #endif |
| 1169 | } |
| 1170 | |
| 1171 | static inline bool cpuinfo_has_x86_bmi2(void) { |
| 1172 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1173 | return cpuinfo_isa.bmi2; |
| 1174 | #else |
| 1175 | return false; |
| 1176 | #endif |
| 1177 | } |
| 1178 | |
| 1179 | static inline bool cpuinfo_has_x86_adx(void) { |
| 1180 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1181 | return cpuinfo_isa.adx; |
| 1182 | #else |
| 1183 | return false; |
| 1184 | #endif |
| 1185 | } |
| 1186 | |
| 1187 | static inline bool cpuinfo_has_x86_aes(void) { |
| 1188 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1189 | return cpuinfo_isa.aes; |
| 1190 | #else |
| 1191 | return false; |
| 1192 | #endif |
| 1193 | } |
| 1194 | |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 1195 | static inline bool cpuinfo_has_x86_vaes(void) { |
| 1196 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1197 | return cpuinfo_isa.vaes; |
| 1198 | #else |
| 1199 | return false; |
| 1200 | #endif |
| 1201 | } |
| 1202 | |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1203 | static inline bool cpuinfo_has_x86_pclmulqdq(void) { |
| 1204 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1205 | return cpuinfo_isa.pclmulqdq; |
| 1206 | #else |
| 1207 | return false; |
| 1208 | #endif |
| 1209 | } |
| 1210 | |
Marat Dukhan | 861d21a | 2017-10-13 07:10:25 -0700 | [diff] [blame] | 1211 | static inline bool cpuinfo_has_x86_vpclmulqdq(void) { |
| 1212 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1213 | return cpuinfo_isa.vpclmulqdq; |
| 1214 | #else |
| 1215 | return false; |
| 1216 | #endif |
| 1217 | } |
| 1218 | |
| 1219 | static inline bool cpuinfo_has_x86_gfni(void) { |
| 1220 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1221 | return cpuinfo_isa.gfni; |
| 1222 | #else |
| 1223 | return false; |
| 1224 | #endif |
| 1225 | } |
| 1226 | |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1227 | static inline bool cpuinfo_has_x86_rdrand(void) { |
| 1228 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1229 | return cpuinfo_isa.rdrand; |
| 1230 | #else |
| 1231 | return false; |
| 1232 | #endif |
| 1233 | } |
| 1234 | |
| 1235 | static inline bool cpuinfo_has_x86_rdseed(void) { |
| 1236 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1237 | return cpuinfo_isa.rdseed; |
| 1238 | #else |
| 1239 | return false; |
| 1240 | #endif |
| 1241 | } |
| 1242 | |
| 1243 | static inline bool cpuinfo_has_x86_sha(void) { |
| 1244 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
| 1245 | return cpuinfo_isa.sha; |
| 1246 | #else |
| 1247 | return false; |
| 1248 | #endif |
| 1249 | } |
| 1250 | |
Marat Dukhan | ab42e7e | 2017-05-09 13:19:39 +0000 | [diff] [blame] | 1251 | #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1252 | /* This structure is not a part of stable API. Use cpuinfo_has_arm_* functions instead. */ |
| 1253 | struct cpuinfo_arm_isa { |
| 1254 | #if CPUINFO_ARCH_ARM |
| 1255 | bool thumb; |
| 1256 | bool thumb2; |
| 1257 | bool thumbee; |
| 1258 | bool jazelle; |
| 1259 | bool armv5e; |
| 1260 | bool armv6; |
| 1261 | bool armv6k; |
| 1262 | bool armv7; |
| 1263 | bool armv7mp; |
| 1264 | bool idiv; |
| 1265 | |
| 1266 | bool vfpv2; |
| 1267 | bool vfpv3; |
| 1268 | bool d32; |
| 1269 | bool fp16; |
| 1270 | bool fma; |
| 1271 | |
| 1272 | bool wmmx; |
| 1273 | bool wmmx2; |
| 1274 | bool neon; |
| 1275 | #endif |
| 1276 | #if CPUINFO_ARCH_ARM64 |
| 1277 | bool atomics; |
| 1278 | bool rdm; |
| 1279 | bool fp16arith; |
| 1280 | bool jscvt; |
| 1281 | bool fcma; |
| 1282 | #endif |
| 1283 | |
| 1284 | bool aes; |
| 1285 | bool sha1; |
| 1286 | bool sha2; |
| 1287 | bool pmull; |
| 1288 | bool crc32; |
| 1289 | }; |
| 1290 | |
Marat Dukhan | 3c98276 | 2017-05-08 06:16:45 +0000 | [diff] [blame] | 1291 | extern struct cpuinfo_arm_isa cpuinfo_isa; |
| 1292 | #endif |
| 1293 | |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1294 | static inline bool cpuinfo_has_arm_thumb(void) { |
| 1295 | #if CPUINFO_ARCH_ARM |
| 1296 | return cpuinfo_isa.thumb; |
| 1297 | #else |
| 1298 | return false; |
| 1299 | #endif |
| 1300 | } |
| 1301 | |
| 1302 | static inline bool cpuinfo_has_arm_thumb2(void) { |
| 1303 | #if CPUINFO_ARCH_ARM |
| 1304 | return cpuinfo_isa.thumb2; |
| 1305 | #else |
| 1306 | return false; |
| 1307 | #endif |
| 1308 | } |
| 1309 | |
| 1310 | static inline bool cpuinfo_has_arm_v5e(void) { |
| 1311 | #if CPUINFO_ARCH_ARM |
| 1312 | return cpuinfo_isa.armv5e; |
| 1313 | #else |
| 1314 | return false; |
| 1315 | #endif |
| 1316 | } |
| 1317 | |
| 1318 | static inline bool cpuinfo_has_arm_v6(void) { |
| 1319 | #if CPUINFO_ARCH_ARM |
| 1320 | return cpuinfo_isa.armv6; |
| 1321 | #else |
| 1322 | return false; |
| 1323 | #endif |
| 1324 | } |
| 1325 | |
| 1326 | static inline bool cpuinfo_has_arm_v6k(void) { |
| 1327 | #if CPUINFO_ARCH_ARM |
| 1328 | return cpuinfo_isa.armv6k; |
| 1329 | #else |
| 1330 | return false; |
| 1331 | #endif |
| 1332 | } |
| 1333 | |
| 1334 | static inline bool cpuinfo_has_arm_v7(void) { |
| 1335 | #if CPUINFO_ARCH_ARM |
| 1336 | return cpuinfo_isa.armv7; |
| 1337 | #else |
| 1338 | return false; |
| 1339 | #endif |
| 1340 | } |
| 1341 | |
| 1342 | static inline bool cpuinfo_has_arm_v7mp(void) { |
| 1343 | #if CPUINFO_ARCH_ARM |
| 1344 | return cpuinfo_isa.armv7mp; |
| 1345 | #else |
| 1346 | return false; |
| 1347 | #endif |
| 1348 | } |
| 1349 | |
| 1350 | static inline bool cpuinfo_has_arm_idiv(void) { |
| 1351 | #if CPUINFO_ARCH_ARM64 |
| 1352 | return true; |
| 1353 | #elif CPUINFO_ARCH_ARM |
| 1354 | return cpuinfo_isa.idiv; |
| 1355 | #else |
| 1356 | return false; |
| 1357 | #endif |
| 1358 | } |
| 1359 | |
| 1360 | static inline bool cpuinfo_has_arm_vfpv2(void) { |
| 1361 | #if CPUINFO_ARCH_ARM |
| 1362 | return cpuinfo_isa.vfpv2; |
| 1363 | #else |
| 1364 | return false; |
| 1365 | #endif |
| 1366 | } |
| 1367 | |
| 1368 | static inline bool cpuinfo_has_arm_vfpv3(void) { |
| 1369 | #if CPUINFO_ARCH_ARM64 |
| 1370 | return true; |
| 1371 | #elif CPUINFO_ARCH_ARM |
| 1372 | return cpuinfo_isa.vfpv3; |
| 1373 | #else |
| 1374 | return false; |
| 1375 | #endif |
| 1376 | } |
| 1377 | |
| 1378 | static inline bool cpuinfo_has_arm_vfpv3_d32(void) { |
| 1379 | #if CPUINFO_ARCH_ARM64 |
| 1380 | return true; |
| 1381 | #elif CPUINFO_ARCH_ARM |
| 1382 | return cpuinfo_isa.vfpv3 && cpuinfo_isa.d32; |
| 1383 | #else |
| 1384 | return false; |
| 1385 | #endif |
| 1386 | } |
| 1387 | |
| 1388 | static inline bool cpuinfo_has_arm_vfpv3_fp16(void) { |
| 1389 | #if CPUINFO_ARCH_ARM64 |
| 1390 | return true; |
| 1391 | #elif CPUINFO_ARCH_ARM |
| 1392 | return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16; |
| 1393 | #else |
| 1394 | return false; |
| 1395 | #endif |
| 1396 | } |
| 1397 | |
| 1398 | static inline bool cpuinfo_has_arm_vfpv3_fp16_d32(void) { |
| 1399 | #if CPUINFO_ARCH_ARM64 |
| 1400 | return true; |
| 1401 | #elif CPUINFO_ARCH_ARM |
| 1402 | return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16 && cpuinfo_isa.d32; |
| 1403 | #else |
| 1404 | return false; |
| 1405 | #endif |
| 1406 | } |
| 1407 | |
Marat Dukhan | 6022f80 | 2017-09-26 11:56:36 -0700 | [diff] [blame] | 1408 | static inline bool cpuinfo_has_arm_vfpv4(void) { |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1409 | #if CPUINFO_ARCH_ARM64 |
| 1410 | return true; |
| 1411 | #elif CPUINFO_ARCH_ARM |
| 1412 | return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma; |
| 1413 | #else |
| 1414 | return false; |
| 1415 | #endif |
| 1416 | } |
| 1417 | |
Marat Dukhan | 6022f80 | 2017-09-26 11:56:36 -0700 | [diff] [blame] | 1418 | static inline bool cpuinfo_has_arm_vfpv4_d32(void) { |
Marat Dukhan | f720d10 | 2017-09-26 10:33:47 -0700 | [diff] [blame] | 1419 | #if CPUINFO_ARCH_ARM64 |
| 1420 | return true; |
| 1421 | #elif CPUINFO_ARCH_ARM |
| 1422 | return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma && cpuinfo_isa.d32; |
| 1423 | #else |
| 1424 | return false; |
| 1425 | #endif |
| 1426 | } |
| 1427 | |
| 1428 | static inline bool cpuinfo_has_arm_wmmx(void) { |
| 1429 | #if CPUINFO_ARCH_ARM |
| 1430 | return cpuinfo_isa.wmmx; |
| 1431 | #else |
| 1432 | return false; |
| 1433 | #endif |
| 1434 | } |
| 1435 | |
| 1436 | static inline bool cpuinfo_has_arm_wmmx2(void) { |
| 1437 | #if CPUINFO_ARCH_ARM |
| 1438 | return cpuinfo_isa.wmmx2; |
| 1439 | #else |
| 1440 | return false; |
| 1441 | #endif |
| 1442 | } |
| 1443 | |
| 1444 | static inline bool cpuinfo_has_arm_neon(void) { |
| 1445 | #if CPUINFO_ARCH_ARM64 |
| 1446 | return true; |
| 1447 | #elif CPUINFO_ARCH_ARM |
| 1448 | return cpuinfo_isa.neon; |
| 1449 | #else |
| 1450 | return false; |
| 1451 | #endif |
| 1452 | } |
| 1453 | |
| 1454 | static inline bool cpuinfo_has_arm_neon_fp16(void) { |
| 1455 | #if CPUINFO_ARCH_ARM64 |
| 1456 | return true; |
| 1457 | #elif CPUINFO_ARCH_ARM |
| 1458 | return cpuinfo_isa.neon && cpuinfo_isa.fp16; |
| 1459 | #else |
| 1460 | return false; |
| 1461 | #endif |
| 1462 | } |
| 1463 | |
| 1464 | static inline bool cpuinfo_has_arm_neon_fma(void) { |
| 1465 | #if CPUINFO_ARCH_ARM64 |
| 1466 | return true; |
| 1467 | #elif CPUINFO_ARCH_ARM |
| 1468 | return cpuinfo_isa.neon && cpuinfo_isa.fma; |
| 1469 | #else |
| 1470 | return false; |
| 1471 | #endif |
| 1472 | } |
| 1473 | |
| 1474 | static inline bool cpuinfo_has_arm_atomics(void) { |
| 1475 | #if CPUINFO_ARCH_ARM64 |
| 1476 | return cpuinfo_isa.atomics; |
| 1477 | #else |
| 1478 | return false; |
| 1479 | #endif |
| 1480 | } |
| 1481 | |
| 1482 | static inline bool cpuinfo_has_arm_neon_rdm(void) { |
| 1483 | #if CPUINFO_ARCH_ARM64 |
| 1484 | return cpuinfo_isa.rdm; |
| 1485 | #else |
| 1486 | return false; |
| 1487 | #endif |
| 1488 | } |
| 1489 | |
| 1490 | static inline bool cpuinfo_has_arm_fp16_arith(void) { |
| 1491 | #if CPUINFO_ARCH_ARM64 |
| 1492 | return cpuinfo_isa.fp16arith; |
| 1493 | #else |
| 1494 | return false; |
| 1495 | #endif |
| 1496 | } |
| 1497 | |
| 1498 | static inline bool cpuinfo_has_arm_jscvt(void) { |
| 1499 | #if CPUINFO_ARCH_ARM64 |
| 1500 | return cpuinfo_isa.jscvt; |
| 1501 | #else |
| 1502 | return false; |
| 1503 | #endif |
| 1504 | } |
| 1505 | |
| 1506 | static inline bool cpuinfo_has_arm_fcma(void) { |
| 1507 | #if CPUINFO_ARCH_ARM64 |
| 1508 | return cpuinfo_isa.fcma; |
| 1509 | #else |
| 1510 | return false; |
| 1511 | #endif |
| 1512 | } |
| 1513 | |
| 1514 | static inline bool cpuinfo_has_arm_aes(void) { |
| 1515 | #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
| 1516 | return cpuinfo_isa.aes; |
| 1517 | #else |
| 1518 | return false; |
| 1519 | #endif |
| 1520 | } |
| 1521 | |
| 1522 | static inline bool cpuinfo_has_arm_sha1(void) { |
| 1523 | #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
| 1524 | return cpuinfo_isa.sha1; |
| 1525 | #else |
| 1526 | return false; |
| 1527 | #endif |
| 1528 | } |
| 1529 | |
| 1530 | static inline bool cpuinfo_has_arm_sha2(void) { |
| 1531 | #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
| 1532 | return cpuinfo_isa.sha2; |
| 1533 | #else |
| 1534 | return false; |
| 1535 | #endif |
| 1536 | } |
| 1537 | |
| 1538 | static inline bool cpuinfo_has_arm_pmull(void) { |
| 1539 | #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
| 1540 | return cpuinfo_isa.pmull; |
| 1541 | #else |
| 1542 | return false; |
| 1543 | #endif |
| 1544 | } |
| 1545 | |
| 1546 | static inline bool cpuinfo_has_arm_crc32(void) { |
| 1547 | #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
| 1548 | return cpuinfo_isa.crc32; |
| 1549 | #else |
| 1550 | return false; |
| 1551 | #endif |
| 1552 | } |
| 1553 | |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 1554 | const struct cpuinfo_processor* cpuinfo_get_processors(void); |
| 1555 | const struct cpuinfo_core* cpuinfo_get_cores(void); |
| 1556 | const struct cpuinfo_package* cpuinfo_get_packages(void); |
| 1557 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_caches(void); |
| 1558 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_caches(void); |
| 1559 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_caches(void); |
| 1560 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_caches(void); |
| 1561 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_caches(void); |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 1562 | |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 1563 | const struct cpuinfo_processor* cpuinfo_get_processor(uint32_t index); |
| 1564 | const struct cpuinfo_core* cpuinfo_get_core(uint32_t index); |
| 1565 | const struct cpuinfo_package* cpuinfo_get_package(uint32_t index); |
| 1566 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_cache(uint32_t index); |
| 1567 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_cache(uint32_t index); |
| 1568 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_cache(uint32_t index); |
| 1569 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_cache(uint32_t index); |
| 1570 | const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_cache(uint32_t index); |
Marat Dukhan | 3045d4f | 2017-03-04 01:51:42 -0500 | [diff] [blame] | 1571 | |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 1572 | uint32_t cpuinfo_get_processors_count(void); |
| 1573 | uint32_t cpuinfo_get_cores_count(void); |
| 1574 | uint32_t cpuinfo_get_packages_count(void); |
| 1575 | uint32_t CPUINFO_ABI cpuinfo_get_l1i_caches_count(void); |
| 1576 | uint32_t CPUINFO_ABI cpuinfo_get_l1d_caches_count(void); |
| 1577 | uint32_t CPUINFO_ABI cpuinfo_get_l2_caches_count(void); |
| 1578 | uint32_t CPUINFO_ABI cpuinfo_get_l3_caches_count(void); |
| 1579 | uint32_t CPUINFO_ABI cpuinfo_get_l4_caches_count(void); |
Marat Dukhan | 8ecad1a | 2017-05-08 07:21:57 +0000 | [diff] [blame] | 1580 | |
Marat Dukhan | 3040197 | 2017-09-26 18:35:52 -0700 | [diff] [blame] | 1581 | const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void); |
| 1582 | const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void); |
Marat Dukhan | 547fa36 | 2017-03-03 02:47:26 -0500 | [diff] [blame] | 1583 | |
| 1584 | #ifdef __cplusplus |
| 1585 | } /* extern "C" */ |
| 1586 | #endif |
| 1587 | |
| 1588 | #endif /* CPUINFO_H */ |