blob: 934e792984ca9d308890f388bbe7109af28ba576 [file] [log] [blame]
Marat Dukhan2f3950c2017-09-08 18:25:26 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
Marat Dukhan30401972017-09-26 18:35:52 -07008 ASSERT_EQ(8, cpuinfo_get_processors_count());
Marat Dukhan2f3950c2017-09-08 18:25:26 -07009}
10
11TEST(PROCESSORS, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070012 ASSERT_TRUE(cpuinfo_get_processors());
Marat Dukhan2f3950c2017-09-08 18:25:26 -070013}
14
Marat Dukhan2d37dc42017-09-25 01:32:37 -070015TEST(PROCESSORS, smt_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070016 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
Marat Dukhan2f3950c2017-09-08 18:25:26 -070018 }
19}
20
Marat Dukhan2d37dc42017-09-25 01:32:37 -070021TEST(PROCESSORS, core) {
Marat Dukhan30401972017-09-26 18:35:52 -070022 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070024 }
25}
26
Marat Dukhan2b307932018-03-18 16:15:36 -070027TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 switch (i) {
30 case 0:
31 case 1:
32 case 2:
33 case 3:
34 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
35 break;
36 case 4:
37 case 5:
38 case 6:
39 case 7:
40 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
41 break;
42 }
43 }
44}
45
Marat Dukhan2d37dc42017-09-25 01:32:37 -070046TEST(PROCESSORS, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070047 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
48 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
Marat Dukhan2f3950c2017-09-08 18:25:26 -070049 }
50}
51
Marat Dukhan846c1782017-09-13 09:47:26 -070052TEST(PROCESSORS, linux_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070053 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan846c1782017-09-13 09:47:26 -070054 switch (i) {
55 case 0:
56 case 1:
57 case 2:
58 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -070059 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070060 break;
61 case 4:
62 case 5:
63 case 6:
64 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -070065 ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070066 break;
67 }
68 }
69}
70
Marat Dukhan2d37dc42017-09-25 01:32:37 -070071TEST(PROCESSORS, l1i) {
Marat Dukhan30401972017-09-26 18:35:52 -070072 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
73 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070074 }
75}
76
77TEST(PROCESSORS, l1d) {
Marat Dukhan30401972017-09-26 18:35:52 -070078 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
79 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070080 }
81}
82
83TEST(PROCESSORS, l2) {
Marat Dukhan30401972017-09-26 18:35:52 -070084 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -070085 switch (i) {
86 case 0:
87 case 1:
88 case 2:
89 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -070090 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070091 break;
92 case 4:
93 case 5:
94 case 6:
95 case 7:
Marat Dukhan30401972017-09-26 18:35:52 -070096 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070097 break;
98 }
99 }
100}
101
102TEST(PROCESSORS, l3) {
Marat Dukhan30401972017-09-26 18:35:52 -0700103 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
104 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700105 }
106}
107
108TEST(PROCESSORS, l4) {
Marat Dukhan30401972017-09-26 18:35:52 -0700109 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
110 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700111 }
112}
113
Marat Dukhan7073e832017-09-24 22:23:55 -0700114TEST(CORES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700115 ASSERT_EQ(8, cpuinfo_get_cores_count());
Marat Dukhan7073e832017-09-24 22:23:55 -0700116}
117
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700118TEST(CORES, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700119 ASSERT_TRUE(cpuinfo_get_cores());
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700120}
121
Marat Dukhan7073e832017-09-24 22:23:55 -0700122TEST(CORES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700123 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
124 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
Marat Dukhan7073e832017-09-24 22:23:55 -0700125 }
126}
127
128TEST(CORES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700129 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
130 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
Marat Dukhan7073e832017-09-24 22:23:55 -0700131 }
132}
133
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700134TEST(CORES, core_id) {
Marat Dukhan30401972017-09-26 18:35:52 -0700135 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
136 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700137 }
138}
139
Marat Dukhan2b307932018-03-18 16:15:36 -0700140TEST(CORES, cluster) {
141 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
142 switch (i) {
143 case 0:
144 case 1:
145 case 2:
146 case 3:
147 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
148 break;
149 case 4:
150 case 5:
151 case 6:
152 case 7:
153 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
154 break;
155 }
156 }
157}
158
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700159TEST(CORES, package) {
Marat Dukhan30401972017-09-26 18:35:52 -0700160 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
161 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700162 }
163}
164
165TEST(CORES, vendor) {
Marat Dukhan30401972017-09-26 18:35:52 -0700166 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
167 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700168 }
169}
170
171TEST(CORES, uarch) {
Marat Dukhan30401972017-09-26 18:35:52 -0700172 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
173 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700174 }
175}
176
177TEST(CORES, midr) {
Marat Dukhan30401972017-09-26 18:35:52 -0700178 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
179 ASSERT_EQ(UINT32_C(0x410FD033), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700180 }
181}
182
Marat Dukhan575a6302018-03-10 14:38:49 -0800183TEST(CORES, DISABLED_frequency) {
184 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
185 ASSERT_EQ(UINT32_C(1500000000), cpuinfo_get_core(i)->frequency);
186 }
187}
188
Marat Dukhandbc78402018-03-18 22:49:35 -0700189TEST(CLUSTERS, count) {
190 ASSERT_EQ(2, cpuinfo_get_clusters_count());
191}
192
193TEST(CLUSTERS, non_null) {
194 ASSERT_TRUE(cpuinfo_get_clusters());
195}
196
197TEST(CLUSTERS, processor_start) {
198 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
199 switch (i) {
200 case 0:
201 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start);
202 break;
203 case 1:
204 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_start);
205 break;
206 }
207 }
208}
209
210TEST(CLUSTERS, processor_count) {
211 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
212 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count);
213 }
214}
215
216TEST(CLUSTERS, core_start) {
217 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
218 switch (i) {
219 case 0:
220 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start);
221 break;
222 case 1:
223 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_start);
224 break;
225 }
226 }
227}
228
229TEST(CLUSTERS, core_count) {
230 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
231 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count);
232 }
233}
234
235TEST(CLUSTERS, cluster_id) {
236 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
237 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id);
238 }
239}
240
241TEST(CLUSTERS, package) {
242 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
243 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package);
244 }
245}
246
247TEST(CLUSTERS, vendor) {
248 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
249 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor);
250 }
251}
252
253TEST(CLUSTERS, uarch) {
254 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
255 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_cluster(i)->uarch);
256 }
257}
258
259TEST(CLUSTERS, midr) {
260 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
261 ASSERT_EQ(UINT32_C(0x410FD033), cpuinfo_get_cluster(i)->midr);
262 }
263}
264
265TEST(CLUSTERS, DISABLED_frequency) {
266 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
267 ASSERT_EQ(UINT64_C(1500000000), cpuinfo_get_cluster(i)->frequency);
268 }
269}
270
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700271TEST(PACKAGES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700272 ASSERT_EQ(1, cpuinfo_get_packages_count());
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700273}
274
275TEST(PACKAGES, name) {
Marat Dukhan30401972017-09-26 18:35:52 -0700276 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700277 ASSERT_EQ("Samsung Exynos 7580",
Marat Dukhan30401972017-09-26 18:35:52 -0700278 std::string(cpuinfo_get_package(i)->name,
279 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700280 }
281}
282
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800283TEST(PACKAGES, gpu_name) {
284 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
285 ASSERT_EQ("ARM Mali-T720",
286 std::string(cpuinfo_get_package(i)->gpu_name,
287 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
288 }
289}
290
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700291TEST(PACKAGES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700292 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
293 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700294 }
295}
296
297TEST(PACKAGES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700298 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
299 ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700300 }
301}
302
303TEST(PACKAGES, core_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700304 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
305 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700306 }
307}
308
309TEST(PACKAGES, core_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700310 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
311 ASSERT_EQ(8, cpuinfo_get_package(i)->core_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700312 }
313}
314
Marat Dukhan2b307932018-03-18 16:15:36 -0700315TEST(PACKAGES, cluster_start) {
316 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
317 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
318 }
319}
320
321TEST(PACKAGES, cluster_count) {
322 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
323 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
324 }
325}
326
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700327TEST(ISA, thumb) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700328 #if CPUINFO_ARCH_ARM
329 ASSERT_TRUE(cpuinfo_has_arm_thumb());
330 #elif CPUINFO_ARCH_ARM64
331 ASSERT_FALSE(cpuinfo_has_arm_thumb());
332 #endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700333}
334
335TEST(ISA, thumb2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700336 #if CPUINFO_ARCH_ARM
337 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
338 #elif CPUINFO_ARCH_ARM64
339 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
340 #endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700341}
342
343TEST(ISA, armv5e) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700344 #if CPUINFO_ARCH_ARM
345 ASSERT_TRUE(cpuinfo_has_arm_v5e());
346 #elif CPUINFO_ARCH_ARM64
347 ASSERT_FALSE(cpuinfo_has_arm_v5e());
348 #endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700349}
350
351TEST(ISA, armv6) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700352 #if CPUINFO_ARCH_ARM
353 ASSERT_TRUE(cpuinfo_has_arm_v6());
354 #elif CPUINFO_ARCH_ARM64
355 ASSERT_FALSE(cpuinfo_has_arm_v6());
356 #endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700357}
358
359TEST(ISA, armv6k) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700360 #if CPUINFO_ARCH_ARM
361 ASSERT_TRUE(cpuinfo_has_arm_v6k());
362 #elif CPUINFO_ARCH_ARM64
363 ASSERT_FALSE(cpuinfo_has_arm_v6k());
364 #endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700365}
366
367TEST(ISA, armv7) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700368 #if CPUINFO_ARCH_ARM
369 ASSERT_TRUE(cpuinfo_has_arm_v7());
370 #elif CPUINFO_ARCH_ARM64
371 ASSERT_FALSE(cpuinfo_has_arm_v7());
372 #endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700373}
374
375TEST(ISA, armv7mp) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700376 #if CPUINFO_ARCH_ARM
377 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
378 #elif CPUINFO_ARCH_ARM64
379 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
380 #endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700381}
382
383TEST(ISA, idiv) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700384 ASSERT_TRUE(cpuinfo_has_arm_idiv());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700385}
386
387TEST(ISA, vfpv2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700388 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700389}
390
391TEST(ISA, vfpv3) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700392 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700393}
394
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700395TEST(ISA, vfpv3_d32) {
396 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700397}
398
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700399TEST(ISA, vfpv3_fp16) {
400 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700401}
402
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700403TEST(ISA, vfpv3_fp16_d32) {
404 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
405}
406
407TEST(ISA, vfpv4) {
408 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
409}
410
411TEST(ISA, vfpv4_d32) {
412 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700413}
414
415TEST(ISA, wmmx) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700416 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700417}
418
419TEST(ISA, wmmx2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700420 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700421}
422
423TEST(ISA, neon) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700424 ASSERT_TRUE(cpuinfo_has_arm_neon());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700425}
426
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700427TEST(ISA, neon_fp16) {
428 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700429}
430
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700431TEST(ISA, neon_fma) {
432 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700433}
434
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700435TEST(ISA, atomics) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700436 ASSERT_FALSE(cpuinfo_has_arm_atomics());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700437}
438
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700439TEST(ISA, neon_rdm) {
440 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700441}
442
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700443TEST(ISA, fp16_arith) {
444 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700445}
446
447TEST(ISA, jscvt) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700448 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700449}
450
451TEST(ISA, fcma) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700452 ASSERT_FALSE(cpuinfo_has_arm_fcma());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700453}
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700454
455TEST(ISA, aes) {
456 ASSERT_TRUE(cpuinfo_has_arm_aes());
457}
458
459TEST(ISA, sha1) {
460 ASSERT_TRUE(cpuinfo_has_arm_sha1());
461}
462
463TEST(ISA, sha2) {
464 ASSERT_TRUE(cpuinfo_has_arm_sha2());
465}
466
467TEST(ISA, pmull) {
468 ASSERT_TRUE(cpuinfo_has_arm_pmull());
469}
470
471TEST(ISA, crc32) {
472 ASSERT_TRUE(cpuinfo_has_arm_crc32());
473}
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700474
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700475TEST(L1I, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700476 ASSERT_EQ(8, cpuinfo_get_l1i_caches_count());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700477}
478
479TEST(L1I, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700480 ASSERT_TRUE(cpuinfo_get_l1i_caches());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700481}
482
483TEST(L1I, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700484 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
485 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700486 }
487}
488
489TEST(L1I, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700490 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
491 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700492 }
493}
494
495TEST(L1I, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700496 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
497 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
498 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700499 }
500}
501
502TEST(L1I, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700503 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
504 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700505 }
506}
507
508TEST(L1I, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700509 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
510 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700511 }
512}
513
514TEST(L1I, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700515 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
516 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700517 }
518}
519
520TEST(L1I, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700521 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
522 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
523 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700524 }
525}
526
527TEST(L1D, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700528 ASSERT_EQ(8, cpuinfo_get_l1d_caches_count());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700529}
530
531TEST(L1D, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700532 ASSERT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700533}
534
535TEST(L1D, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700536 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
537 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700538 }
539}
540
541TEST(L1D, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700542 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
543 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700544 }
545}
546
547TEST(L1D, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700548 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
549 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
550 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700551 }
552}
553
554TEST(L1D, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700555 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
556 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700557 }
558}
559
560TEST(L1D, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700561 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
562 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700563 }
564}
565
566TEST(L1D, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700567 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
568 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700569 }
570}
571
572TEST(L1D, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700573 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
574 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
575 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700576 }
577}
578
579TEST(L2, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700580 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700581}
582
583TEST(L2, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700584 ASSERT_TRUE(cpuinfo_get_l2_caches());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700585}
586
587TEST(L2, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700588 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
589 ASSERT_EQ(256 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700590 }
591}
592
593TEST(L2, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700594 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
595 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700596 }
597}
598
599TEST(L2, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700600 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
601 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
602 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700603 }
604}
605
606TEST(L2, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700607 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
608 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700609 }
610}
611
612TEST(L2, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700613 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
614 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700615 }
616}
617
618TEST(L2, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700619 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
620 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700621 }
622}
623
624TEST(L2, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700625 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
626 switch (i) {
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700627 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700628 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
629 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700630 break;
631 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700632 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_start);
633 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700634 break;
635 }
636 }
637}
638
639TEST(L3, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700640 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
641 ASSERT_FALSE(cpuinfo_get_l3_caches());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700642}
643
644TEST(L4, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700645 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
646 ASSERT_FALSE(cpuinfo_get_l4_caches());
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700647}
648
649#include <galaxy-j7-uae.h>
650
651int main(int argc, char* argv[]) {
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800652#if CPUINFO_ARCH_ARM
653 cpuinfo_set_hwcap(UINT32_C(0x0007B0D6));
654 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800655#endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700656 cpuinfo_mock_filesystem(filesystem);
Marat Dukhand1565252017-09-12 00:29:01 -0700657#ifdef __ANDROID__
658 cpuinfo_mock_android_properties(properties);
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800659 cpuinfo_mock_gl_renderer("Mali-T720");
Marat Dukhand1565252017-09-12 00:29:01 -0700660#endif
Marat Dukhan2f3950c2017-09-08 18:25:26 -0700661 cpuinfo_initialize();
662 ::testing::InitGoogleTest(&argc, argv);
663 return RUN_ALL_TESTS();
Marat Dukhan30401972017-09-26 18:35:52 -0700664}