blob: 07e7a0d8c279fb12a1dbb8a20f45c7cf8eb88ce3 [file] [log] [blame]
Marat Dukhan6e5dcda2017-09-08 17:23:37 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
Marat Dukhan30401972017-09-26 18:35:52 -07008 ASSERT_EQ(4, cpuinfo_get_processors_count());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -07009}
10
11TEST(PROCESSORS, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070012 ASSERT_TRUE(cpuinfo_get_processors());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -070013}
14
Marat Dukhan2d37dc42017-09-25 01:32:37 -070015TEST(PROCESSORS, smt_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070016 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -070018 }
19}
20
Marat Dukhan2d37dc42017-09-25 01:32:37 -070021TEST(PROCESSORS, core) {
Marat Dukhan30401972017-09-26 18:35:52 -070022 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070024 }
25}
26
Marat Dukhan2b307932018-03-18 16:15:36 -070027TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
30 }
31}
32
Marat Dukhan2d37dc42017-09-25 01:32:37 -070033TEST(PROCESSORS, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070034 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
35 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -070036 }
37}
38
Marat Dukhan846c1782017-09-13 09:47:26 -070039TEST(PROCESSORS, linux_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070040 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
41 ASSERT_EQ(i, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070042 }
43}
44
Marat Dukhan2d37dc42017-09-25 01:32:37 -070045TEST(PROCESSORS, l1i) {
Marat Dukhan30401972017-09-26 18:35:52 -070046 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
47 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070048 }
49}
50
51TEST(PROCESSORS, l1d) {
Marat Dukhan30401972017-09-26 18:35:52 -070052 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
53 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070054 }
55}
56
57TEST(PROCESSORS, l2) {
Marat Dukhan30401972017-09-26 18:35:52 -070058 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
59 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070060 }
61}
62
63TEST(PROCESSORS, l3) {
Marat Dukhan30401972017-09-26 18:35:52 -070064 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
65 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070066 }
67}
68
69TEST(PROCESSORS, l4) {
Marat Dukhan30401972017-09-26 18:35:52 -070070 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
71 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070072 }
73}
74
Marat Dukhan7073e832017-09-24 22:23:55 -070075TEST(CORES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -070076 ASSERT_EQ(4, cpuinfo_get_cores_count());
Marat Dukhan7073e832017-09-24 22:23:55 -070077}
78
Marat Dukhan2d37dc42017-09-25 01:32:37 -070079TEST(CORES, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070080 ASSERT_TRUE(cpuinfo_get_cores());
Marat Dukhan2d37dc42017-09-25 01:32:37 -070081}
82
Marat Dukhan7073e832017-09-24 22:23:55 -070083TEST(CORES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -070084 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
85 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
Marat Dukhan7073e832017-09-24 22:23:55 -070086 }
87}
88
89TEST(CORES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -070090 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
91 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
Marat Dukhan7073e832017-09-24 22:23:55 -070092 }
93}
94
Marat Dukhan2d37dc42017-09-25 01:32:37 -070095TEST(CORES, core_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070096 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
97 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070098 }
99}
100
Marat Dukhan2b307932018-03-18 16:15:36 -0700101TEST(CORES, cluster) {
102 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
103 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
104 }
105}
106
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700107TEST(CORES, package) {
Marat Dukhan30401972017-09-26 18:35:52 -0700108 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
109 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700110 }
111}
112
113TEST(CORES, vendor) {
Marat Dukhan30401972017-09-26 18:35:52 -0700114 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
115 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700116 }
117}
118
119TEST(CORES, uarch) {
Marat Dukhan30401972017-09-26 18:35:52 -0700120 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
121 ASSERT_EQ(cpuinfo_uarch_cortex_a57, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700122 }
123}
124
125TEST(CORES, midr) {
Marat Dukhan30401972017-09-26 18:35:52 -0700126 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
127 ASSERT_EQ(UINT32_C(0x411FD071), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700128 }
129}
130
Marat Dukhan575a6302018-03-10 14:38:49 -0800131TEST(CORES, DISABLED_frequency) {
132 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
133 ASSERT_EQ(UINT64_C(1912500000), cpuinfo_get_core(i)->frequency);
134 }
135}
136
Marat Dukhandbc78402018-03-18 22:49:35 -0700137TEST(CLUSTERS, count) {
138 ASSERT_EQ(1, cpuinfo_get_clusters_count());
139}
140
141TEST(CLUSTERS, non_null) {
142 ASSERT_TRUE(cpuinfo_get_clusters());
143}
144
145TEST(CLUSTERS, processor_start) {
146 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
147 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start);
148 }
149}
150
151TEST(CLUSTERS, processor_count) {
152 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
153 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count);
154 }
155}
156
157TEST(CLUSTERS, core_start) {
158 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
159 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start);
160 }
161}
162
163TEST(CLUSTERS, core_count) {
164 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
165 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count);
166 }
167}
168
169TEST(CLUSTERS, cluster_id) {
170 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
171 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id);
172 }
173}
174
175TEST(CLUSTERS, package) {
176 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
177 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package);
178 }
179}
180
181TEST(CLUSTERS, vendor) {
182 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
183 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor);
184 }
185}
186
187TEST(CLUSTERS, uarch) {
188 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
189 ASSERT_EQ(cpuinfo_uarch_cortex_a57, cpuinfo_get_cluster(i)->uarch);
190 }
191}
192
193TEST(CLUSTERS, midr) {
194 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
195 ASSERT_EQ(UINT32_C(0x411FD071), cpuinfo_get_cluster(i)->midr);
196 }
197}
198
199TEST(CLUSTERS, DISABLED_frequency) {
200 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
201 ASSERT_EQ(UINT64_C(1912500000), cpuinfo_get_cluster(i)->frequency);
202 }
203}
204
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700205TEST(PACKAGES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700206 ASSERT_EQ(1, cpuinfo_get_packages_count());
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700207}
208
209TEST(PACKAGES, name) {
Marat Dukhan30401972017-09-26 18:35:52 -0700210 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhan93982f22017-10-20 13:10:23 -0700211 ASSERT_EQ("Nvidia Tegra T210",
Marat Dukhan30401972017-09-26 18:35:52 -0700212 std::string(cpuinfo_get_package(i)->name,
213 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700214 }
215}
216
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800217TEST(PACKAGES, gpu_name) {
218 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhan3985cf82017-12-18 18:58:26 -0800219 ASSERT_EQ("Nvidia Tegra X1",
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800220 std::string(cpuinfo_get_package(i)->gpu_name,
221 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
222 }
223}
224
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700225TEST(PACKAGES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700226 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
227 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700228 }
229}
230
231TEST(PACKAGES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700232 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
233 ASSERT_EQ(4, cpuinfo_get_package(i)->processor_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700234 }
235}
236
237TEST(PACKAGES, core_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700238 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
239 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700240 }
241}
242
243TEST(PACKAGES, core_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700244 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
245 ASSERT_EQ(4, cpuinfo_get_package(i)->core_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700246 }
247}
248
Marat Dukhan2b307932018-03-18 16:15:36 -0700249TEST(PACKAGES, cluster_start) {
250 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
251 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
252 }
253}
254
255TEST(PACKAGES, cluster_count) {
256 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
257 ASSERT_EQ(1, cpuinfo_get_package(i)->cluster_count);
258 }
259}
260
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700261TEST(ISA, thumb) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700262 #if CPUINFO_ARCH_ARM
263 ASSERT_TRUE(cpuinfo_has_arm_thumb());
264 #elif CPUINFO_ARCH_ARM64
265 ASSERT_FALSE(cpuinfo_has_arm_thumb());
266 #endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700267}
268
269TEST(ISA, thumb2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700270 #if CPUINFO_ARCH_ARM
271 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
272 #elif CPUINFO_ARCH_ARM64
273 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
274 #endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700275}
276
277TEST(ISA, armv5e) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700278 #if CPUINFO_ARCH_ARM
279 ASSERT_TRUE(cpuinfo_has_arm_v5e());
280 #elif CPUINFO_ARCH_ARM64
281 ASSERT_FALSE(cpuinfo_has_arm_v5e());
282 #endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700283}
284
285TEST(ISA, armv6) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700286 #if CPUINFO_ARCH_ARM
287 ASSERT_TRUE(cpuinfo_has_arm_v6());
288 #elif CPUINFO_ARCH_ARM64
289 ASSERT_FALSE(cpuinfo_has_arm_v6());
290 #endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700291}
292
293TEST(ISA, armv6k) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700294 #if CPUINFO_ARCH_ARM
295 ASSERT_TRUE(cpuinfo_has_arm_v6k());
296 #elif CPUINFO_ARCH_ARM64
297 ASSERT_FALSE(cpuinfo_has_arm_v6k());
298 #endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700299}
300
301TEST(ISA, armv7) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700302 #if CPUINFO_ARCH_ARM
303 ASSERT_TRUE(cpuinfo_has_arm_v7());
304 #elif CPUINFO_ARCH_ARM64
305 ASSERT_FALSE(cpuinfo_has_arm_v7());
306 #endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700307}
308
309TEST(ISA, armv7mp) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700310 #if CPUINFO_ARCH_ARM
311 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
312 #elif CPUINFO_ARCH_ARM64
313 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
314 #endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700315}
316
317TEST(ISA, idiv) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700318 ASSERT_TRUE(cpuinfo_has_arm_idiv());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700319}
320
321TEST(ISA, vfpv2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700322 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700323}
324
325TEST(ISA, vfpv3) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700326 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700327}
328
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700329TEST(ISA, vfpv3_d32) {
330 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700331}
332
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700333TEST(ISA, vfpv3_fp16) {
334 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700335}
336
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700337TEST(ISA, vfpv3_fp16_d32) {
338 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
339}
340
341TEST(ISA, vfpv4) {
342 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
343}
344
345TEST(ISA, vfpv4_d32) {
346 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700347}
348
349TEST(ISA, wmmx) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700350 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700351}
352
353TEST(ISA, wmmx2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700354 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700355}
356
357TEST(ISA, neon) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700358 ASSERT_TRUE(cpuinfo_has_arm_neon());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700359}
360
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700361TEST(ISA, neon_fp16) {
362 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700363}
364
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700365TEST(ISA, neon_fma) {
366 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700367}
368
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700369TEST(ISA, atomics) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700370 ASSERT_FALSE(cpuinfo_has_arm_atomics());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700371}
372
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700373TEST(ISA, neon_rdm) {
374 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700375}
376
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700377TEST(ISA, fp16_arith) {
378 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700379}
380
381TEST(ISA, jscvt) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700382 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700383}
384
385TEST(ISA, fcma) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700386 ASSERT_FALSE(cpuinfo_has_arm_fcma());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700387}
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700388
389TEST(ISA, aes) {
390 ASSERT_TRUE(cpuinfo_has_arm_aes());
391}
392
393TEST(ISA, sha1) {
394 ASSERT_TRUE(cpuinfo_has_arm_sha1());
395}
396
397TEST(ISA, sha2) {
398 ASSERT_TRUE(cpuinfo_has_arm_sha2());
399}
400
401TEST(ISA, pmull) {
402 ASSERT_TRUE(cpuinfo_has_arm_pmull());
403}
404
405TEST(ISA, crc32) {
406 ASSERT_TRUE(cpuinfo_has_arm_crc32());
407}
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700408
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700409TEST(L1I, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700410 ASSERT_EQ(4, cpuinfo_get_l1i_caches_count());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700411}
412
413TEST(L1I, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700414 ASSERT_TRUE(cpuinfo_get_l1i_caches());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700415}
416
417TEST(L1I, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700418 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
419 ASSERT_EQ(48 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700420 }
421}
422
423TEST(L1I, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700424 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
425 ASSERT_EQ(3, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700426 }
427}
428
429TEST(L1I, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700430 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
431 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
432 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700433 }
434}
435
436TEST(L1I, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700437 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
438 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700439 }
440}
441
442TEST(L1I, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700443 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
444 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700445 }
446}
447
448TEST(L1I, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700449 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
450 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700451 }
452}
453
454TEST(L1I, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700455 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
456 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
457 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700458 }
459}
460
461TEST(L1D, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700462 ASSERT_EQ(4, cpuinfo_get_l1d_caches_count());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700463}
464
465TEST(L1D, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700466 ASSERT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700467}
468
469TEST(L1D, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700470 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
471 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700472 }
473}
474
475TEST(L1D, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700476 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
477 ASSERT_EQ(2, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700478 }
479}
480
481TEST(L1D, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700482 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
483 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
484 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700485 }
486}
487
488TEST(L1D, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700489 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
490 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700491 }
492}
493
494TEST(L1D, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700495 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
496 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700497 }
498}
499
500TEST(L1D, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700501 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
502 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700503 }
504}
505
506TEST(L1D, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700507 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
508 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
509 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700510 }
511}
512
513TEST(L2, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700514 ASSERT_EQ(1, cpuinfo_get_l2_caches_count());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700515}
516
517TEST(L2, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700518 ASSERT_TRUE(cpuinfo_get_l2_caches());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700519}
520
521TEST(L2, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700522 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
523 ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700524 }
525}
526
527TEST(L2, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700528 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
529 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700530 }
531}
532
533TEST(L2, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700534 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
535 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
536 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700537 }
538}
539
540TEST(L2, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700541 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
542 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700543 }
544}
545
546TEST(L2, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700547 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
548 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700549 }
550}
551
552TEST(L2, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700553 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
554 ASSERT_EQ(CPUINFO_CACHE_INCLUSIVE, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700555 }
556}
557
558TEST(L2, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700559 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
560 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
561 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700562 }
563}
564
565TEST(L3, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700566 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
567 ASSERT_FALSE(cpuinfo_get_l3_caches());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700568}
569
570TEST(L4, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700571 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
572 ASSERT_FALSE(cpuinfo_get_l4_caches());
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700573}
574
575#include <pixel-c.h>
576
577int main(int argc, char* argv[]) {
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800578#if CPUINFO_ARCH_ARM
579 cpuinfo_set_hwcap(UINT32_C(0x0027B0D6));
580 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
581#elif CPUINFO_ARCH_ARM64
582 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
583#endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700584 cpuinfo_mock_filesystem(filesystem);
Marat Dukhan5659d292017-09-12 23:21:03 -0700585#ifdef __ANDROID__
586 cpuinfo_mock_android_properties(properties);
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800587 cpuinfo_mock_gl_renderer("NVIDIA Tegra");
Marat Dukhan5659d292017-09-12 23:21:03 -0700588#endif
Marat Dukhan6e5dcda2017-09-08 17:23:37 -0700589 cpuinfo_initialize();
590 ::testing::InitGoogleTest(&argc, argv);
591 return RUN_ALL_TESTS();
Marat Dukhan93982f22017-10-20 13:10:23 -0700592}