blob: a60d4a3fd52e68616feed07ed95630dfe610a459 [file] [log] [blame]
Marat Dukhan6d7938e2017-08-24 16:55:17 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
Marat Dukhan30401972017-09-26 18:35:52 -07008 ASSERT_EQ(5, cpuinfo_get_processors_count());
Marat Dukhan6d7938e2017-08-24 16:55:17 -07009}
10
11TEST(PROCESSORS, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070012 ASSERT_TRUE(cpuinfo_get_processors());
Marat Dukhan6d7938e2017-08-24 16:55:17 -070013}
14
Marat Dukhan2d37dc42017-09-25 01:32:37 -070015TEST(PROCESSORS, smt_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070016 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
Marat Dukhan6d7938e2017-08-24 16:55:17 -070018 }
19}
20
Marat Dukhan2d37dc42017-09-25 01:32:37 -070021TEST(PROCESSORS, core) {
Marat Dukhan30401972017-09-26 18:35:52 -070022 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070024 }
25}
26
Marat Dukhan2b307932018-03-18 16:15:36 -070027TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 switch (i) {
30 case 0:
31 case 1:
32 case 2:
33 case 3:
34 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
35 break;
36 case 4:
37 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
38 break;
39 }
40 }
41}
42
Marat Dukhan2d37dc42017-09-25 01:32:37 -070043TEST(PROCESSORS, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070044 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
45 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
Marat Dukhan6d7938e2017-08-24 16:55:17 -070046 }
47}
48
Marat Dukhan846c1782017-09-13 09:47:26 -070049TEST(PROCESSORS, linux_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070050 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
51 ASSERT_EQ(i, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070052 }
53}
54
Marat Dukhan2d37dc42017-09-25 01:32:37 -070055TEST(PROCESSORS, l1i) {
Marat Dukhan30401972017-09-26 18:35:52 -070056 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
57 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070058 }
59}
60
61TEST(PROCESSORS, l1d) {
Marat Dukhan30401972017-09-26 18:35:52 -070062 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
63 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070064 }
65}
66
67TEST(PROCESSORS, l2) {
Marat Dukhan30401972017-09-26 18:35:52 -070068 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -070069 switch (i) {
70 case 0:
71 case 1:
72 case 2:
73 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -070074 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070075 break;
76 case 4:
Marat Dukhan30401972017-09-26 18:35:52 -070077 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070078 break;
79 }
80 }
81}
82
83TEST(PROCESSORS, l3) {
Marat Dukhan30401972017-09-26 18:35:52 -070084 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
85 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070086 }
87}
88
89TEST(PROCESSORS, l4) {
Marat Dukhan30401972017-09-26 18:35:52 -070090 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
91 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070092 }
93}
94
Marat Dukhan7073e832017-09-24 22:23:55 -070095TEST(CORES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -070096 ASSERT_EQ(5, cpuinfo_get_cores_count());
Marat Dukhan7073e832017-09-24 22:23:55 -070097}
98
Marat Dukhan2d37dc42017-09-25 01:32:37 -070099TEST(CORES, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700100 ASSERT_TRUE(cpuinfo_get_cores());
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700101}
102
Marat Dukhan7073e832017-09-24 22:23:55 -0700103TEST(CORES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700104 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
105 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
Marat Dukhan7073e832017-09-24 22:23:55 -0700106 }
107}
108
109TEST(CORES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700110 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
111 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
Marat Dukhan7073e832017-09-24 22:23:55 -0700112 }
113}
114
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700115TEST(CORES, core_id) {
Marat Dukhan30401972017-09-26 18:35:52 -0700116 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
117 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700118 }
119}
120
Marat Dukhan2b307932018-03-18 16:15:36 -0700121TEST(CORES, cluster) {
122 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
123 switch (i) {
124 case 0:
125 case 1:
126 case 2:
127 case 3:
128 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
129 break;
130 case 4:
131 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
132 break;
133 }
134 }
135}
136
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700137TEST(CORES, package) {
Marat Dukhan30401972017-09-26 18:35:52 -0700138 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
139 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700140 }
141}
142
143TEST(CORES, vendor) {
Marat Dukhan30401972017-09-26 18:35:52 -0700144 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
145 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700146 }
147}
148
149TEST(CORES, uarch) {
Marat Dukhan30401972017-09-26 18:35:52 -0700150 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
151 ASSERT_EQ(cpuinfo_uarch_cortex_a7, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700152 }
153}
154
155TEST(CORES, midr) {
Marat Dukhan30401972017-09-26 18:35:52 -0700156 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
157 ASSERT_EQ(UINT32_C(0x410FC075), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700158 }
159}
160
Marat Dukhan575a6302018-03-10 14:38:49 -0800161TEST(CORES, DISABLED_frequency) {
162 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
163 ASSERT_EQ(UINT64_C(1495000000), cpuinfo_get_core(i)->frequency);
164 }
165}
166
Marat Dukhandbc78402018-03-18 22:49:35 -0700167TEST(CLUSTERS, count) {
168 ASSERT_EQ(2, cpuinfo_get_clusters_count());
169}
170
171TEST(CLUSTERS, non_null) {
172 ASSERT_TRUE(cpuinfo_get_clusters());
173}
174
175TEST(CLUSTERS, processor_start) {
176 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
177 switch (i) {
178 case 0:
179 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start);
180 break;
181 case 1:
182 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_start);
183 break;
184 }
185 }
186}
187
188TEST(CLUSTERS, processor_count) {
189 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
190 switch (i) {
191 case 0:
192 ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count);
193 break;
194 case 1:
195 ASSERT_EQ(1, cpuinfo_get_cluster(i)->processor_count);
196 break;
197 }
198 }
199}
200
201TEST(CLUSTERS, core_start) {
202 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
203 switch (i) {
204 case 0:
205 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start);
206 break;
207 case 1:
208 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_start);
209 break;
210 }
211 }
212}
213
214TEST(CLUSTERS, core_count) {
215 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
216 switch (i) {
217 case 0:
218 ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count);
219 break;
220 case 1:
221 ASSERT_EQ(1, cpuinfo_get_cluster(i)->core_count);
222 break;
223 }
224 }
225}
226
227TEST(CLUSTERS, cluster_id) {
228 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
229 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id);
230 }
231}
232
233TEST(CLUSTERS, package) {
234 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
235 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package);
236 }
237}
238
239TEST(CLUSTERS, vendor) {
240 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
241 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor);
242 }
243}
244
245TEST(CLUSTERS, uarch) {
246 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
247 ASSERT_EQ(cpuinfo_uarch_cortex_a7, cpuinfo_get_cluster(i)->uarch);
248 }
249}
250
251TEST(CLUSTERS, midr) {
252 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
253 ASSERT_EQ(UINT32_C(0x410FC075), cpuinfo_get_cluster(i)->midr);
254 }
255}
256
257TEST(CLUSTERS, DISABLED_frequency) {
258 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
259 ASSERT_EQ(UINT64_C(1495000000), cpuinfo_get_cluster(i)->frequency);
260 }
261}
262
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700263TEST(PACKAGES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700264 ASSERT_EQ(1, cpuinfo_get_packages_count());
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700265}
266
267TEST(PACKAGES, name) {
Marat Dukhan30401972017-09-26 18:35:52 -0700268 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700269 ASSERT_EQ("Leadcore LC1860",
Marat Dukhan30401972017-09-26 18:35:52 -0700270 std::string(cpuinfo_get_package(i)->name,
271 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700272 }
273}
274
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800275TEST(PACKAGES, gpu_name) {
276 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
277 ASSERT_EQ("ARM Mali-T622",
278 std::string(cpuinfo_get_package(i)->gpu_name,
279 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
280 }
281}
282
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700283TEST(PACKAGES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700284 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
285 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700286 }
287}
288
289TEST(PACKAGES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700290 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
291 ASSERT_EQ(5, cpuinfo_get_package(i)->processor_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700292 }
293}
294
295TEST(PACKAGES, core_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700296 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
297 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700298 }
299}
300
301TEST(PACKAGES, core_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700302 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
303 ASSERT_EQ(5, cpuinfo_get_package(i)->core_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700304 }
305}
306
Marat Dukhan2b307932018-03-18 16:15:36 -0700307TEST(PACKAGES, cluster_start) {
308 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
309 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
310 }
311}
312
313TEST(PACKAGES, cluster_count) {
314 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
315 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
316 }
317}
318
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700319TEST(ISA, thumb) {
Marat Dukhan30401972017-09-26 18:35:52 -0700320 ASSERT_TRUE(cpuinfo_has_arm_thumb());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700321}
322
323TEST(ISA, thumb2) {
Marat Dukhan30401972017-09-26 18:35:52 -0700324 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700325}
326
327TEST(ISA, armv5e) {
Marat Dukhan30401972017-09-26 18:35:52 -0700328 ASSERT_TRUE(cpuinfo_has_arm_v5e());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700329}
330
331TEST(ISA, armv6) {
Marat Dukhan30401972017-09-26 18:35:52 -0700332 ASSERT_TRUE(cpuinfo_has_arm_v6());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700333}
334
335TEST(ISA, armv6k) {
Marat Dukhan30401972017-09-26 18:35:52 -0700336 ASSERT_TRUE(cpuinfo_has_arm_v6k());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700337}
338
339TEST(ISA, armv7) {
Marat Dukhan30401972017-09-26 18:35:52 -0700340 ASSERT_TRUE(cpuinfo_has_arm_v7());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700341}
342
343TEST(ISA, armv7mp) {
Marat Dukhan30401972017-09-26 18:35:52 -0700344 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700345}
346
347TEST(ISA, idiv) {
Marat Dukhan30401972017-09-26 18:35:52 -0700348 ASSERT_TRUE(cpuinfo_has_arm_idiv());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700349}
350
351TEST(ISA, vfpv2) {
Marat Dukhan30401972017-09-26 18:35:52 -0700352 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700353}
354
355TEST(ISA, vfpv3) {
Marat Dukhan30401972017-09-26 18:35:52 -0700356 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700357}
358
Marat Dukhan30401972017-09-26 18:35:52 -0700359TEST(ISA, vfpv3_d32) {
360 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700361}
362
Marat Dukhan30401972017-09-26 18:35:52 -0700363TEST(ISA, vfpv3_fp16) {
364 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700365}
366
Marat Dukhan30401972017-09-26 18:35:52 -0700367TEST(ISA, vfpv3_fp16_d32) {
368 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
369}
370
371TEST(ISA, vfpv4) {
372 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
373}
374
375TEST(ISA, vfpv4_d32) {
376 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700377}
378
379TEST(ISA, wmmx) {
Marat Dukhan30401972017-09-26 18:35:52 -0700380 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700381}
382
383TEST(ISA, wmmx2) {
Marat Dukhan30401972017-09-26 18:35:52 -0700384 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700385}
386
387TEST(ISA, neon) {
Marat Dukhan30401972017-09-26 18:35:52 -0700388 ASSERT_TRUE(cpuinfo_has_arm_neon());
389}
390
391TEST(ISA, neon_fp16) {
392 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
393}
394
395TEST(ISA, neon_fma) {
396 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
397}
398
399TEST(ISA, atomics) {
400 ASSERT_FALSE(cpuinfo_has_arm_atomics());
401}
402
403TEST(ISA, neon_rdm) {
404 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
405}
406
407TEST(ISA, fp16_arith) {
408 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
409}
410
411TEST(ISA, jscvt) {
412 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
413}
414
415TEST(ISA, fcma) {
416 ASSERT_FALSE(cpuinfo_has_arm_fcma());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700417}
418
419TEST(ISA, aes) {
Marat Dukhan30401972017-09-26 18:35:52 -0700420 ASSERT_FALSE(cpuinfo_has_arm_aes());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700421}
422
423TEST(ISA, sha1) {
Marat Dukhan30401972017-09-26 18:35:52 -0700424 ASSERT_FALSE(cpuinfo_has_arm_sha1());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700425}
426
427TEST(ISA, sha2) {
Marat Dukhan30401972017-09-26 18:35:52 -0700428 ASSERT_FALSE(cpuinfo_has_arm_sha2());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700429}
430
431TEST(ISA, pmull) {
Marat Dukhan30401972017-09-26 18:35:52 -0700432 ASSERT_FALSE(cpuinfo_has_arm_pmull());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700433}
434
435TEST(ISA, crc32) {
Marat Dukhan30401972017-09-26 18:35:52 -0700436 ASSERT_FALSE(cpuinfo_has_arm_crc32());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700437}
438
439TEST(L1I, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700440 ASSERT_EQ(5, cpuinfo_get_l1i_caches_count());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700441}
442
443TEST(L1I, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700444 ASSERT_TRUE(cpuinfo_get_l1i_caches());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700445}
446
447TEST(L1I, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700448 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
449 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700450 }
451}
452
453TEST(L1I, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700454 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
455 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700456 }
457}
458
459TEST(L1I, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700460 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
461 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
462 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700463 }
464}
465
466TEST(L1I, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700467 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
468 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700469 }
470}
471
472TEST(L1I, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700473 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
474 ASSERT_EQ(32, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700475 }
476}
477
478TEST(L1I, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700479 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
480 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700481 }
482}
483
484TEST(L1I, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700485 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
486 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
487 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700488 }
489}
490
491TEST(L1D, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700492 ASSERT_EQ(5, cpuinfo_get_l1d_caches_count());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700493}
494
495TEST(L1D, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700496 ASSERT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700497}
498
499TEST(L1D, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700500 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
501 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700502 }
503}
504
505TEST(L1D, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700506 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
507 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700508 }
509}
510
511TEST(L1D, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700512 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
513 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
514 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700515 }
516}
517
518TEST(L1D, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700519 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
520 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700521 }
522}
523
524TEST(L1D, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700525 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
526 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700527 }
528}
529
530TEST(L1D, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700531 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
532 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700533 }
534}
535
536TEST(L1D, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700537 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
538 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
539 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700540 }
541}
542
543TEST(L2, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700544 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700545}
546
547TEST(L2, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700548 ASSERT_TRUE(cpuinfo_get_l2_caches());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700549}
550
551TEST(L2, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700552 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
553 switch (i) {
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700554 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700555 ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700556 break;
557 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700558 ASSERT_EQ(128 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700559 break;
560 }
561 }
562}
563
564TEST(L2, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700565 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
566 ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700567 }
568}
569
570TEST(L2, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700571 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
572 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
573 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700574 }
575}
576
577TEST(L2, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700578 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
579 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700580 }
581}
582
583TEST(L2, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700584 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
585 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700586 }
587}
588
589TEST(L2, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700590 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
591 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700592 }
593}
594
595TEST(L2, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700596 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
597 switch (i) {
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700598 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700599 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
600 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700601 break;
602 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700603 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_start);
604 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700605 break;
606 }
607 }
608}
609
610TEST(L3, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700611 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
612 ASSERT_FALSE(cpuinfo_get_l3_caches());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700613}
614
615TEST(L4, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700616 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
617 ASSERT_FALSE(cpuinfo_get_l4_caches());
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700618}
619
620#include <xiaomi-redmi-2a.h>
621
622int main(int argc, char* argv[]) {
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800623#if CPUINFO_ARCH_ARM
624 cpuinfo_set_hwcap(UINT32_C(0x0007B0D7));
625#endif
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700626 cpuinfo_mock_filesystem(filesystem);
Marat Dukhand1565252017-09-12 00:29:01 -0700627#ifdef __ANDROID__
628 cpuinfo_mock_android_properties(properties);
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800629 cpuinfo_mock_gl_renderer("Mali-T622");
Marat Dukhand1565252017-09-12 00:29:01 -0700630#endif
Marat Dukhan6d7938e2017-08-24 16:55:17 -0700631 cpuinfo_initialize();
632 ::testing::InitGoogleTest(&argc, argv);
633 return RUN_ALL_TESTS();
Marat Dukhan30401972017-09-26 18:35:52 -0700634}