Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 1 | #version 450
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| 2 |
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| 3 | #extension GL_ARB_gpu_shader_int64: enable
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| 4 | #extension GL_AMD_gpu_shader_half_float: enable
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 5 | #extension GL_AMD_gpu_shader_int16: enable
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 6 | #extension GL_AMD_shader_ballot: enable
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| 7 |
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| 8 | layout (local_size_x = 8, local_size_y = 8, local_size_z = 1) in;
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| 9 |
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| 10 | layout(binding = 0) buffer Buffers
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| 11 | {
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| 12 | int i;
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| 13 | uvec2 uv;
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| 14 | vec3 fv;
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| 15 | dvec4 dv;
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| 16 | int64_t i64;
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| 17 | u64vec2 u64v;
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| 18 | f16vec3 f16v;
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 19 | i16vec4 i16v;
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| 20 | uint16_t u16;
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 21 | };
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| 22 |
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| 23 | void main()
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| 24 | {
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 25 | i = minInvocationsAMD(i);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 26 | uv = minInvocationsAMD(uv);
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| 27 | fv = minInvocationsAMD(fv);
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| 28 | dv = minInvocationsAMD(dv);
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| 29 | i64 = minInvocationsAMD(i64);
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| 30 | u64v = minInvocationsAMD(u64v);
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| 31 | f16v = minInvocationsAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 32 | i16v = minInvocationsAMD(i16v);
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| 33 | u16 = minInvocationsAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 34 |
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| 35 | i = maxInvocationsAMD(i);
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| 36 | uv = maxInvocationsAMD(uv);
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| 37 | fv = maxInvocationsAMD(fv);
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| 38 | dv = maxInvocationsAMD(dv);
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| 39 | i64 = maxInvocationsAMD(i64);
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| 40 | u64v = maxInvocationsAMD(u64v);
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| 41 | f16v = maxInvocationsAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 42 | i16v = maxInvocationsAMD(i16v);
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| 43 | u16 = maxInvocationsAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 44 |
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| 45 | i = addInvocationsAMD(i);
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| 46 | uv = addInvocationsAMD(uv);
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| 47 | fv = addInvocationsAMD(fv);
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| 48 | dv = addInvocationsAMD(dv);
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| 49 | i64 = addInvocationsAMD(i64);
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| 50 | u64v = addInvocationsAMD(u64v);
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| 51 | f16v = addInvocationsAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 52 | i16v = addInvocationsAMD(i16v);
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| 53 | u16 = addInvocationsAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 54 |
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| 55 | i = minInvocationsNonUniformAMD(i);
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| 56 | uv = minInvocationsNonUniformAMD(uv);
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| 57 | fv = minInvocationsNonUniformAMD(fv);
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| 58 | dv = minInvocationsNonUniformAMD(dv);
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| 59 | i64 = minInvocationsNonUniformAMD(i64);
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| 60 | u64v = minInvocationsNonUniformAMD(u64v);
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| 61 | f16v = minInvocationsNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 62 | i16v = minInvocationsNonUniformAMD(i16v);
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| 63 | u16 = minInvocationsNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 64 |
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| 65 | i = maxInvocationsNonUniformAMD(i);
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| 66 | uv = maxInvocationsNonUniformAMD(uv);
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| 67 | fv = maxInvocationsNonUniformAMD(fv);
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| 68 | dv = maxInvocationsNonUniformAMD(dv);
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| 69 | i64 = maxInvocationsNonUniformAMD(i64);
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| 70 | u64v = maxInvocationsNonUniformAMD(u64v);
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| 71 | f16v = maxInvocationsNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 72 | i16v = maxInvocationsNonUniformAMD(i16v);
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| 73 | u16 = maxInvocationsNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 74 |
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| 75 | i = addInvocationsNonUniformAMD(i);
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| 76 | uv = addInvocationsNonUniformAMD(uv);
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| 77 | fv = addInvocationsNonUniformAMD(fv);
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| 78 | dv = addInvocationsNonUniformAMD(dv);
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| 79 | i64 = addInvocationsNonUniformAMD(i64);
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| 80 | u64v = addInvocationsNonUniformAMD(u64v);
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| 81 | f16v = addInvocationsNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 82 | i16v = addInvocationsNonUniformAMD(i16v);
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| 83 | u16 = addInvocationsNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 84 |
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| 85 | i = minInvocationsInclusiveScanAMD(i);
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| 86 | uv = minInvocationsInclusiveScanAMD(uv);
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| 87 | fv = minInvocationsInclusiveScanAMD(fv);
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| 88 | dv = minInvocationsInclusiveScanAMD(dv);
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| 89 | i64 = minInvocationsInclusiveScanAMD(i64);
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| 90 | u64v = minInvocationsInclusiveScanAMD(u64v);
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| 91 | f16v = minInvocationsInclusiveScanAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 92 | i16v = minInvocationsInclusiveScanAMD(i16v);
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| 93 | u16 = minInvocationsInclusiveScanAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 94 |
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| 95 | i = maxInvocationsInclusiveScanAMD(i);
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| 96 | uv = maxInvocationsInclusiveScanAMD(uv);
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| 97 | fv = maxInvocationsInclusiveScanAMD(fv);
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| 98 | dv = maxInvocationsInclusiveScanAMD(dv);
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| 99 | i64 = maxInvocationsInclusiveScanAMD(i64);
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| 100 | u64v = maxInvocationsInclusiveScanAMD(u64v);
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| 101 | f16v = maxInvocationsInclusiveScanAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 102 | i16v = maxInvocationsInclusiveScanAMD(i16v);
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| 103 | u16 = maxInvocationsInclusiveScanAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 104 |
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| 105 | i = addInvocationsInclusiveScanAMD(i);
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| 106 | uv = addInvocationsInclusiveScanAMD(uv);
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| 107 | fv = addInvocationsInclusiveScanAMD(fv);
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| 108 | dv = addInvocationsInclusiveScanAMD(dv);
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| 109 | i64 = addInvocationsInclusiveScanAMD(i64);
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| 110 | u64v = addInvocationsInclusiveScanAMD(u64v);
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| 111 | f16v = addInvocationsInclusiveScanAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 112 | i16v = addInvocationsInclusiveScanAMD(i16v);
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| 113 | u16 = addInvocationsInclusiveScanAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 114 |
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| 115 | i = minInvocationsExclusiveScanAMD(i);
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| 116 | uv = minInvocationsExclusiveScanAMD(uv);
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| 117 | fv = minInvocationsExclusiveScanAMD(fv);
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| 118 | dv = minInvocationsExclusiveScanAMD(dv);
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| 119 | i64 = minInvocationsExclusiveScanAMD(i64);
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| 120 | u64v = minInvocationsExclusiveScanAMD(u64v);
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| 121 | f16v = minInvocationsExclusiveScanAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 122 | i16v = minInvocationsExclusiveScanAMD(i16v);
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| 123 | u16 = minInvocationsExclusiveScanAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 124 |
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| 125 | i = maxInvocationsExclusiveScanAMD(i);
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| 126 | uv = maxInvocationsExclusiveScanAMD(uv);
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| 127 | fv = maxInvocationsExclusiveScanAMD(fv);
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| 128 | dv = maxInvocationsExclusiveScanAMD(dv);
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| 129 | i64 = maxInvocationsExclusiveScanAMD(i64);
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| 130 | u64v = maxInvocationsExclusiveScanAMD(u64v);
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| 131 | f16v = maxInvocationsExclusiveScanAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 132 | i16v = maxInvocationsExclusiveScanAMD(i16v);
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| 133 | u16 = maxInvocationsExclusiveScanAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 134 |
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| 135 | i = addInvocationsExclusiveScanAMD(i);
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| 136 | uv = addInvocationsExclusiveScanAMD(uv);
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| 137 | fv = addInvocationsExclusiveScanAMD(fv);
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| 138 | dv = addInvocationsExclusiveScanAMD(dv);
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| 139 | i64 = addInvocationsExclusiveScanAMD(i64);
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| 140 | u64v = addInvocationsExclusiveScanAMD(u64v);
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| 141 | f16v = addInvocationsExclusiveScanAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 142 | i16v = addInvocationsExclusiveScanAMD(i16v);
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| 143 | u16 = addInvocationsExclusiveScanAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 144 |
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| 145 | i = minInvocationsInclusiveScanNonUniformAMD(i);
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| 146 | uv = minInvocationsInclusiveScanNonUniformAMD(uv);
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| 147 | fv = minInvocationsInclusiveScanNonUniformAMD(fv);
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| 148 | dv = minInvocationsInclusiveScanNonUniformAMD(dv);
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| 149 | i64 = minInvocationsInclusiveScanNonUniformAMD(i64);
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| 150 | u64v = minInvocationsInclusiveScanNonUniformAMD(u64v);
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| 151 | f16v = minInvocationsInclusiveScanNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 152 | i16v = minInvocationsInclusiveScanNonUniformAMD(i16v);
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| 153 | u16 = minInvocationsInclusiveScanNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 154 |
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| 155 | i = maxInvocationsInclusiveScanNonUniformAMD(i);
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| 156 | uv = maxInvocationsInclusiveScanNonUniformAMD(uv);
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| 157 | fv = maxInvocationsInclusiveScanNonUniformAMD(fv);
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| 158 | dv = maxInvocationsInclusiveScanNonUniformAMD(dv);
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| 159 | i64 = maxInvocationsInclusiveScanNonUniformAMD(i64);
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| 160 | u64v = maxInvocationsInclusiveScanNonUniformAMD(u64v);
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| 161 | f16v = maxInvocationsInclusiveScanNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 162 | i16v = maxInvocationsInclusiveScanNonUniformAMD(i16v);
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| 163 | u16 = maxInvocationsInclusiveScanNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 164 |
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| 165 | i = addInvocationsInclusiveScanNonUniformAMD(i);
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| 166 | uv = addInvocationsInclusiveScanNonUniformAMD(uv);
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| 167 | fv = addInvocationsInclusiveScanNonUniformAMD(fv);
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| 168 | dv = addInvocationsInclusiveScanNonUniformAMD(dv);
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| 169 | i64 = addInvocationsInclusiveScanNonUniformAMD(i64);
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| 170 | u64v = addInvocationsInclusiveScanNonUniformAMD(u64v);
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| 171 | f16v = addInvocationsInclusiveScanNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 172 | i16v = addInvocationsInclusiveScanNonUniformAMD(i16v);
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| 173 | u16 = addInvocationsInclusiveScanNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 174 |
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| 175 | i = minInvocationsExclusiveScanNonUniformAMD(i);
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| 176 | uv = minInvocationsExclusiveScanNonUniformAMD(uv);
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| 177 | fv = minInvocationsExclusiveScanNonUniformAMD(fv);
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| 178 | dv = minInvocationsExclusiveScanNonUniformAMD(dv);
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| 179 | i64 = minInvocationsExclusiveScanNonUniformAMD(i64);
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| 180 | u64v = minInvocationsExclusiveScanNonUniformAMD(u64v);
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| 181 | f16v = minInvocationsExclusiveScanNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 182 | i16v = minInvocationsExclusiveScanNonUniformAMD(i16v);
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| 183 | u16 = minInvocationsExclusiveScanNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 184 |
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| 185 | i = maxInvocationsExclusiveScanNonUniformAMD(i);
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| 186 | uv = maxInvocationsExclusiveScanNonUniformAMD(uv);
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| 187 | fv = maxInvocationsExclusiveScanNonUniformAMD(fv);
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| 188 | dv = maxInvocationsExclusiveScanNonUniformAMD(dv);
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| 189 | i64 = maxInvocationsExclusiveScanNonUniformAMD(i64);
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| 190 | u64v = maxInvocationsExclusiveScanNonUniformAMD(u64v);
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| 191 | f16v = maxInvocationsExclusiveScanNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 192 | i16v = maxInvocationsExclusiveScanNonUniformAMD(i16v);
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| 193 | u16 = maxInvocationsExclusiveScanNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 194 |
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| 195 | i = addInvocationsExclusiveScanNonUniformAMD(i);
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| 196 | uv = addInvocationsExclusiveScanNonUniformAMD(uv);
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| 197 | fv = addInvocationsExclusiveScanNonUniformAMD(fv);
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| 198 | dv = addInvocationsExclusiveScanNonUniformAMD(dv);
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| 199 | i64 = addInvocationsExclusiveScanNonUniformAMD(i64);
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| 200 | u64v = addInvocationsExclusiveScanNonUniformAMD(u64v);
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| 201 | f16v = addInvocationsExclusiveScanNonUniformAMD(f16v);
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Rex Xu | ae06d1f | 2018-03-28 16:33:01 +0800 | [diff] [blame^] | 202 | i16v = addInvocationsExclusiveScanNonUniformAMD(i16v);
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| 203 | u16 = addInvocationsExclusiveScanNonUniformAMD(u16);
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Rex Xu | 430ef40 | 2016-10-14 17:22:23 +0800 | [diff] [blame] | 204 | }
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