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gerrit-public.fairphone.software / platform / external / elfutils / 3cbdd387c752999255aea91600b5cfdefbeac7d0 / . / libcpu / defs / i386
blob: b0cdfb4b9df94d3cc6bedac4c040dd1cbbf4bdb1 [file] [log] [blame]
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame^]1%mask {s} 1
2%mask {w} 1
3%mask {w1} 1
4dnl floating point reg suffix
5%mask {D} 1
6%mask {imm8} 8
7%mask {imms8} 8
8%mask {imm16} 16
9%mask {reg} 3
10%mask {reg16} 3
11%mask {tttn} 4
12%mask {gg} 2
13%mask {mod} 2
14%mask {moda} 2
15%mask {MOD} 2
16%mask {r_m} 3
17dnl like {r_m} but referencing byte register
18%mask {8r_m} 3
19dnl like {r_m} but referencing 16-bit register
20%mask {16r_m} 3
21%mask {disp8} 8
22dnl imm really is 8/16/32 bit depending on the situation.
23%mask {imm} 8
24%mask {imms} 8
25%mask {rel} 32
26%mask {abs} 32
27%mask {absval} 32
28%mask {sel} 16
29%mask {imm32} 32
30%mask {ccc} 3
31%mask {ddd} 3
32%mask {sreg3} 3
33%mask {sreg2} 2
34%mask {mmxreg} 3
35%mask {mmxreg2} 3
36%mask {R_M} 3
37%mask {0g} 2
38%mask {GG} 2
39%mask {gG} 2
40%mask {Mod} 2
41%mask {xmmreg} 3
42%mask {R_m} 3
43%mask {mmreg} 3
44%mask {xmmreg1} 3
45%mask {xmmreg2} 3
46%mask {predpd} 8
47%mask {predps} 8
48%mask {predsd} 8
49%mask {predss} 8
50%mask {freg} 3
51%mask {fmod} 2
52%mask {fr_m} 3
53%prefix {R}
54%prefix {RE}
55%suffix {W}
56%suffix {w0}
57%synonym {xmmreg1} {xmmreg}
58%synonym {xmmreg2} {xmmreg}
59
60%%
61ifdef(`i386',
62`00110111:aaa
6311010101,00001010:aad
6411010100,00001010:aam
6500111111:aas
66')dnl
670001010{w},{imm}:adc {imm}{w},{ax}{w}
681000000{w},{mod}010{r_m},{imm}:adc{w} {imm}{w},{mod}{r_m}{w}
691000001{w},{mod}010{r_m},{imms8}:adc{w} {imms8},{mod}{r_m}
700001000{w},{mod}{reg}{r_m}:adc {reg}{w},{mod}{r_m}
710001001{w},{mod}{reg}{r_m}:adc {mod}{r_m},{reg}{w}
720000010{w},{imm}:add {imm}{w},{ax}{w}
731000000{w},{mod}000{r_m},{imm}:add{w} {imm}{w},{mod}{r_m}{w}
7410000011,{mod}000{r_m},{imms8}:add{w0} {imms8},{mod}{r_m}
750000000{w},{mod}{reg}{r_m}:add {reg}{w},{mod}{r_m}
760000001{w},{mod}{reg}{r_m}:add {mod}{r_m},{reg}{w}
7711110010,00001111,01011000,{Mod}{xmmreg}{R_m}:addsd {Mod}{R_m},{xmmreg}
7811110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg}
7901100110,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubpd {Mod}{R_m},{xmmreg}
8011110010,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubps {Mod}{R_m},{xmmreg}
810010010{w},{imm}:and {imm}{w},{ax}{w}
821000000{w},{mod}100{r_m},{imm}:and{w} {imm}{w},{mod}{r_m}{w}
831000001{w},{mod}100{r_m},{imms}:and{w} {imms},{mod}{r_m}
840010000{w},{mod}{reg}{r_m}:and {reg}{w},{mod}{r_m}{w}
850010001{w},{mod}{reg}{r_m}:and {mod}{r_m}{w},{reg}{w}
8601100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg}
8700001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
8801100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg}
8900001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
90ifdef(`i386',
91`01100011,{mod}{reg16}{r_m}:arpl {reg16},{mod}{r_m}
9201100010,{moda}{reg}{r_m}:bound {reg},{moda}{r_m}
93')dnl
9400001111,10111100,{mod}{reg}{r_m}:bsf {reg},{mod}{r_m}
9500001111,10111101,{mod}{reg}{r_m}:bsr {reg},{mod}{r_m}
9600001111,11001{reg}:bswap {reg}
9700001111,10100011,{mod}{reg}{r_m}:bt {reg},{mod}{r_m}
9800001111,10111010,{mod}100{r_m},{imm8}:bt {imm8},{mod}{r_m}
9900001111,10111011,{mod}{reg}{r_m}:btc {reg},{mod}{r_m}
10000001111,10111010,{mod}111{r_m},{imm8}:btc {imm8},{mod}{r_m}
10100001111,10110011,{mod}{reg}{r_m}:btr {reg},{mod}{r_m}
10200001111,10111010,{mod}110{r_m},{imm8}:btr {imm8},{mod}{r_m}
10300001111,10101011,{mod}{reg}{r_m}:bts {reg},{mod}{r_m}
10400001111,10111010,{mod}101{r_m},{imm8}:bts {imm8},{mod}{r_m}
10511101000,{rel}:call {rel}
10611111111,{mod}010{r_m}:call *{mod}{r_m}
107ifdef(`i386',
108`10011010,{absval},{sel}:lcall {sel},{absval}
109')dnl
11011111111,{mod}011{r_m}:lcall *{mod}{r_m}
111# SPECIAL 10011000:[{rex.w}?cltq:{dpfx}?cbtw:cwtl]
11210011000:INVALID
113# SPECIAL 10011001:[{rew.w}?cqto:{dpfx}?cltd:cwtd]
11410011001:INVALID
11511111000:clc
11611111100:cld
11700001111,10101110,{mod}111{r_m}:clflush {mod}{r_m}
11811111010:cli
11900001111,00000101:syscall
12000001111,00000110:clts
12100001111,00000111:sysret
12200001111,00110100:sysenter
12300001111,00110101:sysexit
12411110101:cmc
12500001111,0100{tttn},{mod}{reg}{r_m}:cmov{tttn} {mod}{r_m},{reg}
1260011110{w},{imm}:cmp {imm}{w},{ax}{w}
1271000000{w},{mod}111{r_m},{imm}:cmp{w} {imm}{w},{mod}{r_m}{w}
12810000011,{mod}111{r_m},{imms8}:cmp{w0} {imms8},{mod}{r_m}
1290011100{w},{mod}{reg}{r_m}:cmp {reg}{w},{mod}{r_m}{w}
1300011101{w},{mod}{reg}{r_m}:cmp {mod}{r_m}{w},{reg}{w}
13101100110,00001111,11000010,{Mod}{xmmreg}{R_m},{predpd}:cmpl{predpd} {Mod}{R_m},{xmmreg}
132ifdef(`ASSEMBLER',
133`01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg
134}')dnl
13500001111,11000010,{Mod}{xmmreg}{R_m},{predps}:cmpl{predps} {Mod}{R_m},{xmmreg}
136ifdef(`ASSEMBLER',
137`00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg}
138')dnl
1391010011{w}:{RE}cmps{w} {es_di},{ds_si}
14011110010,00001111,11000010,{Mod}{xmmreg}{R_m},{predsd}:cmpl{predsd} {Mod}{R_m},{xmmreg}
141ifdef(`ASSEMBLER',
142`11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg}
143')dnl
14411110011,00001111,11000010,{Mod}{xmmreg}{R_m},{predss}:cmpl{predss} {Mod}{R_m},{xmmreg}
145ifdef(`ASSEMBLER',
146`11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg}
147')dnl
14800001111,1011000{w},{mod}{reg}{r_m}:cmpxchg{w} {reg},{mod}{r_m}
149# SPECIAL 00001111,11000111,{mod}001{r_m}:[{rex.w}?cmpxchg16b:cmpxchg8b] {reg},{mod}{r_m}
15000001111,10100010:cpuid
15111110011,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtdq2pd {Mod}{R_m},{xmmreg}
15200001111,01011011,{Mod}{xmmreg}{R_m}:cvtdq2ps {Mod}{R_m},{xmmreg}
15311110010,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtpd2dq {Mod}{R_m},{xmmreg}
15401100110,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtpd2ps {Mod}{R_m},{xmmreg}
15501100110,00001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2pd {MOD}{R_M},{xmmreg}
15600001111,00101010,{MOD}{xmmreg}{R_M}:{R}INVALID {MOD}{R_M},{xmmreg}
15701100110,00001111,01011011,{Mod}{xmmreg}{R_m}:cvtps2dq {Mod}{R_m},{xmmreg}
15800001111,01011010,{Mod}{xmmreg}{R_m}:cvtps2pd {Mod}{R_m},{xmmreg}
15911110010,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtsd2ss {Mod}{R_m},{xmmreg}
16011110010,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2sd {mod}{r_m},{xmmreg}
16111110011,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2ss {mod}{r_m},{xmmreg}
16211110011,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtss2sd {Mod}{R_m},{xmmreg}
16301100110,00001111,11100110,{Mod}{xmmreg}{R_m}:cvttpd2dq {Mod}{R_m},{xmmreg}
16411110011,00001111,01011011,{Mod}{mmxreg}{R_m}:cvttps2dq {Mod}{R_m},{mmxreg}
165ifdef(`i386',
166`00100111:daa
16700101111:das
168')dnl
1691111111{w},{mod}001{r_m}:dec{w} {mod}{r_m}{w}
170ifdef(`i386',
171`01001{reg}:dec {reg}
172')dnl
1731111011{w},{mod}110{r_m}:div{w} {mod}{r_m}{w}
17401100110,00001111,01011110,{Mod}{xmmreg}{R_m}:divpd {Mod}{R_m},{xmmreg}
17500001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg}
17611110010,00001111,01011110,{Mod}{xmmreg}{R_m}:divsd {Mod}{R_m},{xmmreg}
17711110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg}
17800001111,01110111:emms
17911001000,{imm16},{imm8}:enter {imm16},{imm8}
18011011001,11010000:fnop
18111011001,11100000:fchs
18211011001,11100001:fabs
18311011001,11100100:ftst
18411011001,11100101:fxam
18511011001,11101000:fld1
18611011001,11101001:fldl2t
18711011001,11101010:fldl2e
18811011001,11101011:fldpi
18911011001,11101100:fldlg2
19011011001,11101101:fldln2
19111011001,11101110:fldz
19211011001,11110000:f2xm1
19311011001,11110001:fyl2x
19411011001,11110010:fptan
19511011001,11110011:fpatan
19611011001,11110100:fxtract
19711011001,11110101:fprem1
19811011001,11110110:fdecstp
19911011001,11110111:fincstp
20011011001,11111000:fprem
20111011001,11111001:fyl2xp1
20211011001,11111010:fsqrt
20311011001,11111011:fsincos
20411011001,11111100:frndint
20511011001,11111101:fscale
20611011001,11111110:fsin
20711011001,11111111:fcos
208# ORDER
20911011000,11000{freg}:fadd {freg},%st
21011011100,11000{freg}:fadd %st,{freg}
21111011{D}00,{mod}000{r_m}:fadd{D} {mod}{r_m}
212# ORDER END
213# ORDER
21411011000,11001{freg}:fmul {freg},%st
21511011100,11001{freg}:fmul %st,{freg}
21611011{D}00,{mod}001{r_m}:fmul{D} {mod}{r_m}
217# ORDER END
218# ORDER
21911011000,11100{freg}:fsub {freg},%st
22011011100,11100{freg}:fsub %st,{freg}
22111011{D}00,{mod}100{r_m}:fsub{D} {mod}{r_m}
222# ORDER END
223# ORDER
22411011000,11101{freg}:fsubr {freg},%st
22511011100,11101{freg}:fsubr %st,{freg}
22611011{D}00,{mod}101{r_m}:fsubr{D} {mod}{r_m}
227# ORDER END
228# ORDER
22911011101,11010{freg}:fst {freg}
23011011{D}01,{mod}010{r_m}:fst{D} {mod}{r_m}
231# ORDER END
232# ORDER
23311011101,11011{freg}:fstp {freg}
23411011{D}01,{mod}011{r_m}:fstp{D} {mod}{r_m}
235# ORDER END
23611011001,{mod}100{r_m}:fldenv {mod}{r_m}
23711011001,{mod}101{r_m}:fldcw {mod}{r_m}
23811011001,{mod}110{r_m}:fnstenv {mod}{r_m}
23911011001,{mod}111{r_m}:fnstcw {mod}{r_m}
24011011001,11001{freg}:fxch {freg}
241# ORDER
24211011110,11000{freg}:faddp %st,{freg}
243ifdef(`ASSEMBLER',
244`11011110,11000001:faddp
245')dnl
246# ORDER
24711011010,11000{freg}:fcmovb {freg},%st
24811011{w1}10,{mod}000{r_m}:fiadd{w1} {mod}{r_m}
249# ORDER END
250# ORDER
25111011010,11001{freg}:fcmove {freg},%st
25211011110,11001{freg}:fmulp %st,{freg}
25311011{w1}10,{mod}001{r_m}:fimul{w1} {mod}{r_m}
254# ORDER END
255# ORDER
25611011110,11100{freg}:fsubp %st,{freg}
25711011{w1}10,{mod}100{r_m}:fisub{w1} {mod}{r_m}
258# ORDER END
259# ORDER
26011011110,11101{freg}:fsubrp %st,{freg}
26111011{w1}10,{mod}101{r_m}:fisubr{w1} {mod}{r_m}
262# ORDER END
263# ORDER
26411011111,11100000:fnstsw %ax
26511011111,{mod}100{r_m}:fbld {mod}{r_m}
266# ORDER END
267# ORDER
26811011111,11110{freg}:fcomip {freg},%st
26911011111,{mod}110{r_m}:fbstp {mod}{r_m}
270# ORDER END
27111011001,11100000:fchs
272# ORDER
27310011011,11011011,11100010:fclex
27410011011,11011011,11100011:finit
27510011011:fwait
276# END ORDER
27711011011,11100010:fnclex
27811011010,11000{freg}:fcmovb {freg},%st
27911011010,11001{freg}:fcmove {freg},%st
28011011010,11010{freg}:fcmovbe {freg},%st
28111011010,11011{freg}:fcmovu {freg},%st
28211011011,11000{freg}:fcmovnb {freg},%st
28311011011,11001{freg}:fcmovne {freg},%st
28411011011,11010{freg}:fcmovnbe {freg},%st
28511011011,11011{freg}:fcmovnu {freg},%st
286# ORDER
28711011000,11010{freg}:fcom {freg}
288ifdef(`ASSEMBLER',
289`11011000,11010001:fcom
290')dnl
29111011{D}00,{mod}010{r_m}:fcom{D} {mod}{r_m}
292# END ORDER
293# ORDER
29411011000,11011{freg}:fcomp {freg}
295ifdef(`ASSEMBLER',
296`11011000,11011001:fcomp
297')dnl
29811011{D}00,{mod}011{r_m}:fcomp{D} {mod}{r_m}
299# END ORDER
30011011110,11011001:fcompp
30111011011,11110{freg}:fcomi {freg},%st
30211011111,11110{freg}:fcomip {freg},%st
30311011011,11101{freg}:fucomi {freg},%st
30411011111,11101{freg}:fucomip {freg},%st
30511011001,11111111:fcos
30611011001,11110110:fdecstp
307# ORDER
30811011000,11110{freg}:fdiv {freg},%st
30911011100,11110{freg}:fdiv %st,{freg}
31011011{D}00,{mod}110{r_m}:fdiv{D} {mod}{r_m}
311# END ORDER
31211011010,{mod}110{r_m}:fidivl {mod}{r_m}
313# ORDER
31411011110,11110{freg}:fdivp %st,{freg}
31511011110,{mod}110{r_m}:fidiv {mod}{r_m}
316# END ORDER
31711011110,11111{freg}:fdivrp %st,{freg}
318ifdef(`ASSEMBLER',
319`11011110,11111001:fdivp
320')dnl
321# ORDER
32211011000,11111{freg}:fdivr {freg},%st
32311011100,11111{freg}:fdivr %st,{freg}
32411011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m}
325# END ORDER
32611011010,{mod}111{r_m}:fidivrl {mod}{r_m}
32711011110,{mod}111{r_m}:fidivr {mod}{r_m}
32811011110,11110{freg}:fdivrp %st,{freg}
329ifdef(`ASSEMBLER',
330`11011110,11110001:fdivrp
331')dnl
33211011101,11000{freg}:ffree {freg}
33311011010,11010{freg}:fcmovbe {freg}
33411011{w1}10,{mod}010{r_m}:ficom{w1} {mod}{r_m}
33511011010,11011{freg}:fcmovu {freg}
33611011{w1}10,{mod}011{r_m}:ficomp{w1} {mod}{r_m}
33711011111,{mod}000{r_m}:fild {mod}{r_m}
33811011011,{mod}000{r_m}:fildl {mod}{r_m}
33911011111,{mod}101{r_m}:fildll {mod}{r_m}
34011011001,11110111:fincstp
34111011011,11100011:fninit
34211011{w1}11,{mod}010{r_m}:fist{w1} {mod}{r_m}
34311011{w1}11,{mod}011{r_m}:fistp{w1} {mod}{r_m}
34411011111,{mod}111{r_m}:fistpll {mod}{r_m}
34511011{w1}11,{mod}001{r_m}:fisttp{w1} {mod}{r_m}
34611011101,{mod}001{r_m}:fisttpll {mod}{r_m}
34711011011,{mod}101{r_m}:fldt {mod}{r_m}
34811011011,{mod}111{r_m}:fstpt {mod}{r_m}
349# ORDER
35011011001,11000{freg}:fld {freg}
35111011{D}01,{mod}000{r_m}:fld{D} {mod}{r_m}
352# ORDER END
353# ORDER
35411011101,11100{freg}:fucom {freg}
35511011101,{mod}100{r_m}:frstor {mod}{r_m}
356# ORDER END
35711011101,11101{freg}:fucomp {freg}
35811011101,{mod}110{r_m}:fnsave {mod}{r_m}
35911011101,{mod}111{r_m}:fnstsw {mod}{r_m}
360#
361#
362#
36311110100:hlt
3641111011{w},{mod}111{r_m}:idiv{w} {mod}{r_m}{w}
3651111011{w},{mod}101{r_m}:imul{w} {mod}{r_m}{w}
36600001111,10101111,{mod}{reg}{r_m}:imul {reg},{mod}{r_m}
367011010{s}1,{mod}{reg}{r_m},{imm}:imul {imm}{s},{mod}{r_m},{reg}
3681110010{w},{imm8}:in {imm8},{ax}{w}
3691110110{w}:in {dx},{ax}{w}
3701111111{w},{mod}000{r_m}:inc{w} {mod}{r_m}{w}
37101000{reg}:inc {reg}
3720110110{w}:{R}ins{w} {dx},{es_di}
37311001101,{imm8}:int {imm8}
37411001100:int3
37511001110:into
37600001111,00001000:invd
377# ORDER
37800001111,00000001,11111000:swapgs
37900001111,00000001,{mod}111{r_m}:invlpg {mod}{r_m}
380# ORDER END
38111001111:iret{W}
3820111{tttn},{disp8}:j{tttn} {disp8}
38300001111,1000{tttn},{rel}:j{tttn} {rel}
38400001111,1001{tttn},{mod}000{8r_m}:set{tttn} {mod}{8r_m}
385# SPECIAL 11100011,{disp8}:[{dpfx}?jcxz:jecxz] {disp8}
38611100011,{disp8}:INVALID {disp8}
38711101011,{disp8}:jmp {disp8}
38811101001,{rel}:jmp {rel}
38911111111,{mod}100{r_m}:jmp *{mod}{r_m}
39011101010,{absval},{sel}:ljmp {sel},{absval}
39111111111,{mod}101{r_m}:ljmp *{mod}{r_m}
39210011111:lahf
39300001111,00000010,{mod}{reg}{16r_m}:lar {mod}{16r_m},{reg}
39411000101,{mod}{reg}{r_m}:lds {mod}{r_m},{reg}
39510001101,{mod}{reg}{r_m}:lea {mod}{r_m},{reg}
39611001001:leave
39711000100,{mod}{reg}{r_m}:les {mod}{r_m},{reg}
39800001111,10110100,{mod}{reg}{r_m}:lfs {mod}{r_m},{reg}
39900001111,00000001,{mod}010{r_m}:lgdt{w0} {mod}{r_m}
40000001111,10110101,{mod}{reg}{r_m}:lgs {mod}{r_m},{reg}
40100001111,00000001,{mod}011{r_m}:lidt{w0} {mod}{r_m}
40200001111,00000000,{mod}010{16r_m}:lldt {mod}{16r_m}
40300001111,00000001,{mod}110{16r_m}:lmsw {mod}{16r_m}
40411110000:lock
4051010110{w}:{R}lods {ds_si},{ax}{w}
40611100010,{disp8}:loop {disp8}
40711100001,{disp8}:loope {disp8}
40811100000,{disp8}:loopne {disp8}
40900001111,00000011,{mod}{reg}{16r_m}:lsl {mod}{16r_m},{reg}
41000001111,10110010,{mod}{reg}{r_m}:lss {mod}{r_m},{reg}
41100001111,00000000,{mod}011{16r_m}:ltr {mod}{16r_m}
4121000100{w},{mod}{reg}{r_m}:mov {reg}{w},{mod}{r_m}{w}
4131000101{w},{mod}{reg}{r_m}:mov {mod}{r_m}{w},{reg}{w}
4141100011{w},{mod}000{r_m},{imm}:mov{w} {imm}{w},{mod}{r_m}{w}
4151011{w}{reg},{imm}:mov {imm}{w},{reg}{w}
4161010000{w},{abs}:mov {abs},{ax}{w}
4171010001{w},{abs}:mov {ax}{w},{abs}
41800001111,00100000,11{ccc}{reg}:mov {ccc},{reg}
41900001111,00100010,11{ccc}{reg}:mov {reg},{ccc}
42000001111,00100001,11{ddd}{reg}:mov {ddd},{reg}
42100001111,00100011,11{ddd}{reg}:mov {reg},{ddd}
42210001100,{mod}{sreg3}{r_m}:mov {sreg3},{mod}{r_m}
42310001110,{mod}{sreg3}{r_m}:mov {mod}{r_m},{sreg3}
4241010010{w}:{R}movs{w} {ds_si},{es_di}
42500001111,1011111{w},{mod}{reg}{r_m}:movsx{w} {mod}{r_m},{reg}
42600001111,1011011{w},{mod}{reg}{r_m}:movzx{w} {mod}{r_m},{reg}
4271111011{w},{mod}100{r_m}:mul{w} {mod}{r_m}{w}
4281111011{w},{mod}011{r_m}:neg{w} {mod}{r_m}{w}
429ifdef(`ASSEMBLER',
430`10010000:nop
43111110011,10010000:pause
432',
433`10010000:{R}INVALID
434')dnl
4351111011{w},{mod}010{r_m}:not{w} {mod}{r_m}{w}
4360000100{w},{mod}{reg}{r_m}:or {reg}{w},{mod}{r_m}{w}
4370000101{w},{mod}{reg}{r_m}:or {mod}{r_m}{w},{reg}{w}
4381000000{w},{mod}001{r_m},{imm}:or{w} {imm}{w},{mod}{r_m}{w}
439100000{s}{w},{mod}001{r_m},{imm}:or{w} {imm}{s},{mod}{r_m}{w}
4400000110{w},{imm}:or {imm}{w},{ax}{w}
4411110011{w},{imm8}:out {ax}{w},{imm8}
4421110111{w}:out {ax}{w},{dx}
4430110111{w}:{R}outs{w} {ds_si},{dx}
44410001111,{mod}000{r_m}:pop{w} {mod}{r_m}
44501011{reg}:pop {reg}
44600001111,10{sreg3}001:pop {sreg3}
44701100001:popa{W}
44810011101:popf{W}
44911111111,{mod}110{r_m}:push{w} {mod}{r_m}
45001010{reg}:push {reg}
451011010{s}0,{imm}:push {imm}{s}
452000{sreg2}110:push {sreg2}
45300001111,10{sreg3}000:push {sreg3}
45401100000:pusha{W}
45510011100:pushf{W}
4561101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w}
4571101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w}
4581100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w}
4591101000{w},{mod}011{r_m}:rcr{w} {mod}{r_m}{w}
4601101001{w},{mod}011{r_m}:rcr{w} %cl,{mod}{r_m}{w}
4611100000{w},{mod}011{r_m},{imm8}:rcr{w} {imm8},{mod}{r_m}{w}
46200001111,00110010:rdmsr
46300001111,00110011:rdpmc
46400001111,00110001:rdtsc
46511000011:ret
46611000010,{imm16}:ret {imm16}
46711001011:lret
46811001010,{imm16}:lret {imm16}
4691101000{w},{mod}000{r_m}:rol{w} {mod}{r_m}{w}
4701101001{w},{mod}000{r_m}:rol{w} %cl,{mod}{r_m}{w}
4711100000{w},{mod}000{r_m},{imm8}:rol{w} {imm8},{mod}{r_m}{w}
4721101000{w},{mod}001{r_m}:ror{w} {mod}{r_m}{w}
4731101001{w},{mod}001{r_m}:ror{w} %cl,{mod}{r_m}{w}
4741100000{w},{mod}001{r_m},{imm8}:ror{w} {imm8},{mod}{r_m}{w}
47500001111,10101010:rsm
47610011110:sahf
4771101000{w},{mod}111{r_m}:sar{w} {mod}{r_m}{w}
4781101001{w},{mod}111{r_m}:sar{w} %cl,{mod}{r_m}{w}
4791100000{w},{mod}111{r_m},{imm8}:sar{w} {imm8},{mod}{r_m}{w}
4800001100{w},{mod}{reg}{r_m}:sbb {reg}{w},{mod}{r_m}{w}
4810001101{w},{mod}{reg}{r_m}:sbb {mod}{r_m}{w},{reg}{w}
4820001110{w},{imm}:sbb {imm}{w},{ax}{w}
4831000000{w},{mod}011{r_m},{imm}:sbb{w} {imm}{w},{mod}{r_m}{w}
4841000001{w},{mod}011{r_m},{imms}:sbb{w} {imms},{mod}{r_m}
4851010111{w}:{RE}scas {es_di},{ax}{w}
48600001111,1001{tttn},{mod}000{r_m}:set{tttn} {mod}{r_m}
4871101000{w},{mod}100{r_m}:shl{w} {mod}{r_m}{w}
4881101001{w},{mod}100{r_m}:shl{w} %cl,{mod}{r_m}{w}
4891100000{w},{mod}100{r_m},{imm8}:shl{w} {imm8},{mod}{r_m}{w}
4901101000{w},{mod}101{r_m}:shr{w} {mod}{r_m}{w}
49100001111,10100100,{mod}{reg}{r_m},{imm8}:shld {imm8},{reg},{mod}{r_m}
49200001111,10100101,{mod}{reg}{r_m}:shld %cl,{reg},{mod}{r_m}
4931101001{w},{mod}101{r_m}:shr{w} %cl,{mod}{r_m}{w}
4941100000{w},{mod}101{r_m},{imm8}:shr{w} {imm8},{mod}{r_m}{w}
49500001111,10101100,{mod}{reg}{r_m},{imm8}:shrd {imm8},{reg},{mod}{r_m}
49600001111,10101101,{mod}{reg}{r_m}:shrd %cl,{reg},{mod}{r_m}
497# ORDER
49800001111,00000001,11000001:vmcall
49900001111,00000001,11000010:vmlaunch
50000001111,00000001,11000011:vmresume
50100001111,00000001,11000100:vmxoff
50200001111,00000001,{mod}000{r_m}:sgdtl {mod}{r_m}
503# ORDER END
504# ORDER
50500001111,00000001,11001000:monitor %eax,%ecx,%edx
50600001111,00000001,11001001:mwait %eax,%ecx
50700001111,00000001,{mod}001{r_m}:sidtl {mod}{r_m}
508# ORDER END
50900001111,00000000,{mod}000{r_m}:sldt {mod}{r_m}
51000001111,00000001,{mod}100{r_m}:smsw {mod}{r_m}
51111111001:stc
51211111101:std
51311111011:sti
5141010101{w}:{R}stos {ax}{w},{es_di}
51500001111,00000000,{mod}001{r_m}:str {mod}{r_m}
5160010100{w},{mod}{reg}{r_m}:sub {reg}{w},{mod}{r_m}{w}
5170010101{w},{mod}{reg}{r_m}:sub {mod}{r_m}{w},{reg}{w}
5180010110{w},{imm}:sub {imm}{w},{ax}{w}
5191000000{w},{mod}101{r_m},{imm}:sub{w} {imm}{w},{mod}{r_m}{w}
5201000001{w},{mod}101{r_m},{imms}:sub{w} {imms},{mod}{r_m}
5211000010{w},{mod}{reg}{r_m}:test {reg}{w},{mod}{r_m}{w}
5221010100{w},{imm}:test {imm}{w},{ax}{w}
5231111011{w},{mod}000{r_m},{imm}:test{w} {imm}{w},{mod}{r_m}{w}
52400001111,00001011:ud2a
52500001111,00000000,{mod}100{16r_m}:verr {mod}{16r_m}
52600001111,00000000,{mod}101{16r_m}:verw {mod}{16r_m}
52700001111,00001001:wbinvd
52800001111,00001101,{mod}000{8r_m}:prefetch {mod}{8r_m}
52900001111,00001101,{mod}001{8r_m}:prefetchw {mod}{8r_m}
53000001111,00011000,{mod}000{r_m}:prefetchnta {mod}{r_m}
53100001111,00011000,{mod}001{r_m}:prefetcht0 {mod}{r_m}
53200001111,00011000,{mod}010{r_m}:prefetcht1 {mod}{r_m}
53300001111,00011000,{mod}011{r_m}:prefetcht2 {mod}{r_m}
53400001111,00011111,{mod}{reg}{r_m}:nop{w} {mod}{r_m}
535dnl without prefix: movups
536dnl with 0xf3: movss
537dnl with 0x66: movupd
538dnl with 0xf2: movsd
53900001111,00010000,{Mod}{xmmreg}{R_m}:{R}INVALID {Mod}{R_m},{xmmreg}
54000001111,00010001,{Mod}{xmmreg}{R_m}:{R}INVALID {xmmreg},{Mod}{R_m}
54100001111,00110000:wrmsr
54200001111,1100000{w},{mod}{reg}{r_m}:xadd{w} {reg},{mod}{r_m}
5431000011{w},{mod}{reg}{r_m}:xchg {reg}{w},{mod}{r_m}{w}
54410010{reg}:xchg {ax},{reg}
54511010111:xlat {ds_bx}
5460011000{w},{mod}{reg}{r_m}:xor {reg}{w},{mod}{r_m}{w}
5470011001{w},{mod}{reg}{r_m}:xor {mod}{r_m}{w},{reg}{w}
5480011010{w},{imm}:xor {imm}{w},{ax}{w}
5491000000{w},{mod}110{r_m},{imm}:xor{w} {imm}{w},{mod}{r_m}{w}
5501000001{w},{mod}110{r_m},{imms}:xor{w} {imms},{mod}{r_m}
55100001111,01110111:emms
55200001111,01101110,{mod}{mmxreg}{r_m}:movd {mod}{r_m},{mmxreg}
55300001111,01111110,{mod}{mmxreg}{r_m}:movd {mmxreg},{mod}{r_m}
55400001111,01101111,{MOD}{mmxreg}{R_M}:movq {MOD}{R_M},{mmxreg}
55500001111,01111111,{MOD}{mmxreg}{R_M}:movq {mmxreg},{MOD}{R_M}
55600001111,01101011,{MOD}{mmxreg}{R_M}:packssdw {MOD}{R_M},{mmxreg}
55700001111,01100011,{MOD}{mmxreg}{R_M}:packsswb {MOD}{R_M},{mmxreg}
55800001111,01100111,{MOD}{mmxreg}{R_M}:packuswb {MOD}{R_M},{mmxreg}
55900001111,111111{gg},{MOD}{mmxreg}{R_M}:padd{gg} {MOD}{R_M},{mmxreg}
56000001111,111111{0g},{MOD}{mmxreg}{R_M}:padds{0g} {MOD}{R_M},{mmxreg}
56100001111,110111{0g},{MOD}{mmxreg}{R_M}:paddus{0g} {MOD}{R_M},{mmxreg}
56200001111,11011011,{MOD}{mmxreg}{R_M}:pand {MOD}{R_M},{mmxreg}
56300001111,11011111,{MOD}{mmxreg}{R_M}:pandn {MOD}{R_M},{mmxreg}
56400001111,011101{gg},{MOD}{mmxreg}{R_M}:pcmpeq{gg} {MOD}{R_M},{mmxreg}
56500001111,011001{gg},{MOD}{mmxreg}{R_M}:pcmpgt{gg} {MOD}{R_M},{mmxreg}
56600001111,11110101,{MOD}{mmxreg}{R_M}:pmaddwd {MOD}{R_M},{mmxreg}
56700001111,11100101,{MOD}{mmxreg}{R_M}:pmulhw {MOD}{R_M},{mmxreg}
56800001111,11010101,{MOD}{mmxreg}{R_M}:pmullw {MOD}{R_M},{mmxreg}
56900001111,11101011,{MOD}{mmxreg}{R_M}:por {MOD}{R_M},{mmxreg}
57000001111,111100{GG},{MOD}{mmxreg}{R_M}:psll{GG} {MOD}{R_M},{mmxreg}
57100001111,011100{GG},11110{mmxreg},{imm8}:psll{GG} {imm8},{mmxreg}
57200001111,111000{gG},{MOD}{mmxreg}{R_M}:psra{gG} {MOD}{R_M},{mmxreg}
57300001111,011100{gG},11100{mmxreg},{imm8}:psra{gG} {imm8},{mmxreg}
57400001111,110100{GG},{MOD}{mmxreg}{R_M}:psrl{GG} {MOD}{R_M},{mmxreg}
57500001111,011100{GG},11010{mmxreg},{imm8}:psrl{GG} {imm8},{mmxreg}
57600001111,111110{gg},{MOD}{mmxreg}{R_M}:psub{gg} {MOD}{R_M},{mmxreg}
57700001111,111010{0g},{MOD}{mmxreg}{R_M}:psubs{0g} {MOD}{R_M},{mmxreg}
57800001111,110110{0g},{MOD}{mmxreg}{R_M}:psubus{0g} {MOD}{R_M},{mmxreg}
57900001111,011010{gg},{MOD}{mmxreg}{R_M}:punpckh{gg} {MOD}{R_M},{mmxreg}
58000001111,011000{gg},{MOD}{mmxreg}{R_M}:punpckl{gg} {MOD}{R_M},{mmxreg}
58100001111,11101111,{MOD}{mmxreg}{R_M}:pxor {MOD}{R_M},{mmxreg}
58200001111,01011000,{Mod}{xmmreg}{R_m}:addps {Mod}{R_m},{xmmreg}
58311110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg}
58400001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
58500001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
58600001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqps {Mod}{R_m},{xmmreg}
58700001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltps {Mod}{R_m},{xmmreg}
58800001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpleps {Mod}{R_m},{xmmreg}
58900001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordps {Mod}{R_m},{xmmreg}
59000001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqps {Mod}{R_m},{xmmreg}
59100001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltps {Mod}{R_m},{xmmreg}
59200001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnleps {Mod}{R_m},{xmmreg}
59300001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordps {Mod}{R_m},{xmmreg}
59411110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqss {Mod}{R_m},{xmmreg}
59511110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltss {Mod}{R_m},{xmmreg}
59611110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpless {Mod}{R_m},{xmmreg}
59711110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordss {Mod}{R_m},{xmmreg}
59811110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqss {Mod}{R_m},{xmmreg}
59911110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltss {Mod}{R_m},{xmmreg}
60011110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnless {Mod}{R_m},{xmmreg}
60111110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordss {Mod}{R_m},{xmmreg}
60200001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2ps {MOD}{R_M},{xmmreg}
60311110011,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2ss {mod}{r_m},{xmmreg}
60400001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg}
60511110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg}
60600001111,10101110,{mod}001{r_m}:fxrstor {mod}{r_m}
60700001111,10101110,{mod}000{r_m}:fxsave {mod}{r_m}
60800001111,10101110,{mod}010{r_m}:ldmxcsr {mod}{r_m}
60900001111,01011111,{Mod}{xmmreg}{R_m}:maxps {Mod}{R_m},{xmmreg}
61011110011,00001111,01011111,{Mod}{xmmreg}{R_m}:maxss {Mod}{R_m},{xmmreg}
61100001111,01011101,{Mod}{xmmreg}{R_m}:minps {Mod}{R_m},{xmmreg}
61211110011,00001111,01011101,{Mod}{xmmreg}{R_m}:minss {Mod}{R_m},{xmmreg}
61300001111,00101000,{Mod}{xmmreg}{R_m}:INVALID {Mod}{R_m},{xmmreg}
61400001111,00101001,{Mod}{xmmreg}{R_m}:INVALID {xmmreg},{Mod}{R_m}
61500001111,00010010,{Mod}{xmmreg}{R_m}:{R}INVALID {Mod}{R_m},{xmmreg}
61600001111,00010011,{Mod}{xmmreg}{R_m}:INVALID {xmmreg},{Mod}{R_m}
61700001111,00010100,{Mod}{xmmreg}{R_m}:INVALID {Mod}{R_m},{xmmreg}
61800001111,00010101,{Mod}{xmmreg}{R_m}:INVALID {Mod}{R_m},{xmmreg}
61900001111,00010110,{Mod}{xmmreg}{R_m}:{R}INVALID {Mod}{R_m},{xmmreg}
62000001111,00010111,{Mod}{xmmreg}{R_m}:INVALID {xmmreg},{Mod}{R_m}
62100001111,00101011,{mod}{xmmreg}{r_m}:INVALID {xmmreg},{mod}{r_m}
62200001111,00101100,{Mod}{mmxreg2}{R_m}:{R}INVALID {Mod}{R_m},{mmxreg2}
62300001111,00101101,{Mod}{mmxreg2}{R_m}:{R}INVALID {Mod}{R_m},{mmxreg2}
62400001111,00101110,{Mod}{xmmreg}{R_m}:INVALID {Mod}{R_m},{xmmreg}
62500001111,00101111,{Mod}{xmmreg}{R_m}:INVALID {Mod}{R_m},{xmmreg}
62600001111,00110111:getsec
62700001111,01010000,11{reg}{xmmreg}:INVALID {xmmreg},{reg}
62800001111,01010001,{Mod}{xmmreg}{R_m}:{R}INVALID {Mod}{R_m},{xmmreg}
62900001111,01010010,{Mod}{xmmreg}{R_m}:{R}INVALID {Mod}{R_m},{xmmreg}
63000001111,01010011,{Mod}{xmmreg}{R_m}:{R}INVALID {Mod}{R_m},{xmmreg}
631# ORDER:
632dnl Many previous entries depend on this being last.
633000{sreg2}111:pop {sreg2}
634# ORDER END: