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gerrit-public.fairphone.software / platform / external / ethtool / 26e7b97b2292e0ec27c326498ca3924008f0216b / . / e1000.c
blob: 77d799f7b7e20766450ac03837620a65924c29d5 [file] [log] [blame]
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]1/* Copyright (c) 2002 Intel Corporation */
2#include <stdio.h>
3#include "ethtool-util.h"
4
5/* Register Bit Masks */
6/* Device Control */
7#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
8#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
9#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
10#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
11#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
12#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
13#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
14#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
15#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
16#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
17#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
18#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
19#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
20#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
21#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
22#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
23#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
24#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
25#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
26#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
27#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
28#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
29#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
30#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
31#define E1000_CTRL_RST 0x04000000 /* Global reset */
32#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
33#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
34#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
35#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
36#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
37
38/* Device Status */
39#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
40#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
41#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
42#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
43#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
44#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
45#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
46#define E1000_STATUS_SPEED_MASK 0x000000C0
47#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
48#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
49#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
50#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
51#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
52#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
53#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
54#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
55#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
56
57/* Constants used to intrepret the masked PCI-X bus speed. */
58#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
59#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
60#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
61
62/* Receive Control */
63#define E1000_RCTL_RST 0x00000001 /* Software reset */
64#define E1000_RCTL_EN 0x00000002 /* enable */
65#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
66#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
67#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
68#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
69#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
70#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
71#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
72#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
73#define E1000_RCTL_RDMTS 0x00000300 /* rx desc min threshold size */
74#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
75#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
76#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
77#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
78#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
79#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
80#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
81#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
82#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
83#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
84#define E1000_RCTL_SZ 0x00030000 /* rx buffer size */
85/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
86#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
87#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
88#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
89#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
90/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
91#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
92#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
93#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
94#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
95#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
96#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
97#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
98#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
99#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
100
101/* Transmit Control */
102#define E1000_TCTL_RST 0x00000001 /* software reset */
103#define E1000_TCTL_EN 0x00000002 /* enable tx */
104#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
105#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
106#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
107#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
108#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
109#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
110#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
111#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
112
113/* PCI Device IDs */
114#define E1000_DEV_ID_82542 0x1000
115#define E1000_DEV_ID_82543GC_FIBER 0x1001
116#define E1000_DEV_ID_82543GC_COPPER 0x1004
117#define E1000_DEV_ID_82544EI_COPPER 0x1008
118#define E1000_DEV_ID_82544EI_FIBER 0x1009
119#define E1000_DEV_ID_82544GC_COPPER 0x100C
120#define E1000_DEV_ID_82544GC_LOM 0x100D
121#define E1000_DEV_ID_82540EM 0x100E
122#define E1000_DEV_ID_82540EM_LOM 0x1015
123#define E1000_DEV_ID_82540EP_LOM 0x1016
124#define E1000_DEV_ID_82540EP 0x1017
125#define E1000_DEV_ID_82540EP_LP 0x101E
126#define E1000_DEV_ID_82545EM_COPPER 0x100F
127#define E1000_DEV_ID_82545EM_FIBER 0x1011
128#define E1000_DEV_ID_82545GM_COPPER 0x1026
129#define E1000_DEV_ID_82545GM_FIBER 0x1027
130#define E1000_DEV_ID_82545GM_SERDES 0x1028
131#define E1000_DEV_ID_82546EB_COPPER 0x1010
132#define E1000_DEV_ID_82546EB_FIBER 0x1012
133#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
134#define E1000_DEV_ID_82541EI 0x1013
135#define E1000_DEV_ID_82541EI_MOBILE 0x1018
136#define E1000_DEV_ID_82541ER 0x1078
137#define E1000_DEV_ID_82547GI 0x1075
138#define E1000_DEV_ID_82541GI 0x1076
139#define E1000_DEV_ID_82541GI_MOBILE 0x1077
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]140#define E1000_DEV_ID_82541GI_LF 0x107C
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]141#define E1000_DEV_ID_82546GB_COPPER 0x1079
142#define E1000_DEV_ID_82546GB_FIBER 0x107A
143#define E1000_DEV_ID_82546GB_SERDES 0x107B
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]144#define E1000_DEV_ID_82546GB_PCIE 0x108A
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]145#define E1000_DEV_ID_82547EI 0x1019
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]146#define E1000_DEV_ID_82573E 0x108B
147#define E1000_DEV_ID_82573E_IAMT 0x108C
148
149#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]150
151#define E1000_82542_2_0_REV_ID 2
152#define E1000_82542_2_1_REV_ID 3
153
154/* Enumerated types specific to the e1000 hardware */
155/* Media Access Controlers */
156enum e1000_mac_type {
157 e1000_undefined = 0,
158 e1000_82542_rev2_0,
159 e1000_82542_rev2_1,
160 e1000_82543,
161 e1000_82544,
162 e1000_82540,
163 e1000_82545,
164 e1000_82545_rev_3,
165 e1000_82546,
166 e1000_82546_rev_3,
167 e1000_82541,
168 e1000_82541_rev_2,
169 e1000_82547,
170 e1000_82547_rev_2,
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]171 e1000_82573,
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]172 e1000_num_macs
173};
174
175static enum e1000_mac_type
176e1000_get_mac_type(u16 device_id, u8 revision_id)
177{
178 enum e1000_mac_type mac_type = e1000_undefined;
179
180 switch (device_id) {
181 case E1000_DEV_ID_82542:
182 switch (revision_id) {
183 case E1000_82542_2_0_REV_ID:
184 mac_type = e1000_82542_rev2_0;
185 break;
186 case E1000_82542_2_1_REV_ID:
187 mac_type = e1000_82542_rev2_1;
188 break;
189 default:
190 mac_type = e1000_82542_rev2_0;
191 }
192 break;
193 case E1000_DEV_ID_82543GC_FIBER:
194 case E1000_DEV_ID_82543GC_COPPER:
195 mac_type = e1000_82543;
196 break;
197 case E1000_DEV_ID_82544EI_COPPER:
198 case E1000_DEV_ID_82544EI_FIBER:
199 case E1000_DEV_ID_82544GC_COPPER:
200 case E1000_DEV_ID_82544GC_LOM:
201 mac_type = e1000_82544;
202 break;
203 case E1000_DEV_ID_82540EM:
204 case E1000_DEV_ID_82540EM_LOM:
205 case E1000_DEV_ID_82540EP:
206 case E1000_DEV_ID_82540EP_LOM:
207 case E1000_DEV_ID_82540EP_LP:
208 mac_type = e1000_82540;
209 break;
210 case E1000_DEV_ID_82545EM_COPPER:
211 case E1000_DEV_ID_82545EM_FIBER:
212 mac_type = e1000_82545;
213 break;
214 case E1000_DEV_ID_82545GM_COPPER:
215 case E1000_DEV_ID_82545GM_FIBER:
216 case E1000_DEV_ID_82545GM_SERDES:
217 mac_type = e1000_82545_rev_3;
218 break;
219 case E1000_DEV_ID_82546EB_COPPER:
220 case E1000_DEV_ID_82546EB_FIBER:
221 case E1000_DEV_ID_82546EB_QUAD_COPPER:
222 mac_type = e1000_82546;
223 break;
224 case E1000_DEV_ID_82546GB_COPPER:
225 case E1000_DEV_ID_82546GB_FIBER:
226 case E1000_DEV_ID_82546GB_SERDES:
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]227 case E1000_DEV_ID_82546GB_PCIE:
228 case E1000_DEV_ID_82546GB_QUAD_COPPER:
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]229 mac_type = e1000_82546_rev_3;
230 break;
231 case E1000_DEV_ID_82541EI:
232 case E1000_DEV_ID_82541EI_MOBILE:
233 mac_type = e1000_82541;
234 break;
235 case E1000_DEV_ID_82541ER:
236 case E1000_DEV_ID_82541GI:
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]237 case E1000_DEV_ID_82541GI_LF:
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]238 case E1000_DEV_ID_82541GI_MOBILE:
239 mac_type = e1000_82541_rev_2;
240 break;
241 case E1000_DEV_ID_82547EI:
242 mac_type = e1000_82547;
243 break;
244 case E1000_DEV_ID_82547GI:
245 mac_type = e1000_82547_rev_2;
246 break;
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]247 case E1000_DEV_ID_82573E:
248 case E1000_DEV_ID_82573E_IAMT:
249 mac_type = e1000_82573;
250 break;
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]251 default:
252 /* list of supported devices probably needs updating */
253 mac_type = e1000_82543;
254 break;
255 }
256
257 return mac_type;
258}
259
260int
261e1000_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
262{
263 u32 *regs_buff = (u32 *)regs->data;
264 u16 hw_device_id = (u16)regs->version;
265 u8 hw_revision_id = (u8)(regs->version >> 16);
266 u8 version = (u8)(regs->version >> 24);
267 enum e1000_mac_type mac_type;
268 u32 reg;
269
270 if(version != 1)
271 return -1;
272
273 mac_type = e1000_get_mac_type(hw_device_id, hw_revision_id);
274
275 if(mac_type == e1000_undefined)
276 return -1;
277
278 fprintf(stdout, "MAC Registers\n");
279 fprintf(stdout, "-------------\n");
280
281 /* Device control register */
282 reg = regs_buff[0];
283 fprintf(stdout,
284 "0x00000: CTRL (Device control register) 0x%08X\n"
285 " Duplex: %s\n"
286 " Endian mode (buffers): %s\n"
287 " Link reset: %s\n"
288 " Set link up: %s\n"
289 " Invert Loss-Of-Signal: %s\n"
290 " Receive flow control: %s\n"
291 " Transmit flow control: %s\n"
292 " VLAN mode: %s\n",
293 reg,
294 reg & E1000_CTRL_FD ? "full" : "half",
295 reg & E1000_CTRL_BEM ? "big" : "little",
296 reg & E1000_CTRL_LRST ? "reset" : "normal",
297 reg & E1000_CTRL_SLU ? "1" : "0",
298 reg & E1000_CTRL_ILOS ? "yes" : "no",
299 reg & E1000_CTRL_RFCE ? "enabled" : "disabled",
300 reg & E1000_CTRL_TFCE ? "enabled" : "disabled",
301 reg & E1000_CTRL_VME ? "enabled" : "disabled");
302 if(mac_type >= e1000_82543) {
303 fprintf(stdout,
304 " Auto speed detect: %s\n"
305 " Speed select: %s\n"
306 " Force speed: %s\n"
307 " Force duplex: %s\n",
308 reg & E1000_CTRL_ASDE ? "enabled" : "disabled",
309 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_10 ? "10Mb/s" :
310 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_100 ? "100Mb/s" :
311 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_1000 ? "1000Mb/s" :
312 "not used",
313 reg & E1000_CTRL_FRCSPD ? "yes" : "no",
314 reg & E1000_CTRL_FRCDPX ? "yes" : "no");
315 }
316
317 /* Device status register */
318 reg = regs_buff[1];
319 fprintf(stdout,
320 "0x00008: STATUS (Device status register) 0x%08X\n"
321 " Duplex: %s\n"
322 " Link up: %s\n",
323 reg,
324 reg & E1000_STATUS_FD ? "full" : "half",
325 reg & E1000_STATUS_LU ? "link config" : "no link config");
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]326 if(mac_type >= e1000_82573) {
327 fprintf(stdout,
328 " TBI mode: %s\n"
329 " Link speed: %s\n"
330 " Bus type: %s\n"
331 " Port number: %s\n",
332 reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled",
333 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ?
334 "10Mb/s" :
335 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ?
336 "100Mb/s" :
337 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ?
338 "1000Mb/s" : "not used",
339 "PCI Express",
340 (reg & E1000_STATUS_FUNC_MASK) == 0 ? "0" : "1");
341 }
342 else if(mac_type >= e1000_82543) {
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]343 fprintf(stdout,
344 " TBI mode: %s\n"
345 " Link speed: %s\n"
346 " Bus type: %s\n"
347 " Bus speed: %s\n"
348 " Bus width: %s\n",
349 reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled",
350 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ?
351 "10Mb/s" :
352 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ?
353 "100Mb/s" :
354 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ?
355 "1000Mb/s" : "not used",
356 (reg & E1000_STATUS_PCIX_MODE) ? "PCI-X" : "PCI",
357 (reg & E1000_STATUS_PCIX_MODE) ?
358 ((reg & E1000_STATUS_PCIX_SPEED_133) ? "133MHz" :
359 (reg & E1000_STATUS_PCIX_SPEED_100) ? "100MHz" :
360 "66MHz") :
361 ((reg & E1000_STATUS_PCI66) ? "66MHz" : "33MHz"),
362 (reg & E1000_STATUS_BUS64) ? "64-bit" : "32-bit");
363 }
364
365 /* Receive control register */
366 reg = regs_buff[2];
367 fprintf(stdout,
368 "0x00100: RCTL (Receive control register) 0x%08X\n"
369 " Receiver: %s\n"
370 " Store bad packets: %s\n"
371 " Unicast promiscuous: %s\n"
372 " Multicast promiscuous: %s\n"
373 " Long packet: %s\n"
374 " Descriptor minimum threshold size: %s\n"
375 " Broadcast accept mode: %s\n"
376 " VLAN filter: %s\n"
377 " Cononical form indicator: %s\n"
378 " Discard pause frames: %s\n"
379 " Pass MAC control frames: %s\n",
380 reg,
381 reg & E1000_RCTL_EN ? "enabled" : "disabled",
382 reg & E1000_RCTL_SBP ? "enabled" : "disabled",
383 reg & E1000_RCTL_UPE ? "enabled" : "disabled",
384 reg & E1000_RCTL_MPE ? "enabled" : "disabled",
385 reg & E1000_RCTL_LPE ? "enabled" : "disabled",
386 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_HALF ? "1/2" :
387 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_QUAT ? "1/4" :
388 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_EIGTH ? "1/8" :
389 "reserved",
390 reg & E1000_RCTL_BAM ? "accept" : "ignore",
391 reg & E1000_RCTL_VFE ? "enabled" : "disabled",
392 reg & E1000_RCTL_CFIEN ? "enabled" : "disabled",
393 reg & E1000_RCTL_DPF ? "ignored" : "filtered",
394 reg & E1000_RCTL_PMCF ? "pass" : "don't pass");
395 if(mac_type >= e1000_82543) {
396 fprintf(stdout,
397 " Receive buffer size: %s\n",
398 reg & E1000_RCTL_BSEX ?
399 ((reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_16384 ? "16384" :
400 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_8192 ? "8192" :
401 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_4096 ? "4096" :
402 "reserved") :
403 ((reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_2048 ? "2048" :
404 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_1024 ? "1024" :
405 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_512 ? "512" :
406 "256"));
407 } else {
408 fprintf(stdout,
409 " Receive buffer size: %s\n",
410 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_2048 ? "2048" :
411 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_1024 ? "1024" :
412 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_512 ? "512" :
413 "256");
414 }
415
416 /* Receive descriptor registers */
417 fprintf(stdout,
418 "0x02808: RDLEN (Receive desc length) 0x%08X\n",
419 regs_buff[3]);
420 fprintf(stdout,
421 "0x02810: RDH (Receive desc head) 0x%08X\n",
422 regs_buff[4]);
423 fprintf(stdout,
424 "0x02818: RDT (Receive desc tail) 0x%08X\n",
425 regs_buff[5]);
426 fprintf(stdout,
427 "0x02820: RDTR (Receive delay timer) 0x%08X\n",
428 regs_buff[6]);
429
430 /* Transmit control register */
431 reg = regs_buff[7];
432 fprintf(stdout,
433 "0x00400: TCTL (Transmit ctrl register) 0x%08X\n"
434 " Transmitter: %s\n"
435 " Pad short packets: %s\n"
436 " Software XOFF Transmission: %s\n",
437 reg,
438 reg & E1000_TCTL_EN ? "enabled" : "disabled",
439 reg & E1000_TCTL_PSP ? "enabled" : "disabled",
440 reg & E1000_TCTL_SWXOFF ? "enabled" : "disabled");
441 if(mac_type >= e1000_82543) {
442 fprintf(stdout,
443 " Re-transmit on late collision: %s\n",
444 reg & E1000_TCTL_RTLC ? "enabled" : "disabled");
445 }
446
447 /* Transmit descriptor registers */
448 fprintf(stdout,
449 "0x03808: TDLEN (Transmit desc length) 0x%08X\n",
450 regs_buff[8]);
451 fprintf(stdout,
452 "0x03810: TDH (Transmit desc head) 0x%08X\n",
453 regs_buff[9]);
454 fprintf(stdout,
455 "0x03818: TDT (Transmit desc tail) 0x%08X\n",
456 regs_buff[10]);
457 fprintf(stdout,
458 "0x03820: TIDV (Transmit delay timer) 0x%08X\n",
459 regs_buff[11]);
460
461 /* PHY type */
462 fprintf(stdout,
463 "PHY type: %s\n",
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame^]464 regs_buff[12] == 0 ? "M88" :
465 regs_buff[12] == 1 ? "IGP" :
466 regs_buff[12] == 2 ? "IGP2" : "unknown" );
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]467
468 return 0;
469}
470