Jeff Garzik | 5312dbe | 2006-08-24 02:53:26 -0400 | [diff] [blame] | 1 | /* |
Jeff Garzik | 32c8037 | 2005-10-25 01:56:48 -0400 | [diff] [blame] | 2 | * Copyright (C) 2004 Intracom S.A. |
| 3 | * Pantelis Antoniou <panto@intracom.gr> |
| 4 | */ |
| 5 | |
| 6 | #include <stdio.h> |
| 7 | #include <stdint.h> |
| 8 | #include <stddef.h> |
| 9 | |
Ben Hutchings | 5ba70c0 | 2011-11-01 16:48:31 +0000 | [diff] [blame] | 10 | #include "internal.h" |
Jeff Garzik | 32c8037 | 2005-10-25 01:56:48 -0400 | [diff] [blame] | 11 | |
| 12 | struct fec { |
| 13 | uint32_t addr_low; /* lower 32 bits of station address */ |
| 14 | uint32_t addr_high; /* upper 16 bits of station address||0 */ |
| 15 | uint32_t hash_table_high;/* upper 32-bits of hash table */ |
| 16 | uint32_t hash_table_low; /* lower 32-bits of hash table */ |
| 17 | uint32_t r_des_start; /* beginning of Rx descriptor ring */ |
| 18 | uint32_t x_des_start; /* beginning of Tx descriptor ring */ |
| 19 | uint32_t r_buff_size; /* Rx buffer size */ |
| 20 | uint32_t res2[9]; /* reserved */ |
| 21 | uint32_t ecntrl; /* ethernet control register */ |
| 22 | uint32_t ievent; /* interrupt event register */ |
| 23 | uint32_t imask; /* interrupt mask register */ |
| 24 | uint32_t ivec; /* interrupt level and vector status */ |
| 25 | uint32_t r_des_active; /* Rx ring updated flag */ |
| 26 | uint32_t x_des_active; /* Tx ring updated flag */ |
| 27 | uint32_t res3[10]; /* reserved */ |
| 28 | uint32_t mii_data; /* MII data register */ |
| 29 | uint32_t mii_speed; /* MII speed control register */ |
| 30 | uint32_t res4[17]; /* reserved */ |
| 31 | uint32_t r_bound; /* end of RAM (read-only) */ |
| 32 | uint32_t r_fstart; /* Rx FIFO start address */ |
| 33 | uint32_t res5[6]; /* reserved */ |
| 34 | uint32_t x_fstart; /* Tx FIFO start address */ |
| 35 | uint32_t res6[17]; /* reserved */ |
| 36 | uint32_t fun_code; /* fec SDMA function code */ |
| 37 | uint32_t res7[3]; /* reserved */ |
| 38 | uint32_t r_cntrl; /* Rx control register */ |
| 39 | uint32_t r_hash; /* Rx hash register */ |
| 40 | uint32_t res8[14]; /* reserved */ |
| 41 | uint32_t x_cntrl; /* Tx control register */ |
| 42 | uint32_t res9[0x1e]; /* reserved */ |
| 43 | }; |
| 44 | |
| 45 | #define DUMP_REG(f, x) fprintf(stdout, \ |
| 46 | "0x%04lx: %-16s 0x%08x\n", \ |
| 47 | (unsigned long)(offsetof(struct fec, x)), \ |
| 48 | #x, f->x) |
| 49 | |
Maciej Żenczykowski | 211c99e | 2019-10-17 11:21:06 -0700 | [diff] [blame] | 50 | int fec_8xx_dump_regs(struct ethtool_drvinfo *info maybe_unused, |
| 51 | struct ethtool_regs *regs) |
Jeff Garzik | 32c8037 | 2005-10-25 01:56:48 -0400 | [diff] [blame] | 52 | { |
| 53 | struct fec *f = (struct fec *)regs->data; |
| 54 | |
| 55 | fprintf(stdout, "Descriptor Registers\n"); |
| 56 | fprintf(stdout, "---------------------\n"); |
| 57 | |
| 58 | DUMP_REG(f, addr_low); |
| 59 | DUMP_REG(f, addr_high); |
| 60 | DUMP_REG(f, hash_table_high); |
| 61 | DUMP_REG(f, hash_table_low); |
| 62 | DUMP_REG(f, r_des_start); |
| 63 | DUMP_REG(f, x_des_start); |
| 64 | DUMP_REG(f, r_buff_size); |
| 65 | DUMP_REG(f, ecntrl); |
| 66 | DUMP_REG(f, ievent); |
| 67 | DUMP_REG(f, imask); |
| 68 | DUMP_REG(f, ivec); |
| 69 | DUMP_REG(f, r_des_active); |
| 70 | DUMP_REG(f, x_des_active); |
| 71 | DUMP_REG(f, mii_data); |
| 72 | DUMP_REG(f, mii_speed); |
| 73 | DUMP_REG(f, r_bound); |
| 74 | DUMP_REG(f, r_fstart); |
| 75 | DUMP_REG(f, x_fstart); |
| 76 | DUMP_REG(f, fun_code); |
| 77 | DUMP_REG(f, r_cntrl); |
| 78 | DUMP_REG(f, r_hash); |
| 79 | DUMP_REG(f, x_cntrl); |
| 80 | |
| 81 | return 0; |
| 82 | } |