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gerrit-public.fairphone.software / platform / external / ethtool / 861c56b1422927e74292bb6dab30690dfed53db5 / . / amd8111e.c
blob: 5a056b3f84ca9e56eef425616f34a49f65903da8 [file] [log] [blame]
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]1
2/* Copyright (C) 2003 Advanced Micro Devices Inc. */
3#include <stdio.h>
Ben Hutchings5ba70c02011-11-01 16:48:31 +0000[diff] [blame]4#include "internal.h"
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]5
6typedef enum {
7 /* VAL2 */
8 RDMD0 = (1 << 16),
9 /* VAL1 */
10 TDMD3 = (1 << 11),
11 TDMD2 = (1 << 10),
12 TDMD1 = (1 << 9),
13 TDMD0 = (1 << 8),
14 /* VAL0 */
15 UINTCMD = (1 << 6),
16 RX_FAST_SPND = (1 << 5),
17 TX_FAST_SPND = (1 << 4),
18 RX_SPND = (1 << 3),
19 TX_SPND = (1 << 2),
20 INTREN = (1 << 1),
21 RUN = (1 << 0),
22
23 CMD0_CLEAR = 0x000F0F7F, /* Command style register */
24
25}CMD0_BITS;
26typedef enum {
27
28 /* VAL3 */
29 CONDUIT_MODE = (1 << 29),
30 /* VAL2 */
31 RPA = (1 << 19),
32 DRCVPA = (1 << 18),
33 DRCVBC = (1 << 17),
34 PROM = (1 << 16),
35 /* VAL1 */
36 ASTRP_RCV = (1 << 13),
37 RCV_DROP0 = (1 << 12),
38 EMBA = (1 << 11),
39 DXMT2PD = (1 << 10),
40 LTINTEN = (1 << 9),
41 DXMTFCS = (1 << 8),
42 /* VAL0 */
43 APAD_XMT = (1 << 6),
44 DRTY = (1 << 5),
45 INLOOP = (1 << 4),
46 EXLOOP = (1 << 3),
47 REX_RTRY = (1 << 2),
48 REX_UFLO = (1 << 1),
49 REX_LCOL = (1 << 0),
50
51 CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */
52
53}CMD2_BITS;
54typedef enum {
55
56 /* VAL3 */
57 ASF_INIT_DONE_ALIAS = (1 << 29),
58 /* VAL2 */
59 JUMBO = (1 << 21),
60 VSIZE = (1 << 20),
61 VLONLY = (1 << 19),
62 VL_TAG_DEL = (1 << 18),
63 /* VAL1 */
64 EN_PMGR = (1 << 14),
65 INTLEVEL = (1 << 13),
66 FORCE_FULL_DUPLEX = (1 << 12),
67 FORCE_LINK_STATUS = (1 << 11),
68 APEP = (1 << 10),
69 MPPLBA = (1 << 9),
70 /* VAL0 */
71 RESET_PHY_PULSE = (1 << 2),
72 RESET_PHY = (1 << 1),
73 PHY_RST_POL = (1 << 0),
74
75}CMD3_BITS;
76typedef enum {
77
78 INTR = (1 << 31),
79 PCSINT = (1 << 28),
80 LCINT = (1 << 27),
81 APINT5 = (1 << 26),
82 APINT4 = (1 << 25),
83 APINT3 = (1 << 24),
84 TINT_SUM = (1 << 23),
85 APINT2 = (1 << 22),
86 APINT1 = (1 << 21),
87 APINT0 = (1 << 20),
88 MIIPDTINT = (1 << 19),
89 MCCINT = (1 << 17),
90 MREINT = (1 << 16),
91 RINT_SUM = (1 << 15),
92 SPNDINT = (1 << 14),
93 MPINT = (1 << 13),
94 SINT = (1 << 12),
95 TINT3 = (1 << 11),
96 TINT2 = (1 << 10),
97 TINT1 = (1 << 9),
98 TINT0 = (1 << 8),
99 UINT = (1 << 7),
100 STINT = (1 << 4),
101 RINT0 = (1 << 0),
102
103}INT0_BITS;
104typedef enum {
105
106 /* VAL3 */
107 LCINTEN = (1 << 27),
108 APINT5EN = (1 << 26),
109 APINT4EN = (1 << 25),
110 APINT3EN = (1 << 24),
111 /* VAL2 */
112 APINT2EN = (1 << 22),
113 APINT1EN = (1 << 21),
114 APINT0EN = (1 << 20),
115 MIIPDTINTEN = (1 << 19),
116 MCCIINTEN = (1 << 18),
117 MCCINTEN = (1 << 17),
118 MREINTEN = (1 << 16),
119 /* VAL1 */
120 SPNDINTEN = (1 << 14),
121 MPINTEN = (1 << 13),
122 TINTEN3 = (1 << 11),
123 SINTEN = (1 << 12),
124 TINTEN2 = (1 << 10),
125 TINTEN1 = (1 << 9),
126 TINTEN0 = (1 << 8),
127 /* VAL0 */
128 STINTEN = (1 << 4),
129 RINTEN0 = (1 << 0),
130
131 INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */
132
133}INTEN0_BITS;
134
135typedef enum {
136
137 PMAT_DET = (1 << 12),
138 MP_DET = (1 << 11),
139 LC_DET = (1 << 10),
140 SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7),
141 FULL_DPLX = (1 << 6),
142 LINK_STATS = (1 << 5),
143 AUTONEG_COMPLETE = (1 << 4),
144 MIIPD = (1 << 3),
145 RX_SUSPENDED = (1 << 2),
146 TX_SUSPENDED = (1 << 1),
147 RUNNING = (1 << 0),
148
149}STAT0_BITS;
150
151#define PHY_SPEED_10 0x2
152#define PHY_SPEED_100 0x3
153
154
Maciej Żenczykowskia56aba42019-10-17 11:21:16 -0700[diff] [blame]155int amd8111e_dump_regs(struct ethtool_drvinfo *info maybe_unused,
156 struct ethtool_regs *regs)
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]157{
158
159 u32 *reg_buff = (u32 *)regs->data;
160 u32 reg;
161
162 fprintf(stdout, "Descriptor Registers\n");
163 fprintf(stdout, "---------------------\n");
164
165 /* Transmit descriptor base address register */
166 reg = reg_buff[0];
167 fprintf(stdout,
168 "0x00100: Transmit descriptor base address register %08X\n",reg);
169
170 /* Transmit descriptor length register */
171 reg = reg_buff[1];
172 fprintf(stdout,
173 "0x00140: Transmit descriptor length register 0x%08X\n",reg);
174
175 /* Receive descriptor base address register */
176 reg = reg_buff[2];
177 fprintf(stdout,
178 "0x00120: Receive descriptor base address register %08X\n",reg);
179
180 /* Receive descriptor length register */
181 reg = reg_buff[3];
182 fprintf(stdout,
183 "0x00150: Receive descriptor length register 0x%08X\n",reg);
184
185 fprintf(stdout, "\n");
186
187
188 fprintf(stdout, "Command Registers\n");
189 fprintf(stdout, "-------------------\n");
190
191 /* Command 0 Register */
192 reg = reg_buff[4];
193 fprintf(stdout,
194 "0x00048: Command 0 register 0x%08X\n"
195 " Interrupts: %s\n"
196 " Device: %s\n",
197 reg,
198 reg & INTREN ? "Enabled" : "Disabled",
199 reg & RUN ? "Running" : "Stopped");
200
201 /* Command 2 Register */
202 reg = reg_buff[5];
203 fprintf(stdout,
204 "0x00050: Command 2 register 0x%08X\n"
205 " Promiscuous mode: %s\n"
206 " Retransmit on underflow: %s\n",
207 reg,
208 reg & PROM ? "Enabled" : "Disabled",
209 reg & REX_UFLO ? "Enabled" : "Disabled");
210 /* Command 3 Register */
211 reg = reg_buff[6];
212 fprintf(stdout,
213 "0x00054: Command 3 register 0x%08X\n"
214 " Jumbo frame: %s\n"
215 " Admit only VLAN frame: %s\n"
216 " Delete VLAN tag: %s\n",
217 reg,
218 reg & JUMBO ? "Enabled" : "Disabled",
219 reg & VLONLY ? "Yes" : "No",
220 reg & VL_TAG_DEL ? "Yes" : "No");
221
222 /* Command 7 Register */
223 reg = reg_buff[7];
224 fprintf(stdout,
225 "0x00064: Command 7 register 0x%08X\n",
226 reg);
227
228 fprintf(stdout, "\n");
229 fprintf(stdout, "Interrupt Registers\n");
230 fprintf(stdout, "-------------------\n");
231
232 /* Interrupt 0 Register */
233 reg = reg_buff[8];
234 fprintf(stdout,
235 "0x00038: Interrupt register 0x%08X\n"
236 " Any interrupt is set: %s\n"
237 " Link change interrupt: %s\n"
238 " Register 0 auto-poll interrupt: %s\n"
239 " Transmit interrupt: %s\n"
240 " Software timer interrupt: %s\n"
241 " Receive interrupt: %s\n",
242 reg,
243 reg & INTR ? "Yes" : "No",
244 reg & LCINT ? "Yes" : "No",
245 reg & APINT0 ? "Yes" : "No",
246 reg & TINT0 ? "Yes" : "No",
247 reg & STINT ? "Yes" : "No",
248 reg & RINT0 ? "Yes" : "No"
249 );
250 /* Interrupt 0 enable Register */
251 reg = reg_buff[9];
252 fprintf(stdout,
253 "0x00040: Interrupt enable register 0x%08X\n"
254 " Link change interrupt: %s\n"
255 " Register 0 auto-poll interrupt: %s\n"
256 " Transmit interrupt: %s\n"
257 " Software timer interrupt: %s\n"
258 " Receive interrupt: %s\n",
259 reg,
260 reg & LCINTEN ? "Enabled" : "Disabled",
261 reg & APINT0EN ? "Enabled" : "Disabled",
262 reg & TINTEN0 ? "Enabled" : "Disabled",
263 reg & STINTEN ? "Enabled" : "Disabled",
264 reg & RINTEN0 ? "Enabled" : "Disabled"
265 );
266
267 fprintf(stdout, "\n");
268 fprintf(stdout, "Logical Address Filter Register\n");
269 fprintf(stdout, "-------------------\n");
270
271 /* Logical Address Filter Register */
272 fprintf(stdout,
273 "0x00168: Logical address filter register 0x%08X%08X\n",
274 reg_buff[11],reg_buff[10]);
275
276 fprintf(stdout, "\n");
277 fprintf(stdout, "Link status Register\n");
278 fprintf(stdout, "-------------------\n");
279
280 /* Status 0 Register */
281 reg = reg_buff[12];
282 if(reg & LINK_STATS){
283 fprintf(stdout,
284 "0x00030: Link status register 0x%08X\n"
285 " Link status: %s\n"
286 " Auto negotiation complete %s\n"
287 " Duplex %s\n"
288 " Speed %s\n",
289 reg,
290 reg & LINK_STATS ? "Valid" : "Invalid",
291 reg & AUTONEG_COMPLETE ? "Yes" : "No",
292 reg & FULL_DPLX ? "Full" : "Half",
293 ((reg & SPEED_MASK) >> 7 == PHY_SPEED_10) ? "10Mbits/ Sec":
294 "100Mbits/Sec");
295
296 }
297 else{
298 fprintf(stdout,
299 "0x00030: Link status register 0x%08X\n"
300 " Link status: %s\n",
301 reg,
302 reg & LINK_STATS ? "Valid" : "Invalid");
303 }
304 return 0;
305
306}