Vivien Didelot | cb8e980 | 2018-12-18 14:06:35 -0500 | [diff] [blame] | 1 | #include <stdio.h> |
| 2 | #include <string.h> |
| 3 | |
| 4 | #include "internal.h" |
| 5 | |
Vivien Didelot | ff99e46 | 2018-12-18 14:06:36 -0500 | [diff] [blame] | 6 | /* Macros and dump functions for the 16-bit mv88e6xxx per-port registers */ |
| 7 | |
| 8 | #define REG(_reg, _name, _val) \ |
| 9 | printf("%.02u: %-38.38s 0x%.4x\n", _reg, _name, _val) |
| 10 | |
| 11 | #define FIELD(_name, _fmt, ...) \ |
| 12 | printf(" %-36.36s " _fmt "\n", _name, ##__VA_ARGS__) |
| 13 | |
| 14 | #define FIELD_BITMAP(_name, _val) \ |
| 15 | FIELD(_name, "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", \ |
| 16 | ((_val) & 0x0001) ? "0 " : "", \ |
| 17 | ((_val) & 0x0002) ? "1 " : "", \ |
| 18 | ((_val) & 0x0004) ? "2 " : "", \ |
| 19 | ((_val) & 0x0008) ? "3 " : "", \ |
| 20 | ((_val) & 0x0010) ? "4 " : "", \ |
| 21 | ((_val) & 0x0020) ? "5 " : "", \ |
| 22 | ((_val) & 0x0040) ? "6 " : "", \ |
| 23 | ((_val) & 0x0080) ? "7 " : "", \ |
| 24 | ((_val) & 0x0100) ? "8 " : "", \ |
| 25 | ((_val) & 0x0200) ? "9 " : "", \ |
| 26 | ((_val) & 0x0400) ? "10 " : "", \ |
| 27 | ((_val) & 0x0800) ? "11 " : "", \ |
| 28 | ((_val) & 0x1000) ? "12 " : "", \ |
| 29 | ((_val) & 0x2000) ? "13 " : "", \ |
| 30 | ((_val) & 0x4000) ? "14 " : "", \ |
| 31 | ((_val) & 0x8000) ? "15 " : "") |
| 32 | |
Vivien Didelot | a13a053 | 2018-12-18 14:06:38 -0500 | [diff] [blame] | 33 | static void dsa_mv88e6161(int reg, u16 val) |
| 34 | { |
| 35 | switch (reg) { |
| 36 | case 0: |
| 37 | REG(reg, "Port Status", val); |
| 38 | FIELD("Pause Enabled", "%u", !!(val & 0x8000)); |
| 39 | FIELD("My Pause", "%u", !!(val & 0x4000)); |
| 40 | FIELD("Half-duplex Flow Control", "%u", !!(val & 0x2000)); |
| 41 | FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000)); |
| 42 | FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down"); |
| 43 | FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half"); |
| 44 | FIELD("Speed", "%s", |
| 45 | (val & 0x0300) == 0x0000 ? "10 Mbps" : |
| 46 | (val & 0x0300) == 0x0100 ? "100 Mbps" : |
| 47 | (val & 0x0300) == 0x0200 ? "1000 Mbps" : |
| 48 | (val & 0x0300) == 0x0300 ? "Reserved" : "?"); |
| 49 | FIELD("Auto-Media Detect Disable", "%u", !!(val & 0x0040)); |
| 50 | FIELD("Transmitter Paused", "%u", !!(val & 0x0020)); |
| 51 | FIELD("Flow Control", "%u", !!(val & 0x0010)); |
| 52 | FIELD("Config Duplex", "%s", val & 0x0008 ? "Full" : "Half"); |
| 53 | FIELD("Config Mode", "0x%x", val & 0x0007); |
| 54 | break; |
| 55 | case 1: |
| 56 | REG(reg, "PCS Control", val); |
| 57 | FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080)); |
| 58 | FIELD("Force Flow Control", "%u", !!(val & 0x0040)); |
| 59 | FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down"); |
| 60 | FIELD("Force Link", "%u", !!(val & 0x0010)); |
| 61 | FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half"); |
| 62 | FIELD("Force Duplex", "%u", !!(val & 0x0004)); |
| 63 | FIELD("Force Speed", "%s", |
| 64 | (val & 0x0003) == 0x0000 ? "10 Mbps" : |
| 65 | (val & 0x0003) == 0x0001 ? "100 Mbps" : |
| 66 | (val & 0x0003) == 0x0002 ? "1000 Mbps" : |
| 67 | (val & 0x0003) == 0x0003 ? "Not forced" : "?"); |
| 68 | break; |
| 69 | case 2: |
| 70 | REG(reg, "Jamming Control", val); |
| 71 | break; |
| 72 | case 3: |
| 73 | REG(reg, "Switch Identifier", val); |
| 74 | break; |
| 75 | case 4: |
| 76 | REG(reg, "Port Control", val); |
| 77 | FIELD("Source Address Filtering controls", "%s", |
| 78 | (val & 0xc000) == 0x0000 ? "Disabled" : |
| 79 | (val & 0xc000) == 0x4000 ? "Drop On Lock" : |
| 80 | (val & 0xc000) == 0x8000 ? "Drop On Unlock" : |
| 81 | (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?"); |
| 82 | FIELD("Egress Mode", "%s", |
| 83 | (val & 0x3000) == 0x0000 ? "Unmodified" : |
| 84 | (val & 0x3000) == 0x1000 ? "Untagged" : |
| 85 | (val & 0x3000) == 0x2000 ? "Tagged" : |
| 86 | (val & 0x3000) == 0x3000 ? "Reserved" : "?"); |
| 87 | FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800)); |
| 88 | FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400)); |
| 89 | FIELD("Frame Mode", "%s", |
| 90 | (val & 0x0300) == 0x0000 ? "Normal" : |
| 91 | (val & 0x0300) == 0x0100 ? "DSA" : |
| 92 | (val & 0x0300) == 0x0200 ? "Provider" : |
| 93 | (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?"); |
| 94 | FIELD("VLAN Tunnel", "%u", !!(val & 0x0080)); |
| 95 | FIELD("TagIfBoth", "%u", !!(val & 0x0040)); |
| 96 | FIELD("Initial Priority assignment", "%s", |
| 97 | (val & 0x0030) == 0x0000 ? "Defaults" : |
| 98 | (val & 0x0030) == 0x0010 ? "Tag Priority" : |
| 99 | (val & 0x0030) == 0x0020 ? "IP Priority" : |
| 100 | (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?"); |
| 101 | FIELD("Egress Flooding mode", "%s", |
| 102 | (val & 0x000c) == 0x0000 ? "No unknown DA" : |
| 103 | (val & 0x000c) == 0x0004 ? "No unknown multicast DA" : |
| 104 | (val & 0x000c) == 0x0008 ? "No unknown unicast DA" : |
| 105 | (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?"); |
| 106 | FIELD("Port State", "%s", |
| 107 | (val & 0x0003) == 0x0000 ? "Disabled" : |
| 108 | (val & 0x0003) == 0x0001 ? "Blocking/Listening" : |
| 109 | (val & 0x0003) == 0x0002 ? "Learning" : |
| 110 | (val & 0x0003) == 0x0003 ? "Forwarding" : "?"); |
| 111 | break; |
| 112 | case 5: |
| 113 | REG(reg, "Port Control 1", val); |
| 114 | FIELD("Message Port", "%u", !!(val & 0x8000)); |
| 115 | FIELD("Trunk Port", "%u", !!(val & 0x4000)); |
| 116 | FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8); |
| 117 | FIELD("FID[5:4]", "0x%.2x", (val & 0x0003) << 4); |
| 118 | break; |
| 119 | case 6: |
| 120 | REG(reg, "Port Base VLAN Map (Header)", val); |
| 121 | FIELD("FID[3:0]", "0x%.2x", (val & 0xf000) >> 12); |
| 122 | FIELD_BITMAP("VLANTable", val & 0x003f); |
| 123 | break; |
| 124 | case 7: |
| 125 | REG(reg, "Default VLAN ID & Priority", val); |
| 126 | FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13); |
| 127 | FIELD("Force to use Default VID", "%u", !!(val & 0x1000)); |
| 128 | FIELD("Default VLAN Identifier", "%u", val & 0x0fff); |
| 129 | break; |
| 130 | case 8: |
| 131 | REG(reg, "Port Control 2", val); |
| 132 | FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000)); |
| 133 | FIELD("Jumbo Mode", "%s", |
| 134 | (val & 0x3000) == 0x0000 ? "1522" : |
| 135 | (val & 0x3000) == 0x1000 ? "2048" : |
| 136 | (val & 0x3000) == 0x2000 ? "10240" : |
| 137 | (val & 0x3000) == 0x3000 ? "Reserved" : "?"); |
| 138 | FIELD("802.1QMode", "%s", |
| 139 | (val & 0x0c00) == 0x0000 ? "Disabled" : |
| 140 | (val & 0x0c00) == 0x0400 ? "Fallback" : |
| 141 | (val & 0x0c00) == 0x0800 ? "Check" : |
| 142 | (val & 0x0c00) == 0x0c00 ? "Secure" : "?"); |
| 143 | FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200)); |
| 144 | FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100)); |
| 145 | FIELD("Map using DA hits", "%u", !!(val & 0x0080)); |
| 146 | FIELD("ARP Mirror enable", "%u", !!(val & 0x0040)); |
| 147 | FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020)); |
| 148 | FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010)); |
| 149 | break; |
| 150 | case 9: |
| 151 | REG(reg, "Egress Rate Control", val); |
| 152 | break; |
| 153 | case 10: |
| 154 | REG(reg, "Egress Rate Control 2", val); |
| 155 | break; |
| 156 | case 11: |
| 157 | REG(reg, "Port Association Vector", val); |
| 158 | break; |
| 159 | case 12: |
| 160 | REG(reg, "Port ATU Control", val); |
| 161 | break; |
| 162 | case 13: |
| 163 | REG(reg, "Priority Override", val); |
| 164 | break; |
| 165 | case 15: |
| 166 | REG(reg, "PortEType", val); |
| 167 | break; |
| 168 | case 16: |
| 169 | REG(reg, "InDiscardsLo Frame Counter", val); |
| 170 | break; |
| 171 | case 17: |
| 172 | REG(reg, "InDiscardsHi Frame Counter", val); |
| 173 | break; |
| 174 | case 18: |
| 175 | REG(reg, "InFiltered Frame Counter", val); |
| 176 | break; |
| 177 | case 19: |
| 178 | REG(reg, "OutFiltered Frame Counter", val); |
| 179 | break; |
| 180 | case 24: |
| 181 | REG(reg, "Tag Remap 0-3", val); |
| 182 | break; |
| 183 | case 25: |
| 184 | REG(reg, "Tag Remap 4-7", val); |
| 185 | break; |
| 186 | case 27: |
| 187 | REG(reg, "Queue Counters", val); |
| 188 | break; |
| 189 | default: |
| 190 | REG(reg, "Reserved", val); |
| 191 | break; |
| 192 | } |
| 193 | } |
| 194 | |
Vivien Didelot | 4e98029 | 2018-12-18 14:06:37 -0500 | [diff] [blame] | 195 | static void dsa_mv88e6185(int reg, u16 val) |
| 196 | { |
| 197 | switch (reg) { |
| 198 | case 0: |
| 199 | REG(reg, "Port Status", val); |
| 200 | break; |
| 201 | case 1: |
| 202 | REG(reg, "PCS Control", val); |
| 203 | break; |
| 204 | case 3: |
| 205 | REG(reg, "Switch Identifier", val); |
| 206 | break; |
| 207 | case 4: |
| 208 | REG(reg, "Port Control", val); |
| 209 | break; |
| 210 | case 5: |
| 211 | REG(reg, "Port Control 1", val); |
| 212 | break; |
| 213 | case 6: |
| 214 | REG(reg, "Port Base VLAN Map (Header)", val); |
| 215 | break; |
| 216 | case 7: |
| 217 | REG(reg, "Default VLAN ID & Priority", val); |
| 218 | break; |
| 219 | case 8: |
| 220 | REG(reg, "Port Control 2", val); |
| 221 | break; |
| 222 | case 9: |
| 223 | REG(reg, "Rate Control", val); |
| 224 | break; |
| 225 | case 10: |
| 226 | REG(reg, "Rate Control 2", val); |
| 227 | break; |
| 228 | case 11: |
| 229 | REG(reg, "Port Association Vector", val); |
| 230 | break; |
| 231 | case 16: |
| 232 | REG(reg, "InDiscardsLo Frame Counter", val); |
| 233 | break; |
| 234 | case 17: |
| 235 | REG(reg, "InDiscardsHi Frame Counter", val); |
| 236 | break; |
| 237 | case 18: |
| 238 | REG(reg, "InFiltered Frame Counter", val); |
| 239 | break; |
| 240 | case 19: |
| 241 | REG(reg, "OutFiltered Frame Counter", val); |
| 242 | break; |
| 243 | case 24: |
| 244 | REG(reg, "Tag Remap 0-3", val); |
| 245 | break; |
| 246 | case 25: |
| 247 | REG(reg, "Tag Remap 4-7", val); |
| 248 | break; |
| 249 | default: |
| 250 | REG(reg, "Reserved", val); |
| 251 | break; |
| 252 | } |
| 253 | }; |
| 254 | |
Vivien Didelot | 7f1cc44 | 2018-12-18 14:06:39 -0500 | [diff] [blame] | 255 | static void dsa_mv88e6352(int reg, u16 val) |
| 256 | { |
| 257 | switch (reg) { |
| 258 | case 0: |
| 259 | REG(reg, "Port Status", val); |
| 260 | FIELD("Pause Enabled", "%u", !!(val & 0x8000)); |
| 261 | FIELD("My Pause", "%u", !!(val & 0x4000)); |
| 262 | FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000)); |
| 263 | FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down"); |
| 264 | FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half"); |
| 265 | FIELD("Speed", "%s", |
| 266 | (val & 0x0300) == 0x0000 ? "10 Mbps" : |
| 267 | (val & 0x0300) == 0x0100 ? "100 or 200 Mbps" : |
| 268 | (val & 0x0300) == 0x0200 ? "1000 Mbps" : |
| 269 | (val & 0x0300) == 0x0300 ? "Reserved" : "?"); |
| 270 | FIELD("EEE Enabled", "%u", !!(val & 0x0040)); |
| 271 | FIELD("Transmitter Paused", "%u", !!(val & 0x0020)); |
| 272 | FIELD("Flow Control", "%u", !!(val & 0x0010)); |
| 273 | FIELD("Config Mode", "0x%x", val & 0x000f); |
| 274 | break; |
| 275 | case 1: |
| 276 | REG(reg, "Physical Control", val); |
| 277 | FIELD("RGMII Receive Timing Control", "%s", val & 0x8000 ? "Delay" : "Default"); |
| 278 | FIELD("RGMII Transmit Timing Control", "%s", val & 0x4000 ? "Delay" : "Default"); |
| 279 | FIELD("200 BASE Mode", "%s", val & 0x1000 ? "200" : "100"); |
| 280 | FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080)); |
| 281 | FIELD("Force Flow Control", "%u", !!(val & 0x0040)); |
| 282 | FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down"); |
| 283 | FIELD("Force Link", "%u", !!(val & 0x0010)); |
| 284 | FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half"); |
| 285 | FIELD("Force Duplex", "%u", !!(val & 0x0004)); |
| 286 | FIELD("Force Speed", "%s", |
| 287 | (val & 0x0003) == 0x0000 ? "10 Mbps" : |
| 288 | (val & 0x0003) == 0x0001 ? "100 or 200 Mbps" : |
| 289 | (val & 0x0003) == 0x0002 ? "1000 Mbps" : |
| 290 | (val & 0x0003) == 0x0003 ? "Not forced" : "?"); |
| 291 | break; |
| 292 | case 2: |
| 293 | REG(reg, "Jamming Control", val); |
| 294 | break; |
| 295 | case 3: |
| 296 | REG(reg, "Switch Identifier", val); |
| 297 | break; |
| 298 | case 4: |
| 299 | REG(reg, "Port Control", val); |
| 300 | FIELD("Source Address Filtering controls", "%s", |
| 301 | (val & 0xc000) == 0x0000 ? "Disabled" : |
| 302 | (val & 0xc000) == 0x4000 ? "Drop On Lock" : |
| 303 | (val & 0xc000) == 0x8000 ? "Drop On Unlock" : |
| 304 | (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?"); |
| 305 | FIELD("Egress Mode", "%s", |
| 306 | (val & 0x3000) == 0x0000 ? "Unmodified" : |
| 307 | (val & 0x3000) == 0x1000 ? "Untagged" : |
| 308 | (val & 0x3000) == 0x2000 ? "Tagged" : |
| 309 | (val & 0x3000) == 0x3000 ? "Reserved" : "?"); |
| 310 | FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800)); |
| 311 | FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400)); |
| 312 | FIELD("Frame Mode", "%s", |
| 313 | (val & 0x0300) == 0x0000 ? "Normal" : |
| 314 | (val & 0x0300) == 0x0100 ? "DSA" : |
| 315 | (val & 0x0300) == 0x0200 ? "Provider" : |
| 316 | (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?"); |
| 317 | FIELD("VLAN Tunnel", "%u", !!(val & 0x0080)); |
| 318 | FIELD("TagIfBoth", "%u", !!(val & 0x0040)); |
| 319 | FIELD("Initial Priority assignment", "%s", |
| 320 | (val & 0x0030) == 0x0000 ? "Defaults" : |
| 321 | (val & 0x0030) == 0x0010 ? "Tag Priority" : |
| 322 | (val & 0x0030) == 0x0020 ? "IP Priority" : |
| 323 | (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?"); |
| 324 | FIELD("Egress Flooding mode", "%s", |
| 325 | (val & 0x000c) == 0x0000 ? "No unknown DA" : |
| 326 | (val & 0x000c) == 0x0004 ? "No unknown multicast DA" : |
| 327 | (val & 0x000c) == 0x0008 ? "No unknown unicast DA" : |
| 328 | (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?"); |
| 329 | FIELD("Port State", "%s", |
| 330 | (val & 0x0003) == 0x0000 ? "Disabled" : |
| 331 | (val & 0x0003) == 0x0001 ? "Blocking/Listening" : |
| 332 | (val & 0x0003) == 0x0002 ? "Learning" : |
| 333 | (val & 0x0003) == 0x0003 ? "Forwarding" : "?"); |
| 334 | break; |
| 335 | case 5: |
| 336 | REG(reg, "Port Control 1", val); |
| 337 | FIELD("Message Port", "%u", !!(val & 0x8000)); |
| 338 | FIELD("Trunk Port", "%u", !!(val & 0x4000)); |
| 339 | FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8); |
| 340 | FIELD("FID[11:4]", "0x%.3x", (val & 0x00ff) << 4); |
| 341 | break; |
| 342 | case 6: |
| 343 | REG(reg, "Port Base VLAN Map (Header)", val); |
| 344 | FIELD("FID[3:0]", "0x%.3x", (val & 0xf000) >> 12); |
| 345 | FIELD_BITMAP("VLANTable", val & 0x007f); |
| 346 | break; |
| 347 | case 7: |
| 348 | REG(reg, "Default VLAN ID & Priority", val); |
| 349 | FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13); |
| 350 | FIELD("Force to use Default VID", "%u", !!(val & 0x1000)); |
| 351 | FIELD("Default VLAN Identifier", "%u", val & 0x0fff); |
| 352 | break; |
| 353 | case 8: |
| 354 | REG(reg, "Port Control 2", val); |
| 355 | FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000)); |
| 356 | FIELD("Jumbo Mode", "%s", |
| 357 | (val & 0x3000) == 0x0000 ? "1522" : |
| 358 | (val & 0x3000) == 0x1000 ? "2048" : |
| 359 | (val & 0x3000) == 0x2000 ? "10240" : |
| 360 | (val & 0x3000) == 0x3000 ? "Reserved" : "?"); |
| 361 | FIELD("802.1QMode", "%s", |
| 362 | (val & 0x0c00) == 0x0000 ? "Disabled" : |
| 363 | (val & 0x0c00) == 0x0400 ? "Fallback" : |
| 364 | (val & 0x0c00) == 0x0800 ? "Check" : |
| 365 | (val & 0x0c00) == 0x0c00 ? "Secure" : "?"); |
| 366 | FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200)); |
| 367 | FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100)); |
| 368 | FIELD("Map using DA hits", "%u", !!(val & 0x0080)); |
| 369 | FIELD("ARP Mirror enable", "%u", !!(val & 0x0040)); |
| 370 | FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020)); |
| 371 | FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010)); |
| 372 | FIELD("Use Default Queue Priority", "%u", !!(val & 0x0008)); |
| 373 | FIELD("Default Queue Priority", "0x%x", (val & 0x0006) >> 1); |
| 374 | break; |
| 375 | case 9: |
| 376 | REG(reg, "Egress Rate Control", val); |
| 377 | break; |
| 378 | case 10: |
| 379 | REG(reg, "Egress Rate Control 2", val); |
| 380 | break; |
| 381 | case 11: |
| 382 | REG(reg, "Port Association Vector", val); |
| 383 | break; |
| 384 | case 12: |
| 385 | REG(reg, "Port ATU Control", val); |
| 386 | break; |
| 387 | case 13: |
| 388 | REG(reg, "Override", val); |
| 389 | break; |
| 390 | case 14: |
| 391 | REG(reg, "Policy Control", val); |
| 392 | break; |
| 393 | case 15: |
| 394 | REG(reg, "Port Ether Type", val); |
| 395 | break; |
| 396 | case 16: |
| 397 | REG(reg, "InDiscardsLo Frame Counter", val); |
| 398 | break; |
| 399 | case 17: |
| 400 | REG(reg, "InDiscardsHi Frame Counter", val); |
| 401 | break; |
| 402 | case 18: |
| 403 | REG(reg, "InFiltered/TcamCtr Frame Counter", val); |
| 404 | break; |
| 405 | case 19: |
| 406 | REG(reg, "Rx Frame Counter", val); |
| 407 | break; |
| 408 | case 22: |
| 409 | REG(reg, "LED Control", val); |
| 410 | break; |
| 411 | case 24: |
| 412 | REG(reg, "Tag Remap 0-3", val); |
| 413 | break; |
| 414 | case 25: |
| 415 | REG(reg, "Tag Remap 4-7", val); |
| 416 | break; |
| 417 | case 27: |
| 418 | REG(reg, "Queue Counters", val); |
| 419 | break; |
| 420 | default: |
| 421 | REG(reg, "Reserved", val); |
| 422 | break; |
| 423 | } |
| 424 | }; |
| 425 | |
Vivien Didelot | 034a17b | 2018-12-18 14:06:40 -0500 | [diff] [blame] | 426 | static void dsa_mv88e6390(int reg, u16 val) |
| 427 | { |
| 428 | switch (reg) { |
| 429 | case 0: |
| 430 | REG(reg, "Port Status", val); |
| 431 | FIELD("Transmit Pause Enable bit", "%u", !!(val & 0x8000)); |
| 432 | FIELD("Receive Pause Enable bit", "%u", !!(val & 0x4000)); |
| 433 | FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000)); |
| 434 | FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down"); |
| 435 | FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half"); |
| 436 | FIELD("Speed", "%s", |
| 437 | (val & 0x0300) == 0x0000 ? "10 Mbps" : |
| 438 | (val & 0x0300) == 0x0100 ? "100 or 200 Mbps" : |
| 439 | (val & 0x0300) == 0x0200 ? "1000 Mbps" : |
| 440 | (val & 0x0300) == 0x0300 ? "10 Gb or 2500 Mbps" : "?"); |
| 441 | FIELD("Duplex Fixed", "%u", !!(val & 0x0080)); |
| 442 | FIELD("EEE Enabled", "%u", !!(val & 0x0040)); |
| 443 | FIELD("Transmitter Paused", "%u", !!(val & 0x0020)); |
| 444 | FIELD("Flow Control", "%u", !!(val & 0x0010)); |
| 445 | FIELD("Config Mode", "0x%x", val & 0x000f); |
| 446 | break; |
| 447 | case 1: |
| 448 | REG(reg, "Physical Control", val); |
| 449 | FIELD("RGMII Receive Timing Control", "%s", val & 0x8000 ? "Delay" : "Default"); |
| 450 | FIELD("RGMII Transmit Timing Control", "%s", val & 0x4000 ? "Delay" : "Default"); |
| 451 | FIELD("Force Speed", "%u", !!(val & 0x2000)); |
| 452 | FIELD("Alternate Speed Mode", "%s", val & 0x1000 ? "Alternate" : "Normal"); |
| 453 | FIELD("MII PHY Mode", "%s", val & 0x0800 ? "PHY" : "MAC"); |
| 454 | FIELD("EEE force value", "%u", !!(val & 0x0200)); |
| 455 | FIELD("Force EEE", "%u", !!(val & 0x0100)); |
| 456 | FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down"); |
| 457 | FIELD("Force Link", "%u", !!(val & 0x0010)); |
| 458 | FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half"); |
| 459 | FIELD("Force Duplex", "%u", !!(val & 0x0004)); |
| 460 | FIELD("Force Speed", "%s", |
| 461 | (val & 0x0003) == 0x0000 ? "10 Mbps" : |
| 462 | (val & 0x0003) == 0x0001 ? "100 or 200 Mbps" : |
| 463 | (val & 0x0003) == 0x0002 ? "1000 Mbps" : |
| 464 | (val & 0x0003) == 0x0003 ? "10 Gb or 2500 Mbps" : "?"); |
| 465 | break; |
| 466 | case 2: |
| 467 | REG(reg, "Flow Control", val); |
| 468 | break; |
| 469 | case 3: |
| 470 | REG(reg, "Switch Identifier", val); |
| 471 | break; |
| 472 | case 4: |
| 473 | REG(reg, "Port Control", val); |
| 474 | FIELD("Source Address Filtering controls", "%s", |
| 475 | (val & 0xc000) == 0x0000 ? "Disabled" : |
| 476 | (val & 0xc000) == 0x4000 ? "Drop On Lock" : |
| 477 | (val & 0xc000) == 0x8000 ? "Drop On Unlock" : |
| 478 | (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?"); |
| 479 | FIELD("Egress Mode", "%s", |
| 480 | (val & 0x3000) == 0x0000 ? "Unmodified" : |
| 481 | (val & 0x3000) == 0x1000 ? "Untagged" : |
| 482 | (val & 0x3000) == 0x2000 ? "Tagged" : |
| 483 | (val & 0x3000) == 0x3000 ? "Reserved" : "?"); |
| 484 | FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800)); |
| 485 | FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400)); |
| 486 | FIELD("Frame Mode", "%s", |
| 487 | (val & 0x0300) == 0x0000 ? "Normal" : |
| 488 | (val & 0x0300) == 0x0100 ? "DSA" : |
| 489 | (val & 0x0300) == 0x0200 ? "Provider" : |
| 490 | (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?"); |
| 491 | FIELD("VLAN Tunnel", "%u", !!(val & 0x0080)); |
| 492 | FIELD("TagIfBoth", "%u", !!(val & 0x0040)); |
| 493 | FIELD("Initial Priority assignment", "%s", |
| 494 | (val & 0x0030) == 0x0000 ? "Defaults" : |
| 495 | (val & 0x0030) == 0x0010 ? "Tag Priority" : |
| 496 | (val & 0x0030) == 0x0020 ? "IP Priority" : |
| 497 | (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?"); |
| 498 | FIELD("Egress Flooding mode", "%s", |
| 499 | (val & 0x000c) == 0x0000 ? "No unknown DA" : |
| 500 | (val & 0x000c) == 0x0004 ? "No unknown multicast DA" : |
| 501 | (val & 0x000c) == 0x0008 ? "No unknown unicast DA" : |
| 502 | (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?"); |
| 503 | FIELD("Port State", "%s", |
| 504 | (val & 0x0003) == 0x0000 ? "Disabled" : |
| 505 | (val & 0x0003) == 0x0001 ? "Blocking/Listening" : |
| 506 | (val & 0x0003) == 0x0002 ? "Learning" : |
| 507 | (val & 0x0003) == 0x0003 ? "Forwarding" : "?"); |
| 508 | break; |
| 509 | case 5: |
| 510 | REG(reg, "Port Control 1", val); |
| 511 | FIELD("Message Port", "%u", !!(val & 0x8000)); |
| 512 | FIELD("LAG Port", "%u", !!(val & 0x4000)); |
| 513 | FIELD("VTU Page", "%u", !!(val & 0x2000)); |
| 514 | FIELD("LAG ID", "%u", (val & 0x0f00) >> 8); |
| 515 | FIELD("FID[11:4]", "0x%.3x", (val & 0x00ff) << 4); |
| 516 | break; |
| 517 | case 6: |
| 518 | REG(reg, "Port Base VLAN Map (Header)", val); |
| 519 | FIELD("FID[3:0]", "0x%.3x", (val & 0xf000) >> 12); |
| 520 | FIELD("Force Mapping", "%u", !!(val & 0x0800)); |
| 521 | FIELD_BITMAP("VLANTable", val & 0x007ff); |
| 522 | break; |
| 523 | case 7: |
| 524 | REG(reg, "Default VLAN ID & Priority", val); |
| 525 | FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13); |
| 526 | FIELD("Force to use Default VID", "%u", !!(val & 0x1000)); |
| 527 | FIELD("Default VLAN Identifier", "%u", val & 0x0fff); |
| 528 | break; |
| 529 | case 8: |
| 530 | REG(reg, "Port Control 2", val); |
| 531 | FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000)); |
| 532 | FIELD("Allow bad FCS", "%u", !!(val & 0x4000)); |
| 533 | FIELD("Jumbo Mode", "%s", |
| 534 | (val & 0x3000) == 0x0000 ? "1522" : |
| 535 | (val & 0x3000) == 0x1000 ? "2048" : |
| 536 | (val & 0x3000) == 0x2000 ? "10240" : |
| 537 | (val & 0x3000) == 0x3000 ? "Reserved" : "?"); |
| 538 | FIELD("802.1QMode", "%s", |
| 539 | (val & 0x0c00) == 0x0000 ? "Disabled" : |
| 540 | (val & 0x0c00) == 0x0400 ? "Fallback" : |
| 541 | (val & 0x0c00) == 0x0800 ? "Check" : |
| 542 | (val & 0x0c00) == 0x0c00 ? "Secure" : "?"); |
| 543 | FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200)); |
| 544 | FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100)); |
| 545 | FIELD("Map using DA hits", "%u", !!(val & 0x0080)); |
| 546 | FIELD("ARP Mirror enable", "%u", !!(val & 0x0040)); |
| 547 | FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020)); |
| 548 | FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010)); |
| 549 | FIELD("Allow VID of Zero", "%u", !!(val & 0x0008)); |
| 550 | FIELD("Default Queue Priority", "0x%x", val & 0x0007); |
| 551 | break; |
| 552 | case 9: |
| 553 | REG(reg, "Egress Rate Control", val); |
| 554 | break; |
| 555 | case 10: |
| 556 | REG(reg, "Egress Rate Control 2", val); |
| 557 | break; |
| 558 | case 11: |
| 559 | REG(reg, "Port Association Vector", val); |
| 560 | break; |
| 561 | case 12: |
| 562 | REG(reg, "Port ATU Control", val); |
| 563 | break; |
| 564 | case 13: |
| 565 | REG(reg, "Override", val); |
| 566 | break; |
| 567 | case 14: |
| 568 | REG(reg, "Policy Control", val); |
| 569 | break; |
| 570 | case 15: |
| 571 | REG(reg, "Port Ether Type", val); |
| 572 | break; |
| 573 | case 22: |
| 574 | REG(reg, "LED Control", val); |
| 575 | break; |
| 576 | case 23: |
| 577 | REG(reg, "IP Priority Mapping Table", val); |
| 578 | break; |
| 579 | case 24: |
| 580 | REG(reg, "IEEE Priority Mapping Table", val); |
| 581 | break; |
| 582 | case 25: |
| 583 | REG(reg, "Port Control 3", val); |
| 584 | break; |
| 585 | case 27: |
| 586 | REG(reg, "Queue Counters", val); |
| 587 | break; |
| 588 | case 28: |
| 589 | REG(reg, "Queue Control", val); |
| 590 | break; |
| 591 | case 30: |
| 592 | REG(reg, "Cut Through Control", val); |
| 593 | break; |
| 594 | case 31: |
| 595 | REG(reg, "Debug Counters", val); |
| 596 | break; |
| 597 | default: |
| 598 | REG(reg, "Reserved", val); |
| 599 | break; |
| 600 | } |
| 601 | }; |
| 602 | |
Vivien Didelot | ff99e46 | 2018-12-18 14:06:36 -0500 | [diff] [blame] | 603 | struct dsa_mv88e6xxx_switch { |
| 604 | void (*dump)(int reg, u16 val); |
| 605 | const char *name; |
| 606 | u16 id; |
| 607 | }; |
| 608 | |
| 609 | static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = { |
Vivien Didelot | a484274 | 2018-12-18 14:06:41 -0500 | [diff] [blame] | 610 | { .id = 0x04a0, .name = "88E6085 ", .dump = NULL }, |
| 611 | { .id = 0x0950, .name = "88E6095 ", .dump = NULL }, |
| 612 | { .id = 0x0990, .name = "88E6097 ", .dump = NULL }, |
Vivien Didelot | 034a17b | 2018-12-18 14:06:40 -0500 | [diff] [blame] | 613 | { .id = 0x0a00, .name = "88E6190X", .dump = dsa_mv88e6390 }, |
| 614 | { .id = 0x0a10, .name = "88E6390X", .dump = dsa_mv88e6390 }, |
Vivien Didelot | a484274 | 2018-12-18 14:06:41 -0500 | [diff] [blame] | 615 | { .id = 0x1060, .name = "88E6131 ", .dump = NULL }, |
| 616 | { .id = 0x1150, .name = "88E6320 ", .dump = NULL }, |
Vivien Didelot | a13a053 | 2018-12-18 14:06:38 -0500 | [diff] [blame] | 617 | { .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 }, |
| 618 | { .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 }, |
Vivien Didelot | a484274 | 2018-12-18 14:06:41 -0500 | [diff] [blame] | 619 | { .id = 0x1650, .name = "88E6165 ", .dump = NULL }, |
| 620 | { .id = 0x1710, .name = "88E6171 ", .dump = NULL }, |
Vivien Didelot | 7f1cc44 | 2018-12-18 14:06:39 -0500 | [diff] [blame] | 621 | { .id = 0x1720, .name = "88E6172 ", .dump = dsa_mv88e6352 }, |
Vivien Didelot | a484274 | 2018-12-18 14:06:41 -0500 | [diff] [blame] | 622 | { .id = 0x1750, .name = "88E6175 ", .dump = NULL }, |
Vivien Didelot | 7f1cc44 | 2018-12-18 14:06:39 -0500 | [diff] [blame] | 623 | { .id = 0x1760, .name = "88E6176 ", .dump = dsa_mv88e6352 }, |
Vivien Didelot | 034a17b | 2018-12-18 14:06:40 -0500 | [diff] [blame] | 624 | { .id = 0x1900, .name = "88E6190 ", .dump = dsa_mv88e6390 }, |
Vivien Didelot | a484274 | 2018-12-18 14:06:41 -0500 | [diff] [blame] | 625 | { .id = 0x1910, .name = "88E6191 ", .dump = NULL }, |
Vivien Didelot | 4e98029 | 2018-12-18 14:06:37 -0500 | [diff] [blame] | 626 | { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 }, |
Vivien Didelot | 7f1cc44 | 2018-12-18 14:06:39 -0500 | [diff] [blame] | 627 | { .id = 0x2400, .name = "88E6240 ", .dump = dsa_mv88e6352 }, |
Vivien Didelot | 034a17b | 2018-12-18 14:06:40 -0500 | [diff] [blame] | 628 | { .id = 0x2900, .name = "88E6290 ", .dump = dsa_mv88e6390 }, |
Vivien Didelot | a484274 | 2018-12-18 14:06:41 -0500 | [diff] [blame] | 629 | { .id = 0x3100, .name = "88E6321 ", .dump = NULL }, |
| 630 | { .id = 0x3400, .name = "88E6141 ", .dump = NULL }, |
| 631 | { .id = 0x3410, .name = "88E6341 ", .dump = NULL }, |
Vivien Didelot | 7f1cc44 | 2018-12-18 14:06:39 -0500 | [diff] [blame] | 632 | { .id = 0x3520, .name = "88E6352 ", .dump = dsa_mv88e6352 }, |
Vivien Didelot | a484274 | 2018-12-18 14:06:41 -0500 | [diff] [blame] | 633 | { .id = 0x3710, .name = "88E6350 ", .dump = NULL }, |
| 634 | { .id = 0x3750, .name = "88E6351 ", .dump = NULL }, |
Vivien Didelot | 034a17b | 2018-12-18 14:06:40 -0500 | [diff] [blame] | 635 | { .id = 0x3900, .name = "88E6390 ", .dump = dsa_mv88e6390 }, |
Vivien Didelot | ff99e46 | 2018-12-18 14:06:36 -0500 | [diff] [blame] | 636 | }; |
| 637 | |
| 638 | static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs) |
| 639 | { |
| 640 | const struct dsa_mv88e6xxx_switch *sw = NULL; |
| 641 | const u16 *data = (u16 *)regs->data; |
| 642 | u16 id; |
| 643 | int i; |
| 644 | |
| 645 | /* Marvell chips have 32 per-port 16-bit registers */ |
| 646 | if (regs->len < 32 * 2) |
| 647 | return 1; |
| 648 | |
| 649 | id = regs->version & 0xfff0; |
| 650 | |
| 651 | for (i = 0; i < ARRAY_SIZE(dsa_mv88e6xxx_switches); i++) { |
| 652 | if (id == dsa_mv88e6xxx_switches[i].id) { |
| 653 | sw = &dsa_mv88e6xxx_switches[i]; |
| 654 | break; |
| 655 | } |
| 656 | } |
| 657 | |
| 658 | if (!sw) |
| 659 | return 1; |
| 660 | |
| 661 | printf("%s Switch Port Registers\n", sw->name); |
| 662 | printf("------------------------------\n"); |
| 663 | |
| 664 | for (i = 0; i < 32; i++) |
| 665 | if (sw->dump) |
| 666 | sw->dump(i, data[i]); |
| 667 | else |
| 668 | REG(i, "", data[i]); |
| 669 | |
| 670 | return 0; |
| 671 | } |
| 672 | |
| 673 | #undef FIELD_BITMAP |
| 674 | #undef FIELD |
| 675 | #undef REG |
| 676 | |
Maciej Żenczykowski | 313c9f8 | 2019-10-17 11:21:02 -0700 | [diff] [blame] | 677 | int dsa_dump_regs(struct ethtool_drvinfo *info maybe_unused, |
| 678 | struct ethtool_regs *regs) |
Vivien Didelot | cb8e980 | 2018-12-18 14:06:35 -0500 | [diff] [blame] | 679 | { |
| 680 | /* DSA per-driver register dump */ |
Vivien Didelot | ff99e46 | 2018-12-18 14:06:36 -0500 | [diff] [blame] | 681 | if (!dsa_mv88e6xxx_dump_regs(regs)) |
| 682 | return 0; |
Vivien Didelot | cb8e980 | 2018-12-18 14:06:35 -0500 | [diff] [blame] | 683 | |
| 684 | /* Fallback to hexdump */ |
| 685 | return 1; |
| 686 | } |