| Vidya Sagar Ravipati | a5e73bb | 2016-08-23 06:30:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * SFF 8636 standards based QSFP EEPROM Field Definitions |
| 3 | * |
| 4 | * Vidya Ravipati <vidya@cumulusnetworks.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | #ifndef QSFP_H__ |
| 14 | #define QSFP_H__ |
| 15 | |
| 16 | /*------------------------------------------------------------------------------ |
| 17 | * |
| 18 | * QSFP EEPROM data structures |
| 19 | * |
| 20 | * register info from SFF-8636 Rev 2.7 |
| 21 | */ |
| 22 | |
| 23 | /*------------------------------------------------------------------------------ |
| 24 | * |
| 25 | * Lower Memory Page 00h |
| 26 | * Measurement, Diagnostic and Control Functions |
| 27 | * |
| 28 | */ |
| 29 | /* Identifier - 0 */ |
| 30 | /* Values are defined under SFF8024_ID_OFFSET */ |
| 31 | #define SFF8636_ID_OFFSET 0x00 |
| 32 | |
| 33 | #define SFF8636_REV_COMPLIANCE_OFFSET 0x01 |
| 34 | #define SFF8636_REV_UNSPECIFIED 0x00 |
| 35 | #define SFF8636_REV_8436_48 0x01 |
| 36 | #define SFF8636_REV_8436_8636 0x02 |
| 37 | #define SFF8636_REV_8636_13 0x03 |
| 38 | #define SFF8636_REV_8636_14 0x04 |
| 39 | #define SFF8636_REV_8636_15 0x05 |
| 40 | #define SFF8636_REV_8636_20 0x06 |
| 41 | #define SFF8636_REV_8636_27 0x07 |
| 42 | |
| 43 | #define SFF8636_STATUS_2_OFFSET 0x02 |
| 44 | /* Flat Memory:0- Paging, 1- Page 0 only */ |
| 45 | #define SFF8636_STATUS_PAGE_3_PRESENT (1 << 2) |
| 46 | #define SFF8636_STATUS_INTL_OUTPUT (1 << 1) |
| 47 | #define SFF8636_STATUS_DATA_NOT_READY (1 << 0) |
| 48 | |
| 49 | /* Channel Status Interrupt Flags - 3-5 */ |
| 50 | #define SFF8636_LOS_AW_OFFSET 0x03 |
| 51 | #define SFF8636_TX4_LOS_AW (1 << 7) |
| 52 | #define SFF8636_TX3_LOS_AW (1 << 6) |
| 53 | #define SFF8636_TX2_LOS_AW (1 << 5) |
| 54 | #define SFF8636_TX1_LOS_AW (1 << 4) |
| 55 | #define SFF8636_RX4_LOS_AW (1 << 3) |
| 56 | #define SFF8636_RX3_LOS_AW (1 << 2) |
| 57 | #define SFF8636_RX2_LOS_AW (1 << 1) |
| 58 | #define SFF8636_RX1_LOS_AW (1 << 0) |
| 59 | |
| 60 | #define SFF8636_FAULT_AW_OFFSET 0x04 |
| 61 | #define SFF8636_TX4_FAULT_AW (1 << 3) |
| 62 | #define SFF8636_TX3_FAULT_AW (1 << 2) |
| 63 | #define SFF8636_TX2_FAULT_AW (1 << 1) |
| 64 | #define SFF8636_TX1_FAULT_AW (1 << 0) |
| 65 | |
| 66 | /* Module Monitor Interrupt Flags - 6-8 */ |
| 67 | #define SFF8636_TEMP_AW_OFFSET 0x06 |
| 68 | #define SFF8636_TEMP_HALARM_STATUS (1 << 7) |
| 69 | #define SFF8636_TEMP_LALARM_STATUS (1 << 6) |
| 70 | #define SFF8636_TEMP_HWARN_STATUS (1 << 5) |
| 71 | #define SFF8636_TEMP_LWARN_STATUS (1 << 4) |
| 72 | |
| 73 | #define SFF8636_VCC_AW_OFFSET 0x07 |
| 74 | #define SFF8636_VCC_HALARM_STATUS (1 << 7) |
| 75 | #define SFF8636_VCC_LALARM_STATUS (1 << 6) |
| 76 | #define SFF8636_VCC_HWARN_STATUS (1 << 5) |
| 77 | #define SFF8636_VCC_LWARN_STATUS (1 << 4) |
| 78 | |
| 79 | /* Channel Monitor Interrupt Flags - 9-21 */ |
| 80 | #define SFF8636_RX_PWR_12_AW_OFFSET 0x09 |
| 81 | #define SFF8636_RX_PWR_1_HALARM (1 << 7) |
| 82 | #define SFF8636_RX_PWR_1_LALARM (1 << 6) |
| 83 | #define SFF8636_RX_PWR_1_HWARN (1 << 5) |
| 84 | #define SFF8636_RX_PWR_1_LWARN (1 << 4) |
| 85 | #define SFF8636_RX_PWR_2_HALARM (1 << 3) |
| 86 | #define SFF8636_RX_PWR_2_LALARM (1 << 2) |
| 87 | #define SFF8636_RX_PWR_2_HWARN (1 << 1) |
| 88 | #define SFF8636_RX_PWR_2_LWARN (1 << 0) |
| 89 | |
| 90 | #define SFF8636_RX_PWR_34_AW_OFFSET 0x0A |
| 91 | #define SFF8636_RX_PWR_3_HALARM (1 << 7) |
| 92 | #define SFF8636_RX_PWR_3_LALARM (1 << 6) |
| 93 | #define SFF8636_RX_PWR_3_HWARN (1 << 5) |
| 94 | #define SFF8636_RX_PWR_3_LWARN (1 << 4) |
| 95 | #define SFF8636_RX_PWR_4_HALARM (1 << 3) |
| 96 | #define SFF8636_RX_PWR_4_LALARM (1 << 2) |
| 97 | #define SFF8636_RX_PWR_4_HWARN (1 << 1) |
| 98 | #define SFF8636_RX_PWR_4_LWARN (1 << 0) |
| 99 | |
| 100 | #define SFF8636_TX_BIAS_12_AW_OFFSET 0x0B |
| 101 | #define SFF8636_TX_BIAS_1_HALARM (1 << 7) |
| 102 | #define SFF8636_TX_BIAS_1_LALARM (1 << 6) |
| 103 | #define SFF8636_TX_BIAS_1_HWARN (1 << 5) |
| 104 | #define SFF8636_TX_BIAS_1_LWARN (1 << 4) |
| 105 | #define SFF8636_TX_BIAS_2_HALARM (1 << 3) |
| 106 | #define SFF8636_TX_BIAS_2_LALARM (1 << 2) |
| 107 | #define SFF8636_TX_BIAS_2_HWARN (1 << 1) |
| 108 | #define SFF8636_TX_BIAS_2_LWARN (1 << 0) |
| 109 | |
| 110 | #define SFF8636_TX_BIAS_34_AW_OFFSET 0xC |
| 111 | #define SFF8636_TX_BIAS_3_HALARM (1 << 7) |
| 112 | #define SFF8636_TX_BIAS_3_LALARM (1 << 6) |
| 113 | #define SFF8636_TX_BIAS_3_HWARN (1 << 5) |
| 114 | #define SFF8636_TX_BIAS_3_LWARN (1 << 4) |
| 115 | #define SFF8636_TX_BIAS_4_HALARM (1 << 3) |
| 116 | #define SFF8636_TX_BIAS_4_LALARM (1 << 2) |
| 117 | #define SFF8636_TX_BIAS_4_HWARN (1 << 1) |
| 118 | #define SFF8636_TX_BIAS_4_LWARN (1 << 0) |
| 119 | |
| 120 | #define SFF8636_TX_PWR_12_AW_OFFSET 0x0D |
| 121 | #define SFF8636_TX_PWR_1_HALARM (1 << 7) |
| 122 | #define SFF8636_TX_PWR_1_LALARM (1 << 6) |
| 123 | #define SFF8636_TX_PWR_1_HWARN (1 << 5) |
| 124 | #define SFF8636_TX_PWR_1_LWARN (1 << 4) |
| 125 | #define SFF8636_TX_PWR_2_HALARM (1 << 3) |
| 126 | #define SFF8636_TX_PWR_2_LALARM (1 << 2) |
| 127 | #define SFF8636_TX_PWR_2_HWARN (1 << 1) |
| 128 | #define SFF8636_TX_PWR_2_LWARN (1 << 0) |
| 129 | |
| 130 | #define SFF8636_TX_PWR_34_AW_OFFSET 0x0E |
| 131 | #define SFF8636_TX_PWR_3_HALARM (1 << 7) |
| 132 | #define SFF8636_TX_PWR_3_LALARM (1 << 6) |
| 133 | #define SFF8636_TX_PWR_3_HWARN (1 << 5) |
| 134 | #define SFF8636_TX_PWR_3_LWARN (1 << 4) |
| 135 | #define SFF8636_TX_PWR_4_HALARM (1 << 3) |
| 136 | #define SFF8636_TX_PWR_4_LALARM (1 << 2) |
| 137 | #define SFF8636_TX_PWR_4_HWARN (1 << 1) |
| 138 | #define SFF8636_TX_PWR_4_LWARN (1 << 0) |
| 139 | |
| 140 | /* Module Monitoring Values - 22-33 */ |
| 141 | #define SFF8636_TEMP_CURR 0x16 |
| 142 | #define SFF8636_TEMP_MSB_OFFSET 0x16 |
| 143 | #define SFF8636_TEMP_LSB_OFFSET 0x17 |
| 144 | |
| 145 | #define SFF8636_VCC_CURR 0x1A |
| 146 | #define SFF8636_VCC_MSB_OFFSET 0x1A |
| 147 | #define SFF8636_VCC_LSB_OFFSET 0x1B |
| 148 | |
| 149 | /* Channel Monitoring Values - 34-81 */ |
| 150 | #define SFF8636_RX_PWR_1_OFFSET 0x22 |
| 151 | #define SFF8636_RX_PWR_2_OFFSET 0x24 |
| 152 | #define SFF8636_RX_PWR_3_OFFSET 0x26 |
| 153 | #define SFF8636_RX_PWR_4_OFFSET 0x28 |
| 154 | |
| 155 | #define SFF8636_TX_BIAS_1_OFFSET 0x2A |
| 156 | #define SFF8636_TX_BIAS_2_OFFSET 0x2C |
| 157 | #define SFF8636_TX_BIAS_3_OFFSET 0x2E |
| 158 | #define SFF8636_TX_BIAS_4_OFFSET 0x30 |
| 159 | |
| 160 | #define SFF8636_TX_PWR_1_OFFSET 0x32 |
| 161 | #define SFF8636_TX_PWR_2_OFFSET 0x34 |
| 162 | #define SFF8636_TX_PWR_3_OFFSET 0x36 |
| 163 | #define SFF8636_TX_PWR_4_OFFSET 0x38 |
| 164 | |
| 165 | /* Control Bytes - 86 - 99 */ |
| 166 | #define SFF8636_TX_DISABLE_OFFSET 0x56 |
| 167 | #define SFF8636_TX_DISABLE_4 (1 << 3) |
| 168 | #define SFF8636_TX_DISABLE_3 (1 << 2) |
| 169 | #define SFF8636_TX_DISABLE_2 (1 << 1) |
| 170 | #define SFF8636_TX_DISABLE_1 (1 << 0) |
| 171 | |
| 172 | #define SFF8636_RX_RATE_SELECT_OFFSET 0x57 |
| 173 | #define SFF8636_RX_RATE_SELECT_4_MASK (3 << 6) |
| 174 | #define SFF8636_RX_RATE_SELECT_3_MASK (3 << 4) |
| 175 | #define SFF8636_RX_RATE_SELECT_2_MASK (3 << 2) |
| 176 | #define SFF8636_RX_RATE_SELECT_1_MASK (3 << 0) |
| 177 | |
| 178 | #define SFF8636_TX_RATE_SELECT_OFFSET 0x58 |
| 179 | #define SFF8636_TX_RATE_SELECT_4_MASK (3 << 6) |
| 180 | #define SFF8636_TX_RATE_SELECT_3_MASK (3 << 4) |
| 181 | #define SFF8636_TX_RATE_SELECT_2_MASK (3 << 2) |
| 182 | #define SFF8636_TX_RATE_SELECT_1_MASK (3 << 0) |
| 183 | |
| 184 | #define SFF8636_RX_APP_SELECT_4_OFFSET 0x58 |
| 185 | #define SFF8636_RX_APP_SELECT_3_OFFSET 0x59 |
| 186 | #define SFF8636_RX_APP_SELECT_2_OFFSET 0x5A |
| 187 | #define SFF8636_RX_APP_SELECT_1_OFFSET 0x5B |
| 188 | |
| 189 | #define SFF8636_PWR_MODE_OFFSET 0x5D |
| 190 | #define SFF8636_HIGH_PWR_ENABLE (1 << 2) |
| 191 | #define SFF8636_LOW_PWR_MODE (1 << 1) |
| 192 | #define SFF8636_PWR_OVERRIDE (1 << 0) |
| 193 | |
| 194 | #define SFF8636_TX_APP_SELECT_4_OFFSET 0x5E |
| 195 | #define SFF8636_TX_APP_SELECT_3_OFFSET 0x5F |
| 196 | #define SFF8636_TX_APP_SELECT_2_OFFSET 0x60 |
| 197 | #define SFF8636_TX_APP_SELECT_1_OFFSET 0x61 |
| 198 | |
| 199 | #define SFF8636_LOS_MASK_OFFSET 0x64 |
| 200 | #define SFF8636_TX_LOS_4_MASK (1 << 7) |
| 201 | #define SFF8636_TX_LOS_3_MASK (1 << 6) |
| 202 | #define SFF8636_TX_LOS_2_MASK (1 << 5) |
| 203 | #define SFF8636_TX_LOS_1_MASK (1 << 4) |
| 204 | #define SFF8636_RX_LOS_4_MASK (1 << 3) |
| 205 | #define SFF8636_RX_LOS_3_MASK (1 << 2) |
| 206 | #define SFF8636_RX_LOS_2_MASK (1 << 1) |
| 207 | #define SFF8636_RX_LOS_1_MASK (1 << 0) |
| 208 | |
| 209 | #define SFF8636_FAULT_MASK_OFFSET 0x65 |
| 210 | #define SFF8636_TX_FAULT_1_MASK (1 << 3) |
| 211 | #define SFF8636_TX_FAULT_2_MASK (1 << 2) |
| 212 | #define SFF8636_TX_FAULT_3_MASK (1 << 1) |
| 213 | #define SFF8636_TX_FAULT_4_MASK (1 << 0) |
| 214 | |
| 215 | #define SFF8636_TEMP_MASK_OFFSET 0x67 |
| 216 | #define SFF8636_TEMP_HALARM_MASK (1 << 7) |
| 217 | #define SFF8636_TEMP_LALARM_MASK (1 << 6) |
| 218 | #define SFF8636_TEMP_HWARN_MASK (1 << 5) |
| 219 | #define SFF8636_TEMP_LWARN_MASK (1 << 4) |
| 220 | |
| 221 | #define SFF8636_VCC_MASK_OFFSET 0x68 |
| 222 | #define SFF8636_VCC_HALARM_MASK (1 << 7) |
| 223 | #define SFF8636_VCC_LALARM_MASK (1 << 6) |
| 224 | #define SFF8636_VCC_HWARN_MASK (1 << 5) |
| 225 | #define SFF8636_VCC_LWARN_MASK (1 << 4) |
| 226 | |
| 227 | /*------------------------------------------------------------------------------ |
| 228 | * |
| 229 | * Upper Memory Page 00h |
| 230 | * Serial ID - Base ID, Extended ID and Vendor Specific ID fields |
| 231 | * |
| 232 | */ |
| 233 | /* Identifier - 128 */ |
| 234 | /* Identifier values same as Lower Memory Page 00h */ |
| 235 | #define SFF8636_UPPER_PAGE_0_ID_OFFSET 0x80 |
| 236 | |
| 237 | /* Extended Identifier - 128 */ |
| 238 | #define SFF8636_EXT_ID_OFFSET 0x81 |
| 239 | #define SFF8636_EXT_ID_PWR_CLASS_MASK 0xC0 |
| 240 | #define SFF8636_EXT_ID_PWR_CLASS_1 (0 << 6) |
| 241 | #define SFF8636_EXT_ID_PWR_CLASS_2 (1 << 6) |
| 242 | #define SFF8636_EXT_ID_PWR_CLASS_3 (2 << 6) |
| 243 | #define SFF8636_EXT_ID_PWR_CLASS_4 (3 << 6) |
| 244 | #define SFF8636_EXT_ID_CLIE_MASK 0x10 |
| 245 | #define SFF8636_EXT_ID_CLIEI_CODE_PRESENT (1 << 4) |
| 246 | #define SFF8636_EXT_ID_CDR_TX_MASK 0x08 |
| 247 | #define SFF8636_EXT_ID_CDR_TX_PRESENT (1 << 3) |
| 248 | #define SFF8636_EXT_ID_CDR_RX_MASK 0x04 |
| 249 | #define SFF8636_EXT_ID_CDR_RX_PRESENT (1 << 2) |
| 250 | #define SFF8636_EXT_ID_EPWR_CLASS_MASK 0x03 |
| 251 | #define SFF8636_EXT_ID_PWR_CLASS_LEGACY 0 |
| 252 | #define SFF8636_EXT_ID_PWR_CLASS_5 1 |
| 253 | #define SFF8636_EXT_ID_PWR_CLASS_6 2 |
| 254 | #define SFF8636_EXT_ID_PWR_CLASS_7 3 |
| 255 | |
| 256 | /* Connector Values offset - 130 */ |
| 257 | /* Values are defined under SFF8024_CTOR */ |
| 258 | #define SFF8636_CTOR_OFFSET 0x82 |
| 259 | #define SFF8636_CTOR_UNKNOWN 0x00 |
| 260 | #define SFF8636_CTOR_SC 0x01 |
| 261 | #define SFF8636_CTOR_FC_STYLE_1 0x02 |
| 262 | #define SFF8636_CTOR_FC_STYLE_2 0x03 |
| 263 | #define SFF8636_CTOR_BNC_TNC 0x04 |
| 264 | #define SFF8636_CTOR_FC_COAX 0x05 |
| 265 | #define SFF8636_CTOR_FIBER_JACK 0x06 |
| 266 | #define SFF8636_CTOR_LC 0x07 |
| 267 | #define SFF8636_CTOR_MT_RJ 0x08 |
| 268 | #define SFF8636_CTOR_MU 0x09 |
| 269 | #define SFF8636_CTOR_SG 0x0A |
| 270 | #define SFF8636_CTOR_OPT_PT 0x0B |
| 271 | #define SFF8636_CTOR_MPO 0x0C |
| 272 | /* 0D-1Fh --- Reserved */ |
| 273 | #define SFF8636_CTOR_HSDC_II 0x20 |
| 274 | #define SFF8636_CTOR_COPPER_PT 0x21 |
| 275 | #define SFF8636_CTOR_RJ45 0x22 |
| 276 | #define SFF8636_CTOR_NO_SEPARABLE 0x23 |
| 277 | #define SFF8636_CTOR_MXC_2X16 0x24 |
| 278 | |
| 279 | /* Specification Compliance - 131-138 */ |
| 280 | /* Ethernet Compliance Codes - 131 */ |
| 281 | #define SFF8636_ETHERNET_COMP_OFFSET 0x83 |
| 282 | #define SFF8636_ETHERNET_RSRVD (1 << 7) |
| 283 | #define SFF8636_ETHERNET_10G_LRM (1 << 6) |
| 284 | #define SFF8636_ETHERNET_10G_LR (1 << 5) |
| 285 | #define SFF8636_ETHERNET_10G_SR (1 << 4) |
| 286 | #define SFF8636_ETHERNET_40G_CR4 (1 << 3) |
| 287 | #define SFF8636_ETHERNET_40G_SR4 (1 << 2) |
| 288 | #define SFF8636_ETHERNET_40G_LR4 (1 << 1) |
| 289 | #define SFF8636_ETHERNET_40G_ACTIVE (1 << 0) |
| 290 | |
| 291 | /* SONET Compliance Codes - 132 */ |
| 292 | #define SFF8636_SONET_COMP_OFFSET 0x84 |
| 293 | #define SFF8636_SONET_40G_OTN (1 << 3) |
| 294 | #define SFF8636_SONET_OC48_LR (1 << 2) |
| 295 | #define SFF8636_SONET_OC48_IR (1 << 1) |
| 296 | #define SFF8636_SONET_OC48_SR (1 << 0) |
| 297 | |
| 298 | /* SAS/SATA Complaince Codes - 133 */ |
| 299 | #define SFF8636_SAS_COMP_OFFSET 0x85 |
| 300 | #define SFF8636_SAS_12G (1 << 6) |
| 301 | #define SFF8636_SAS_6G (1 << 5) |
| 302 | #define SFF8636_SAS_3G (1 << 4) |
| 303 | |
| 304 | /* Gigabit Ethernet Compliance Codes - 134 */ |
| 305 | #define SFF8636_GIGE_COMP_OFFSET 0x86 |
| 306 | #define SFF8636_GIGE_1000_BASE_T (1 << 3) |
| 307 | #define SFF8636_GIGE_1000_BASE_CX (1 << 2) |
| 308 | #define SFF8636_GIGE_1000_BASE_LX (1 << 1) |
| 309 | #define SFF8636_GIGE_1000_BASE_SX (1 << 0) |
| 310 | |
| 311 | /* Fibre Channel Link length/Transmitter Tech. - 135,136 */ |
| 312 | #define SFF8636_FC_LEN_OFFSET 0x87 |
| 313 | #define SFF8636_FC_LEN_VERY_LONG (1 << 7) |
| 314 | #define SFF8636_FC_LEN_SHORT (1 << 6) |
| 315 | #define SFF8636_FC_LEN_INT (1 << 5) |
| 316 | #define SFF8636_FC_LEN_LONG (1 << 4) |
| 317 | #define SFF8636_FC_LEN_MED (1 << 3) |
| 318 | #define SFF8636_FC_TECH_LONG_LC (1 << 1) |
| 319 | #define SFF8636_FC_TECH_ELEC_INTER (1 << 0) |
| 320 | |
| 321 | #define SFF8636_FC_TECH_OFFSET 0x88 |
| 322 | #define SFF8636_FC_TECH_ELEC_INTRA (1 << 7) |
| 323 | #define SFF8636_FC_TECH_SHORT_WO_OFC (1 << 6) |
| 324 | #define SFF8636_FC_TECH_SHORT_W_OFC (1 << 5) |
| 325 | #define SFF8636_FC_TECH_LONG_LL (1 << 4) |
| 326 | |
| 327 | /* Fibre Channel Transmitter Media - 137 */ |
| 328 | #define SFF8636_FC_TRANS_MEDIA_OFFSET 0x89 |
| 329 | /* Twin Axial Pair */ |
| 330 | #define SFF8636_FC_TRANS_MEDIA_TW (1 << 7) |
| 331 | /* Shielded Twisted Pair */ |
| 332 | #define SFF8636_FC_TRANS_MEDIA_TP (1 << 6) |
| 333 | /* Miniature Coax */ |
| 334 | #define SFF8636_FC_TRANS_MEDIA_MI (1 << 5) |
| 335 | /* Video Coax */ |
| 336 | #define SFF8636_FC_TRANS_MEDIA_TV (1 << 4) |
| 337 | /* Multi-mode 62.5m */ |
| 338 | #define SFF8636_FC_TRANS_MEDIA_M6 (1 << 3) |
| 339 | /* Multi-mode 50m */ |
| 340 | #define SFF8636_FC_TRANS_MEDIA_M5 (1 << 2) |
| 341 | /* Multi-mode 50um */ |
| 342 | #define SFF8636_FC_TRANS_MEDIA_OM3 (1 << 1) |
| 343 | /* Single Mode */ |
| 344 | #define SFF8636_FC_TRANS_MEDIA_SM (1 << 0) |
| 345 | |
| 346 | /* Fibre Channel Speed - 138 */ |
| 347 | #define SFF8636_FC_SPEED_OFFSET 0x8A |
| 348 | #define SFF8636_FC_SPEED_1200_MBPS (1 << 7) |
| 349 | #define SFF8636_FC_SPEED_800_MBPS (1 << 6) |
| 350 | #define SFF8636_FC_SPEED_1600_MBPS (1 << 5) |
| 351 | #define SFF8636_FC_SPEED_400_MBPS (1 << 4) |
| 352 | #define SFF8636_FC_SPEED_200_MBPS (1 << 2) |
| 353 | #define SFF8636_FC_SPEED_100_MBPS (1 << 0) |
| 354 | |
| 355 | /* Encoding - 139 */ |
| 356 | /* Values are defined under SFF8024_ENCODING */ |
| 357 | #define SFF8636_ENCODING_OFFSET 0x8B |
| 358 | #define SFF8636_ENCODING_MANCHESTER 0x06 |
| 359 | #define SFF8636_ENCODING_64B66B 0x05 |
| 360 | #define SFF8636_ENCODING_SONET 0x04 |
| 361 | #define SFF8636_ENCODING_NRZ 0x03 |
| 362 | #define SFF8636_ENCODING_4B5B 0x02 |
| 363 | #define SFF8636_ENCODING_8B10B 0x01 |
| 364 | #define SFF8636_ENCODING_UNSPEC 0x00 |
| 365 | |
| 366 | /* BR, Nominal - 140 */ |
| 367 | #define SFF8636_BR_NOMINAL_OFFSET 0x8C |
| 368 | |
| 369 | /* Extended RateSelect - 141 */ |
| 370 | #define SFF8636_EXT_RS_OFFSET 0x8D |
| 371 | #define SFF8636_EXT_RS_V1 (1 << 0) |
| 372 | |
| 373 | /* Length (Standard SM Fiber)-km - 142 */ |
| 374 | #define SFF8636_SM_LEN_OFFSET 0x8E |
| 375 | |
| 376 | /* Length (OM3)-Unit 2m - 143 */ |
| 377 | #define SFF8636_OM3_LEN_OFFSET 0x8F |
| 378 | |
| 379 | /* Length (OM2)-Unit 1m - 144 */ |
| 380 | #define SFF8636_OM2_LEN_OFFSET 0x90 |
| 381 | |
| 382 | /* Length (OM1)-Unit 1m - 145 */ |
| 383 | #define SFF8636_OM1_LEN_OFFSET 0x91 |
| 384 | |
| 385 | /* Cable Assembly Length -Unit 1m - 146 */ |
| 386 | #define SFF8636_CBL_LEN_OFFSET 0x92 |
| 387 | |
| 388 | /* Device Technology - 147 */ |
| 389 | #define SFF8636_DEVICE_TECH_OFFSET 0x93 |
| 390 | /* Transmitter Technology */ |
| 391 | #define SFF8636_TRANS_TECH_MASK 0xF0 |
| 392 | /* Copper cable, linear active equalizers */ |
| 393 | #define SFF8636_TRANS_COPPER_LNR_EQUAL (15 << 4) |
| 394 | /* Copper cable, near end limiting active equalizers */ |
| 395 | #define SFF8636_TRANS_COPPER_NEAR_EQUAL (14 << 4) |
| 396 | /* Copper cable, far end limiting active equalizers */ |
| 397 | #define SFF8636_TRANS_COPPER_FAR_EQUAL (13 << 4) |
| 398 | /* Copper cable, near & far end limiting active equalizers */ |
| 399 | #define SFF8636_TRANS_COPPER_LNR_FAR_EQUAL (12 << 4) |
| 400 | /* Copper cable, passive equalized */ |
| 401 | #define SFF8636_TRANS_COPPER_PAS_EQUAL (11 << 4) |
| 402 | /* Copper cable, unequalized */ |
| 403 | #define SFF8636_TRANS_COPPER_PAS_UNEQUAL (10 << 4) |
| 404 | /* 1490 nm DFB */ |
| 405 | #define SFF8636_TRANS_1490_DFB (9 << 4) |
| 406 | /* Others */ |
| 407 | #define SFF8636_TRANS_OTHERS (8 << 4) |
| 408 | /* 1550 nm EML */ |
| 409 | #define SFF8636_TRANS_1550_EML (7 << 4) |
| 410 | /* 1310 nm EML */ |
| 411 | #define SFF8636_TRANS_1310_EML (6 << 4) |
| 412 | /* 1550 nm DFB */ |
| 413 | #define SFF8636_TRANS_1550_DFB (5 << 4) |
| 414 | /* 1310 nm DFB */ |
| 415 | #define SFF8636_TRANS_1310_DFB (4 << 4) |
| 416 | /* 1310 nm FP */ |
| 417 | #define SFF8636_TRANS_1310_FP (3 << 4) |
| 418 | /* 1550 nm VCSEL */ |
| 419 | #define SFF8636_TRANS_1550_VCSEL (2 << 4) |
| 420 | /* 1310 nm VCSEL */ |
| 421 | #define SFF8636_TRANS_1310_VCSEL (1 << 4) |
| 422 | /* 850 nm VCSEL */ |
| 423 | #define SFF8636_TRANS_850_VCSEL (0 << 4) |
| 424 | |
| 425 | /* Active/No wavelength control */ |
| 426 | #define SFF8636_DEV_TECH_ACTIVE_WAVE_LEN (1 << 3) |
| 427 | /* Cooled transmitter */ |
| 428 | #define SFF8636_DEV_TECH_COOL_TRANS (1 << 2) |
| 429 | /* APD/Pin Detector */ |
| 430 | #define SFF8636_DEV_TECH_APD_DETECTOR (1 << 1) |
| 431 | /* Transmitter tunable */ |
| 432 | #define SFF8636_DEV_TECH_TUNABLE (1 << 0) |
| 433 | |
| 434 | /* Vendor Name - 148-163 */ |
| 435 | #define SFF8636_VENDOR_NAME_START_OFFSET 0x94 |
| 436 | #define SFF8636_VENDOR_NAME_END_OFFSET 0xA3 |
| 437 | |
| 438 | /* Extended Module Codes - 164 */ |
| 439 | #define SFF8636_EXT_MOD_CODE_OFFSET 0xA4 |
| 440 | #define SFF8636_EXT_MOD_INFINIBAND_EDR (1 << 4) |
| 441 | #define SFF8636_EXT_MOD_INFINIBAND_FDR (1 << 3) |
| 442 | #define SFF8636_EXT_MOD_INFINIBAND_QDR (1 << 2) |
| 443 | #define SFF8636_EXT_MOD_INFINIBAND_DDR (1 << 1) |
| 444 | #define SFF8636_EXT_MOD_INFINIBAND_SDR (1 << 0) |
| 445 | |
| 446 | /* Vendor OUI - 165-167 */ |
| 447 | #define SFF8636_VENDOR_OUI_OFFSET 0xA5 |
| 448 | #define SFF8636_VENDOR_OUI_LEN 3 |
| 449 | |
| 450 | /* Vendor OUI - 165-167 */ |
| 451 | #define SFF8636_VENDOR_PN_START_OFFSET 0xA8 |
| 452 | #define SFF8636_VENDOR_PN_END_OFFSET 0xB7 |
| 453 | |
| 454 | /* Vendor Revision - 184-185 */ |
| 455 | #define SFF8636_VENDOR_REV_START_OFFSET 0xB8 |
| 456 | #define SFF8636_VENDOR_REV_END_OFFSET 0xB9 |
| 457 | |
| 458 | /* Wavelength - 186-187 */ |
| 459 | #define SFF8636_WAVELEN_HIGH_BYTE_OFFSET 0xBA |
| 460 | #define SFF8636_WAVELEN_LOW_BYTE_OFFSET 0xBB |
| 461 | |
| 462 | /* Wavelength Tolerance- 188-189 */ |
| 463 | #define SFF8636_WAVE_TOL_HIGH_BYTE_OFFSET 0xBC |
| 464 | #define SFF8636_WAVE_TOL_LOW_BYTE_OFFSET 0xBD |
| 465 | |
| 466 | /* Max case temp - Other than 70 C - 190 */ |
| 467 | #define SFF8636_MAXCASE_TEMP_OFFSET 0xBE |
| 468 | |
| 469 | /* CC_BASE - 191 */ |
| 470 | #define SFF8636_CC_BASE_OFFSET 0xBF |
| 471 | |
| 472 | /* Option Values - 192-195 */ |
| 473 | #define SFF8636_OPTION_1_OFFSET 0xC0 |
| 474 | #define SFF8636_ETHERNET_UNSPECIFIED 0x00 |
| 475 | #define SFF8636_ETHERNET_100G_AOC 0x01 |
| 476 | #define SFF8636_ETHERNET_100G_SR4 0x02 |
| 477 | #define SFF8636_ETHERNET_100G_LR4 0x03 |
| 478 | #define SFF8636_ETHERNET_100G_ER4 0x04 |
| 479 | #define SFF8636_ETHERNET_100G_SR10 0x05 |
| 480 | #define SFF8636_ETHERNET_100G_CWDM4_FEC 0x06 |
| 481 | #define SFF8636_ETHERNET_100G_PSM4 0x07 |
| 482 | #define SFF8636_ETHERNET_100G_ACC 0x08 |
| 483 | #define SFF8636_ETHERNET_100G_CWDM4_NO_FEC 0x09 |
| 484 | #define SFF8636_ETHERNET_100G_RSVD1 0x0A |
| 485 | #define SFF8636_ETHERNET_100G_CR4 0x0B |
| 486 | #define SFF8636_ETHERNET_25G_CR_CA_S 0x0C |
| 487 | #define SFF8636_ETHERNET_25G_CR_CA_N 0x0D |
| 488 | #define SFF8636_ETHERNET_40G_ER4 0x10 |
| 489 | #define SFF8636_ETHERNET_4X10_SR 0x11 |
| 490 | #define SFF8636_ETHERNET_40G_PSM4 0x12 |
| 491 | #define SFF8636_ETHERNET_G959_P1I1_2D1 0x13 |
| 492 | #define SFF8636_ETHERNET_G959_P1S1_2D2 0x14 |
| 493 | #define SFF8636_ETHERNET_G959_P1L1_2D2 0x15 |
| 494 | #define SFF8636_ETHERNET_10GT_SFI 0x16 |
| 495 | #define SFF8636_ETHERNET_100G_CLR4 0x17 |
| 496 | #define SFF8636_ETHERNET_100G_AOC2 0x18 |
| 497 | #define SFF8636_ETHERNET_100G_ACC2 0x19 |
| 498 | |
| 499 | #define SFF8636_OPTION_2_OFFSET 0xC1 |
| 500 | /* Rx output amplitude */ |
| 501 | #define SFF8636_O2_RX_OUTPUT_AMP (1 << 0) |
| 502 | #define SFF8636_OPTION_3_OFFSET 0xC2 |
| 503 | /* Rx Squelch Disable */ |
| 504 | #define SFF8636_O3_RX_SQL_DSBL (1 << 3) |
| 505 | /* Rx Output Disable capable */ |
| 506 | #define SFF8636_O3_RX_OUTPUT_DSBL (1 << 2) |
| 507 | /* Tx Squelch Disable */ |
| 508 | #define SFF8636_O3_TX_SQL_DSBL (1 << 1) |
| 509 | /* Tx Squelch Impl */ |
| 510 | #define SFF8636_O3_TX_SQL_IMPL (1 << 0) |
| 511 | #define SFF8636_OPTION_4_OFFSET 0xC3 |
| 512 | /* Memory Page 02 present */ |
| 513 | #define SFF8636_O4_PAGE_02_PRESENT (1 << 7) |
| 514 | /* Memory Page 01 present */ |
| 515 | #define SFF8636_O4_PAGE_01_PRESENT (1 << 6) |
| 516 | /* Rate Select implemented */ |
| 517 | #define SFF8636_O4_RATE_SELECT (1 << 5) |
| 518 | /* Tx_DISABLE implemented */ |
| 519 | #define SFF8636_O4_TX_DISABLE (1 << 4) |
| 520 | /* Tx_FAULT implemented */ |
| 521 | #define SFF8636_O4_TX_FAULT (1 << 3) |
| 522 | /* Tx Squelch implemented */ |
| 523 | #define SFF8636_O4_TX_SQUELCH (1 << 2) |
| 524 | /* Tx Loss of Signal */ |
| 525 | #define SFF8636_O4_TX_LOS (1 << 1) |
| 526 | |
| 527 | /* Vendor SN - 196-211 */ |
| 528 | #define SFF8636_VENDOR_SN_START_OFFSET 0xC4 |
| 529 | #define SFF8636_VENDOR_SN_END_OFFSET 0xD3 |
| 530 | |
| 531 | /* Vendor Date - 212-219 */ |
| 532 | #define SFF8636_DATE_YEAR_OFFSET 0xD4 |
| 533 | #define SFF8636_DATE_YEAR_LEN 2 |
| 534 | #define SFF8636_DATE_MONTH_OFFSET 0xD6 |
| 535 | #define SFF8636_DATE_MONTH_LEN 2 |
| 536 | #define SFF8636_DATE_DAY_OFFSET 0xD8 |
| 537 | #define SFF8636_DATE_DAY_LEN 2 |
| Saeed Mahameed | bde4c54 | 2018-02-21 12:35:09 -0800 | [diff] [blame] | 538 | #define SFF8636_DATE_VENDOR_LOT_OFFSET 0xDA |
| 539 | #define SFF8636_DATE_VENDOR_LOT_LEN 2 |
| Vidya Sagar Ravipati | a5e73bb | 2016-08-23 06:30:32 -0700 | [diff] [blame] | 540 | |
| 541 | /* Diagnostic Monitoring Type - 220 */ |
| 542 | #define SFF8636_DIAG_TYPE_OFFSET 0xDC |
| 543 | #define SFF8636_RX_PWR_TYPE_MASK 0x8 |
| 544 | #define SFF8636_RX_PWR_TYPE_AVG_PWR (1 << 3) |
| 545 | #define SFF8636_RX_PWR_TYPE_OMA (0 << 3) |
| 546 | #define SFF8636_TX_PWR_TYPE_MASK 0x4 |
| 547 | #define SFF8636_TX_PWR_TYPE_AVG_PWR (1 << 2) |
| 548 | |
| 549 | /* Enhanced Options - 221 */ |
| 550 | #define SFF8636_ENH_OPTIONS_OFFSET 0xDD |
| 551 | #define SFF8636_RATE_SELECT_EXT_SUPPORT (1 << 3) |
| 552 | #define SFF8636_RATE_SELECT_APP_TABLE_SUPPORT (1 << 2) |
| 553 | |
| 554 | /* Check code - 223 */ |
| 555 | #define SFF8636_CC_EXT_OFFSET 0xDF |
| 556 | #define SFF8636_CC_EXT_LEN 1 |
| 557 | |
| 558 | /*------------------------------------------------------------------------------ |
| 559 | * |
| 560 | * Upper Memory Page 03h |
| 561 | * Contains module thresholds, channel thresholds and masks, |
| 562 | * and optional channel controls |
| 563 | * |
| 564 | * Offset - Page Num(3) * PageSize(0x80) + Page offset |
| 565 | */ |
| 566 | |
| 567 | /* Module Thresholds (48 Bytes) 128-175 */ |
| 568 | /* MSB at low address, LSB at high address */ |
| 569 | #define SFF8636_TEMP_HALRM 0x200 |
| 570 | #define SFF8636_TEMP_LALRM 0x202 |
| 571 | #define SFF8636_TEMP_HWARN 0x204 |
| 572 | #define SFF8636_TEMP_LWARN 0x206 |
| 573 | |
| 574 | #define SFF8636_VCC_HALRM 0x210 |
| 575 | #define SFF8636_VCC_LALRM 0x212 |
| 576 | #define SFF8636_VCC_HWARN 0x214 |
| 577 | #define SFF8636_VCC_LWARN 0x216 |
| 578 | |
| 579 | #define SFF8636_RX_PWR_HALRM 0x230 |
| 580 | #define SFF8636_RX_PWR_LALRM 0x232 |
| 581 | #define SFF8636_RX_PWR_HWARN 0x234 |
| 582 | #define SFF8636_RX_PWR_LWARN 0x236 |
| 583 | |
| 584 | #define SFF8636_TX_BIAS_HALRM 0x238 |
| 585 | #define SFF8636_TX_BIAS_LALRM 0x23A |
| 586 | #define SFF8636_TX_BIAS_HWARN 0x23C |
| 587 | #define SFF8636_TX_BIAS_LWARN 0x23E |
| 588 | |
| 589 | #define SFF8636_TX_PWR_HALRM 0x240 |
| 590 | #define SFF8636_TX_PWR_LALRM 0x242 |
| 591 | #define SFF8636_TX_PWR_HWARN 0x244 |
| 592 | #define SFF8636_TX_PWR_LWARN 0x246 |
| 593 | |
| 594 | #define ETH_MODULE_SFF_8636_MAX_LEN 640 |
| 595 | #define ETH_MODULE_SFF_8436_MAX_LEN 640 |
| 596 | |
| 597 | #endif /* QSFP_H__ */ |