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gerrit-public.fairphone.software / platform / external / ethtool / refs/heads/int/11/fp3 / . / vmxnet3.c
blob: c97214511e93812dcb6aaf591eb7f9e3ddadeb59 [file] [log] [blame]
Shrikrishna Khare009799a2015-09-23 15:19:12 -0700[diff] [blame]1/* Copyright (c) 2015 VMware Inc.*/
2#include <stdio.h>
3#include "internal.h"
4
5int
Maciej Żenczykowskic1eaddf2019-10-17 11:21:03 -0700[diff] [blame]6vmxnet3_dump_regs(struct ethtool_drvinfo *info maybe_unused,
7 struct ethtool_regs *regs)
Shrikrishna Khare009799a2015-09-23 15:19:12 -0700[diff] [blame]8{
9 u32 *regs_buff = (u32 *)regs->data;
10 u32 version = regs->version;
11 int i = 0, j = 0, cnt;
12
13 if (version != 2)
14 return -1;
15
16 fprintf(stdout, "Control Registers\n");
17 fprintf(stdout, "=================\n");
18
19 fprintf(stdout,
20 " VRRS (Vmxnet3 Revision Report and Selection) 0x%x\n",
21 regs_buff[j++]);
22 fprintf(stdout,
23 " UVRS (UPT Version Report and Selection) 0x%x\n",
24 regs_buff[j++]);
25 fprintf(stdout,
26 " DSA (Driver Shared Address) 0x%08x%08x\n",
27 regs_buff[j+1], regs_buff[j]);
28 j += 2;
29 fprintf(stdout,
30 " CMD (Command Register) 0x%x\n",
31 regs_buff[j++]);
32 fprintf(stdout,
33 " MAC (Media Access Control address) %02x:%02x:%02x:%02x:%02x:%02x\n",
34 regs_buff[j] & 0xff,
35 (regs_buff[j] >> 8) & 0xff,
36 (regs_buff[j] >> 16) & 0xff,
37 (regs_buff[j] >> 24) & 0xff,
38 regs_buff[j + 1] & 0xff,
39 (regs_buff[j + 1] >> 8) & 0xff);
40 j += 2;
41 fprintf(stdout,
42 " ICR (Interrupt Cause Register) 0x%x\n",
43 regs_buff[j++]);
44 fprintf(stdout,
45 " ECR (Event Cause Register) 0x%x\n",
46 regs_buff[j++]);
47
48 fprintf(stdout, "Datapath Registers\n");
49 fprintf(stdout, "==================\n");
50
51 /* Interrupt Mask Registers */
52 cnt = regs_buff[j++];
53 for (i = 0; i < cnt; i++) {
54 fprintf(stdout,
55 " IMR (Interrupt Mask Register) %d 0x%x\n",
56 i, regs_buff[j++]);
57 }
58
59 /* Transmit Queue Registers */
60 cnt = regs_buff[j++];
61 for (i = 0; i < cnt; i++) {
62 fprintf(stdout, " Transmit Queue %d\n", i);
63 fprintf(stdout, " ----------------\n");
64 fprintf(stdout,
65 " TXPROD (Transmit Ring Producer Register) 0x%x\n",
66 regs_buff[j++]);
67 fprintf(stdout,
68 " Transmit Ring\n");
69 fprintf(stdout,
70 " Base Address 0x%08x%08x\n",
71 regs_buff[j+1], regs_buff[j]);
72 j += 2;
73 fprintf(stdout,
74 " Size %u\n",
75 regs_buff[j++]);
76 fprintf(stdout,
77 " next2fill %u\n",
78 regs_buff[j++]);
79 fprintf(stdout,
80 " next2comp %u\n",
81 regs_buff[j++]);
82 fprintf(stdout,
83 " gen %u\n",
84 regs_buff[j++]);
85
86 fprintf(stdout,
87 " Transmit Data Ring\n");
88 fprintf(stdout,
89 " Base Address 0x%08x%08x\n",
90 regs_buff[j+1], regs_buff[j]);
91 j += 2;
92 fprintf(stdout,
93 " Size %u\n",
94 regs_buff[j++]);
95 fprintf(stdout,
96 " Buffer Size %u\n",
97 regs_buff[j++]);
98
99 fprintf(stdout,
100 " Transmit Completion Ring\n");
101 fprintf(stdout,
102 " Base Address 0x%08x%08x\n",
103 regs_buff[j+1], regs_buff[j]);
104 j += 2;
105 fprintf(stdout,
106 " size %u\n",
107 regs_buff[j++]);
108 fprintf(stdout,
109 " next2proc %u\n",
110 regs_buff[j++]);
111 fprintf(stdout,
112 " gen %u\n",
113 regs_buff[j++]);
114 fprintf(stdout,
115 " stopped %u\n",
116 regs_buff[j++]);
117 }
118
119 /* Receive Queue Registers */
120 cnt = regs_buff[j++];
121 for (i = 0; i < cnt; i++) {
122 fprintf(stdout, " Receive Queue %d\n", i);
123 fprintf(stdout, " ----------------\n");
124 fprintf(stdout,
125 " RXPROD1 (Receive Ring Producer Register) 1 0x%x\n",
126 regs_buff[j++]);
127 fprintf(stdout,
128 " RXPROD2 (Receive Ring Producer Register) 2 0x%x\n",
129 regs_buff[j++]);
130 fprintf(stdout,
131 " Receive Ring 0\n");
132 fprintf(stdout,
133 " Base Address 0x%08x%08x\n",
134 regs_buff[j+1], regs_buff[j]);
135 j += 2;
136 fprintf(stdout,
137 " Size %u\n",
138 regs_buff[j++]);
139 fprintf(stdout,
140 " next2fill %u\n",
141 regs_buff[j++]);
142 fprintf(stdout,
143 " next2comp %u\n",
144 regs_buff[j++]);
145 fprintf(stdout,
146 " gen %u\n",
147 regs_buff[j++]);
148
149 fprintf(stdout,
150 " Receive Ring 1\n");
151 fprintf(stdout,
152 " Base Address 0x%08x%08x\n",
153 regs_buff[j+1], regs_buff[j]);
154 j += 2;
155 fprintf(stdout,
156 " Size %u\n",
157 regs_buff[j++]);
158 fprintf(stdout,
159 " next2fill %u\n",
160 regs_buff[j++]);
161 fprintf(stdout,
162 " next2comp %u\n",
163 regs_buff[j++]);
164 fprintf(stdout,
165 " gen %u\n",
166 regs_buff[j++]);
167
168 fprintf(stdout,
169 " Receive Data Ring\n");
170 fprintf(stdout,
171 " Base Address 0x%08x%08x\n",
172 regs_buff[j+1], regs_buff[j]);
173 j += 2;
174 fprintf(stdout,
175 " Size %u\n",
176 regs_buff[j++]);
177 fprintf(stdout,
178 " Buffer Size %u\n",
179 regs_buff[j++]);
180
181 fprintf(stdout,
182 " Receive Completion Ring\n");
183 fprintf(stdout,
184 " Base Address 0x%08x%08x\n",
185 regs_buff[j+1], regs_buff[j]);
186 j += 2;
187 fprintf(stdout,
188 " size %u\n",
189 regs_buff[j++]);
190 fprintf(stdout,
191 " next2proc %u\n",
192 regs_buff[j++]);
193 fprintf(stdout,
194 " gen %u\n",
195 regs_buff[j++]);
196 }
197
198 return 0;
199}