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gerrit-public.fairphone.software / platform / external / ethtool / refs/heads/int/13/fp4 / . / fec.c
blob: 22bc09f982a09023f0e5cb2768b57d97db26a36f [file] [log] [blame]
Vivien Didelot8612d8b2019-02-14 11:15:36 -0500[diff] [blame]1#include <stdio.h>
2#include <string.h>
3
4#include "internal.h"
5
6/* Macros and dump functions for the 32-bit "fec" driver registers */
7
8#define REG(_reg, _name, _val) \
9 printf("0x%.03x: %-44.44s 0x%.8x\n", _reg, _name, _val)
10
11#define FIELD(_name, _fmt, ...) \
12 printf(" %-47.47s " _fmt "\n", _name, ##__VA_ARGS__)
13
14static void fec_dump_reg_v1(int reg, u32 val)
15{
16 switch (reg) {
17 case 0x000: /* FEC_ECNTRL */
18 case 0x004: /* FEC_IEVENT */
19 case 0x008: /* FEC_IMASK */
20 case 0x00c: /* FEC_IVEC */
21 case 0x010: /* FEC_R_DES_ACTIVE_0 */
22 case 0x014: /* FEC_X_DES_ACTIVE_0 */
23 case 0x040: /* FEC_MII_DATA */
24 case 0x044: /* FEC_MII_SPEED */
25 case 0x08c: /* FEC_R_BOUND */
26 case 0x090: /* FEC_R_FSTART */
27 case 0x0a4: /* FEC_X_WMRK */
28 case 0x0ac: /* FEC_X_FSTART */
29 case 0x104: /* FEC_R_CNTRL */
30 case 0x108: /* FEC_MAX_FRM_LEN */
31 case 0x144: /* FEC_X_CNTRL */
32 case 0x3c0: /* FEC_ADDR_LOW */
33 case 0x3c4: /* FEC_ADDR_HIGH */
34 case 0x3c8: /* FEC_GRP_HASH_TABLE_HIGH */
35 case 0x3cc: /* FEC_GRP_HASH_TABLE_LOW */
36 case 0x3d0: /* FEC_R_DES_START_0 */
37 case 0x3d4: /* FEC_X_DES_START_0 */
38 case 0x3d8: /* FEC_R_BUFF_SIZE_0 */
39 REG(reg, "", val);
40 break;
41 }
42}
43
44static void fec_dump_reg_v2(int reg, u32 val)
45{
46 switch (reg) {
47 case 0x084: /* FEC_R_CNTRL */
48 REG(reg, "RCR (Receive Control Register)", val);
49 FIELD("MAX_FL (Maximum frame length)", "%u", (val & 0x07ff0000) >> 16);
50 FIELD("FCE (Flow control enable)", "%u", !!(val & 0x00000020));
51 FIELD("BC_REJ (Broadcast frame reject)", "%u", !!(val & 0x00000010));
52 FIELD("PROM (Promiscuous mode)", "%u", !!(val & 0x00000008));
53 FIELD("DRT (Disable receive on transmit)", "%u", !!(val & 0x00000002));
54 FIELD("LOOP (Internal loopback)", "%u", !!(val & 0x00000001));
55 break;
56 case 0x0c4: /* FEC_X_CNTRL */
57 REG(reg, "TCR (Transmit Control Register)", val);
58 FIELD("RFC_PAUSE (Receive frame control pause)", "%u", !!(val & 0x00000010));
59 FIELD("TFC_PAUSE (Transmit frame control pause)", "%u", !!(val & 0x00000008));
60 FIELD("FDEN (Full duplex enable)", "%u", !!(val & 0x00000004));
61 FIELD("HBC (Heartbeat control)", "%u", !!(val & 0x00000002));
62 FIELD("GTS (Graceful transmit stop)", "%u", !!(val & 0x00000001));
63 break;
64 case 0x118: /* FEC_HASH_TABLE_HIGH */
65 REG(reg, "IAUR (Individual Address Upper Register)", val);
66 FIELD("IADDR1", "0x%.16llx", (u64)((u64)val) << 32);
67 break;
68 case 0x11c: /* FEC_HASH_TABLE_LOW */
69 REG(reg, "IALR (Individual Address Lower Register)", val);
70 FIELD("IADDR2", "0x%.16x", val);
71 break;
72 case 0x120: /* FEC_GRP_HASH_TABLE_HIGH */
73 REG(reg, "GAUR (Group Address Upper Register)", val);
74 FIELD("GADDR1", "0x%.16llx", (u64)((u64)val) << 32);
75 break;
76 case 0x124: /* FEC_GRP_HASH_TABLE_LOW */
77 REG(reg, "GALR (Group Address Lower Register)", val);
78 FIELD("GADDR2", "0x%.16x", val);
79 break;
80 case 0x144: /* FEC_X_WMRK */
81 REG(reg, "TFWR (Transmit FIFO Watermark Register)", val);
82 FIELD("X_WMRK", "%s",
83 (val & 0x00000003) == 0x00000000 ? "64 bytes" :
84 (val & 0x00000003) == 0x00000002 ? "128 bytes" :
85 (val & 0x00000003) == 0x00000003 ? "192 bytes" : "?");
86 break;
87 case 0x14c: /* FEC_R_BOUND */
88 REG(reg, "FRBR (FIFO Receive Bound Register)", val);
89 FIELD("R_BOUND (Highest valid FIFO RAM address)", "0x%.2x", (val & 0x000003fc) >> 2);
90 break;
91 case 0x188: /* FEC_R_BUFF_SIZE_0 */
92 REG(reg, "EMRBR (Maximum Receive Buffer Size)", val);
93 FIELD("R_BUF_SIZE (Receive buffer size)", "%u", (val & 0x000007f0) >> 4);
94 break;
95 case 0x004: /* FEC_IEVENT */
96 case 0x008: /* FEC_IMASK */
97 case 0x010: /* FEC_R_DES_ACTIVE_0 */
98 case 0x014: /* FEC_X_DES_ACTIVE_0 */
99 case 0x024: /* FEC_ECNTRL */
100 case 0x040: /* FEC_MII_DATA */
101 case 0x044: /* FEC_MII_SPEED */
102 case 0x064: /* FEC_MIB_CTRLSTAT */
103 case 0x0e4: /* FEC_ADDR_LOW */
104 case 0x0e8: /* FEC_ADDR_HIGH */
105 case 0x0ec: /* FEC_OPD */
106 case 0x0f0: /* FEC_TXIC0 */
107 case 0x0f4: /* FEC_TXIC1 */
108 case 0x0f8: /* FEC_TXIC2 */
109 case 0x100: /* FEC_RXIC0 */
110 case 0x104: /* FEC_RXIC1 */
111 case 0x108: /* FEC_RXIC2 */
112 case 0x150: /* FEC_R_FSTART */
113 case 0x160: /* FEC_R_DES_START_1 */
114 case 0x164: /* FEC_X_DES_START_1 */
115 case 0x168: /* FEC_R_BUFF_SIZE_1 */
116 case 0x16c: /* FEC_R_DES_START_2 */
117 case 0x170: /* FEC_X_DES_START_2 */
118 case 0x174: /* FEC_R_BUFF_SIZE_2 */
119 case 0x180: /* FEC_R_DES_START_0 */
120 case 0x184: /* FEC_X_DES_START_0 */
121 case 0x190: /* FEC_R_FIFO_RSFL */
122 case 0x194: /* FEC_R_FIFO_RSEM */
123 case 0x198: /* FEC_R_FIFO_RAEM */
124 case 0x19c: /* FEC_R_FIFO_RAFL */
125 case 0x1c4: /* FEC_RACC */
126 case 0x1c8: /* FEC_RCMR_1 */
127 case 0x1cc: /* FEC_RCMR_2 */
128 case 0x1d8: /* FEC_DMA_CFG_1 */
129 case 0x1dc: /* FEC_DMA_CFG_2 */
130 case 0x1e0: /* FEC_R_DES_ACTIVE_1 */
131 case 0x1e4: /* FEC_X_DES_ACTIVE_1 */
132 case 0x1e8: /* FEC_R_DES_ACTIVE_2 */
133 case 0x1ec: /* FEC_X_DES_ACTIVE_2 */
134 case 0x1f0: /* FEC_QOS_SCHEME */
135 case 0x200: /* RMON_T_DROP */
136 case 0x204: /* RMON_T_PACKETS */
137 case 0x208: /* RMON_T_BC_PKT */
138 case 0x20c: /* RMON_T_MC_PKT */
139 case 0x210: /* RMON_T_CRC_ALIGN */
140 case 0x214: /* RMON_T_UNDERSIZE */
141 case 0x218: /* RMON_T_OVERSIZE */
142 case 0x21c: /* RMON_T_FRAG */
143 case 0x220: /* RMON_T_JAB */
144 case 0x224: /* RMON_T_COL */
145 case 0x228: /* RMON_T_P64 */
146 case 0x22c: /* RMON_T_P65TO127 */
147 case 0x230: /* RMON_T_P128TO255 */
148 case 0x234: /* RMON_T_P256TO511 */
149 case 0x238: /* RMON_T_P512TO1023 */
150 case 0x23c: /* RMON_T_P1024TO2047 */
151 case 0x240: /* RMON_T_P_GTE2048 */
152 case 0x244: /* RMON_T_OCTETS */
153 case 0x248: /* IEEE_T_DROP */
154 case 0x24c: /* IEEE_T_FRAME_OK */
155 case 0x250: /* IEEE_T_1COL */
156 case 0x254: /* IEEE_T_MCOL */
157 case 0x258: /* IEEE_T_DEF */
158 case 0x25c: /* IEEE_T_LCOL */
159 case 0x260: /* IEEE_T_EXCOL */
160 case 0x264: /* IEEE_T_MACERR */
161 case 0x268: /* IEEE_T_CSERR */
162 case 0x26c: /* IEEE_T_SQE */
163 case 0x270: /* IEEE_T_FDXFC */
164 case 0x274: /* IEEE_T_OCTETS_OK */
165 case 0x284: /* RMON_R_PACKETS */
166 case 0x288: /* RMON_R_BC_PKT */
167 case 0x28c: /* RMON_R_MC_PKT */
168 case 0x290: /* RMON_R_CRC_ALIGN */
169 case 0x294: /* RMON_R_UNDERSIZE */
170 case 0x298: /* RMON_R_OVERSIZE */
171 case 0x29c: /* RMON_R_FRAG */
172 case 0x2a0: /* RMON_R_JAB */
173 case 0x2a4: /* RMON_R_RESVD_O */
174 case 0x2a8: /* RMON_R_P64 */
175 case 0x2ac: /* RMON_R_P65TO127 */
176 case 0x2b0: /* RMON_R_P128TO255 */
177 case 0x2b4: /* RMON_R_P256TO511 */
178 case 0x2b8: /* RMON_R_P512TO1023 */
179 case 0x2bc: /* RMON_R_P1024TO2047 */
180 case 0x2c0: /* RMON_R_P_GTE2048 */
181 case 0x2c4: /* RMON_R_OCTETS */
182 case 0x2c8: /* IEEE_R_DROP */
183 case 0x2cc: /* IEEE_R_FRAME_OK */
184 case 0x2d0: /* IEEE_R_CRC */
185 case 0x2d4: /* IEEE_R_ALIGN */
186 case 0x2d8: /* IEEE_R_MACERR */
187 case 0x2dc: /* IEEE_R_FDXFC */
188 case 0x2e0: /* IEEE_R_OCTETS_OK */
189 REG(reg, "", val);
190 break;
191 }
192}
193
194#undef FIELD
195#undef REG
196
Maciej Żenczykowskif40d32d2019-10-17 11:21:15 -0700[diff] [blame]197int fec_dump_regs(struct ethtool_drvinfo *info maybe_unused,
198 struct ethtool_regs *regs)
Vivien Didelot8612d8b2019-02-14 11:15:36 -0500[diff] [blame]199{
200 const u32 *data = (u32 *)regs->data;
201 int offset;
202 u32 val;
203
204 for (offset = 0; offset < regs->len; offset += 4) {
205 val = data[offset / 4];
206
207 switch (regs->version) {
208 case 1:
209 fec_dump_reg_v1(offset, val);
210 break;
211 case 2:
212 fec_dump_reg_v2(offset, val);
213 break;
214 default:
215 return 1;
216 }
217 }
218
219 return 0;
220}