Jani Nikula | dfda0b6 | 2014-12-10 14:27:07 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006,2009,2015 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <errno.h> |
| 29 | #include <stdbool.h> |
| 30 | #include <stdint.h> |
| 31 | #include <stdio.h> |
| 32 | #include <stdlib.h> |
| 33 | #include <string.h> |
Derek Morton | 1b492e3 | 2015-10-01 16:09:02 +0100 | [diff] [blame^] | 34 | #include <strings.h> |
Jani Nikula | dfda0b6 | 2014-12-10 14:27:07 +0200 | [diff] [blame] | 35 | |
| 36 | #include "intel_chipset.h" |
| 37 | #include "intel_reg.h" |
| 38 | |
| 39 | #include "intel_reg_spec.h" |
| 40 | |
| 41 | #define _DEBUGSTRING(func) \ |
| 42 | void func(char *result, int len, int reg, uint32_t val, uint32_t devid) |
| 43 | #define DEBUGSTRING(func) static _DEBUGSTRING(func) |
| 44 | |
| 45 | DEBUGSTRING(i830_16bit_func) |
| 46 | { |
| 47 | snprintf(result, len, "0x%04x", (uint16_t) val); |
| 48 | } |
| 49 | |
| 50 | DEBUGSTRING(i830_debug_dcc) |
| 51 | { |
| 52 | const char *addressing = NULL; |
| 53 | |
| 54 | if (!IS_MOBILE(devid)) |
| 55 | return; |
| 56 | |
| 57 | if (IS_965(devid)) { |
| 58 | if (val & (1 << 1)) |
| 59 | addressing = "dual channel interleaved"; |
| 60 | else |
| 61 | addressing = "single or dual channel asymmetric"; |
| 62 | } else { |
| 63 | switch (val & 3) { |
| 64 | case 0: |
| 65 | addressing = "single channel"; |
| 66 | break; |
| 67 | case 1: |
| 68 | addressing = "dual channel asymmetric"; |
| 69 | break; |
| 70 | case 2: |
| 71 | addressing = "dual channel interleaved"; |
| 72 | break; |
| 73 | case 3: |
| 74 | addressing = "unknown channel layout"; |
| 75 | break; |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | snprintf(result, len, "%s, XOR randomization: %sabled, XOR bit: %d", |
| 80 | addressing, |
| 81 | (val & (1 << 10)) ? "dis" : "en", |
| 82 | (val & (1 << 9)) ? 17 : 11); |
| 83 | } |
| 84 | |
| 85 | DEBUGSTRING(i830_debug_chdecmisc) |
| 86 | { |
| 87 | const char *enhmodesel = NULL; |
| 88 | |
| 89 | switch ((val >> 5) & 3) { |
| 90 | case 1: |
| 91 | enhmodesel = "XOR bank/rank"; |
| 92 | break; |
| 93 | case 2: |
| 94 | enhmodesel = "swap bank"; |
| 95 | break; |
| 96 | case 3: |
| 97 | enhmodesel = "XOR bank"; |
| 98 | break; |
| 99 | case 0: |
| 100 | enhmodesel = "none"; |
| 101 | break; |
| 102 | } |
| 103 | |
| 104 | snprintf(result, len, |
| 105 | "%s, ch2 enh %sabled, ch1 enh %sabled, " |
| 106 | "ch0 enh %sabled, " |
| 107 | "flex %sabled, ep %spresent", enhmodesel, |
| 108 | (val & (1 << 4)) ? "en" : "dis", |
| 109 | (val & (1 << 3)) ? "en" : "dis", |
| 110 | (val & (1 << 2)) ? "en" : "dis", |
| 111 | (val & (1 << 1)) ? "en" : "dis", |
| 112 | (val & (1 << 0)) ? "" : "not "); |
| 113 | } |
| 114 | |
| 115 | DEBUGSTRING(i830_debug_xyminus1) |
| 116 | { |
| 117 | snprintf(result, len, "%d, %d", (val & 0xffff) + 1, |
| 118 | ((val & 0xffff0000) >> 16) + 1); |
| 119 | } |
| 120 | |
| 121 | DEBUGSTRING(i830_debug_yxminus1) |
| 122 | { |
| 123 | snprintf(result, len, "%d, %d", ((val & 0xffff0000) >> 16) + 1, |
| 124 | (val & 0xffff) + 1); |
| 125 | } |
| 126 | |
| 127 | DEBUGSTRING(i830_debug_xy) |
| 128 | { |
| 129 | snprintf(result, len, "%d, %d", (val & 0xffff), ((val & 0xffff0000) >> 16)); |
| 130 | } |
| 131 | |
| 132 | DEBUGSTRING(i830_debug_dspstride) |
| 133 | { |
| 134 | snprintf(result, len, "%d bytes", val); |
| 135 | } |
| 136 | |
| 137 | DEBUGSTRING(i830_debug_dspcntr) |
| 138 | { |
| 139 | const char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled"; |
| 140 | char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A'; |
| 141 | if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid)) |
| 142 | snprintf(result, len, "%s", enabled); |
| 143 | else |
| 144 | snprintf(result, len, "%s, pipe %c", enabled, plane); |
| 145 | } |
| 146 | |
| 147 | DEBUGSTRING(i830_debug_pipeconf) |
| 148 | { |
| 149 | const char *enabled = val & PIPEACONF_ENABLE ? "enabled" : "disabled"; |
| 150 | const char *bit30; |
| 151 | char buf[256]; |
| 152 | int buf_len; |
| 153 | |
| 154 | if (IS_965(devid)) |
| 155 | bit30 = val & I965_PIPECONF_ACTIVE ? "active" : "inactive"; |
| 156 | else |
| 157 | bit30 = |
| 158 | val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide"; |
| 159 | |
| 160 | buf_len = snprintf(buf, sizeof(buf), "%s, %s", enabled, bit30); |
| 161 | |
| 162 | if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid)) { |
| 163 | const char *interlace; |
| 164 | int interlace_mode; |
| 165 | |
| 166 | if ((IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || |
| 167 | IS_BROADWELL(devid) || IS_GEN9(devid))) |
| 168 | interlace_mode = (val >> 21) & 3; |
| 169 | else |
| 170 | interlace_mode = (val >> 21) & 7; |
| 171 | |
| 172 | switch (interlace_mode) { |
| 173 | case 0: |
| 174 | interlace = "pf-pd"; |
| 175 | break; |
| 176 | case 1: |
| 177 | interlace = "pf-id"; |
| 178 | break; |
| 179 | case 3: |
| 180 | interlace = "if-id"; |
| 181 | break; |
| 182 | case 4: |
| 183 | interlace = "if-id-dbl"; |
| 184 | break; |
| 185 | case 5: |
| 186 | interlace = "pf-id-dbl"; |
| 187 | break; |
| 188 | default: |
| 189 | interlace = "rsvd"; |
| 190 | break; |
| 191 | } |
| 192 | if (buf_len < sizeof(buf)) |
| 193 | buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, |
| 194 | ", %s", interlace); |
| 195 | } else if (IS_GEN4(devid) || IS_VALLEYVIEW(devid) || |
| 196 | IS_CHERRYVIEW(devid)) { |
| 197 | const char *interlace; |
| 198 | |
| 199 | switch ((val >> 21) & 7) { |
| 200 | case 0: |
| 201 | case 1: |
| 202 | case 2: |
| 203 | case 3: |
| 204 | interlace = "progressive"; |
| 205 | break; |
| 206 | case 4: |
| 207 | interlace = "interlaced embedded"; |
| 208 | break; |
| 209 | case 5: |
| 210 | interlace = "interlaced"; |
| 211 | break; |
| 212 | case 6: |
| 213 | interlace = "interlaced sdvo"; |
| 214 | break; |
| 215 | case 7: |
| 216 | interlace = "interlaced legacy"; |
| 217 | break; |
| 218 | } |
| 219 | if (buf_len < sizeof(buf)) |
| 220 | buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, |
| 221 | ", %s", interlace); |
| 222 | } |
| 223 | |
| 224 | if (IS_HASWELL(devid) || IS_IVYBRIDGE(devid) || |
| 225 | IS_GEN6(devid) || IS_GEN5(devid)) { |
| 226 | const char *rotation; |
| 227 | |
| 228 | switch ((val >> 14) & 3) { |
| 229 | case 0: |
| 230 | rotation = "rotate 0"; |
| 231 | break; |
| 232 | case 1: |
| 233 | rotation = "rotate 90"; |
| 234 | break; |
| 235 | case 2: |
| 236 | rotation = "rotate 180"; |
| 237 | break; |
| 238 | case 3: |
| 239 | rotation = "rotate 270"; |
| 240 | break; |
| 241 | } |
| 242 | if (buf_len < sizeof(buf)) |
| 243 | buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, |
| 244 | ", %s", rotation); |
| 245 | } |
| 246 | |
| 247 | if (IS_IVYBRIDGE(devid) || IS_GEN6(devid) || IS_GEN5(devid)) { |
| 248 | const char *bpc; |
| 249 | |
| 250 | switch (val & (7 << 5)) { |
| 251 | case PIPECONF_8BPP: |
| 252 | bpc = "8bpc"; |
| 253 | break; |
| 254 | case PIPECONF_10BPP: |
| 255 | bpc = "10bpc"; |
| 256 | break; |
| 257 | case PIPECONF_6BPP: |
| 258 | bpc = "6bpc"; |
| 259 | break; |
| 260 | case PIPECONF_12BPP: |
| 261 | bpc = "12bpc"; |
| 262 | break; |
| 263 | default: |
| 264 | bpc = "invalid bpc"; |
| 265 | break; |
| 266 | } |
| 267 | if (buf_len < sizeof(buf)) |
| 268 | buf_len += snprintf(&buf[buf_len], sizeof(buf) - buf_len, |
| 269 | ", %s", bpc); |
| 270 | } |
| 271 | |
| 272 | snprintf(result, len, "%s", buf); |
| 273 | } |
| 274 | |
| 275 | DEBUGSTRING(i830_debug_pipestat) |
| 276 | { |
| 277 | const char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : ""; |
| 278 | const char *_CRC_ERROR_ENABLE = |
| 279 | val & CRC_ERROR_ENABLE ? " CRC_ERROR_ENABLE" : ""; |
| 280 | const char *_CRC_DONE_ENABLE = |
| 281 | val & CRC_DONE_ENABLE ? " CRC_DONE_ENABLE" : ""; |
| 282 | const char *_GMBUS_EVENT_ENABLE = |
| 283 | val & GMBUS_EVENT_ENABLE ? " GMBUS_EVENT_ENABLE" : ""; |
| 284 | const char *_VSYNC_INT_ENABLE = |
| 285 | val & VSYNC_INT_ENABLE ? " VSYNC_INT_ENABLE" : ""; |
| 286 | const char *_DLINE_COMPARE_ENABLE = |
| 287 | val & DLINE_COMPARE_ENABLE ? " DLINE_COMPARE_ENABLE" : ""; |
| 288 | const char *_DPST_EVENT_ENABLE = |
| 289 | val & DPST_EVENT_ENABLE ? " DPST_EVENT_ENABLE" : ""; |
| 290 | const char *_LBLC_EVENT_ENABLE = |
| 291 | val & LBLC_EVENT_ENABLE ? " LBLC_EVENT_ENABLE" : ""; |
| 292 | const char *_OFIELD_INT_ENABLE = |
| 293 | val & OFIELD_INT_ENABLE ? " OFIELD_INT_ENABLE" : ""; |
| 294 | const char *_EFIELD_INT_ENABLE = |
| 295 | val & EFIELD_INT_ENABLE ? " EFIELD_INT_ENABLE" : ""; |
| 296 | const char *_SVBLANK_INT_ENABLE = |
| 297 | val & SVBLANK_INT_ENABLE ? " SVBLANK_INT_ENABLE" : ""; |
| 298 | const char *_VBLANK_INT_ENABLE = |
| 299 | val & VBLANK_INT_ENABLE ? " VBLANK_INT_ENABLE" : ""; |
| 300 | const char *_OREG_UPDATE_ENABLE = |
| 301 | val & OREG_UPDATE_ENABLE ? " OREG_UPDATE_ENABLE" : ""; |
| 302 | const char *_CRC_ERROR_INT_STATUS = |
| 303 | val & CRC_ERROR_INT_STATUS ? " CRC_ERROR_INT_STATUS" : ""; |
| 304 | const char *_CRC_DONE_INT_STATUS = |
| 305 | val & CRC_DONE_INT_STATUS ? " CRC_DONE_INT_STATUS" : ""; |
| 306 | const char *_GMBUS_INT_STATUS = |
| 307 | val & GMBUS_INT_STATUS ? " GMBUS_INT_STATUS" : ""; |
| 308 | const char *_VSYNC_INT_STATUS = |
| 309 | val & VSYNC_INT_STATUS ? " VSYNC_INT_STATUS" : ""; |
| 310 | const char *_DLINE_COMPARE_STATUS = |
| 311 | val & DLINE_COMPARE_STATUS ? " DLINE_COMPARE_STATUS" : ""; |
| 312 | const char *_DPST_EVENT_STATUS = |
| 313 | val & DPST_EVENT_STATUS ? " DPST_EVENT_STATUS" : ""; |
| 314 | const char *_LBLC_EVENT_STATUS = |
| 315 | val & LBLC_EVENT_STATUS ? " LBLC_EVENT_STATUS" : ""; |
| 316 | const char *_OFIELD_INT_STATUS = |
| 317 | val & OFIELD_INT_STATUS ? " OFIELD_INT_STATUS" : ""; |
| 318 | const char *_EFIELD_INT_STATUS = |
| 319 | val & EFIELD_INT_STATUS ? " EFIELD_INT_STATUS" : ""; |
| 320 | const char *_SVBLANK_INT_STATUS = |
| 321 | val & SVBLANK_INT_STATUS ? " SVBLANK_INT_STATUS" : ""; |
| 322 | const char *_VBLANK_INT_STATUS = |
| 323 | val & VBLANK_INT_STATUS ? " VBLANK_INT_STATUS" : ""; |
| 324 | const char *_OREG_UPDATE_STATUS = |
| 325 | val & OREG_UPDATE_STATUS ? " OREG_UPDATE_STATUS" : ""; |
| 326 | snprintf(result, len, |
| 327 | "status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
| 328 | _FIFO_UNDERRUN, |
| 329 | _CRC_ERROR_ENABLE, |
| 330 | _CRC_DONE_ENABLE, |
| 331 | _GMBUS_EVENT_ENABLE, |
| 332 | _VSYNC_INT_ENABLE, |
| 333 | _DLINE_COMPARE_ENABLE, |
| 334 | _DPST_EVENT_ENABLE, |
| 335 | _LBLC_EVENT_ENABLE, |
| 336 | _OFIELD_INT_ENABLE, |
| 337 | _EFIELD_INT_ENABLE, |
| 338 | _SVBLANK_INT_ENABLE, |
| 339 | _VBLANK_INT_ENABLE, |
| 340 | _OREG_UPDATE_ENABLE, |
| 341 | _CRC_ERROR_INT_STATUS, |
| 342 | _CRC_DONE_INT_STATUS, |
| 343 | _GMBUS_INT_STATUS, |
| 344 | _VSYNC_INT_STATUS, |
| 345 | _DLINE_COMPARE_STATUS, |
| 346 | _DPST_EVENT_STATUS, |
| 347 | _LBLC_EVENT_STATUS, |
| 348 | _OFIELD_INT_STATUS, |
| 349 | _EFIELD_INT_STATUS, |
| 350 | _SVBLANK_INT_STATUS, |
| 351 | _VBLANK_INT_STATUS, |
| 352 | _OREG_UPDATE_STATUS); |
| 353 | } |
| 354 | |
| 355 | DEBUGSTRING(ivb_debug_port) |
| 356 | { |
| 357 | const char *drrs = NULL; |
| 358 | switch (val & (2 << 30)) { |
| 359 | case PORT_DBG_DRRS_HW_STATE_OFF: |
| 360 | drrs = "off"; |
| 361 | break; |
| 362 | case PORT_DBG_DRRS_HW_STATE_LOW: |
| 363 | drrs = "low"; |
| 364 | break; |
| 365 | case PORT_DBG_DRRS_HW_STATE_HIGH: |
| 366 | drrs = "high"; |
| 367 | break; |
| 368 | } |
| 369 | snprintf(result, len, "HW DRRS %s", |
| 370 | drrs); |
| 371 | } |
| 372 | |
| 373 | DEBUGSTRING(i830_debug_hvtotal) |
| 374 | { |
| 375 | snprintf(result, len, "%d active, %d total", |
| 376 | (val & 0xffff) + 1, |
| 377 | ((val & 0xffff0000) >> 16) + 1); |
| 378 | } |
| 379 | |
| 380 | DEBUGSTRING(i830_debug_hvsyncblank) |
| 381 | { |
| 382 | snprintf(result, len, "%d start, %d end", |
| 383 | (val & 0xffff) + 1, |
| 384 | ((val & 0xffff0000) >> 16) + 1); |
| 385 | } |
| 386 | |
| 387 | DEBUGSTRING(i830_debug_vgacntrl) |
| 388 | { |
| 389 | snprintf(result, len, "%s", |
| 390 | val & VGA_DISP_DISABLE ? "disabled" : "enabled"); |
| 391 | } |
| 392 | |
| 393 | DEBUGSTRING(i830_debug_fp) |
| 394 | { |
| 395 | if (IS_IGD(devid)) { |
| 396 | snprintf(result, len, "n = %d, m1 = %d, m2 = %d", |
| 397 | ffs((val & FP_N_IGD_DIV_MASK) >> |
| 398 | FP_N_DIV_SHIFT) - 1, |
| 399 | ((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT), |
| 400 | ((val & FP_M2_IGD_DIV_MASK) >> |
| 401 | FP_M2_DIV_SHIFT)); |
| 402 | } |
| 403 | snprintf(result, len, "n = %d, m1 = %d, m2 = %d", |
| 404 | ((val & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT), |
| 405 | ((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT), |
| 406 | ((val & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT)); |
| 407 | } |
| 408 | |
| 409 | DEBUGSTRING(i830_debug_vga_pd) |
| 410 | { |
| 411 | int vga0_p1, vga0_p2, vga1_p1, vga1_p2; |
| 412 | |
| 413 | /* XXX: i9xx version */ |
| 414 | |
| 415 | if (val & VGA0_PD_P1_DIV_2) |
| 416 | vga0_p1 = 2; |
| 417 | else |
| 418 | vga0_p1 = ((val & VGA0_PD_P1_MASK) >> VGA0_PD_P1_SHIFT) + 2; |
| 419 | vga0_p2 = (val & VGA0_PD_P2_DIV_4) ? 4 : 2; |
| 420 | |
| 421 | if (val & VGA1_PD_P1_DIV_2) |
| 422 | vga1_p1 = 2; |
| 423 | else |
| 424 | vga1_p1 = ((val & VGA1_PD_P1_MASK) >> VGA1_PD_P1_SHIFT) + 2; |
| 425 | vga1_p2 = (val & VGA1_PD_P2_DIV_4) ? 4 : 2; |
| 426 | |
| 427 | snprintf(result, len, "vga0 p1 = %d, p2 = %d, vga1 p1 = %d, p2 = %d", |
| 428 | vga0_p1, vga0_p2, vga1_p1, vga1_p2); |
| 429 | } |
| 430 | |
| 431 | DEBUGSTRING(i830_debug_pp_status) |
| 432 | { |
| 433 | const char *status = val & PP_ON ? "on" : "off"; |
| 434 | const char *ready = val & PP_READY ? "ready" : "not ready"; |
| 435 | const char *seq = "unknown"; |
| 436 | |
| 437 | switch (val & PP_SEQUENCE_MASK) { |
| 438 | case PP_SEQUENCE_NONE: |
| 439 | seq = "idle"; |
| 440 | break; |
| 441 | case PP_SEQUENCE_ON: |
| 442 | seq = "on"; |
| 443 | break; |
| 444 | case PP_SEQUENCE_OFF: |
| 445 | seq = "off"; |
| 446 | break; |
| 447 | } |
| 448 | |
| 449 | snprintf(result, len, "%s, %s, sequencing %s", status, ready, seq); |
| 450 | } |
| 451 | |
| 452 | DEBUGSTRING(i830_debug_pp_control) |
| 453 | { |
| 454 | snprintf(result, len, "power target: %s", |
| 455 | val & POWER_TARGET_ON ? "on" : "off"); |
| 456 | } |
| 457 | |
| 458 | DEBUGSTRING(i830_debug_dpll) |
| 459 | { |
| 460 | const char *enabled = val & DPLL_VCO_ENABLE ? "enabled" : "disabled"; |
| 461 | const char *dvomode = val & DPLL_DVO_HIGH_SPEED ? "dvo" : "non-dvo"; |
| 462 | const char *vgamode = val & DPLL_VGA_MODE_DIS ? "" : ", VGA"; |
| 463 | const char *mode = "unknown"; |
| 464 | const char *clock = "unknown"; |
| 465 | const char *fpextra = val & DISPLAY_RATE_SELECT_FPA1 ? ", using FPx1!" : ""; |
| 466 | char sdvoextra[20]; |
| 467 | int p1 = 0, p2 = 0; |
| 468 | |
| 469 | if (IS_GEN2(devid)) { |
| 470 | #if 0 /* removed due to use of INREG */ |
| 471 | char is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B); |
| 472 | |
| 473 | if (is_lvds) { |
| 474 | mode = "LVDS"; |
| 475 | p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) |
| 476 | >> DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 477 | if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 478 | LVDS_CLKB_POWER_UP) |
| 479 | p2 = 7; |
| 480 | else |
| 481 | p2 = 14; |
| 482 | |
| 483 | } else { |
| 484 | mode = "DAC/serial"; |
| 485 | if (val & PLL_P1_DIVIDE_BY_TWO) { |
| 486 | p1 = 2; |
| 487 | } else { |
| 488 | /* Map the number in the field to (3, 33) */ |
| 489 | p1 = ((val & DPLL_FPA01_P1_POST_DIV_MASK_I830) |
| 490 | >> DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 491 | } |
| 492 | if (val & PLL_P2_DIVIDE_BY_4) |
| 493 | p2 = 4; |
| 494 | else |
| 495 | p2 = 2; |
| 496 | } |
| 497 | #endif |
| 498 | } else { |
| 499 | if (IS_IGD(devid)) { |
| 500 | p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> |
| 501 | DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); |
| 502 | } else { |
| 503 | p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> |
| 504 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 505 | } |
| 506 | switch (val & DPLL_MODE_MASK) { |
| 507 | case DPLLB_MODE_DAC_SERIAL: |
| 508 | mode = "DAC/serial"; |
| 509 | p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10; |
| 510 | break; |
| 511 | case DPLLB_MODE_LVDS: |
| 512 | mode = "LVDS"; |
| 513 | p2 = val & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14; |
| 514 | break; |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | switch (val & PLL_REF_INPUT_MASK) { |
| 519 | case PLL_REF_INPUT_DREFCLK: |
| 520 | clock = "default"; |
| 521 | break; |
| 522 | case PLL_REF_INPUT_TVCLKINA: |
| 523 | clock = "TV A"; |
| 524 | break; |
| 525 | case PLL_REF_INPUT_TVCLKINBC: |
| 526 | clock = "TV B/C"; |
| 527 | break; |
| 528 | case PLLB_REF_INPUT_SPREADSPECTRUMIN: |
| 529 | if (reg == DPLL_B) |
| 530 | clock = "spread spectrum"; |
| 531 | break; |
| 532 | } |
| 533 | |
| 534 | if (IS_945(devid)) { |
| 535 | sprintf(sdvoextra, ", SDVO mult %d", |
| 536 | (int)((val & SDVO_MULTIPLIER_MASK) >> |
| 537 | SDVO_MULTIPLIER_SHIFT_HIRES) + 1); |
| 538 | } else { |
| 539 | sdvoextra[0] = '\0'; |
| 540 | } |
| 541 | |
| 542 | snprintf(result, len, "%s, %s%s, %s clock, %s mode, p1 = %d, " |
| 543 | "p2 = %d%s%s", |
| 544 | enabled, dvomode, vgamode, clock, mode, p1, p2, |
| 545 | fpextra, sdvoextra); |
| 546 | } |
| 547 | |
| 548 | DEBUGSTRING(i830_debug_dpll_test) |
| 549 | { |
| 550 | const char *dpllandiv = val & DPLLA_TEST_N_BYPASS ? ", DPLLA N bypassed" : ""; |
| 551 | const char *dpllamdiv = val & DPLLA_TEST_M_BYPASS ? ", DPLLA M bypassed" : ""; |
| 552 | const char *dpllainput = val & DPLLA_INPUT_BUFFER_ENABLE ? |
| 553 | "" : ", DPLLA input buffer disabled"; |
| 554 | const char *dpllbndiv = val & DPLLB_TEST_N_BYPASS ? ", DPLLB N bypassed" : ""; |
| 555 | const char *dpllbmdiv = val & DPLLB_TEST_M_BYPASS ? ", DPLLB M bypassed" : ""; |
| 556 | const char *dpllbinput = val & DPLLB_INPUT_BUFFER_ENABLE ? |
| 557 | "" : ", DPLLB input buffer disabled"; |
| 558 | |
| 559 | snprintf(result, len, "%s%s%s%s%s%s", |
| 560 | dpllandiv, dpllamdiv, dpllainput, |
| 561 | dpllbndiv, dpllbmdiv, dpllbinput); |
| 562 | } |
| 563 | |
| 564 | DEBUGSTRING(i830_debug_adpa) |
| 565 | { |
| 566 | char disp_pipe = (val & ADPA_PIPE_B_SELECT) ? 'B' : 'A'; |
| 567 | const char *enable = (val & ADPA_DAC_ENABLE) ? "enabled" : "disabled"; |
| 568 | char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-'; |
| 569 | char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-'; |
| 570 | |
| 571 | if (HAS_CPT) |
| 572 | disp_pipe = val & (1<<29) ? 'B' : 'A'; |
| 573 | |
| 574 | if (HAS_PCH_SPLIT(devid)) |
| 575 | snprintf(result, len, "%s, transcoder %c, %chsync, %cvsync", |
| 576 | enable, disp_pipe, hsync, vsync); |
| 577 | else |
| 578 | snprintf(result, len, "%s, pipe %c, %chsync, %cvsync", |
| 579 | enable, disp_pipe, hsync, vsync); |
| 580 | } |
| 581 | |
| 582 | DEBUGSTRING(i830_debug_lvds) |
| 583 | { |
| 584 | char disp_pipe = val & LVDS_PIPEB_SELECT ? 'B' : 'A'; |
| 585 | const char *enable = val & LVDS_PORT_EN ? "enabled" : "disabled"; |
| 586 | int depth; |
| 587 | const char *channels; |
| 588 | |
| 589 | if ((val & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
| 590 | depth = 24; |
| 591 | else |
| 592 | depth = 18; |
| 593 | if ((val & LVDS_B0B3_POWER_MASK) == LVDS_B0B3_POWER_UP) |
| 594 | channels = "2 channels"; |
| 595 | else |
| 596 | channels = "1 channel"; |
| 597 | |
| 598 | if (HAS_CPT) |
| 599 | disp_pipe = val & (1<<29) ? 'B' : 'A'; |
| 600 | |
| 601 | snprintf(result, len, "%s, pipe %c, %d bit, %s", |
| 602 | enable, disp_pipe, depth, channels); |
| 603 | } |
| 604 | |
| 605 | DEBUGSTRING(i830_debug_dvo) |
| 606 | { |
| 607 | const char *enable = val & DVO_ENABLE ? "enabled" : "disabled"; |
| 608 | char disp_pipe = val & DVO_PIPE_B_SELECT ? 'B' : 'A'; |
| 609 | const char *stall; |
| 610 | char hsync = val & DVO_HSYNC_ACTIVE_HIGH ? '+' : '-'; |
| 611 | char vsync = val & DVO_VSYNC_ACTIVE_HIGH ? '+' : '-'; |
| 612 | |
| 613 | switch (val & DVO_PIPE_STALL_MASK) { |
| 614 | case DVO_PIPE_STALL_UNUSED: |
| 615 | stall = "no stall"; |
| 616 | break; |
| 617 | case DVO_PIPE_STALL: |
| 618 | stall = "stall"; |
| 619 | break; |
| 620 | case DVO_PIPE_STALL_TV: |
| 621 | stall = "TV stall"; |
| 622 | break; |
| 623 | default: |
| 624 | stall = "unknown stall"; |
| 625 | break; |
| 626 | } |
| 627 | |
| 628 | snprintf(result, len, "%s, pipe %c, %s, %chsync, %cvsync", |
| 629 | enable, disp_pipe, stall, hsync, vsync); |
| 630 | } |
| 631 | |
| 632 | DEBUGSTRING(i830_debug_sdvo) |
| 633 | { |
| 634 | const char *enable = val & SDVO_ENABLE ? "enabled" : "disabled"; |
| 635 | char disp_pipe = val & SDVO_PIPE_B_SELECT ? 'B' : 'A'; |
| 636 | const char *stall = val & SDVO_STALL_SELECT ? "enabled" : "disabled"; |
| 637 | const char *detected = val & SDVO_DETECTED ? "" : "not "; |
| 638 | const char *gang = val & SDVOC_GANG_MODE ? ", gang mode" : ""; |
| 639 | char sdvoextra[20]; |
| 640 | |
| 641 | if (IS_915(devid)) { |
| 642 | sprintf(sdvoextra, ", SDVO mult %d", |
| 643 | (int)((val & SDVO_PORT_MULTIPLY_MASK) >> |
| 644 | SDVO_PORT_MULTIPLY_SHIFT) + 1); |
| 645 | } else { |
| 646 | sdvoextra[0] = '\0'; |
| 647 | } |
| 648 | |
| 649 | snprintf(result, len, "%s, pipe %c, stall %s, %sdetected%s%s", |
| 650 | enable, disp_pipe, stall, detected, sdvoextra, gang); |
| 651 | } |
| 652 | |
| 653 | DEBUGSTRING(i830_debug_dspclk_gate_d) |
| 654 | { |
| 655 | const char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : ""; |
| 656 | const char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : ""; |
| 657 | const char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : ""; |
| 658 | const char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : ""; |
| 659 | const char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : ""; |
| 660 | const char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : ""; |
| 661 | const char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : ""; |
| 662 | const char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : ""; |
| 663 | const char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : ""; |
| 664 | const char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : ""; |
| 665 | const char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : ""; |
| 666 | const char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : ""; |
| 667 | const char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : ""; |
| 668 | const char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : ""; |
| 669 | const char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : ""; |
| 670 | const char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : ""; |
| 671 | const char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : ""; |
| 672 | const char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : ""; |
| 673 | const char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : ""; |
| 674 | const char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : ""; |
| 675 | const char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : ""; |
| 676 | const char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : ""; |
| 677 | const char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : ""; |
| 678 | const char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : ""; |
| 679 | const char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : ""; |
| 680 | const char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : ""; |
| 681 | const char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : ""; |
| 682 | const char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : ""; |
| 683 | const char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : ""; |
| 684 | const char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : ""; |
| 685 | const char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : ""; |
| 686 | const char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : ""; |
| 687 | |
| 688 | snprintf(result, len, |
| 689 | "clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
| 690 | DPUNIT_B, VSUNIT, VRHUNIT, VRDUNIT, AUDUNIT, DPUNIT_A, DPCUNIT, |
| 691 | TVRUNIT, TVCUNIT, TVFUNIT, TVEUNIT, DVSUNIT, DSSUNIT, DDBUNIT, |
| 692 | DPRUNIT, DPFUNIT, DPBMUNIT, DPLSUNIT, DPLUNIT, DPOUNIT, DPBUNIT, |
| 693 | DCUNIT, DPUNIT, VRUNIT, OVHUNIT, DPIOUNIT, OVFUNIT, OVBUNIT, |
| 694 | OVRUNIT, OVCUNIT, OVUUNIT, OVLUNIT); |
| 695 | } |
| 696 | |
| 697 | DEBUGSTRING(i810_debug_915_fence) |
| 698 | { |
| 699 | char format = (val & 1 << 12) ? 'Y' : 'X'; |
| 700 | int pitch = 128 << ((val & 0x70) >> 4); |
| 701 | unsigned int offset = val & 0x0ff00000; |
| 702 | int size = (1024 * 1024) << ((val & 0x700) >> 8); |
| 703 | |
| 704 | if (IS_965(devid) || (IS_915(devid) && reg >= FENCE_NEW)) |
| 705 | return; |
| 706 | |
| 707 | if (format == 'X') |
| 708 | pitch *= 4; |
| 709 | if (val & 1) { |
| 710 | snprintf(result, len, "enabled, %c tiled, %4d pitch, 0x%08x - 0x%08x (%dkb)", |
| 711 | format, pitch, offset, offset + size, |
| 712 | size / 1024); |
| 713 | } else { |
| 714 | snprintf(result, len, "disabled"); |
| 715 | } |
| 716 | } |
| 717 | |
| 718 | DEBUGSTRING(i810_debug_965_fence_start) |
| 719 | { |
| 720 | const char *enable = (val & FENCE_VALID) ? " enabled" : "disabled"; |
| 721 | char format = (val & I965_FENCE_Y_MAJOR) ? 'Y' : 'X'; |
| 722 | int pitch = ((val & 0xffc) >> 2) * 128 + 128; |
| 723 | unsigned int offset = val & 0xfffff000; |
| 724 | |
| 725 | if (!IS_965(devid)) |
| 726 | return; |
| 727 | |
| 728 | snprintf(result, len, "%s, %c tile walk, %4d pitch, 0x%08x start", |
| 729 | enable, format, pitch, offset); |
| 730 | } |
| 731 | |
| 732 | DEBUGSTRING(i810_debug_965_fence_end) |
| 733 | { |
| 734 | unsigned int end = val & 0xfffff000; |
| 735 | |
| 736 | if (!IS_965(devid)) |
| 737 | return; |
| 738 | |
| 739 | snprintf(result, len, " 0x%08x end", end); |
| 740 | } |
| 741 | |
| 742 | #define DEFINEREG(reg) \ |
| 743 | { reg, #reg, NULL } |
| 744 | #define DEFINEREG_16BIT(reg) \ |
| 745 | { reg, #reg, i830_16bit_func } |
| 746 | #define DEFINEREG2(reg, func) \ |
| 747 | { reg, #reg, func } |
| 748 | |
| 749 | struct reg_debug { |
| 750 | int reg; |
| 751 | const char *name; |
| 752 | _DEBUGSTRING((*debug_output)); |
| 753 | }; |
| 754 | |
| 755 | static const struct reg_debug intel_debug_regs[] = { |
| 756 | DEFINEREG2(DCC, i830_debug_dcc), |
| 757 | DEFINEREG2(CHDECMISC, i830_debug_chdecmisc), |
| 758 | DEFINEREG_16BIT(C0DRB0), |
| 759 | DEFINEREG_16BIT(C0DRB1), |
| 760 | DEFINEREG_16BIT(C0DRB2), |
| 761 | DEFINEREG_16BIT(C0DRB3), |
| 762 | DEFINEREG_16BIT(C1DRB0), |
| 763 | DEFINEREG_16BIT(C1DRB1), |
| 764 | DEFINEREG_16BIT(C1DRB2), |
| 765 | DEFINEREG_16BIT(C1DRB3), |
| 766 | DEFINEREG_16BIT(C0DRA01), |
| 767 | DEFINEREG_16BIT(C0DRA23), |
| 768 | DEFINEREG_16BIT(C1DRA01), |
| 769 | DEFINEREG_16BIT(C1DRA23), |
| 770 | |
| 771 | DEFINEREG(PGETBL_CTL), |
| 772 | |
| 773 | DEFINEREG2(VCLK_DIVISOR_VGA0, i830_debug_fp), |
| 774 | DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp), |
| 775 | DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd), |
| 776 | DEFINEREG2(DPLL_TEST, i830_debug_dpll_test), |
| 777 | DEFINEREG(CACHE_MODE_0), |
| 778 | DEFINEREG(D_STATE), |
| 779 | DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d), |
| 780 | DEFINEREG(RENCLK_GATE_D1), |
| 781 | DEFINEREG(RENCLK_GATE_D2), |
| 782 | /* DEFINEREG(RAMCLK_GATE_D), CRL only */ |
| 783 | DEFINEREG2(SDVOB, i830_debug_sdvo), |
| 784 | DEFINEREG2(SDVOC, i830_debug_sdvo), |
| 785 | /* DEFINEREG(UDIB_SVB_SHB_CODES), CRL only */ |
| 786 | /* DEFINEREG(UDIB_SHA_BLANK_CODES), CRL only */ |
| 787 | DEFINEREG(SDVOUDI), |
| 788 | DEFINEREG(DSPARB), |
| 789 | DEFINEREG(FW_BLC), |
| 790 | DEFINEREG(FW_BLC2), |
| 791 | DEFINEREG(FW_BLC_SELF), |
| 792 | DEFINEREG(DSPFW1), |
| 793 | DEFINEREG(DSPFW2), |
| 794 | DEFINEREG(DSPFW3), |
| 795 | |
| 796 | DEFINEREG2(ADPA, i830_debug_adpa), |
| 797 | DEFINEREG2(LVDS, i830_debug_lvds), |
| 798 | DEFINEREG2(DVOA, i830_debug_dvo), |
| 799 | DEFINEREG2(DVOB, i830_debug_dvo), |
| 800 | DEFINEREG2(DVOC, i830_debug_dvo), |
| 801 | DEFINEREG(DVOA_SRCDIM), |
| 802 | DEFINEREG(DVOB_SRCDIM), |
| 803 | DEFINEREG(DVOC_SRCDIM), |
| 804 | |
| 805 | DEFINEREG(BLC_PWM_CTL), |
| 806 | DEFINEREG(BLC_PWM_CTL2), |
| 807 | |
| 808 | DEFINEREG2(PP_CONTROL, i830_debug_pp_control), |
| 809 | DEFINEREG2(PP_STATUS, i830_debug_pp_status), |
| 810 | DEFINEREG(PP_ON_DELAYS), |
| 811 | DEFINEREG(PP_OFF_DELAYS), |
| 812 | DEFINEREG(PP_DIVISOR), |
| 813 | DEFINEREG(PFIT_CONTROL), |
| 814 | DEFINEREG(PFIT_PGM_RATIOS), |
| 815 | DEFINEREG(PORT_HOTPLUG_EN), |
| 816 | DEFINEREG(PORT_HOTPLUG_STAT), |
| 817 | |
| 818 | DEFINEREG2(DSPACNTR, i830_debug_dspcntr), |
| 819 | DEFINEREG2(DSPASTRIDE, i830_debug_dspstride), |
| 820 | DEFINEREG2(DSPAPOS, i830_debug_xy), |
| 821 | DEFINEREG2(DSPASIZE, i830_debug_xyminus1), |
| 822 | DEFINEREG(DSPABASE), |
| 823 | DEFINEREG(DSPASURF), |
| 824 | DEFINEREG(DSPATILEOFF), |
| 825 | DEFINEREG2(PIPEACONF, i830_debug_pipeconf), |
| 826 | DEFINEREG2(PIPEASRC, i830_debug_yxminus1), |
| 827 | DEFINEREG2(PIPEASTAT, i830_debug_pipestat), |
| 828 | DEFINEREG(PIPEA_GMCH_DATA_M), |
| 829 | DEFINEREG(PIPEA_GMCH_DATA_N), |
| 830 | DEFINEREG(PIPEA_DP_LINK_M), |
| 831 | DEFINEREG(PIPEA_DP_LINK_N), |
| 832 | DEFINEREG(CURSOR_A_BASE), |
| 833 | DEFINEREG(CURSOR_A_CONTROL), |
| 834 | DEFINEREG(CURSOR_A_POSITION), |
| 835 | |
| 836 | DEFINEREG2(FPA0, i830_debug_fp), |
| 837 | DEFINEREG2(FPA1, i830_debug_fp), |
| 838 | DEFINEREG2(DPLL_A, i830_debug_dpll), |
| 839 | DEFINEREG(DPLL_A_MD), |
| 840 | DEFINEREG2(HTOTAL_A, i830_debug_hvtotal), |
| 841 | DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank), |
| 842 | DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank), |
| 843 | DEFINEREG2(VTOTAL_A, i830_debug_hvtotal), |
| 844 | DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank), |
| 845 | DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank), |
| 846 | DEFINEREG(BCLRPAT_A), |
| 847 | DEFINEREG(VSYNCSHIFT_A), |
| 848 | |
| 849 | DEFINEREG2(DSPBCNTR, i830_debug_dspcntr), |
| 850 | DEFINEREG2(DSPBSTRIDE, i830_debug_dspstride), |
| 851 | DEFINEREG2(DSPBPOS, i830_debug_xy), |
| 852 | DEFINEREG2(DSPBSIZE, i830_debug_xyminus1), |
| 853 | DEFINEREG(DSPBBASE), |
| 854 | DEFINEREG(DSPBSURF), |
| 855 | DEFINEREG(DSPBTILEOFF), |
| 856 | DEFINEREG2(PIPEBCONF, i830_debug_pipeconf), |
| 857 | DEFINEREG2(PIPEBSRC, i830_debug_yxminus1), |
| 858 | DEFINEREG2(PIPEBSTAT, i830_debug_pipestat), |
| 859 | DEFINEREG(PIPEB_GMCH_DATA_M), |
| 860 | DEFINEREG(PIPEB_GMCH_DATA_N), |
| 861 | DEFINEREG(PIPEB_DP_LINK_M), |
| 862 | DEFINEREG(PIPEB_DP_LINK_N), |
| 863 | DEFINEREG(CURSOR_B_BASE), |
| 864 | DEFINEREG(CURSOR_B_CONTROL), |
| 865 | DEFINEREG(CURSOR_B_POSITION), |
| 866 | |
| 867 | DEFINEREG2(FPB0, i830_debug_fp), |
| 868 | DEFINEREG2(FPB1, i830_debug_fp), |
| 869 | DEFINEREG2(DPLL_B, i830_debug_dpll), |
| 870 | DEFINEREG(DPLL_B_MD), |
| 871 | DEFINEREG2(HTOTAL_B, i830_debug_hvtotal), |
| 872 | DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank), |
| 873 | DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank), |
| 874 | DEFINEREG2(VTOTAL_B, i830_debug_hvtotal), |
| 875 | DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank), |
| 876 | DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank), |
| 877 | DEFINEREG(BCLRPAT_B), |
| 878 | DEFINEREG(VSYNCSHIFT_B), |
| 879 | |
| 880 | DEFINEREG(VCLK_DIVISOR_VGA0), |
| 881 | DEFINEREG(VCLK_DIVISOR_VGA1), |
| 882 | DEFINEREG(VCLK_POST_DIV), |
| 883 | DEFINEREG2(VGACNTRL, i830_debug_vgacntrl), |
| 884 | |
| 885 | DEFINEREG(TV_CTL), |
| 886 | DEFINEREG(TV_DAC), |
| 887 | DEFINEREG(TV_CSC_Y), |
| 888 | DEFINEREG(TV_CSC_Y2), |
| 889 | DEFINEREG(TV_CSC_U), |
| 890 | DEFINEREG(TV_CSC_U2), |
| 891 | DEFINEREG(TV_CSC_V), |
| 892 | DEFINEREG(TV_CSC_V2), |
| 893 | DEFINEREG(TV_CLR_KNOBS), |
| 894 | DEFINEREG(TV_CLR_LEVEL), |
| 895 | DEFINEREG(TV_H_CTL_1), |
| 896 | DEFINEREG(TV_H_CTL_2), |
| 897 | DEFINEREG(TV_H_CTL_3), |
| 898 | DEFINEREG(TV_V_CTL_1), |
| 899 | DEFINEREG(TV_V_CTL_2), |
| 900 | DEFINEREG(TV_V_CTL_3), |
| 901 | DEFINEREG(TV_V_CTL_4), |
| 902 | DEFINEREG(TV_V_CTL_5), |
| 903 | DEFINEREG(TV_V_CTL_6), |
| 904 | DEFINEREG(TV_V_CTL_7), |
| 905 | DEFINEREG(TV_SC_CTL_1), |
| 906 | DEFINEREG(TV_SC_CTL_2), |
| 907 | DEFINEREG(TV_SC_CTL_3), |
| 908 | DEFINEREG(TV_WIN_POS), |
| 909 | DEFINEREG(TV_WIN_SIZE), |
| 910 | DEFINEREG(TV_FILTER_CTL_1), |
| 911 | DEFINEREG(TV_FILTER_CTL_2), |
| 912 | DEFINEREG(TV_FILTER_CTL_3), |
| 913 | DEFINEREG(TV_CC_CONTROL), |
| 914 | DEFINEREG(TV_CC_DATA), |
| 915 | DEFINEREG(TV_H_LUMA_0), |
| 916 | DEFINEREG(TV_H_LUMA_59), |
| 917 | DEFINEREG(TV_H_CHROMA_0), |
| 918 | DEFINEREG(TV_H_CHROMA_59), |
| 919 | |
| 920 | DEFINEREG(FBC_CFB_BASE), |
| 921 | DEFINEREG(FBC_LL_BASE), |
| 922 | DEFINEREG(FBC_CONTROL), |
| 923 | DEFINEREG(FBC_COMMAND), |
| 924 | DEFINEREG(FBC_STATUS), |
| 925 | DEFINEREG(FBC_CONTROL2), |
| 926 | DEFINEREG(FBC_FENCE_OFF), |
| 927 | DEFINEREG(FBC_MOD_NUM), |
| 928 | |
| 929 | DEFINEREG(MI_MODE), |
| 930 | /* DEFINEREG(MI_DISPLAY_POWER_DOWN), CRL only */ |
| 931 | DEFINEREG(MI_ARB_STATE), |
| 932 | DEFINEREG(MI_RDRET_STATE), |
| 933 | DEFINEREG(ECOSKPD), |
| 934 | |
| 935 | DEFINEREG(DP_B), |
| 936 | DEFINEREG(DPB_AUX_CH_CTL), |
| 937 | DEFINEREG(DPB_AUX_CH_DATA1), |
| 938 | DEFINEREG(DPB_AUX_CH_DATA2), |
| 939 | DEFINEREG(DPB_AUX_CH_DATA3), |
| 940 | DEFINEREG(DPB_AUX_CH_DATA4), |
| 941 | DEFINEREG(DPB_AUX_CH_DATA5), |
| 942 | |
| 943 | DEFINEREG(DP_C), |
| 944 | DEFINEREG(DPC_AUX_CH_CTL), |
| 945 | DEFINEREG(DPC_AUX_CH_DATA1), |
| 946 | DEFINEREG(DPC_AUX_CH_DATA2), |
| 947 | DEFINEREG(DPC_AUX_CH_DATA3), |
| 948 | DEFINEREG(DPC_AUX_CH_DATA4), |
| 949 | DEFINEREG(DPC_AUX_CH_DATA5), |
| 950 | |
| 951 | DEFINEREG(DP_D), |
| 952 | DEFINEREG(DPD_AUX_CH_CTL), |
| 953 | DEFINEREG(DPD_AUX_CH_DATA1), |
| 954 | DEFINEREG(DPD_AUX_CH_DATA2), |
| 955 | DEFINEREG(DPD_AUX_CH_DATA3), |
| 956 | DEFINEREG(DPD_AUX_CH_DATA4), |
| 957 | DEFINEREG(DPD_AUX_CH_DATA5), |
| 958 | |
| 959 | DEFINEREG(AUD_CONFIG), |
| 960 | DEFINEREG(AUD_HDMIW_STATUS), |
| 961 | DEFINEREG(AUD_CONV_CHCNT), |
| 962 | DEFINEREG(VIDEO_DIP_CTL), |
| 963 | DEFINEREG(AUD_PINW_CNTR), |
| 964 | DEFINEREG(AUD_CNTL_ST), |
| 965 | DEFINEREG(AUD_PIN_CAP), |
| 966 | DEFINEREG(AUD_PINW_CAP), |
| 967 | DEFINEREG(AUD_PINW_UNSOLRESP), |
| 968 | DEFINEREG(AUD_OUT_DIG_CNVT), |
| 969 | DEFINEREG(AUD_OUT_CWCAP), |
| 970 | DEFINEREG(AUD_GRP_CAP), |
| 971 | |
| 972 | #define DEFINEFENCE_915(i) \ |
| 973 | { FENCE+i*4, "FENCE " #i, i810_debug_915_fence } |
| 974 | #define DEFINEFENCE_945(i) \ |
| 975 | { FENCE_NEW+(i - 8) * 4, "FENCE " #i, i810_debug_915_fence } |
| 976 | |
| 977 | DEFINEFENCE_915(0), |
| 978 | DEFINEFENCE_915(1), |
| 979 | DEFINEFENCE_915(2), |
| 980 | DEFINEFENCE_915(3), |
| 981 | DEFINEFENCE_915(4), |
| 982 | DEFINEFENCE_915(5), |
| 983 | DEFINEFENCE_915(6), |
| 984 | DEFINEFENCE_915(7), |
| 985 | DEFINEFENCE_945(8), |
| 986 | DEFINEFENCE_945(9), |
| 987 | DEFINEFENCE_945(10), |
| 988 | DEFINEFENCE_945(11), |
| 989 | DEFINEFENCE_945(12), |
| 990 | DEFINEFENCE_945(13), |
| 991 | DEFINEFENCE_945(14), |
| 992 | DEFINEFENCE_945(15), |
| 993 | |
| 994 | #define DEFINEFENCE_965(i) \ |
| 995 | { FENCE_NEW+i*8, "FENCE START " #i, i810_debug_965_fence_start }, \ |
| 996 | { FENCE_NEW+i*8+4, "FENCE END " #i, i810_debug_965_fence_end } |
| 997 | |
| 998 | DEFINEFENCE_965(0), |
| 999 | DEFINEFENCE_965(1), |
| 1000 | DEFINEFENCE_965(2), |
| 1001 | DEFINEFENCE_965(3), |
| 1002 | DEFINEFENCE_965(4), |
| 1003 | DEFINEFENCE_965(5), |
| 1004 | DEFINEFENCE_965(6), |
| 1005 | DEFINEFENCE_965(7), |
| 1006 | DEFINEFENCE_965(8), |
| 1007 | DEFINEFENCE_965(9), |
| 1008 | DEFINEFENCE_965(10), |
| 1009 | DEFINEFENCE_965(11), |
| 1010 | DEFINEFENCE_965(12), |
| 1011 | DEFINEFENCE_965(13), |
| 1012 | DEFINEFENCE_965(14), |
| 1013 | DEFINEFENCE_965(15), |
| 1014 | |
| 1015 | DEFINEREG(INST_PM), |
| 1016 | }; |
| 1017 | |
| 1018 | DEBUGSTRING(ironlake_debug_rr_hw_ctl) |
| 1019 | { |
| 1020 | snprintf(result, len, "low %d, high %d", val & RR_HW_LOW_POWER_FRAMES_MASK, |
| 1021 | (val & RR_HW_HIGH_POWER_FRAMES_MASK) >> 8); |
| 1022 | } |
| 1023 | |
| 1024 | DEBUGSTRING(ironlake_debug_m_tu) |
| 1025 | { |
| 1026 | snprintf(result, len, "TU %d, val 0x%x %d", (val >> 25) + 1, val & 0xffffff, |
| 1027 | val & 0xffffff); |
| 1028 | } |
| 1029 | |
| 1030 | DEBUGSTRING(ironlake_debug_n) |
| 1031 | { |
| 1032 | snprintf(result, len, "val 0x%x %d", val & 0xffffff, val & 0xffffff); |
| 1033 | } |
| 1034 | |
| 1035 | DEBUGSTRING(ironlake_debug_fdi_tx_ctl) |
| 1036 | { |
| 1037 | const char *train = NULL, *voltage = NULL, *pre_emphasis = NULL, *portw = |
| 1038 | NULL; |
| 1039 | |
| 1040 | switch (val & FDI_LINK_TRAIN_NONE) { |
| 1041 | case FDI_LINK_TRAIN_PATTERN_1: |
| 1042 | train = "pattern_1"; |
| 1043 | break; |
| 1044 | case FDI_LINK_TRAIN_PATTERN_2: |
| 1045 | train = "pattern_2"; |
| 1046 | break; |
| 1047 | case FDI_LINK_TRAIN_PATTERN_IDLE: |
| 1048 | train = "pattern_idle"; |
| 1049 | break; |
| 1050 | case FDI_LINK_TRAIN_NONE: |
| 1051 | train = "not train"; |
| 1052 | break; |
| 1053 | } |
| 1054 | |
| 1055 | if (HAS_CPT) { |
| 1056 | /* SNB B0 */ |
| 1057 | switch (val & (0x3f << 22)) { |
| 1058 | case FDI_LINK_TRAIN_400MV_0DB_SNB_B: |
| 1059 | voltage = "0.4V"; |
| 1060 | pre_emphasis = "0dB"; |
| 1061 | break; |
| 1062 | case FDI_LINK_TRAIN_400MV_6DB_SNB_B: |
| 1063 | voltage = "0.4V"; |
| 1064 | pre_emphasis = "6dB"; |
| 1065 | break; |
| 1066 | case FDI_LINK_TRAIN_600MV_3_5DB_SNB_B: |
| 1067 | voltage = "0.6V"; |
| 1068 | pre_emphasis = "3.5dB"; |
| 1069 | break; |
| 1070 | case FDI_LINK_TRAIN_800MV_0DB_SNB_B: |
| 1071 | voltage = "0.8V"; |
| 1072 | pre_emphasis = "0dB"; |
| 1073 | break; |
| 1074 | } |
| 1075 | |
| 1076 | } else { |
| 1077 | |
| 1078 | switch (val & (7 << 25)) { |
| 1079 | case FDI_LINK_TRAIN_VOLTAGE_0_4V: |
| 1080 | voltage = "0.4V"; |
| 1081 | break; |
| 1082 | case FDI_LINK_TRAIN_VOLTAGE_0_6V: |
| 1083 | voltage = "0.6V"; |
| 1084 | break; |
| 1085 | case FDI_LINK_TRAIN_VOLTAGE_0_8V: |
| 1086 | voltage = "0.8V"; |
| 1087 | break; |
| 1088 | case FDI_LINK_TRAIN_VOLTAGE_1_2V: |
| 1089 | voltage = "1.2V"; |
| 1090 | break; |
| 1091 | default: |
| 1092 | voltage = "reserved"; |
| 1093 | } |
| 1094 | |
| 1095 | switch (val & (7 << 22)) { |
| 1096 | case FDI_LINK_TRAIN_PRE_EMPHASIS_NONE: |
| 1097 | pre_emphasis = "none"; |
| 1098 | break; |
| 1099 | case FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X: |
| 1100 | pre_emphasis = "1.5x"; |
| 1101 | break; |
| 1102 | case FDI_LINK_TRAIN_PRE_EMPHASIS_2X: |
| 1103 | pre_emphasis = "2x"; |
| 1104 | break; |
| 1105 | case FDI_LINK_TRAIN_PRE_EMPHASIS_3X: |
| 1106 | pre_emphasis = "3x"; |
| 1107 | break; |
| 1108 | default: |
| 1109 | pre_emphasis = "reserved"; |
| 1110 | } |
| 1111 | |
| 1112 | } |
| 1113 | |
| 1114 | switch (val & (7 << 19)) { |
| 1115 | case FDI_DP_PORT_WIDTH_X1: |
| 1116 | portw = "X1"; |
| 1117 | break; |
| 1118 | case FDI_DP_PORT_WIDTH_X2: |
| 1119 | portw = "X2"; |
| 1120 | break; |
| 1121 | case FDI_DP_PORT_WIDTH_X3: |
| 1122 | portw = "X3"; |
| 1123 | break; |
| 1124 | case FDI_DP_PORT_WIDTH_X4: |
| 1125 | portw = "X4"; |
| 1126 | break; |
| 1127 | } |
| 1128 | |
| 1129 | snprintf(result, len, "%s, train pattern %s, voltage swing %s," |
| 1130 | "pre-emphasis %s, port width %s, enhanced framing %s, FDI PLL %s, scrambing %s, master mode %s", |
| 1131 | val & FDI_TX_ENABLE ? "enable" : "disable", |
| 1132 | train, voltage, pre_emphasis, portw, |
| 1133 | val & FDI_TX_ENHANCE_FRAME_ENABLE ? "enable" : |
| 1134 | "disable", |
| 1135 | val & FDI_TX_PLL_ENABLE ? "enable" : "disable", |
| 1136 | val & (1 << 7) ? "disable" : "enable", |
| 1137 | val & (1 << 0) ? "enable" : "disable"); |
| 1138 | } |
| 1139 | |
| 1140 | DEBUGSTRING(ironlake_debug_fdi_rx_ctl) |
| 1141 | { |
| 1142 | const char *train = NULL, *portw = NULL, *bpc = NULL; |
| 1143 | |
| 1144 | if (HAS_CPT) { |
| 1145 | switch (val & FDI_LINK_TRAIN_PATTERN_MASK_CPT) { |
| 1146 | case FDI_LINK_TRAIN_PATTERN_1_CPT: |
| 1147 | train = "pattern_1"; |
| 1148 | break; |
| 1149 | case FDI_LINK_TRAIN_PATTERN_2_CPT: |
| 1150 | train = "pattern_2"; |
| 1151 | break; |
| 1152 | case FDI_LINK_TRAIN_PATTERN_IDLE_CPT: |
| 1153 | train = "pattern_idle"; |
| 1154 | break; |
| 1155 | case FDI_LINK_TRAIN_NORMAL_CPT: |
| 1156 | train = "not train"; |
| 1157 | break; |
| 1158 | } |
| 1159 | } else { |
| 1160 | switch (val & FDI_LINK_TRAIN_NONE) { |
| 1161 | case FDI_LINK_TRAIN_PATTERN_1: |
| 1162 | train = "pattern_1"; |
| 1163 | break; |
| 1164 | case FDI_LINK_TRAIN_PATTERN_2: |
| 1165 | train = "pattern_2"; |
| 1166 | break; |
| 1167 | case FDI_LINK_TRAIN_PATTERN_IDLE: |
| 1168 | train = "pattern_idle"; |
| 1169 | break; |
| 1170 | case FDI_LINK_TRAIN_NONE: |
| 1171 | train = "not train"; |
| 1172 | break; |
| 1173 | } |
| 1174 | } |
| 1175 | |
| 1176 | switch (val & (7 << 19)) { |
| 1177 | case FDI_DP_PORT_WIDTH_X1: |
| 1178 | portw = "X1"; |
| 1179 | break; |
| 1180 | case FDI_DP_PORT_WIDTH_X2: |
| 1181 | portw = "X2"; |
| 1182 | break; |
| 1183 | case FDI_DP_PORT_WIDTH_X3: |
| 1184 | portw = "X3"; |
| 1185 | break; |
| 1186 | case FDI_DP_PORT_WIDTH_X4: |
| 1187 | portw = "X4"; |
| 1188 | break; |
| 1189 | } |
| 1190 | |
| 1191 | switch (val & (7 << 16)) { |
| 1192 | case FDI_8BPC: |
| 1193 | bpc = "8bpc"; |
| 1194 | break; |
| 1195 | case FDI_10BPC: |
| 1196 | bpc = "10bpc"; |
| 1197 | break; |
| 1198 | case FDI_6BPC: |
| 1199 | bpc = "6bpc"; |
| 1200 | break; |
| 1201 | case FDI_12BPC: |
| 1202 | bpc = "12bpc"; |
| 1203 | break; |
| 1204 | } |
| 1205 | |
| 1206 | snprintf(result, len, "%s, train pattern %s, port width %s, %s," |
| 1207 | "link_reverse_strap_overwrite %s, dmi_link_reverse %s, FDI PLL %s," |
| 1208 | "FS ecc %s, FE ecc %s, FS err report %s, FE err report %s," |
| 1209 | "scrambing %s, enhanced framing %s, %s", |
| 1210 | val & FDI_RX_ENABLE ? "enable" : "disable", |
| 1211 | train, portw, bpc, |
| 1212 | val & FDI_LINK_REVERSE_OVERWRITE ? "yes" : "no", |
| 1213 | val & FDI_DMI_LINK_REVERSE_MASK ? "yes" : "no", |
| 1214 | val & FDI_RX_PLL_ENABLE ? "enable" : "disable", |
| 1215 | val & FDI_FS_ERR_CORRECT_ENABLE ? "enable" : "disable", |
| 1216 | val & FDI_FE_ERR_CORRECT_ENABLE ? "enable" : "disable", |
| 1217 | val & FDI_FS_ERR_REPORT_ENABLE ? "enable" : "disable", |
| 1218 | val & FDI_FE_ERR_REPORT_ENABLE ? "enable" : "disable", |
| 1219 | val & (1 << 7) ? "disable" : "enable", |
| 1220 | val & FDI_RX_ENHANCE_FRAME_ENABLE ? "enable" : |
| 1221 | "disable", val & FDI_SEL_PCDCLK ? "PCDClk" : "RawClk"); |
| 1222 | } |
| 1223 | |
| 1224 | DEBUGSTRING(ironlake_debug_dspstride) |
| 1225 | { |
| 1226 | snprintf(result, len, "%d", val >> 6); |
| 1227 | } |
| 1228 | |
| 1229 | DEBUGSTRING(ironlake_debug_pch_dpll) |
| 1230 | { |
| 1231 | const char *enable = val & DPLL_VCO_ENABLE ? "enable" : "disable"; |
| 1232 | const char *highspeed = val & DPLL_DVO_HIGH_SPEED ? "yes" : "no"; |
| 1233 | const char *mode = NULL; |
| 1234 | const char *p2 = NULL; |
| 1235 | int fpa0_p1, fpa1_p1; |
| 1236 | const char *refclk = NULL; |
| 1237 | int sdvo_mul; |
| 1238 | |
| 1239 | if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_LVDS) { |
| 1240 | mode = "LVDS"; |
| 1241 | if (val & DPLLB_LVDS_P2_CLOCK_DIV_7) |
| 1242 | p2 = "Div 7"; |
| 1243 | else |
| 1244 | p2 = "Div 14"; |
| 1245 | } else if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_DAC_SERIAL) { |
| 1246 | mode = "Non-LVDS"; |
| 1247 | if (val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) |
| 1248 | p2 = "Div 5"; |
| 1249 | else |
| 1250 | p2 = "Div 10"; |
| 1251 | } |
| 1252 | fpa0_p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> 16); |
| 1253 | fpa1_p1 = ffs((val & DPLL_FPA1_P1_POST_DIV_MASK)); |
| 1254 | |
| 1255 | switch (val & PLL_REF_INPUT_MASK) { |
| 1256 | case PLL_REF_INPUT_DREFCLK: |
| 1257 | refclk = "default 120Mhz"; |
| 1258 | break; |
| 1259 | case PLL_REF_INPUT_SUPER_SSC: |
| 1260 | refclk = "SuperSSC 120Mhz"; |
| 1261 | break; |
| 1262 | case PLL_REF_INPUT_TVCLKINBC: |
| 1263 | refclk = "SDVO TVClkIn"; |
| 1264 | break; |
| 1265 | case PLLB_REF_INPUT_SPREADSPECTRUMIN: |
| 1266 | refclk = "SSC"; |
| 1267 | break; |
| 1268 | case PLL_REF_INPUT_DMICLK: |
| 1269 | refclk = "DMI RefCLK"; |
| 1270 | break; |
| 1271 | } |
| 1272 | |
| 1273 | sdvo_mul = ((val & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) >> 9) + 1; |
| 1274 | |
| 1275 | snprintf(result, len, "%s, sdvo high speed %s, mode %s, p2 %s, " |
| 1276 | "FPA0 P1 %d, FPA1 P1 %d, refclk %s, sdvo/hdmi mul %d", |
| 1277 | enable, highspeed, mode, p2, fpa0_p1, fpa1_p1, refclk, |
| 1278 | sdvo_mul); |
| 1279 | } |
| 1280 | |
| 1281 | DEBUGSTRING(ironlake_debug_dref_ctl) |
| 1282 | { |
| 1283 | const char *cpu_source; |
| 1284 | const char *ssc_source = val & DREF_SSC_SOURCE_ENABLE ? "enable" : "disable"; |
| 1285 | const char *nonspread_source = |
| 1286 | val & DREF_NONSPREAD_SOURCE_ENABLE ? "enable" : "disable"; |
| 1287 | const char *superspread_source = |
| 1288 | val & DREF_SUPERSPREAD_SOURCE_ENABLE ? "enable" : "disable"; |
| 1289 | const char *ssc4_mode = |
| 1290 | val & DREF_SSC4_CENTERSPREAD ? "centerspread" : "downspread"; |
| 1291 | const char *ssc1 = val & DREF_SSC1_ENABLE ? "enable" : "disable"; |
| 1292 | const char *ssc4 = val & DREF_SSC4_ENABLE ? "enable" : "disable"; |
| 1293 | |
| 1294 | switch (val & DREF_CPU_SOURCE_OUTPUT_NONSPREAD) { |
| 1295 | case DREF_CPU_SOURCE_OUTPUT_DISABLE: |
| 1296 | cpu_source = "disable"; |
| 1297 | break; |
| 1298 | case DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD: |
| 1299 | cpu_source = "downspread"; |
| 1300 | break; |
| 1301 | case DREF_CPU_SOURCE_OUTPUT_NONSPREAD: |
| 1302 | cpu_source = "nonspread"; |
| 1303 | break; |
| 1304 | default: |
| 1305 | cpu_source = "reserved"; |
| 1306 | } |
| 1307 | snprintf(result, len, "cpu source %s, ssc_source %s, nonspread_source %s, " |
| 1308 | "superspread_source %s, ssc4_mode %s, ssc1 %s, ssc4 %s", |
| 1309 | cpu_source, ssc_source, nonspread_source, |
| 1310 | superspread_source, ssc4_mode, ssc1, ssc4); |
| 1311 | } |
| 1312 | |
| 1313 | DEBUGSTRING(ironlake_debug_rawclk_freq) |
| 1314 | { |
| 1315 | const char *tp1 = NULL, *tp2 = NULL; |
| 1316 | |
| 1317 | switch (val & FDL_TP1_TIMER_MASK) { |
| 1318 | case 0: |
| 1319 | tp1 = "0.5us"; |
| 1320 | break; |
| 1321 | case (1 << 12): |
| 1322 | tp1 = "1.0us"; |
| 1323 | break; |
| 1324 | case (2 << 12): |
| 1325 | tp1 = "2.0us"; |
| 1326 | break; |
| 1327 | case (3 << 12): |
| 1328 | tp1 = "4.0us"; |
| 1329 | break; |
| 1330 | } |
| 1331 | switch (val & FDL_TP2_TIMER_MASK) { |
| 1332 | case 0: |
| 1333 | tp2 = "1.5us"; |
| 1334 | break; |
| 1335 | case (1 << 10): |
| 1336 | tp2 = "3.0us"; |
| 1337 | break; |
| 1338 | case (2 << 10): |
| 1339 | tp2 = "6.0us"; |
| 1340 | break; |
| 1341 | case (3 << 10): |
| 1342 | tp2 = "12.0us"; |
| 1343 | break; |
| 1344 | } |
| 1345 | snprintf(result, len, "FDL_TP1 timer %s, FDL_TP2 timer %s, freq %d", |
| 1346 | tp1, tp2, val & RAWCLK_FREQ_MASK); |
| 1347 | |
| 1348 | } |
| 1349 | |
| 1350 | DEBUGSTRING(ironlake_debug_fdi_rx_misc) |
| 1351 | { |
| 1352 | snprintf(result, len, "FDI Delay %d", val & ((1 << 13) - 1)); |
| 1353 | } |
| 1354 | |
| 1355 | DEBUGSTRING(ironlake_debug_transconf) |
| 1356 | { |
| 1357 | const char *enable = val & TRANS_ENABLE ? "enable" : "disable"; |
| 1358 | const char *state = val & TRANS_STATE_ENABLE ? "active" : "inactive"; |
| 1359 | const char *interlace; |
| 1360 | |
| 1361 | switch ((val >> 21) & 7) { |
| 1362 | case 0: |
| 1363 | interlace = "progressive"; |
| 1364 | break; |
| 1365 | case 2: |
| 1366 | if (IS_GEN5(devid)) |
| 1367 | interlace = "interlaced sdvo"; |
| 1368 | else |
| 1369 | interlace = "rsvd"; |
| 1370 | break; |
| 1371 | case 3: |
| 1372 | interlace = "interlaced"; |
| 1373 | break; |
| 1374 | default: |
| 1375 | interlace = "rsvd"; |
| 1376 | } |
| 1377 | |
| 1378 | snprintf(result, len, "%s, %s, %s", enable, state, interlace); |
| 1379 | } |
| 1380 | |
| 1381 | DEBUGSTRING(ironlake_debug_panel_fitting) |
| 1382 | { |
| 1383 | const char *vadapt = NULL, *filter_sel = NULL; |
| 1384 | |
| 1385 | switch (val & (3 << 25)) { |
| 1386 | case 0: |
| 1387 | vadapt = "least"; |
| 1388 | break; |
| 1389 | case (1 << 25): |
| 1390 | vadapt = "moderate"; |
| 1391 | break; |
| 1392 | case (2 << 25): |
| 1393 | vadapt = "reserved"; |
| 1394 | break; |
| 1395 | case (3 << 25): |
| 1396 | vadapt = "most"; |
| 1397 | break; |
| 1398 | } |
| 1399 | |
| 1400 | switch (val & (3 << 23)) { |
| 1401 | case 0: |
| 1402 | filter_sel = "programmed"; |
| 1403 | break; |
| 1404 | case (1 << 23): |
| 1405 | filter_sel = "hardcoded"; |
| 1406 | break; |
| 1407 | case (2 << 23): |
| 1408 | filter_sel = "edge_enhance"; |
| 1409 | break; |
| 1410 | case (3 << 23): |
| 1411 | filter_sel = "edge_soften"; |
| 1412 | break; |
| 1413 | } |
| 1414 | |
| 1415 | snprintf(result, len, |
| 1416 | "%s, auto_scale %s, auto_scale_cal %s, v_filter %s, vadapt %s, mode %s, filter_sel %s," |
| 1417 | "chroma pre-filter %s, vert3tap %s, v_inter_invert %s", |
| 1418 | val & PF_ENABLE ? "enable" : "disable", |
| 1419 | val & (1 << 30) ? "no" : "yes", |
| 1420 | val & (1 << 29) ? "yes" : "no", |
| 1421 | val & (1 << 28) ? "bypass" : "enable", |
| 1422 | val & (1 << 27) ? "enable" : "disable", |
| 1423 | vadapt, |
| 1424 | filter_sel, |
| 1425 | val & (1 << 22) ? "enable" : "disable", |
| 1426 | val & (1 << 21) ? "force" : "auto", |
| 1427 | val & (1 << 20) ? "field 0" : "field 1"); |
| 1428 | } |
| 1429 | |
| 1430 | DEBUGSTRING(ironlake_debug_panel_fitting_2) |
| 1431 | { |
| 1432 | snprintf(result, len, |
| 1433 | "vscale %f", |
| 1434 | val / (float) (1<<15)); |
| 1435 | } |
| 1436 | |
| 1437 | DEBUGSTRING(ironlake_debug_panel_fitting_3) |
| 1438 | { |
| 1439 | snprintf(result, len, |
| 1440 | "vscale initial phase %f", |
| 1441 | val / (float) (1<<15)); |
| 1442 | } |
| 1443 | |
| 1444 | DEBUGSTRING(ironlake_debug_panel_fitting_4) |
| 1445 | { |
| 1446 | snprintf(result, len, |
| 1447 | "hscale %f", |
| 1448 | val / (float) (1<<15)); |
| 1449 | } |
| 1450 | |
| 1451 | DEBUGSTRING(ironlake_debug_pf_win) |
| 1452 | { |
| 1453 | int a, b; |
| 1454 | |
| 1455 | a = (val >> 16) & 0x1fff; |
| 1456 | b = val & 0xfff; |
| 1457 | |
| 1458 | snprintf(result, len, "%d, %d", a, b); |
| 1459 | } |
| 1460 | |
| 1461 | DEBUGSTRING(ironlake_debug_hdmi) |
| 1462 | { |
| 1463 | int disp_pipe; |
| 1464 | const char *enable, *bpc = NULL, *encoding; |
| 1465 | const char *mode, *audio, *vsync, *hsync, *detect; |
| 1466 | |
| 1467 | if (val & PORT_ENABLE) |
| 1468 | enable = "enabled"; |
| 1469 | else |
| 1470 | enable = "disabled"; |
| 1471 | |
| 1472 | if (HAS_CPT) |
| 1473 | disp_pipe = (val & (3<<29)) >> 29; |
| 1474 | else |
| 1475 | disp_pipe = (val & TRANSCODER_B) >> 29; |
| 1476 | |
| 1477 | switch (val & (7 << 26)) { |
| 1478 | case COLOR_FORMAT_8bpc: |
| 1479 | bpc = "8bpc"; |
| 1480 | break; |
| 1481 | case COLOR_FORMAT_12bpc: |
| 1482 | bpc = "12bpc"; |
| 1483 | break; |
| 1484 | } |
| 1485 | |
| 1486 | if ((val & (3 << 10)) == TMDS_ENCODING) |
| 1487 | encoding = "TMDS"; |
| 1488 | else |
| 1489 | encoding = "SDVO"; |
| 1490 | |
| 1491 | if (val & (1 << 9)) |
| 1492 | mode = "HDMI"; |
| 1493 | else |
| 1494 | mode = "DVI"; |
| 1495 | |
| 1496 | if (val & AUDIO_ENABLE) |
| 1497 | audio = "enabled"; |
| 1498 | else |
| 1499 | audio = "disabled"; |
| 1500 | |
| 1501 | if (val & VSYNC_ACTIVE_HIGH) |
| 1502 | vsync = "+vsync"; |
| 1503 | else |
| 1504 | vsync = "-vsync"; |
| 1505 | |
| 1506 | if (val & HSYNC_ACTIVE_HIGH) |
| 1507 | hsync = "+hsync"; |
| 1508 | else |
| 1509 | hsync = "-hsync"; |
| 1510 | |
| 1511 | if (val & PORT_DETECTED) |
| 1512 | detect = "detected"; |
| 1513 | else |
| 1514 | detect = "non-detected"; |
| 1515 | |
| 1516 | snprintf(result, len, "%s pipe %c %s %s %s audio %s %s %s %s", |
| 1517 | enable, disp_pipe + 'A', bpc, encoding, mode, audio, vsync, hsync, detect); |
| 1518 | } |
| 1519 | |
| 1520 | DEBUGSTRING(snb_debug_dpll_sel) |
| 1521 | { |
| 1522 | const char *transa, *transb; |
| 1523 | const char *dplla = NULL, *dpllb = NULL; |
| 1524 | |
| 1525 | if (!HAS_CPT) |
| 1526 | return; |
| 1527 | |
| 1528 | if (val & TRANSA_DPLL_ENABLE) { |
| 1529 | transa = "enable"; |
| 1530 | if (val & TRANSA_DPLLB_SEL) |
| 1531 | dplla = "B"; |
| 1532 | else |
| 1533 | dplla = "A"; |
| 1534 | } else |
| 1535 | transa = "disable"; |
| 1536 | |
| 1537 | if (val & TRANSB_DPLL_ENABLE) { |
| 1538 | transb = "enable"; |
| 1539 | if (val & TRANSB_DPLLB_SEL) |
| 1540 | dpllb = "B"; |
| 1541 | else |
| 1542 | dpllb = "A"; |
| 1543 | } else |
| 1544 | transb = "disable"; |
| 1545 | |
| 1546 | snprintf(result, len, "TransA DPLL %s (DPLL %s), TransB DPLL %s (DPLL %s)", |
| 1547 | transa, dplla, transb, dpllb); |
| 1548 | } |
| 1549 | |
| 1550 | DEBUGSTRING(snb_debug_trans_dp_ctl) |
| 1551 | { |
| 1552 | const char *enable, *port = NULL, *bpc = NULL, *vsync, *hsync; |
| 1553 | |
| 1554 | if (!HAS_CPT) |
| 1555 | return; |
| 1556 | |
| 1557 | if (val & TRANS_DP_OUTPUT_ENABLE) |
| 1558 | enable = "enable"; |
| 1559 | else |
| 1560 | enable = "disable"; |
| 1561 | |
| 1562 | switch (val & TRANS_DP_PORT_SEL_MASK) { |
| 1563 | case TRANS_DP_PORT_SEL_B: |
| 1564 | port = "B"; |
| 1565 | break; |
| 1566 | case TRANS_DP_PORT_SEL_C: |
| 1567 | port = "C"; |
| 1568 | break; |
| 1569 | case TRANS_DP_PORT_SEL_D: |
| 1570 | port = "D"; |
| 1571 | break; |
| 1572 | default: |
| 1573 | port = "none"; |
| 1574 | break; |
| 1575 | } |
| 1576 | |
| 1577 | switch (val & (7<<9)) { |
| 1578 | case TRANS_DP_8BPC: |
| 1579 | bpc = "8bpc"; |
| 1580 | break; |
| 1581 | case TRANS_DP_10BPC: |
| 1582 | bpc = "10bpc"; |
| 1583 | break; |
| 1584 | case TRANS_DP_6BPC: |
| 1585 | bpc = "6bpc"; |
| 1586 | break; |
| 1587 | case TRANS_DP_12BPC: |
| 1588 | bpc = "12bpc"; |
| 1589 | break; |
| 1590 | } |
| 1591 | |
| 1592 | if (val & TRANS_DP_VSYNC_ACTIVE_HIGH) |
| 1593 | vsync = "+vsync"; |
| 1594 | else |
| 1595 | vsync = "-vsync"; |
| 1596 | |
| 1597 | if (val & TRANS_DP_HSYNC_ACTIVE_HIGH) |
| 1598 | hsync = "+hsync"; |
| 1599 | else |
| 1600 | hsync = "-hsync"; |
| 1601 | |
| 1602 | snprintf(result, len, "%s port %s %s %s %s", |
| 1603 | enable, port, bpc, vsync, hsync); |
| 1604 | } |
| 1605 | |
| 1606 | DEBUGSTRING(ilk_debug_pp_control) |
| 1607 | { |
| 1608 | snprintf(result, len, "blacklight %s, %spower down on reset, panel %s", |
| 1609 | (val & (1 << 2)) ? "enabled" : "disabled", |
| 1610 | (val & (1 << 1)) ? "" : "do not ", |
| 1611 | (val & (1 << 0)) ? "on" : "off"); |
| 1612 | } |
| 1613 | |
| 1614 | DEBUGSTRING(hsw_debug_port_clk_sel) |
| 1615 | { |
| 1616 | const char *clock = NULL; |
| 1617 | |
| 1618 | switch ((val >> 29 ) & 7) { |
| 1619 | case 0: |
| 1620 | clock = "LCPLL 2700"; |
| 1621 | break; |
| 1622 | case 1: |
| 1623 | clock = "LCPLL 1350"; |
| 1624 | break; |
| 1625 | case 2: |
| 1626 | clock = "LCPLL 810"; |
| 1627 | break; |
| 1628 | case 3: |
| 1629 | clock = "SPLL"; |
| 1630 | break; |
| 1631 | case 4: |
| 1632 | clock = "WRPLL 1"; |
| 1633 | break; |
| 1634 | case 5: |
| 1635 | clock = "WRPLL 2"; |
| 1636 | break; |
| 1637 | case 6: |
| 1638 | clock = "Reserved"; |
| 1639 | break; |
| 1640 | case 7: |
| 1641 | clock = "None"; |
| 1642 | break; |
| 1643 | } |
| 1644 | |
| 1645 | snprintf(result, len, "%s", clock); |
| 1646 | } |
| 1647 | |
| 1648 | DEBUGSTRING(hsw_debug_pipe_clk_sel) |
| 1649 | { |
| 1650 | const char *clock; |
| 1651 | |
| 1652 | switch ((val >> 29) & 7) { |
| 1653 | case 0: |
| 1654 | clock = "None"; |
| 1655 | break; |
| 1656 | case 2: |
| 1657 | clock = "DDIB"; |
| 1658 | break; |
| 1659 | case 3: |
| 1660 | clock = "DDIC"; |
| 1661 | break; |
| 1662 | case 4: |
| 1663 | clock = "DDID"; |
| 1664 | break; |
| 1665 | case 5: |
| 1666 | clock = "DDIE"; |
| 1667 | break; |
| 1668 | default: |
| 1669 | clock = "Reserved"; |
| 1670 | break; |
| 1671 | } |
| 1672 | |
| 1673 | snprintf(result, len, "%s", clock); |
| 1674 | } |
| 1675 | |
| 1676 | DEBUGSTRING(hsw_debug_ddi_buf_ctl) |
| 1677 | { |
| 1678 | const char *enable, *reversal, *width, *detected; |
| 1679 | |
| 1680 | enable = (val & (1<<31)) ? "enabled" : "disabled"; |
| 1681 | reversal = (val & (1<<16)) ? "reversed" : "not reversed"; |
| 1682 | |
| 1683 | switch ((val >> 1) & 7) { |
| 1684 | case 0: |
| 1685 | width = "x1"; |
| 1686 | break; |
| 1687 | case 1: |
| 1688 | width = "x2"; |
| 1689 | break; |
| 1690 | case 3: |
| 1691 | width = "x4"; |
| 1692 | break; |
| 1693 | default: |
| 1694 | width = "reserved"; |
| 1695 | break; |
| 1696 | } |
| 1697 | |
| 1698 | detected = (val & 1) ? "detected" : "not detected"; |
| 1699 | |
| 1700 | snprintf(result, len, "%s %s %s %s", enable, reversal, width, detected); |
| 1701 | } |
| 1702 | |
| 1703 | DEBUGSTRING(hsw_debug_sfuse_strap) |
| 1704 | { |
| 1705 | const char *display, *crt, *lane_reversal, *portb, *portc, *portd; |
| 1706 | |
| 1707 | display = (val & (1<<7)) ? "disabled" : "enabled"; |
| 1708 | crt = (val & (1<<6)) ? "yes" : "no"; |
| 1709 | lane_reversal = (val & (1<<4)) ? "yes" : "no"; |
| 1710 | portb = (val & (1<<2)) ? "yes" : "no"; |
| 1711 | portc = (val & (1<<1)) ? "yes" : "no"; |
| 1712 | portd = (val & (1<<0)) ? "yes" : "no"; |
| 1713 | |
| 1714 | snprintf(result, len, "display %s, crt %s, lane reversal %s, " |
| 1715 | "port b %s, port c %s, port d %s", display, crt, lane_reversal, |
| 1716 | portb, portc, portd); |
| 1717 | } |
| 1718 | |
| 1719 | DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl) |
| 1720 | { |
| 1721 | const char *enable, *port, *mode, *bpc, *vsync, *hsync, *edp_input; |
| 1722 | const char *width; |
| 1723 | |
| 1724 | enable = (val & (1<<31)) ? "enabled" : "disabled"; |
| 1725 | |
| 1726 | switch ((val >> 28) & 7) { |
| 1727 | case 0: |
| 1728 | port = "no port"; |
| 1729 | break; |
| 1730 | case 1: |
| 1731 | port = "DDIB"; |
| 1732 | break; |
| 1733 | case 2: |
| 1734 | port = "DDIC"; |
| 1735 | break; |
| 1736 | case 3: |
| 1737 | port = "DDID"; |
| 1738 | break; |
| 1739 | case 4: |
| 1740 | port = "DDIE"; |
| 1741 | break; |
| 1742 | default: |
| 1743 | port = "port reserved"; |
| 1744 | break; |
| 1745 | } |
| 1746 | |
| 1747 | switch ((val >> 24) & 7) { |
| 1748 | case 0: |
| 1749 | mode = "HDMI"; |
| 1750 | break; |
| 1751 | case 1: |
| 1752 | mode = "DVI"; |
| 1753 | break; |
| 1754 | case 2: |
| 1755 | mode = "DP SST"; |
| 1756 | break; |
| 1757 | case 3: |
| 1758 | mode = "DP MST"; |
| 1759 | break; |
| 1760 | case 4: |
| 1761 | mode = "FDI"; |
| 1762 | break; |
| 1763 | case 5: |
| 1764 | default: |
| 1765 | mode = "mode reserved"; |
| 1766 | break; |
| 1767 | } |
| 1768 | |
| 1769 | switch ((val >> 20) & 7) { |
| 1770 | case 0: |
| 1771 | bpc = "8 bpc"; |
| 1772 | break; |
| 1773 | case 1: |
| 1774 | bpc = "10 bpc"; |
| 1775 | break; |
| 1776 | case 2: |
| 1777 | bpc = "6 bpc"; |
| 1778 | break; |
| 1779 | case 3: |
| 1780 | bpc = "12 bpc"; |
| 1781 | break; |
| 1782 | default: |
| 1783 | bpc = "bpc reserved"; |
| 1784 | break; |
| 1785 | } |
| 1786 | |
| 1787 | hsync = (val & (1<<16)) ? "+HSync" : "-HSync"; |
| 1788 | vsync = (val & (1<<17)) ? "+VSync" : "-VSync"; |
| 1789 | |
| 1790 | switch ((val >> 12) & 7) { |
| 1791 | case 0: |
| 1792 | edp_input = "EDP A ON"; |
| 1793 | break; |
| 1794 | case 4: |
| 1795 | edp_input = "EDP A ONOFF"; |
| 1796 | break; |
| 1797 | case 5: |
| 1798 | edp_input = "EDP B ONOFF"; |
| 1799 | break; |
| 1800 | case 6: |
| 1801 | edp_input = "EDP C ONOFF"; |
| 1802 | break; |
| 1803 | default: |
| 1804 | edp_input = "EDP input reserved"; |
| 1805 | break; |
| 1806 | } |
| 1807 | |
| 1808 | switch ((val >> 1) & 7) { |
| 1809 | case 0: |
| 1810 | width = "x1"; |
| 1811 | break; |
| 1812 | case 1: |
| 1813 | width = "x2"; |
| 1814 | break; |
| 1815 | case 3: |
| 1816 | width = "x4"; |
| 1817 | break; |
| 1818 | default: |
| 1819 | width = "reserved width"; |
| 1820 | break; |
| 1821 | } |
| 1822 | |
| 1823 | snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s", enable, |
| 1824 | port, mode, bpc, vsync, hsync, edp_input, width); |
| 1825 | } |
| 1826 | |
| 1827 | DEBUGSTRING(hsw_debug_wm_pipe) |
| 1828 | { |
| 1829 | uint32_t primary, sprite, cursor; |
| 1830 | |
| 1831 | primary = (val >> 16) & 0x7F; |
| 1832 | sprite = (val >> 8) & 0x7F; |
| 1833 | cursor = val & 0x3F; |
| 1834 | |
| 1835 | snprintf(result, len, "primary %d, sprite %d, pipe %d", primary, |
| 1836 | sprite, cursor); |
| 1837 | } |
| 1838 | |
| 1839 | DEBUGSTRING(hsw_debug_lp_wm) |
| 1840 | { |
| 1841 | const char *enable; |
| 1842 | uint32_t latency, fbc, pri, cur; |
| 1843 | |
| 1844 | enable = ((val >> 31) & 1) ? "enabled" : "disabled"; |
| 1845 | latency = (val >> 24) & 0x7F; |
| 1846 | fbc = (val >> 20) & 0xF; |
| 1847 | pri = (val >> 8) & 0x3FF; |
| 1848 | cur = val & 0xFF; |
| 1849 | |
| 1850 | snprintf(result, len, "%s, latency %d, fbc %d, pri %d, cur %d", |
| 1851 | enable, latency, fbc, pri, cur); |
| 1852 | } |
| 1853 | |
| 1854 | DEBUGSTRING(hsw_debug_sinterrupt) |
| 1855 | { |
| 1856 | int portd, portc, portb, crt; |
| 1857 | |
| 1858 | portd = (val >> 23) & 1; |
| 1859 | portc = (val >> 22) & 1; |
| 1860 | portb = (val >> 21) & 1; |
| 1861 | crt = (val >> 19) & 1; |
| 1862 | |
| 1863 | snprintf(result, len, "port d:%d, port c:%d, port b:%d, crt:%d", |
| 1864 | portd, portc, portb, crt); |
| 1865 | } |
| 1866 | |
| 1867 | DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl2) |
| 1868 | { |
| 1869 | int enable, blinking, granularity; |
| 1870 | const char *pipe; |
| 1871 | |
| 1872 | enable = (val >> 31) & 1; |
| 1873 | |
| 1874 | if (IS_GEN5(devid) || IS_GEN6(devid)) { |
| 1875 | pipe = ((val >> 29) & 1) ? "B" : "A"; |
| 1876 | } else { |
| 1877 | switch ((val >> 29) & 3) { |
| 1878 | case 0: |
| 1879 | pipe = "A"; |
| 1880 | break; |
| 1881 | case 1: |
| 1882 | pipe = "B"; |
| 1883 | break; |
| 1884 | case 2: |
| 1885 | pipe = "C"; |
| 1886 | break; |
| 1887 | case 3: |
| 1888 | if (IS_IVYBRIDGE(devid)) |
| 1889 | pipe = "reserved"; |
| 1890 | else |
| 1891 | pipe = "EDP"; |
| 1892 | break; |
| 1893 | } |
| 1894 | } |
| 1895 | |
| 1896 | if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)) { |
| 1897 | snprintf(result, len, "enable %d, pipe %s", enable, pipe); |
| 1898 | } else { |
| 1899 | blinking = (val >> 28) & 1; |
| 1900 | granularity = ((val >> 27) & 1) ? 8 : 128; |
| 1901 | |
| 1902 | snprintf(result, len, "enable %d, pipe %s, blinking %d, " |
| 1903 | "granularity %d", enable, pipe, blinking, |
| 1904 | granularity); |
| 1905 | } |
| 1906 | } |
| 1907 | |
| 1908 | DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl) |
| 1909 | { |
| 1910 | int cycle, freq; |
| 1911 | |
| 1912 | cycle = (val & 0xFFFF); |
| 1913 | |
| 1914 | if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)) { |
| 1915 | snprintf(result, len, "cycle %d", cycle); |
| 1916 | } else { |
| 1917 | freq = (val >> 16) & 0xFFFF; |
| 1918 | |
| 1919 | snprintf(result, len, "cycle %d, freq %d", cycle, freq); |
| 1920 | } |
| 1921 | } |
| 1922 | |
| 1923 | DEBUGSTRING(ibx_debug_blc_pwm_ctl1) |
| 1924 | { |
| 1925 | int enable, override, inverted_polarity; |
| 1926 | |
| 1927 | enable = (val >> 31) & 1; |
| 1928 | override = (val >> 30) & 1; |
| 1929 | inverted_polarity = (val >> 29) & 1; |
| 1930 | |
| 1931 | snprintf(result, len, "enable %d, override %d, inverted polarity %d", |
| 1932 | enable, override, inverted_polarity); |
| 1933 | } |
| 1934 | |
| 1935 | DEBUGSTRING(ibx_debug_blc_pwm_ctl2) |
| 1936 | { |
| 1937 | int freq, cycle; |
| 1938 | |
| 1939 | freq = (val >> 16) & 0xFFFF; |
| 1940 | cycle = val & 0xFFFF; |
| 1941 | |
| 1942 | snprintf(result, len, "freq %d, cycle %d", freq, cycle); |
| 1943 | } |
| 1944 | |
| 1945 | DEBUGSTRING(hsw_debug_blc_misc_ctl) |
| 1946 | { |
| 1947 | const char *sel; |
| 1948 | |
| 1949 | sel = (val & 1) ? "PWM1-CPU PWM2-PCH" : "PWM1-PCH PWM2-CPU"; |
| 1950 | |
| 1951 | snprintf(result, len, "%s", sel); |
| 1952 | } |
| 1953 | |
| 1954 | DEBUGSTRING(hsw_debug_util_pin_ctl) |
| 1955 | { |
| 1956 | int enable, data, inverted_polarity; |
| 1957 | const char *transcoder, *mode; |
| 1958 | |
| 1959 | enable = (val >> 31) & 1; |
| 1960 | |
| 1961 | switch ((val >> 29) & 3) { |
| 1962 | case 0: |
| 1963 | transcoder = "A"; |
| 1964 | break; |
| 1965 | case 1: |
| 1966 | transcoder = "B"; |
| 1967 | break; |
| 1968 | case 2: |
| 1969 | transcoder = "C"; |
| 1970 | break; |
| 1971 | case 3: |
| 1972 | transcoder = "EDP"; |
| 1973 | break; |
| 1974 | } |
| 1975 | |
| 1976 | switch ((val >> 24) & 0xF) { |
| 1977 | case 0: |
| 1978 | mode = "data"; |
| 1979 | break; |
| 1980 | case 1: |
| 1981 | mode = "PWM"; |
| 1982 | break; |
| 1983 | case 4: |
| 1984 | mode = "Vblank"; |
| 1985 | break; |
| 1986 | case 5: |
| 1987 | mode = "Vsync"; |
| 1988 | break; |
| 1989 | default: |
| 1990 | mode = "reserved"; |
| 1991 | break; |
| 1992 | } |
| 1993 | |
| 1994 | data = (val >> 23) & 1; |
| 1995 | inverted_polarity = (val >> 22) & 1; |
| 1996 | |
| 1997 | snprintf(result, len, "enable %d, transcoder %s, mode %s, data %d " |
| 1998 | "inverted polarity %d", enable, transcoder, mode, data, |
| 1999 | inverted_polarity); |
| 2000 | } |
| 2001 | |
| 2002 | static const struct reg_debug gen6_fences[] = { |
| 2003 | #define DEFINEFENCE_SNB(i) \ |
| 2004 | { FENCE_REG_SANDYBRIDGE_0 + (i) * 8, "FENCE START "#i, NULL }, \ |
| 2005 | { FENCE_REG_SANDYBRIDGE_0 + (i) * 8 + 4, "FENCE END "#i, NULL } |
| 2006 | DEFINEFENCE_SNB(0), |
| 2007 | DEFINEFENCE_SNB(1), |
| 2008 | DEFINEFENCE_SNB(2), |
| 2009 | DEFINEFENCE_SNB(3), |
| 2010 | DEFINEFENCE_SNB(4), |
| 2011 | DEFINEFENCE_SNB(5), |
| 2012 | DEFINEFENCE_SNB(6), |
| 2013 | DEFINEFENCE_SNB(7), |
| 2014 | DEFINEFENCE_SNB(8), |
| 2015 | DEFINEFENCE_SNB(9), |
| 2016 | DEFINEFENCE_SNB(10), |
| 2017 | DEFINEFENCE_SNB(11), |
| 2018 | DEFINEFENCE_SNB(12), |
| 2019 | DEFINEFENCE_SNB(13), |
| 2020 | DEFINEFENCE_SNB(14), |
| 2021 | DEFINEFENCE_SNB(15), |
| 2022 | DEFINEFENCE_SNB(16), |
| 2023 | DEFINEFENCE_SNB(17), |
| 2024 | DEFINEFENCE_SNB(18), |
| 2025 | DEFINEFENCE_SNB(19), |
| 2026 | DEFINEFENCE_SNB(20), |
| 2027 | DEFINEFENCE_SNB(20), |
| 2028 | DEFINEFENCE_SNB(21), |
| 2029 | DEFINEFENCE_SNB(22), |
| 2030 | DEFINEFENCE_SNB(23), |
| 2031 | DEFINEFENCE_SNB(24), |
| 2032 | DEFINEFENCE_SNB(25), |
| 2033 | DEFINEFENCE_SNB(26), |
| 2034 | DEFINEFENCE_SNB(27), |
| 2035 | DEFINEFENCE_SNB(28), |
| 2036 | DEFINEFENCE_SNB(29), |
| 2037 | DEFINEFENCE_SNB(30), |
| 2038 | DEFINEFENCE_SNB(31), |
| 2039 | }; |
| 2040 | |
| 2041 | static const struct reg_debug ironlake_debug_regs[] = { |
| 2042 | DEFINEREG(PGETBL_CTL), |
| 2043 | DEFINEREG(INSTDONE_I965), |
| 2044 | DEFINEREG(INSTDONE_1), |
| 2045 | DEFINEREG2(CPU_VGACNTRL, i830_debug_vgacntrl), |
| 2046 | DEFINEREG(DIGITAL_PORT_HOTPLUG_CNTRL), |
| 2047 | |
| 2048 | DEFINEREG2(RR_HW_CTL, ironlake_debug_rr_hw_ctl), |
| 2049 | |
| 2050 | DEFINEREG(FDI_PLL_BIOS_0), |
| 2051 | DEFINEREG(FDI_PLL_BIOS_1), |
| 2052 | DEFINEREG(FDI_PLL_BIOS_2), |
| 2053 | |
| 2054 | DEFINEREG(DISPLAY_PORT_PLL_BIOS_0), |
| 2055 | DEFINEREG(DISPLAY_PORT_PLL_BIOS_1), |
| 2056 | DEFINEREG(DISPLAY_PORT_PLL_BIOS_2), |
| 2057 | |
| 2058 | DEFINEREG(FDI_PLL_FREQ_CTL), |
| 2059 | |
| 2060 | /* pipe B */ |
| 2061 | |
| 2062 | DEFINEREG2(PIPEACONF, i830_debug_pipeconf), |
| 2063 | |
| 2064 | DEFINEREG2(HTOTAL_A, i830_debug_hvtotal), |
| 2065 | DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank), |
| 2066 | DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank), |
| 2067 | DEFINEREG2(VTOTAL_A, i830_debug_hvtotal), |
| 2068 | DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank), |
| 2069 | DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank), |
| 2070 | DEFINEREG(VSYNCSHIFT_A), |
| 2071 | DEFINEREG2(PIPEASRC, i830_debug_yxminus1), |
| 2072 | |
| 2073 | DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu), |
| 2074 | DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n), |
| 2075 | DEFINEREG2(PIPEA_DATA_M2, ironlake_debug_m_tu), |
| 2076 | DEFINEREG2(PIPEA_DATA_N2, ironlake_debug_n), |
| 2077 | |
| 2078 | DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n), |
| 2079 | DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n), |
| 2080 | DEFINEREG2(PIPEA_LINK_M2, ironlake_debug_n), |
| 2081 | DEFINEREG2(PIPEA_LINK_N2, ironlake_debug_n), |
| 2082 | |
| 2083 | DEFINEREG2(DSPACNTR, i830_debug_dspcntr), |
| 2084 | DEFINEREG(DSPABASE), |
| 2085 | DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride), |
| 2086 | DEFINEREG(DSPASURF), |
| 2087 | DEFINEREG2(DSPATILEOFF, i830_debug_xy), |
| 2088 | |
| 2089 | /* pipe B */ |
| 2090 | |
| 2091 | DEFINEREG2(PIPEBCONF, i830_debug_pipeconf), |
| 2092 | |
| 2093 | DEFINEREG2(HTOTAL_B, i830_debug_hvtotal), |
| 2094 | DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank), |
| 2095 | DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank), |
| 2096 | DEFINEREG2(VTOTAL_B, i830_debug_hvtotal), |
| 2097 | DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank), |
| 2098 | DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank), |
| 2099 | DEFINEREG(VSYNCSHIFT_B), |
| 2100 | DEFINEREG2(PIPEBSRC, i830_debug_yxminus1), |
| 2101 | |
| 2102 | DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu), |
| 2103 | DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n), |
| 2104 | DEFINEREG2(PIPEB_DATA_M2, ironlake_debug_m_tu), |
| 2105 | DEFINEREG2(PIPEB_DATA_N2, ironlake_debug_n), |
| 2106 | |
| 2107 | DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n), |
| 2108 | DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n), |
| 2109 | DEFINEREG2(PIPEB_LINK_M2, ironlake_debug_n), |
| 2110 | DEFINEREG2(PIPEB_LINK_N2, ironlake_debug_n), |
| 2111 | |
| 2112 | DEFINEREG2(DSPBCNTR, i830_debug_dspcntr), |
| 2113 | DEFINEREG(DSPBBASE), |
| 2114 | DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride), |
| 2115 | DEFINEREG(DSPBSURF), |
| 2116 | DEFINEREG2(DSPBTILEOFF, i830_debug_xy), |
| 2117 | |
| 2118 | /* pipe C */ |
| 2119 | |
| 2120 | DEFINEREG2(PIPECCONF, i830_debug_pipeconf), |
| 2121 | |
| 2122 | DEFINEREG2(HTOTAL_C, i830_debug_hvtotal), |
| 2123 | DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank), |
| 2124 | DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank), |
| 2125 | DEFINEREG2(VTOTAL_C, i830_debug_hvtotal), |
| 2126 | DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank), |
| 2127 | DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank), |
| 2128 | DEFINEREG(VSYNCSHIFT_C), |
| 2129 | DEFINEREG2(PIPECSRC, i830_debug_yxminus1), |
| 2130 | |
| 2131 | DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu), |
| 2132 | DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n), |
| 2133 | DEFINEREG2(PIPEC_DATA_M2, ironlake_debug_m_tu), |
| 2134 | DEFINEREG2(PIPEC_DATA_N2, ironlake_debug_n), |
| 2135 | |
| 2136 | DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n), |
| 2137 | DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n), |
| 2138 | DEFINEREG2(PIPEC_LINK_M2, ironlake_debug_n), |
| 2139 | DEFINEREG2(PIPEC_LINK_N2, ironlake_debug_n), |
| 2140 | |
| 2141 | DEFINEREG2(DSPCCNTR, i830_debug_dspcntr), |
| 2142 | DEFINEREG(DSPCBASE), |
| 2143 | DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride), |
| 2144 | DEFINEREG(DSPCSURF), |
| 2145 | DEFINEREG2(DSPCTILEOFF, i830_debug_xy), |
| 2146 | |
| 2147 | /* Panel fitter */ |
| 2148 | |
| 2149 | DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting), |
| 2150 | DEFINEREG2(PFA_CTL_2, ironlake_debug_panel_fitting_2), |
| 2151 | DEFINEREG2(PFA_CTL_3, ironlake_debug_panel_fitting_3), |
| 2152 | DEFINEREG2(PFA_CTL_4, ironlake_debug_panel_fitting_4), |
| 2153 | DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win), |
| 2154 | DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win), |
| 2155 | DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting), |
| 2156 | DEFINEREG2(PFB_CTL_2, ironlake_debug_panel_fitting_2), |
| 2157 | DEFINEREG2(PFB_CTL_3, ironlake_debug_panel_fitting_3), |
| 2158 | DEFINEREG2(PFB_CTL_4, ironlake_debug_panel_fitting_4), |
| 2159 | DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win), |
| 2160 | DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win), |
| 2161 | DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting), |
| 2162 | DEFINEREG2(PFC_CTL_2, ironlake_debug_panel_fitting_2), |
| 2163 | DEFINEREG2(PFC_CTL_3, ironlake_debug_panel_fitting_3), |
| 2164 | DEFINEREG2(PFC_CTL_4, ironlake_debug_panel_fitting_4), |
| 2165 | DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win), |
| 2166 | DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win), |
| 2167 | |
| 2168 | /* PCH */ |
| 2169 | |
| 2170 | DEFINEREG2(PCH_DREF_CONTROL, ironlake_debug_dref_ctl), |
| 2171 | DEFINEREG2(PCH_RAWCLK_FREQ, ironlake_debug_rawclk_freq), |
| 2172 | DEFINEREG(PCH_DPLL_TMR_CFG), |
| 2173 | DEFINEREG(PCH_SSC4_PARMS), |
| 2174 | DEFINEREG(PCH_SSC4_AUX_PARMS), |
| 2175 | DEFINEREG2(PCH_DPLL_SEL, snb_debug_dpll_sel), |
| 2176 | DEFINEREG(PCH_DPLL_ANALOG_CTL), |
| 2177 | |
| 2178 | DEFINEREG2(PCH_DPLL_A, ironlake_debug_pch_dpll), |
| 2179 | DEFINEREG2(PCH_DPLL_B, ironlake_debug_pch_dpll), |
| 2180 | DEFINEREG2(PCH_FPA0, i830_debug_fp), |
| 2181 | DEFINEREG2(PCH_FPA1, i830_debug_fp), |
| 2182 | DEFINEREG2(PCH_FPB0, i830_debug_fp), |
| 2183 | DEFINEREG2(PCH_FPB1, i830_debug_fp), |
| 2184 | |
| 2185 | DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal), |
| 2186 | DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank), |
| 2187 | DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank), |
| 2188 | DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal), |
| 2189 | DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank), |
| 2190 | DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank), |
| 2191 | DEFINEREG(TRANS_VSYNCSHIFT_A), |
| 2192 | |
| 2193 | DEFINEREG2(TRANSA_DATA_M1, ironlake_debug_m_tu), |
| 2194 | DEFINEREG2(TRANSA_DATA_N1, ironlake_debug_n), |
| 2195 | DEFINEREG2(TRANSA_DATA_M2, ironlake_debug_m_tu), |
| 2196 | DEFINEREG2(TRANSA_DATA_N2, ironlake_debug_n), |
| 2197 | DEFINEREG2(TRANSA_DP_LINK_M1, ironlake_debug_n), |
| 2198 | DEFINEREG2(TRANSA_DP_LINK_N1, ironlake_debug_n), |
| 2199 | DEFINEREG2(TRANSA_DP_LINK_M2, ironlake_debug_n), |
| 2200 | DEFINEREG2(TRANSA_DP_LINK_N2, ironlake_debug_n), |
| 2201 | |
| 2202 | DEFINEREG2(TRANS_HTOTAL_B, i830_debug_hvtotal), |
| 2203 | DEFINEREG2(TRANS_HBLANK_B, i830_debug_hvsyncblank), |
| 2204 | DEFINEREG2(TRANS_HSYNC_B, i830_debug_hvsyncblank), |
| 2205 | DEFINEREG2(TRANS_VTOTAL_B, i830_debug_hvtotal), |
| 2206 | DEFINEREG2(TRANS_VBLANK_B, i830_debug_hvsyncblank), |
| 2207 | DEFINEREG2(TRANS_VSYNC_B, i830_debug_hvsyncblank), |
| 2208 | DEFINEREG(TRANS_VSYNCSHIFT_B), |
| 2209 | |
| 2210 | DEFINEREG2(TRANSB_DATA_M1, ironlake_debug_m_tu), |
| 2211 | DEFINEREG2(TRANSB_DATA_N1, ironlake_debug_n), |
| 2212 | DEFINEREG2(TRANSB_DATA_M2, ironlake_debug_m_tu), |
| 2213 | DEFINEREG2(TRANSB_DATA_N2, ironlake_debug_n), |
| 2214 | DEFINEREG2(TRANSB_DP_LINK_M1, ironlake_debug_n), |
| 2215 | DEFINEREG2(TRANSB_DP_LINK_N1, ironlake_debug_n), |
| 2216 | DEFINEREG2(TRANSB_DP_LINK_M2, ironlake_debug_n), |
| 2217 | DEFINEREG2(TRANSB_DP_LINK_N2, ironlake_debug_n), |
| 2218 | |
| 2219 | DEFINEREG2(TRANS_HTOTAL_C, i830_debug_hvtotal), |
| 2220 | DEFINEREG2(TRANS_HBLANK_C, i830_debug_hvsyncblank), |
| 2221 | DEFINEREG2(TRANS_HSYNC_C, i830_debug_hvsyncblank), |
| 2222 | DEFINEREG2(TRANS_VTOTAL_C, i830_debug_hvtotal), |
| 2223 | DEFINEREG2(TRANS_VBLANK_C, i830_debug_hvsyncblank), |
| 2224 | DEFINEREG2(TRANS_VSYNC_C, i830_debug_hvsyncblank), |
| 2225 | DEFINEREG(TRANS_VSYNCSHIFT_C), |
| 2226 | |
| 2227 | DEFINEREG2(TRANSC_DATA_M1, ironlake_debug_m_tu), |
| 2228 | DEFINEREG2(TRANSC_DATA_N1, ironlake_debug_n), |
| 2229 | DEFINEREG2(TRANSC_DATA_M2, ironlake_debug_m_tu), |
| 2230 | DEFINEREG2(TRANSC_DATA_N2, ironlake_debug_n), |
| 2231 | DEFINEREG2(TRANSC_DP_LINK_M1, ironlake_debug_n), |
| 2232 | DEFINEREG2(TRANSC_DP_LINK_N1, ironlake_debug_n), |
| 2233 | DEFINEREG2(TRANSC_DP_LINK_M2, ironlake_debug_n), |
| 2234 | DEFINEREG2(TRANSC_DP_LINK_N2, ironlake_debug_n), |
| 2235 | |
| 2236 | DEFINEREG2(TRANSACONF, ironlake_debug_transconf), |
| 2237 | DEFINEREG2(TRANSBCONF, ironlake_debug_transconf), |
| 2238 | DEFINEREG2(TRANSCCONF, ironlake_debug_transconf), |
| 2239 | |
| 2240 | DEFINEREG2(FDI_TXA_CTL, ironlake_debug_fdi_tx_ctl), |
| 2241 | DEFINEREG2(FDI_TXB_CTL, ironlake_debug_fdi_tx_ctl), |
| 2242 | DEFINEREG2(FDI_TXC_CTL, ironlake_debug_fdi_tx_ctl), |
| 2243 | DEFINEREG2(FDI_RXA_CTL, ironlake_debug_fdi_rx_ctl), |
| 2244 | DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl), |
| 2245 | DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl), |
| 2246 | |
| 2247 | DEFINEREG(DPAFE_BMFUNC), |
| 2248 | DEFINEREG(DPAFE_DL_IREFCAL0), |
| 2249 | DEFINEREG(DPAFE_DL_IREFCAL1), |
| 2250 | DEFINEREG(DPAFE_DP_IREFCAL), |
| 2251 | |
| 2252 | DEFINEREG(PCH_DSPCLK_GATE_D), |
| 2253 | DEFINEREG(PCH_DSP_CHICKEN1), |
| 2254 | DEFINEREG(PCH_DSP_CHICKEN2), |
| 2255 | DEFINEREG(PCH_DSP_CHICKEN3), |
| 2256 | |
| 2257 | DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc), |
| 2258 | DEFINEREG2(FDI_RXB_MISC, ironlake_debug_fdi_rx_misc), |
| 2259 | DEFINEREG2(FDI_RXC_MISC, ironlake_debug_fdi_rx_misc), |
| 2260 | DEFINEREG(FDI_RXA_TUSIZE1), |
| 2261 | DEFINEREG(FDI_RXA_TUSIZE2), |
| 2262 | DEFINEREG(FDI_RXB_TUSIZE1), |
| 2263 | DEFINEREG(FDI_RXB_TUSIZE2), |
| 2264 | DEFINEREG(FDI_RXC_TUSIZE1), |
| 2265 | DEFINEREG(FDI_RXC_TUSIZE2), |
| 2266 | |
| 2267 | DEFINEREG(FDI_PLL_CTL_1), |
| 2268 | DEFINEREG(FDI_PLL_CTL_2), |
| 2269 | |
| 2270 | DEFINEREG(FDI_RXA_IIR), |
| 2271 | DEFINEREG(FDI_RXA_IMR), |
| 2272 | DEFINEREG(FDI_RXB_IIR), |
| 2273 | DEFINEREG(FDI_RXB_IMR), |
| 2274 | |
| 2275 | DEFINEREG2(PCH_ADPA, i830_debug_adpa), |
| 2276 | DEFINEREG2(HDMIB, ironlake_debug_hdmi), |
| 2277 | DEFINEREG2(HDMIC, ironlake_debug_hdmi), |
| 2278 | DEFINEREG2(HDMID, ironlake_debug_hdmi), |
| 2279 | DEFINEREG2(PCH_LVDS, i830_debug_lvds), |
| 2280 | DEFINEREG(CPU_eDP_A), |
| 2281 | DEFINEREG(PCH_DP_B), |
| 2282 | DEFINEREG(PCH_DP_C), |
| 2283 | DEFINEREG(PCH_DP_D), |
| 2284 | DEFINEREG2(TRANS_DP_CTL_A, snb_debug_trans_dp_ctl), |
| 2285 | DEFINEREG2(TRANS_DP_CTL_B, snb_debug_trans_dp_ctl), |
| 2286 | DEFINEREG2(TRANS_DP_CTL_C, snb_debug_trans_dp_ctl), |
| 2287 | |
| 2288 | DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2), |
| 2289 | DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl), |
| 2290 | DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1), |
| 2291 | DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2), |
| 2292 | |
| 2293 | DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status), |
| 2294 | DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control), |
| 2295 | DEFINEREG(PCH_PP_ON_DELAYS), |
| 2296 | DEFINEREG(PCH_PP_OFF_DELAYS), |
| 2297 | DEFINEREG(PCH_PP_DIVISOR), |
| 2298 | |
| 2299 | DEFINEREG2(PORT_DBG, ivb_debug_port), |
| 2300 | |
| 2301 | DEFINEREG(RC6_RESIDENCY_TIME), |
| 2302 | DEFINEREG(RC6p_RESIDENCY_TIME), |
| 2303 | DEFINEREG(RC6pp_RESIDENCY_TIME), |
| 2304 | }; |
| 2305 | |
| 2306 | static const struct reg_debug haswell_debug_regs[] = { |
| 2307 | /* Power wells */ |
| 2308 | DEFINEREG(HSW_PWR_WELL_CTL1), |
| 2309 | DEFINEREG(HSW_PWR_WELL_CTL2), |
| 2310 | DEFINEREG(HSW_PWR_WELL_CTL3), |
| 2311 | DEFINEREG(HSW_PWR_WELL_CTL4), |
| 2312 | DEFINEREG(HSW_PWR_WELL_CTL5), |
| 2313 | DEFINEREG(HSW_PWR_WELL_CTL6), |
| 2314 | |
| 2315 | /* DDI pipe function */ |
| 2316 | DEFINEREG2(PIPE_DDI_FUNC_CTL_A, hsw_debug_pipe_ddi_func_ctl), |
| 2317 | DEFINEREG2(PIPE_DDI_FUNC_CTL_B, hsw_debug_pipe_ddi_func_ctl), |
| 2318 | DEFINEREG2(PIPE_DDI_FUNC_CTL_C, hsw_debug_pipe_ddi_func_ctl), |
| 2319 | DEFINEREG2(PIPE_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl), |
| 2320 | |
| 2321 | /* DP transport control */ |
| 2322 | DEFINEREG(DP_TP_CTL_A), |
| 2323 | DEFINEREG(DP_TP_CTL_B), |
| 2324 | DEFINEREG(DP_TP_CTL_C), |
| 2325 | DEFINEREG(DP_TP_CTL_D), |
| 2326 | DEFINEREG(DP_TP_CTL_E), |
| 2327 | |
| 2328 | /* DP status */ |
| 2329 | DEFINEREG(DP_TP_STATUS_B), |
| 2330 | DEFINEREG(DP_TP_STATUS_C), |
| 2331 | DEFINEREG(DP_TP_STATUS_D), |
| 2332 | DEFINEREG(DP_TP_STATUS_E), |
| 2333 | |
| 2334 | /* DDI buffer control */ |
| 2335 | DEFINEREG2(DDI_BUF_CTL_A, hsw_debug_ddi_buf_ctl), |
| 2336 | DEFINEREG2(DDI_BUF_CTL_B, hsw_debug_ddi_buf_ctl), |
| 2337 | DEFINEREG2(DDI_BUF_CTL_C, hsw_debug_ddi_buf_ctl), |
| 2338 | DEFINEREG2(DDI_BUF_CTL_D, hsw_debug_ddi_buf_ctl), |
| 2339 | DEFINEREG2(DDI_BUF_CTL_E, hsw_debug_ddi_buf_ctl), |
| 2340 | |
| 2341 | /* Clocks */ |
| 2342 | DEFINEREG(SPLL_CTL), |
| 2343 | DEFINEREG(LCPLL_CTL), |
| 2344 | DEFINEREG(WRPLL_CTL1), |
| 2345 | DEFINEREG(WRPLL_CTL2), |
| 2346 | |
| 2347 | /* DDI port clock control */ |
| 2348 | DEFINEREG2(PORT_CLK_SEL_A, hsw_debug_port_clk_sel), |
| 2349 | DEFINEREG2(PORT_CLK_SEL_B, hsw_debug_port_clk_sel), |
| 2350 | DEFINEREG2(PORT_CLK_SEL_C, hsw_debug_port_clk_sel), |
| 2351 | DEFINEREG2(PORT_CLK_SEL_D, hsw_debug_port_clk_sel), |
| 2352 | DEFINEREG2(PORT_CLK_SEL_E, hsw_debug_port_clk_sel), |
| 2353 | |
| 2354 | /* Pipe clock control */ |
| 2355 | DEFINEREG2(PIPE_CLK_SEL_A, hsw_debug_pipe_clk_sel), |
| 2356 | DEFINEREG2(PIPE_CLK_SEL_B, hsw_debug_pipe_clk_sel), |
| 2357 | DEFINEREG2(PIPE_CLK_SEL_C, hsw_debug_pipe_clk_sel), |
| 2358 | |
| 2359 | /* Watermarks */ |
| 2360 | DEFINEREG2(WM_PIPE_A, hsw_debug_wm_pipe), |
| 2361 | DEFINEREG2(WM_PIPE_B, hsw_debug_wm_pipe), |
| 2362 | DEFINEREG2(WM_PIPE_C, hsw_debug_wm_pipe), |
| 2363 | DEFINEREG2(WM_LP1, hsw_debug_lp_wm), |
| 2364 | DEFINEREG2(WM_LP2, hsw_debug_lp_wm), |
| 2365 | DEFINEREG2(WM_LP3, hsw_debug_lp_wm), |
| 2366 | DEFINEREG(WM_LP1_SPR), |
| 2367 | DEFINEREG(WM_LP2_SPR), |
| 2368 | DEFINEREG(WM_LP3_SPR), |
| 2369 | DEFINEREG(WM_MISC), |
| 2370 | DEFINEREG(WM_SR_CNT), |
| 2371 | DEFINEREG(PIPE_WM_LINETIME_A), |
| 2372 | DEFINEREG(PIPE_WM_LINETIME_B), |
| 2373 | DEFINEREG(PIPE_WM_LINETIME_C), |
| 2374 | DEFINEREG(WM_DBG), |
| 2375 | |
| 2376 | /* Fuses */ |
| 2377 | DEFINEREG2(SFUSE_STRAP, hsw_debug_sfuse_strap), |
| 2378 | |
| 2379 | /* Pipe A */ |
| 2380 | DEFINEREG2(PIPEASRC, i830_debug_yxminus1), |
| 2381 | DEFINEREG2(DSPACNTR, i830_debug_dspcntr), |
| 2382 | DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride), |
| 2383 | DEFINEREG(DSPASURF), |
| 2384 | DEFINEREG2(DSPATILEOFF, i830_debug_xy), |
| 2385 | |
| 2386 | /* Pipe B */ |
| 2387 | DEFINEREG2(PIPEBSRC, i830_debug_yxminus1), |
| 2388 | DEFINEREG2(DSPBCNTR, i830_debug_dspcntr), |
| 2389 | DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride), |
| 2390 | DEFINEREG(DSPBSURF), |
| 2391 | DEFINEREG2(DSPBTILEOFF, i830_debug_xy), |
| 2392 | |
| 2393 | /* Pipe C */ |
| 2394 | DEFINEREG2(PIPECSRC, i830_debug_yxminus1), |
| 2395 | DEFINEREG2(DSPCCNTR, i830_debug_dspcntr), |
| 2396 | DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride), |
| 2397 | DEFINEREG(DSPCSURF), |
| 2398 | DEFINEREG2(DSPCTILEOFF, i830_debug_xy), |
| 2399 | |
| 2400 | /* Transcoder A */ |
| 2401 | DEFINEREG2(PIPEACONF, i830_debug_pipeconf), |
| 2402 | DEFINEREG2(HTOTAL_A, i830_debug_hvtotal), |
| 2403 | DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank), |
| 2404 | DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank), |
| 2405 | DEFINEREG2(VTOTAL_A, i830_debug_hvtotal), |
| 2406 | DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank), |
| 2407 | DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank), |
| 2408 | DEFINEREG(VSYNCSHIFT_A), |
| 2409 | DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu), |
| 2410 | DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n), |
| 2411 | DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n), |
| 2412 | DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n), |
| 2413 | |
| 2414 | /* Transcoder B */ |
| 2415 | DEFINEREG2(PIPEBCONF, i830_debug_pipeconf), |
| 2416 | DEFINEREG2(HTOTAL_B, i830_debug_hvtotal), |
| 2417 | DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank), |
| 2418 | DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank), |
| 2419 | DEFINEREG2(VTOTAL_B, i830_debug_hvtotal), |
| 2420 | DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank), |
| 2421 | DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank), |
| 2422 | DEFINEREG(VSYNCSHIFT_B), |
| 2423 | DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu), |
| 2424 | DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n), |
| 2425 | DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n), |
| 2426 | DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n), |
| 2427 | |
| 2428 | /* Transcoder C */ |
| 2429 | DEFINEREG2(PIPECCONF, i830_debug_pipeconf), |
| 2430 | DEFINEREG2(HTOTAL_C, i830_debug_hvtotal), |
| 2431 | DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank), |
| 2432 | DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank), |
| 2433 | DEFINEREG2(VTOTAL_C, i830_debug_hvtotal), |
| 2434 | DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank), |
| 2435 | DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank), |
| 2436 | DEFINEREG(VSYNCSHIFT_C), |
| 2437 | DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu), |
| 2438 | DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n), |
| 2439 | DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n), |
| 2440 | DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n), |
| 2441 | |
| 2442 | /* Transcoder EDP */ |
| 2443 | DEFINEREG2(PIPEEDPCONF, i830_debug_pipeconf), |
| 2444 | DEFINEREG2(HTOTAL_EDP, i830_debug_hvtotal), |
| 2445 | DEFINEREG2(HBLANK_EDP, i830_debug_hvsyncblank), |
| 2446 | DEFINEREG2(HSYNC_EDP, i830_debug_hvsyncblank), |
| 2447 | DEFINEREG2(VTOTAL_EDP, i830_debug_hvtotal), |
| 2448 | DEFINEREG2(VBLANK_EDP, i830_debug_hvsyncblank), |
| 2449 | DEFINEREG2(VSYNC_EDP, i830_debug_hvsyncblank), |
| 2450 | DEFINEREG(VSYNCSHIFT_EDP), |
| 2451 | DEFINEREG2(PIPEEDP_DATA_M1, ironlake_debug_m_tu), |
| 2452 | DEFINEREG2(PIPEEDP_DATA_N1, ironlake_debug_n), |
| 2453 | DEFINEREG2(PIPEEDP_LINK_M1, ironlake_debug_n), |
| 2454 | DEFINEREG2(PIPEEDP_LINK_N1, ironlake_debug_n), |
| 2455 | |
| 2456 | /* Panel fitter */ |
| 2457 | DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting), |
| 2458 | DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win), |
| 2459 | DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win), |
| 2460 | |
| 2461 | DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting), |
| 2462 | DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win), |
| 2463 | DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win), |
| 2464 | |
| 2465 | DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting), |
| 2466 | DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win), |
| 2467 | DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win), |
| 2468 | |
| 2469 | /* LPT */ |
| 2470 | |
| 2471 | DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal), |
| 2472 | DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank), |
| 2473 | DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank), |
| 2474 | DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal), |
| 2475 | DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank), |
| 2476 | DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank), |
| 2477 | DEFINEREG(TRANS_VSYNCSHIFT_A), |
| 2478 | |
| 2479 | DEFINEREG2(TRANSACONF, ironlake_debug_transconf), |
| 2480 | |
| 2481 | DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc), |
| 2482 | DEFINEREG(FDI_RXA_TUSIZE1), |
| 2483 | DEFINEREG(FDI_RXA_IIR), |
| 2484 | DEFINEREG(FDI_RXA_IMR), |
| 2485 | |
| 2486 | DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2), |
| 2487 | DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl), |
| 2488 | DEFINEREG2(BLC_PWM2_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2), |
| 2489 | DEFINEREG2(BLC_PWM2_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl), |
| 2490 | DEFINEREG2(BLC_MISC_CTL, hsw_debug_blc_misc_ctl), |
| 2491 | DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1), |
| 2492 | DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2), |
| 2493 | |
| 2494 | DEFINEREG2(UTIL_PIN_CTL, hsw_debug_util_pin_ctl), |
| 2495 | |
| 2496 | DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status), |
| 2497 | DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control), |
| 2498 | DEFINEREG(PCH_PP_ON_DELAYS), |
| 2499 | DEFINEREG(PCH_PP_OFF_DELAYS), |
| 2500 | DEFINEREG(PCH_PP_DIVISOR), |
| 2501 | |
| 2502 | DEFINEREG(PIXCLK_GATE), |
| 2503 | |
| 2504 | DEFINEREG2(SDEISR, hsw_debug_sinterrupt), |
| 2505 | |
| 2506 | DEFINEREG(RC6_RESIDENCY_TIME), |
| 2507 | }; |
| 2508 | |
| 2509 | static const struct reg_debug i945gm_mi_regs[] = { |
| 2510 | DEFINEREG(PGETBL_CTL), |
| 2511 | DEFINEREG(PGTBL_ER), |
| 2512 | DEFINEREG(EXCC), |
| 2513 | DEFINEREG(HWS_PGA), |
| 2514 | DEFINEREG(IPEIR), |
| 2515 | DEFINEREG(IPEHR), |
| 2516 | DEFINEREG(INSTDONE), |
| 2517 | DEFINEREG(NOP_ID), |
| 2518 | DEFINEREG(HWSTAM), |
| 2519 | DEFINEREG(SCPD0), |
| 2520 | DEFINEREG(IER), |
| 2521 | DEFINEREG(IIR), |
| 2522 | DEFINEREG(IMR), |
| 2523 | DEFINEREG(ISR), |
| 2524 | DEFINEREG(EIR), |
| 2525 | DEFINEREG(EMR), |
| 2526 | DEFINEREG(ESR), |
| 2527 | DEFINEREG(INST_PM), |
| 2528 | DEFINEREG(ECOSKPD), |
| 2529 | }; |
| 2530 | |
| 2531 | DEBUGSTRING(gen6_rp_control) |
| 2532 | { |
| 2533 | snprintf(result, len, "%s", |
| 2534 | (val & (1 << 7)) ? "enabled" : "disabled"); |
| 2535 | } |
| 2536 | |
| 2537 | static const struct reg_debug gen6_rp_debug_regs[] = { |
| 2538 | DEFINEREG2(GEN6_RP_CONTROL, gen6_rp_control), |
| 2539 | DEFINEREG(GEN6_RPNSWREQ), |
| 2540 | DEFINEREG(GEN6_RP_DOWN_TIMEOUT), |
| 2541 | DEFINEREG(GEN6_RP_INTERRUPT_LIMITS), |
| 2542 | DEFINEREG(GEN6_RP_UP_THRESHOLD), |
| 2543 | DEFINEREG(GEN6_RP_UP_EI), |
| 2544 | DEFINEREG(GEN6_RP_DOWN_EI), |
| 2545 | DEFINEREG(GEN6_RP_IDLE_HYSTERSIS), |
| 2546 | DEFINEREG(GEN6_RC_STATE), |
| 2547 | DEFINEREG(GEN6_RC_CONTROL), |
| 2548 | DEFINEREG(GEN6_RC1_WAKE_RATE_LIMIT), |
| 2549 | DEFINEREG(GEN6_RC6_WAKE_RATE_LIMIT), |
| 2550 | DEFINEREG(GEN6_RC_EVALUATION_INTERVAL), |
| 2551 | DEFINEREG(GEN6_RC_IDLE_HYSTERSIS), |
| 2552 | DEFINEREG(GEN6_RC_SLEEP), |
| 2553 | DEFINEREG(GEN6_RC1e_THRESHOLD), |
| 2554 | DEFINEREG(GEN6_RC6_THRESHOLD), |
| 2555 | DEFINEREG(GEN6_RC_VIDEO_FREQ), |
| 2556 | DEFINEREG(GEN6_PMIER), |
| 2557 | DEFINEREG(GEN6_PMIMR), |
| 2558 | DEFINEREG(GEN6_PMINTRMSK), |
| 2559 | }; |
| 2560 | |
| 2561 | static bool is_hsw_plus(uint32_t devid, uint32_t pch) |
| 2562 | { |
| 2563 | return IS_HASWELL(devid) || intel_gen(devid) >= 8; |
| 2564 | } |
| 2565 | |
| 2566 | static bool is_gen6_plus(uint32_t devid, uint32_t pch) |
| 2567 | { |
| 2568 | return intel_gen(devid) >= 6; |
| 2569 | } |
| 2570 | |
| 2571 | static bool is_gen56ivb(uint32_t devid, uint32_t pch) |
| 2572 | { |
| 2573 | return IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid); |
| 2574 | } |
| 2575 | |
| 2576 | static bool is_945gm(uint32_t devid, uint32_t pch) |
| 2577 | { |
| 2578 | return IS_945GM(devid); |
| 2579 | } |
| 2580 | |
| 2581 | static bool is_gen234(uint32_t devid, uint32_t pch) |
| 2582 | { |
| 2583 | return IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN3(devid); |
| 2584 | } |
| 2585 | |
| 2586 | #define DECLARE_REGS(d,r,m) \ |
| 2587 | { .description = d, .regs = r, .count = ARRAY_SIZE(r), .match = m } |
| 2588 | static struct { |
| 2589 | const char *description; |
| 2590 | const struct reg_debug *regs; |
| 2591 | bool (*match)(uint32_t devid, uint32_t pch); |
| 2592 | int count; |
| 2593 | } known_registers[] = { |
| 2594 | DECLARE_REGS("Gen2", intel_debug_regs, is_gen234), |
| 2595 | DECLARE_REGS("i945GM", i945gm_mi_regs, is_945gm), |
| 2596 | DECLARE_REGS("Gen5", ironlake_debug_regs, is_gen56ivb), |
| 2597 | DECLARE_REGS("Gen6", gen6_rp_debug_regs, is_gen6_plus), |
| 2598 | DECLARE_REGS("Gen6+", gen6_fences, is_gen6_plus), |
| 2599 | DECLARE_REGS("Gen7.5", haswell_debug_regs, is_hsw_plus), |
| 2600 | }; |
| 2601 | #undef DECLARE_REGS |
| 2602 | |
| 2603 | /* |
| 2604 | * Decode register value into buffer for devid. |
| 2605 | * |
| 2606 | * If devid is 0, decode for all known platforms, with newline after each |
| 2607 | * decode. |
| 2608 | */ |
| 2609 | int intel_reg_spec_decode(char *buf, size_t bufsize, const struct reg *reg, |
| 2610 | uint32_t val, uint32_t devid) |
| 2611 | { |
| 2612 | char tmp[1024]; |
| 2613 | int i, j; |
| 2614 | |
| 2615 | if (!bufsize) |
| 2616 | return -1; |
| 2617 | |
| 2618 | *buf = 0; |
| 2619 | |
| 2620 | for (i = 0; i < ARRAY_SIZE(known_registers); i++) { |
| 2621 | const struct reg_debug *regs = known_registers[i].regs; |
| 2622 | |
| 2623 | if (devid) { |
| 2624 | if (known_registers[i].match && |
| 2625 | !known_registers[i].match(devid, 0)) |
| 2626 | continue; |
| 2627 | } |
| 2628 | |
| 2629 | for (j = 0; j < known_registers[i].count; j++) { |
| 2630 | const struct reg_debug *r = ®s[j]; |
| 2631 | if (reg->addr != r->reg) |
| 2632 | continue; |
| 2633 | |
| 2634 | if (r->debug_output) |
| 2635 | r->debug_output(tmp, sizeof(tmp), r->reg, |
| 2636 | val, devid); |
| 2637 | else if (devid) |
| 2638 | return 0; |
| 2639 | else |
| 2640 | continue; |
| 2641 | |
| 2642 | if (devid) { |
| 2643 | strncpy(buf, tmp, bufsize); |
| 2644 | return 0; |
| 2645 | } |
| 2646 | |
| 2647 | strncat(buf, known_registers[i].description, bufsize); |
| 2648 | strncat(buf, "\t", bufsize); |
| 2649 | strncat(buf, tmp, bufsize); |
| 2650 | strncat(buf, "\n", bufsize); |
| 2651 | } |
| 2652 | } |
| 2653 | |
| 2654 | return 0; |
| 2655 | } |
| 2656 | |
| 2657 | static ssize_t get_regs(struct reg **regs, size_t *nregs, ssize_t index, |
| 2658 | uint32_t devid) |
| 2659 | { |
| 2660 | ssize_t ret = -1; |
| 2661 | int i, j; |
| 2662 | |
| 2663 | if (!devid) |
| 2664 | return 0; |
| 2665 | |
| 2666 | for (i = 0; i < ARRAY_SIZE(known_registers); i++) { |
| 2667 | if (known_registers[i].match && |
| 2668 | !known_registers[i].match(devid, 0)) |
| 2669 | continue; |
| 2670 | |
| 2671 | for (j = 0; j < known_registers[i].count; j++) { |
| 2672 | const struct reg_debug *reg_in = |
| 2673 | &known_registers[i].regs[j]; |
| 2674 | struct reg reg; |
| 2675 | |
| 2676 | /* XXX: Could be optimized. */ |
| 2677 | parse_port_desc(®, NULL); |
| 2678 | |
| 2679 | reg.name = strdup(reg_in->name); |
| 2680 | reg.addr = reg_in->reg; |
| 2681 | |
| 2682 | if (!*regs || index >= *nregs) { |
| 2683 | if (!*regs) |
| 2684 | *nregs = 64; |
| 2685 | else |
| 2686 | *nregs *= 2; |
| 2687 | |
| 2688 | *regs = recalloc(*regs, *nregs, sizeof(**regs)); |
| 2689 | if (!*regs) { |
| 2690 | fprintf(stderr, "Error: %s\n", strerror(ENOMEM)); |
| 2691 | goto out; |
| 2692 | } |
| 2693 | } |
| 2694 | |
| 2695 | (*regs)[index++] = reg; |
| 2696 | } |
| 2697 | } |
| 2698 | |
| 2699 | ret = index; |
| 2700 | |
| 2701 | out: |
| 2702 | return ret; |
| 2703 | } |
| 2704 | |
| 2705 | /* |
| 2706 | * Get builtin register definitions for devid. |
| 2707 | */ |
| 2708 | ssize_t intel_reg_spec_builtin(struct reg **regs, uint32_t devid) |
| 2709 | { |
| 2710 | size_t nregs = 0; |
| 2711 | *regs = NULL; |
| 2712 | |
| 2713 | return get_regs(regs, &nregs, 0, devid); |
| 2714 | } |