blob: 2351ce91511ff76ee72a5e6b2aebd4e48bc1cd03 [file] [log] [blame]
Chris Wilsondaa9e3d2014-05-15 08:43:11 +01001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <chris@chris-wilson.co.uk>
25 *
26 */
27
Thomas Wood804e11f2015-08-17 17:57:43 +010028#include "igt.h"
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010029#include <unistd.h>
30#include <stdlib.h>
31#include <stdint.h>
32#include <stdio.h>
33#include <string.h>
34#include <fcntl.h>
35#include <inttypes.h>
36#include <errno.h>
37#include <sys/stat.h>
38#include <sys/ioctl.h>
39#include <sys/time.h>
40#include "drm.h"
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010041
Thomas Woodb2ac2642014-11-28 11:02:44 +000042IGT_TEST_DESCRIPTION("Simulates SNA behaviour using negative self-relocations"
43 " for STATE_BASE_ADDRESS command packets.");
44
Chris Wilsonefd5a572014-05-15 13:10:21 +010045#define USE_LUT (1 << 12)
Chris Wilson1430eb02016-03-14 20:40:53 +000046#define BIAS (256*1024)
Chris Wilsonefd5a572014-05-15 13:10:21 +010047
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010048/* Simulates SNA behaviour using negative self-relocations for
49 * STATE_BASE_ADDRESS command packets. If they wrap around (to values greater
50 * than the total size of the GTT), the GPU will hang.
51 * See https://bugs.freedesktop.org/show_bug.cgi?id=78533
52 */
Chris Wilson1430eb02016-03-14 20:40:53 +000053static void negative_reloc(int fd, unsigned engine, unsigned flags)
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010054{
55 struct drm_i915_gem_execbuffer2 execbuf;
Chris Wilson1430eb02016-03-14 20:40:53 +000056 struct drm_i915_gem_exec_object2 obj;
57 struct drm_i915_gem_relocation_entry reloc[1000];
Chris Wilson391b32c2016-02-05 18:35:21 +000058 uint64_t gtt_max = gem_aperture_size(fd);
Chris Wilson1430eb02016-03-14 20:40:53 +000059 uint32_t bbe = MI_BATCH_BUFFER_END;
60 uint64_t *offsets;
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010061 int i;
62
Chris Wilson1430eb02016-03-14 20:40:53 +000063 gem_require_ring(fd, engine);
Chris Wilsonef519882014-05-15 13:23:44 +010064 igt_require(intel_gen(intel_get_drm_devid(fd)) >= 7);
65
Chris Wilson1430eb02016-03-14 20:40:53 +000066 memset(&obj, 0, sizeof(obj));
67 obj.handle = gem_create(fd, 8192);
68 gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010069
70 memset(&execbuf, 0, sizeof(execbuf));
Chris Wilson1430eb02016-03-14 20:40:53 +000071 execbuf.buffers_ptr = (uintptr_t)&obj;
72 execbuf.buffer_count = 1;
73 execbuf.flags = engine | (flags & USE_LUT);
74 igt_require(__gem_execbuf(fd, &execbuf) == 0);
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010075
Chris Wilson1430eb02016-03-14 20:40:53 +000076 igt_info("Found offset %lld for 4k batch\n", (long long)obj.offset);
Damien Lespiau88ff1ce2014-12-04 13:42:12 +000077 /*
78 * Ideally we'd like to be able to control where the kernel is going to
79 * place the buffer. We don't SKIP here because it causes the test
80 * to "randomly" flip-flop between the SKIP and PASS states.
81 */
Chris Wilson1430eb02016-03-14 20:40:53 +000082 if (obj.offset < BIAS) {
Damien Lespiau88ff1ce2014-12-04 13:42:12 +000083 igt_info("Offset is below BIAS, not testing anything\n");
Chris Wilson1430eb02016-03-14 20:40:53 +000084 return;
Damien Lespiau88ff1ce2014-12-04 13:42:12 +000085 }
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010086
Chris Wilson1430eb02016-03-14 20:40:53 +000087 memset(reloc, 0, sizeof(reloc));
88 for (i = 0; i < ARRAY_SIZE(reloc); i++) {
89 reloc[i].offset = 8 + 8*i;
90 reloc[i].delta = -BIAS*i/1024;
91 reloc[i].presumed_offset = -1;
92 reloc[i].target_handle = flags & USE_LUT ? 0 : obj.handle;
93 reloc[i].read_domains = I915_GEM_DOMAIN_COMMAND;
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010094 }
Chris Wilson1430eb02016-03-14 20:40:53 +000095 obj.relocation_count = i;
96 obj.relocs_ptr = (uintptr_t)reloc;
97 gem_execbuf(fd, &execbuf);
Chris Wilsondaa9e3d2014-05-15 08:43:11 +010098
Chris Wilson1430eb02016-03-14 20:40:53 +000099 igt_info("Batch is now at offset %#llx, max GTT %#llx\n",
100 (long long)obj.offset, (long long)gtt_max);
Chris Wilsondaa9e3d2014-05-15 08:43:11 +0100101
Chris Wilson1430eb02016-03-14 20:40:53 +0000102 offsets = gem_mmap__cpu(fd, obj.handle, 0, 8192, PROT_READ);
103 gem_set_domain(fd, obj.handle, I915_GEM_DOMAIN_CPU, 0);
104 gem_close(fd, obj.handle);
Chris Wilsondaa9e3d2014-05-15 08:43:11 +0100105
Chris Wilson1430eb02016-03-14 20:40:53 +0000106 for (i = 0; i < ARRAY_SIZE(reloc); i++)
107 igt_assert_f(offsets[1 + i] < gtt_max,
108 "Offset[%d]=%#llx, expected less than %#llx\n",
109 i, (long long)offsets[i+i], (long long)gtt_max);
110 munmap(offsets, 8192);
Chris Wilsondaa9e3d2014-05-15 08:43:11 +0100111}
112
Chris Wilson1430eb02016-03-14 20:40:53 +0000113static void negative_reloc_blt(int fd)
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100114{
115 const int gen = intel_gen(intel_get_drm_devid(fd));
116 struct drm_i915_gem_execbuffer2 execbuf;
Chris Wilson1430eb02016-03-14 20:40:53 +0000117 struct drm_i915_gem_exec_object2 obj[1024][2];
118 struct drm_i915_gem_relocation_entry reloc;
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100119 uint32_t buf[1024], *b;
120 int i;
121
Chris Wilson1430eb02016-03-14 20:40:53 +0000122 memset(&reloc, 0, sizeof(reloc));
123 reloc.offset = 4 * sizeof(uint32_t);
124 reloc.presumed_offset = ~0ULL;
125 reloc.delta = -4096;
126 reloc.target_handle = 0;
127 reloc.read_domains = I915_GEM_DOMAIN_RENDER;
128 reloc.write_domain = I915_GEM_DOMAIN_RENDER;
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100129
130 for (i = 0; i < 1024; i++) {
Chris Wilson1430eb02016-03-14 20:40:53 +0000131 memset(obj[i], 0, sizeof(obj[i]));
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100132
Chris Wilson1430eb02016-03-14 20:40:53 +0000133 obj[i][0].handle = gem_create(fd, 4096);
134 obj[i][0].flags = EXEC_OBJECT_NEEDS_FENCE;
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100135
136 b = buf;
137 *b++ = XY_COLOR_BLT_CMD_NOLEN |
138 ((gen >= 8) ? 5 : 4) |
139 COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
140 *b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096;
141 *b++ = 1 << 16 | 0;
142 *b++ = 2 << 16 | 1024;
Chris Wilson8aa7fda2014-10-14 10:10:42 +0100143 *b++ = ~0;
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100144 if (gen >= 8)
Chris Wilson8aa7fda2014-10-14 10:10:42 +0100145 *b++ = ~0;
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100146 *b++ = 0xc0ffee ^ i;
147 *b++ = MI_BATCH_BUFFER_END;
148 if ((b - buf) & 1)
149 *b++ = 0;
150
Chris Wilson1430eb02016-03-14 20:40:53 +0000151 obj[i][1].handle = gem_create(fd, 4096);
152 gem_write(fd, obj[i][1].handle, 0, buf, (b - buf) * sizeof(uint32_t));
153 obj[i][1].relocation_count = 1;
154 obj[i][1].relocs_ptr = (uintptr_t)&reloc;
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100155 }
156
157 memset(&execbuf, 0, sizeof(execbuf));
158 execbuf.buffer_count = 2;
159 execbuf.batch_len = (b - buf) * sizeof(uint32_t);
160 execbuf.flags = USE_LUT;
161 if (gen >= 6)
162 execbuf.flags |= I915_EXEC_BLT;
163
164 for (i = 0; i < 1024; i++) {
Chris Wilson1430eb02016-03-14 20:40:53 +0000165 execbuf.buffers_ptr = (uintptr_t)obj[i];
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100166 gem_execbuf(fd, &execbuf);
167 }
168
169 for (i = 1024; i--;) {
Chris Wilson1430eb02016-03-14 20:40:53 +0000170 gem_read(fd, obj[i][0].handle,
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100171 i*sizeof(uint32_t), buf + i, sizeof(uint32_t));
Chris Wilson1430eb02016-03-14 20:40:53 +0000172 gem_close(fd, obj[i][0].handle);
173 gem_close(fd, obj[i][1].handle);
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100174 }
175
176 if (0) {
177 for (i = 0; i < 1024; i += 8)
Daniel Vetter8b556f72014-10-23 17:54:44 +0200178 igt_info("%08x %08x %08x %08x %08x %08x %08x %08x\n",
179 buf[i + 0], buf[i + 1], buf[i + 2], buf[i + 3],
180 buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]);
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100181 }
182 for (i = 0; i < 1024; i++)
183 igt_assert_eq(buf[i], 0xc0ffee ^ i);
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100184}
185
Chris Wilsondaa9e3d2014-05-15 08:43:11 +0100186igt_main
187{
Chris Wilson1430eb02016-03-14 20:40:53 +0000188 const struct intel_execution_engine *e;
189 int fd = -1;
190
191 igt_fixture
Micah Fedkec81d2932015-07-22 21:54:02 +0000192 fd = drm_open_driver(DRIVER_INTEL);
Chris Wilson1430eb02016-03-14 20:40:53 +0000193
194 for (e = intel_execution_engines; e->name; e++) {
195 igt_subtest_f("negative-reloc-%s", e->name)
196 negative_reloc(fd, e->exec_id | e->flags, 0);
197
198 igt_subtest_f("negative-reloc-lut-%s", e->name)
199 negative_reloc(fd, e->exec_id | e->flags, USE_LUT);
Chris Wilsondaa9e3d2014-05-15 08:43:11 +0100200 }
201
Chris Wilson314fa172016-03-15 09:44:48 +0000202 igt_subtest("negative-reloc-bltcopy")
Chris Wilsoncd5ed452014-10-14 09:27:40 +0100203 negative_reloc_blt(fd);
204
Chris Wilson1430eb02016-03-14 20:40:53 +0000205 igt_fixture
Chris Wilsondaa9e3d2014-05-15 08:43:11 +0100206 close(fd);
Chris Wilsondaa9e3d2014-05-15 08:43:11 +0100207}