blob: e2be147c90178f7e850cd5a321cd1570133cec13 [file] [log] [blame]
Eric Anholt22a10632006-08-22 10:15:33 -07001 /**************************************************************************
2 *
3 * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#ifndef BRW_STRUCTS_H
29#define BRW_STRUCTS_H
30
31/* Command packets:
32 */
33struct header
34{
35 GLuint length:16;
36 GLuint opcode:16;
37} bits;
38
39
40union header_union
41{
42 struct header bits;
43 GLuint dword;
44};
45
46struct brw_3d_control
47{
48 struct
49 {
50 GLuint length:8;
51 GLuint notify_enable:1;
52 GLuint pad:3;
53 GLuint wc_flush_enable:1;
54 GLuint depth_stall_enable:1;
55 GLuint operation:2;
56 GLuint opcode:16;
57 } header;
58
59 struct
60 {
61 GLuint pad:2;
62 GLuint dest_addr_type:1;
63 GLuint dest_addr:29;
64 } dest;
65
66 GLuint dword2;
67 GLuint dword3;
68};
69
70
71struct brw_3d_primitive
72{
73 struct
74 {
75 GLuint length:8;
76 GLuint pad:2;
77 GLuint topology:5;
78 GLuint indexed:1;
79 GLuint opcode:16;
80 } header;
81
82 GLuint verts_per_instance;
83 GLuint start_vert_location;
84 GLuint instance_count;
85 GLuint start_instance_location;
86 GLuint base_vert_location;
87};
88
89/* These seem to be passed around as function args, so it works out
90 * better to keep them as #defines:
91 */
92#define BRW_FLUSH_READ_CACHE 0x1
93#define BRW_FLUSH_STATE_CACHE 0x2
94#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
95#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8
96
97struct brw_mi_flush
98{
99 GLuint flags:4;
100 GLuint pad:12;
101 GLuint opcode:16;
102};
103
104struct brw_vf_statistics
105{
106 GLuint statistics_enable:1;
107 GLuint pad:15;
108 GLuint opcode:16;
109};
110
111
112
113struct brw_binding_table_pointers
114{
115 struct header header;
116 GLuint vs;
117 GLuint gs;
118 GLuint clp;
119 GLuint sf;
120 GLuint wm;
121};
122
123
124struct brw_blend_constant_color
125{
126 struct header header;
127 GLfloat blend_constant_color[4];
128};
129
130
131struct brw_depthbuffer
132{
133 union header_union header;
134
135 union {
136 struct {
137 GLuint pitch:18;
138 GLuint format:3;
139 GLuint pad:4;
140 GLuint depth_offset_disable:1;
141 GLuint tile_walk:1;
142 GLuint tiled_surface:1;
143 GLuint pad2:1;
144 GLuint surface_type:3;
145 } bits;
146 GLuint dword;
147 } dword1;
148
149 GLuint dword2_base_addr;
150
151 union {
152 struct {
153 GLuint pad:1;
154 GLuint mipmap_layout:1;
155 GLuint lod:4;
156 GLuint width:13;
157 GLuint height:13;
158 } bits;
159 GLuint dword;
160 } dword3;
161
162 union {
163 struct {
164 GLuint pad:12;
165 GLuint min_array_element:9;
166 GLuint depth:11;
167 } bits;
168 GLuint dword;
169 } dword4;
170};
171
172struct brw_drawrect
173{
174 struct header header;
175 GLuint xmin:16;
176 GLuint ymin:16;
177 GLuint xmax:16;
178 GLuint ymax:16;
179 GLuint xorg:16;
180 GLuint yorg:16;
181};
182
183
184
185
186struct brw_global_depth_offset_clamp
187{
188 struct header header;
189 GLfloat depth_offset_clamp;
190};
191
192struct brw_indexbuffer
193{
194 union {
195 struct
196 {
197 GLuint length:8;
198 GLuint index_format:2;
199 GLuint cut_index_enable:1;
200 GLuint pad:5;
201 GLuint opcode:16;
202 } bits;
203 GLuint dword;
204
205 } header;
206
207 GLuint buffer_start;
208 GLuint buffer_end;
209};
210
211
212struct brw_line_stipple
213{
214 struct header header;
215
216 struct
217 {
218 GLuint pattern:16;
219 GLuint pad:16;
220 } bits0;
221
222 struct
223 {
224 GLuint repeat_count:9;
225 GLuint pad:7;
226 GLuint inverse_repeat_count:16;
227 } bits1;
228};
229
230
231struct brw_pipelined_state_pointers
232{
233 struct header header;
234
235 struct {
236 GLuint pad:5;
237 GLuint offset:27;
238 } vs;
239
240 struct
241 {
242 GLuint enable:1;
243 GLuint pad:4;
244 GLuint offset:27;
245 } gs;
246
247 struct
248 {
249 GLuint enable:1;
250 GLuint pad:4;
251 GLuint offset:27;
252 } clp;
253
254 struct
255 {
256 GLuint pad:5;
257 GLuint offset:27;
258 } sf;
259
260 struct
261 {
262 GLuint pad:5;
263 GLuint offset:27;
264 } wm;
265
266 struct
267 {
268 GLuint pad:5;
269 GLuint offset:27; /* KW: check me! */
270 } cc;
271};
272
273
274struct brw_polygon_stipple_offset
275{
276 struct header header;
277
278 struct {
279 GLuint y_offset:5;
280 GLuint pad:3;
281 GLuint x_offset:5;
282 GLuint pad0:19;
283 } bits0;
284};
285
286
287
288struct brw_polygon_stipple
289{
290 struct header header;
291 GLuint stipple[32];
292};
293
294
295
296struct brw_pipeline_select
297{
298 struct
299 {
300 GLuint pipeline_select:1;
301 GLuint pad:15;
302 GLuint opcode:16;
303 } header;
304};
305
306
307struct brw_pipe_control
308{
309 struct
310 {
311 GLuint length:8;
312 GLuint notify_enable:1;
313 GLuint pad:2;
314 GLuint instruction_state_cache_flush_enable:1;
315 GLuint write_cache_flush_enable:1;
316 GLuint depth_stall_enable:1;
317 GLuint post_sync_operation:2;
318
319 GLuint opcode:16;
320 } header;
321
322 struct
323 {
324 GLuint pad:2;
325 GLuint dest_addr_type:1;
326 GLuint dest_addr:29;
327 } bits1;
328
329 GLuint data0;
330 GLuint data1;
331};
332
333
334struct brw_urb_fence
335{
336 struct
337 {
338 GLuint length:8;
339 GLuint vs_realloc:1;
340 GLuint gs_realloc:1;
341 GLuint clp_realloc:1;
342 GLuint sf_realloc:1;
343 GLuint vfe_realloc:1;
344 GLuint cs_realloc:1;
345 GLuint pad:2;
346 GLuint opcode:16;
347 } header;
348
349 struct
350 {
351 GLuint vs_fence:10;
352 GLuint gs_fence:10;
353 GLuint clp_fence:10;
354 GLuint pad:2;
355 } bits0;
356
357 struct
358 {
359 GLuint sf_fence:10;
360 GLuint vf_fence:10;
361 GLuint cs_fence:10;
362 GLuint pad:2;
363 } bits1;
364};
365
366struct brw_constant_buffer_state /* previously brw_command_streamer */
367{
368 struct header header;
369
370 struct
371 {
372 GLuint nr_urb_entries:3;
373 GLuint pad:1;
374 GLuint urb_entry_size:5;
375 GLuint pad0:23;
376 } bits0;
377};
378
379struct brw_constant_buffer
380{
381 struct
382 {
383 GLuint length:8;
384 GLuint valid:1;
385 GLuint pad:7;
386 GLuint opcode:16;
387 } header;
388
389 struct
390 {
391 GLuint buffer_length:6;
392 GLuint buffer_address:26;
393 } bits0;
394};
395
396struct brw_state_base_address
397{
398 struct header header;
399
400 struct
401 {
402 GLuint modify_enable:1;
403 GLuint pad:4;
404 GLuint general_state_address:27;
405 } bits0;
406
407 struct
408 {
409 GLuint modify_enable:1;
410 GLuint pad:4;
411 GLuint surface_state_address:27;
412 } bits1;
413
414 struct
415 {
416 GLuint modify_enable:1;
417 GLuint pad:4;
418 GLuint indirect_object_state_address:27;
419 } bits2;
420
421 struct
422 {
423 GLuint modify_enable:1;
424 GLuint pad:11;
425 GLuint general_state_upper_bound:20;
426 } bits3;
427
428 struct
429 {
430 GLuint modify_enable:1;
431 GLuint pad:11;
432 GLuint indirect_object_state_upper_bound:20;
433 } bits4;
434};
435
436struct brw_state_prefetch
437{
438 struct header header;
439
440 struct
441 {
442 GLuint prefetch_count:3;
443 GLuint pad:3;
444 GLuint prefetch_pointer:26;
445 } bits0;
446};
447
448struct brw_system_instruction_pointer
449{
450 struct header header;
451
452 struct
453 {
454 GLuint pad:4;
455 GLuint system_instruction_pointer:28;
456 } bits0;
457};
458
459
460
461
462/* State structs for the various fixed function units:
463 */
464
465
466struct thread0
467{
468 GLuint pad0:1;
469 GLuint grf_reg_count:3;
470 GLuint pad1:2;
471 GLuint kernel_start_pointer:26;
472};
473
474struct thread1
475{
476 GLuint ext_halt_exception_enable:1;
477 GLuint sw_exception_enable:1;
478 GLuint mask_stack_exception_enable:1;
479 GLuint timeout_exception_enable:1;
480 GLuint illegal_op_exception_enable:1;
481 GLuint pad0:3;
482 GLuint depth_coef_urb_read_offset:6; /* WM only */
483 GLuint pad1:2;
484 GLuint floating_point_mode:1;
485 GLuint thread_priority:1;
486 GLuint binding_table_entry_count:8;
487 GLuint pad3:5;
488 GLuint single_program_flow:1;
489};
490
491struct thread2
492{
493 GLuint per_thread_scratch_space:4;
494 GLuint pad0:6;
495 GLuint scratch_space_base_pointer:22;
496};
497
498
499struct thread3
500{
501 GLuint dispatch_grf_start_reg:4;
502 GLuint urb_entry_read_offset:6;
503 GLuint pad0:1;
504 GLuint urb_entry_read_length:6;
505 GLuint pad1:1;
506 GLuint const_urb_entry_read_offset:6;
507 GLuint pad2:1;
508 GLuint const_urb_entry_read_length:6;
509 GLuint pad3:1;
510};
511
512
513
514struct brw_clip_unit_state
515{
516 struct thread0 thread0;
517 struct thread1 thread1;
518 struct thread2 thread2;
519 struct thread3 thread3;
520
521 struct
522 {
523 GLuint pad0:9;
524 GLuint gs_output_stats:1; /* not always */
525 GLuint stats_enable:1;
526 GLuint nr_urb_entries:7;
527 GLuint pad1:1;
528 GLuint urb_entry_allocation_size:5;
529 GLuint pad2:1;
530 GLuint max_threads:6; /* may be less */
531 GLuint pad3:1;
532 } thread4;
533
534 struct
535 {
536 GLuint pad0:13;
537 GLuint clip_mode:3;
538 GLuint userclip_enable_flags:8;
539 GLuint userclip_must_clip:1;
540 GLuint pad1:1;
541 GLuint guard_band_enable:1;
542 GLuint viewport_z_clip_enable:1;
543 GLuint viewport_xy_clip_enable:1;
544 GLuint vertex_position_space:1;
545 GLuint api_mode:1;
546 GLuint pad2:1;
547 } clip5;
548
549 struct
550 {
551 GLuint pad0:5;
552 GLuint clipper_viewport_state_ptr:27;
553 } clip6;
554
555
556 GLfloat viewport_xmin;
557 GLfloat viewport_xmax;
558 GLfloat viewport_ymin;
559 GLfloat viewport_ymax;
560};
561
562
563
564struct brw_cc_unit_state
565{
566 struct
567 {
568 GLuint pad0:3;
569 GLuint bf_stencil_pass_depth_pass_op:3;
570 GLuint bf_stencil_pass_depth_fail_op:3;
571 GLuint bf_stencil_fail_op:3;
572 GLuint bf_stencil_func:3;
573 GLuint bf_stencil_enable:1;
574 GLuint pad1:2;
575 GLuint stencil_write_enable:1;
576 GLuint stencil_pass_depth_pass_op:3;
577 GLuint stencil_pass_depth_fail_op:3;
578 GLuint stencil_fail_op:3;
579 GLuint stencil_func:3;
580 GLuint stencil_enable:1;
581 } cc0;
582
583
584 struct
585 {
586 GLuint bf_stencil_ref:8;
587 GLuint stencil_write_mask:8;
588 GLuint stencil_test_mask:8;
589 GLuint stencil_ref:8;
590 } cc1;
591
592
593 struct
594 {
595 GLuint logicop_enable:1;
596 GLuint pad0:10;
597 GLuint depth_write_enable:1;
598 GLuint depth_test_function:3;
599 GLuint depth_test:1;
600 GLuint bf_stencil_write_mask:8;
601 GLuint bf_stencil_test_mask:8;
602 } cc2;
603
604
605 struct
606 {
607 GLuint pad0:8;
608 GLuint alpha_test_func:3;
609 GLuint alpha_test:1;
610 GLuint blend_enable:1;
611 GLuint ia_blend_enable:1;
612 GLuint pad1:1;
613 GLuint alpha_test_format:1;
614 GLuint pad2:16;
615 } cc3;
616
617 struct
618 {
619 GLuint pad0:5;
620 GLuint cc_viewport_state_offset:27;
621 } cc4;
622
623 struct
624 {
625 GLuint pad0:2;
626 GLuint ia_dest_blend_factor:5;
627 GLuint ia_src_blend_factor:5;
628 GLuint ia_blend_function:3;
629 GLuint statistics_enable:1;
630 GLuint logicop_func:4;
631 GLuint pad1:11;
632 GLuint dither_enable:1;
633 } cc5;
634
635 struct
636 {
637 GLuint clamp_post_alpha_blend:1;
638 GLuint clamp_pre_alpha_blend:1;
639 GLuint clamp_range:2;
640 GLuint pad0:11;
641 GLuint y_dither_offset:2;
642 GLuint x_dither_offset:2;
643 GLuint dest_blend_factor:5;
644 GLuint src_blend_factor:5;
645 GLuint blend_function:3;
646 } cc6;
647
648 struct {
649 union {
650 GLfloat f;
651 GLubyte ub[4];
652 } alpha_ref;
653 } cc7;
654};
655
656
657
658struct brw_sf_unit_state
659{
660 struct thread0 thread0;
661 struct thread1 thread1;
662 struct thread2 thread2;
663 struct thread3 thread3;
664
665 struct
666 {
667 GLuint pad0:10;
668 GLuint stats_enable:1;
669 GLuint nr_urb_entries:7;
670 GLuint pad1:1;
671 GLuint urb_entry_allocation_size:5;
672 GLuint pad2:1;
673 GLuint max_threads:6;
674 GLuint pad3:1;
675 } thread4;
676
677 struct
678 {
679 GLuint front_winding:1;
680 GLuint viewport_transform:1;
681 GLuint pad0:3;
682 GLuint sf_viewport_state_offset:27;
683 } sf5;
684
685 struct
686 {
687 GLuint pad0:9;
688 GLuint dest_org_vbias:4;
689 GLuint dest_org_hbias:4;
690 GLuint scissor:1;
691 GLuint disable_2x2_trifilter:1;
692 GLuint disable_zero_pix_trifilter:1;
693 GLuint point_rast_rule:2;
694 GLuint line_endcap_aa_region_width:2;
695 GLuint line_width:4;
696 GLuint fast_scissor_disable:1;
697 GLuint cull_mode:2;
698 GLuint aa_enable:1;
699 } sf6;
700
701 struct
702 {
703 GLuint point_size:11;
704 GLuint use_point_size_state:1;
705 GLuint subpixel_precision:1;
706 GLuint sprite_point:1;
707 GLuint pad0:11;
708 GLuint trifan_pv:2;
709 GLuint linestrip_pv:2;
710 GLuint tristrip_pv:2;
711 GLuint line_last_pixel_enable:1;
712 } sf7;
713
714};
715
716
717struct brw_gs_unit_state
718{
719 struct thread0 thread0;
720 struct thread1 thread1;
721 struct thread2 thread2;
722 struct thread3 thread3;
723
724 struct
725 {
726 GLuint pad0:10;
727 GLuint stats_enable:1;
728 GLuint nr_urb_entries:7;
729 GLuint pad1:1;
730 GLuint urb_entry_allocation_size:5;
731 GLuint pad2:1;
732 GLuint max_threads:1;
733 GLuint pad3:6;
734 } thread4;
735
736 struct
737 {
738 GLuint sampler_count:3;
739 GLuint pad0:2;
740 GLuint sampler_state_pointer:27;
741 } gs5;
742
743
744 struct
745 {
746 GLuint max_vp_index:4;
747 GLuint pad0:26;
748 GLuint reorder_enable:1;
749 GLuint pad1:1;
750 } gs6;
751};
752
753
754struct brw_vs_unit_state
755{
756 struct thread0 thread0;
757 struct thread1 thread1;
758 struct thread2 thread2;
759 struct thread3 thread3;
760
761 struct
762 {
763 GLuint pad0:10;
764 GLuint stats_enable:1;
765 GLuint nr_urb_entries:7;
766 GLuint pad1:1;
767 GLuint urb_entry_allocation_size:5;
768 GLuint pad2:1;
769 GLuint max_threads:4;
770 GLuint pad3:3;
771 } thread4;
772
773 struct
774 {
775 GLuint sampler_count:3;
776 GLuint pad0:2;
777 GLuint sampler_state_pointer:27;
778 } vs5;
779
780 struct
781 {
782 GLuint vs_enable:1;
783 GLuint vert_cache_disable:1;
784 GLuint pad0:30;
785 } vs6;
786};
787
788
789struct brw_wm_unit_state
790{
791 struct thread0 thread0;
792 struct thread1 thread1;
793 struct thread2 thread2;
794 struct thread3 thread3;
795
796 struct {
797 GLuint stats_enable:1;
798 GLuint pad0:1;
799 GLuint sampler_count:3;
800 GLuint sampler_state_pointer:27;
801 } wm4;
802
803 struct
804 {
805 GLuint enable_8_pix:1;
806 GLuint enable_16_pix:1;
807 GLuint enable_32_pix:1;
808 GLuint pad0:7;
809 GLuint legacy_global_depth_bias:1;
810 GLuint line_stipple:1;
811 GLuint depth_offset:1;
812 GLuint polygon_stipple:1;
813 GLuint line_aa_region_width:2;
814 GLuint line_endcap_aa_region_width:2;
815 GLuint early_depth_test:1;
816 GLuint thread_dispatch_enable:1;
817 GLuint program_uses_depth:1;
818 GLuint program_computes_depth:1;
819 GLuint program_uses_killpixel:1;
820 GLuint legacy_line_rast: 1;
821 GLuint pad1:1;
822 GLuint max_threads:6;
823 GLuint pad2:1;
824 } wm5;
825
826 GLfloat global_depth_offset_constant;
827 GLfloat global_depth_offset_scale;
828};
829
830struct brw_sampler_default_color {
831 GLfloat color[4];
832};
833
834struct brw_sampler_state
835{
836
837 struct
838 {
839 GLuint shadow_function:3;
840 GLuint lod_bias:11;
841 GLuint min_filter:3;
842 GLuint mag_filter:3;
843 GLuint mip_filter:2;
844 GLuint base_level:5;
845 GLuint pad:1;
846 GLuint lod_preclamp:1;
847 GLuint default_color_mode:1;
848 GLuint pad0:1;
849 GLuint disable:1;
850 } ss0;
851
852 struct
853 {
854 GLuint r_wrap_mode:3;
855 GLuint t_wrap_mode:3;
856 GLuint s_wrap_mode:3;
857 GLuint pad:3;
858 GLuint max_lod:10;
859 GLuint min_lod:10;
860 } ss1;
861
862
863 struct
864 {
865 GLuint pad:5;
866 GLuint default_color_pointer:27;
867 } ss2;
868
869 struct
870 {
871 GLuint pad:19;
872 GLuint max_aniso:3;
873 GLuint chroma_key_mode:1;
874 GLuint chroma_key_index:2;
875 GLuint chroma_key_enable:1;
876 GLuint monochrome_filter_width:3;
877 GLuint monochrome_filter_height:3;
878 } ss3;
879};
880
881
882struct brw_clipper_viewport
883{
884 GLfloat xmin;
885 GLfloat xmax;
886 GLfloat ymin;
887 GLfloat ymax;
888};
889
890struct brw_cc_viewport
891{
892 GLfloat min_depth;
893 GLfloat max_depth;
894};
895
896struct brw_sf_viewport
897{
898 struct {
899 GLfloat m00;
900 GLfloat m11;
901 GLfloat m22;
902 GLfloat m30;
903 GLfloat m31;
904 GLfloat m32;
905 } viewport;
906
907 struct {
908 GLshort xmin;
909 GLshort ymin;
910 GLshort xmax;
911 GLshort ymax;
912 } scissor;
913};
914
915/* Documented in the subsystem/shared-functions/sampler chapter...
916 */
917struct brw_surface_state
918{
919 struct {
920 GLuint cube_pos_z:1;
921 GLuint cube_neg_z:1;
922 GLuint cube_pos_y:1;
923 GLuint cube_neg_y:1;
924 GLuint cube_pos_x:1;
925 GLuint cube_neg_x:1;
926 GLuint pad:4;
927 GLuint mipmap_layout_mode:1;
928 GLuint vert_line_stride_ofs:1;
929 GLuint vert_line_stride:1;
930 GLuint color_blend:1;
931 GLuint writedisable_blue:1;
932 GLuint writedisable_green:1;
933 GLuint writedisable_red:1;
934 GLuint writedisable_alpha:1;
935 GLuint surface_format:9;
936 GLuint data_return_format:1;
937 GLuint pad0:1;
938 GLuint surface_type:3;
939 } ss0;
940
941 struct {
942 GLuint base_addr;
943 } ss1;
944
945 struct {
946 GLuint pad:2;
947 GLuint mip_count:4;
948 GLuint width:13;
949 GLuint height:13;
950 } ss2;
951
952 struct {
953 GLuint tile_walk:1;
954 GLuint tiled_surface:1;
955 GLuint pad:1;
956 GLuint pitch:18;
957 GLuint depth:11;
958 } ss3;
959
960 struct {
961 GLuint pad:19;
962 GLuint min_array_elt:9;
963 GLuint min_lod:4;
964 } ss4;
965};
966
967
968
969struct brw_vertex_buffer_state
970{
971 struct {
972 GLuint pitch:11;
973 GLuint pad:15;
974 GLuint access_type:1;
975 GLuint vb_index:5;
976 } vb0;
977
978 GLuint start_addr;
979 GLuint max_index;
980#if 1
981 GLuint instance_data_step_rate; /* not included for sequential/random vertices? */
982#endif
983};
984
985#define BRW_VBP_MAX 17
986
987struct brw_vb_array_state {
988 struct header header;
989 struct brw_vertex_buffer_state vb[BRW_VBP_MAX];
990};
991
992
993struct brw_vertex_element_state
994{
995 struct
996 {
997 GLuint src_offset:11;
998 GLuint pad:5;
999 GLuint src_format:9;
1000 GLuint pad0:1;
1001 GLuint valid:1;
1002 GLuint vertex_buffer_index:5;
1003 } ve0;
1004
1005 struct
1006 {
1007 GLuint dst_offset:8;
1008 GLuint pad:8;
1009 GLuint vfcomponent3:4;
1010 GLuint vfcomponent2:4;
1011 GLuint vfcomponent1:4;
1012 GLuint vfcomponent0:4;
1013 } ve1;
1014};
1015
1016#define BRW_VEP_MAX 18
1017
1018struct brw_vertex_element_packet {
1019 struct header header;
1020 struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */
1021};
1022
1023
1024struct brw_urb_immediate {
1025 GLuint opcode:4;
1026 GLuint offset:6;
1027 GLuint swizzle_control:2;
1028 GLuint pad:1;
1029 GLuint allocate:1;
1030 GLuint used:1;
1031 GLuint complete:1;
1032 GLuint response_length:4;
1033 GLuint msg_length:4;
1034 GLuint msg_target:4;
1035 GLuint pad1:3;
1036 GLuint end_of_thread:1;
1037};
1038
1039/* Instruction format for the execution units:
1040 */
1041
1042struct brw_instruction
1043{
1044 struct
1045 {
Damien Lespiaue71f1d22013-01-14 19:13:19 +00001046 GLuint opcode:7;
1047 GLuint pad:1;
1048 GLuint access_mode:1;
1049 GLuint mask_control:1;
1050 GLuint dependency_control:2;
1051 GLuint compression_control:2; /* gen6: quater control */
1052 GLuint thread_control:2;
1053 GLuint predicate_control:4;
1054 GLuint predicate_inverse:1;
1055 GLuint execution_size:3;
1056 /**
1057 * Conditional Modifier for most instructions. On Gen6+, this is also
1058 * used for the SEND instruction's Message Target/SFID.
1059 */
1060 GLuint destreg__conditionalmod:4;
1061 GLuint acc_wr_control:1;
1062 GLuint cmpt_control:1;
1063 GLuint debug_control:1;
1064 GLuint saturate:1;
Eric Anholt22a10632006-08-22 10:15:33 -07001065 } header;
1066
1067 union {
1068 struct
1069 {
Eric Anholt78cb82a2006-08-31 15:08:52 -07001070 GLuint dest_reg_file:2; /* 0x00000003 */
1071 GLuint dest_reg_type:3; /* 0x0000001c */
1072 GLuint src0_reg_file:2; /* 0x00000060 */
1073 GLuint src0_reg_type:3; /* 0x00000380 */
1074 GLuint src1_reg_file:2; /* 0x00000c00 */
1075 GLuint src1_reg_type:3; /* 0x00007000 */
1076 GLuint pad:1; /* 0x00008000 */
1077 GLuint dest_subreg_nr:5; /* 0x001f0000 */
1078 GLuint dest_reg_nr:8; /* 0x1f700000 */
1079 GLuint dest_horiz_stride:2; /* 0x60000000 */
1080 GLuint dest_address_mode:1; /* 0x80000000 */
Homer Hsing75f1d802012-09-07 09:20:50 +08001081 } da1; /* direct align1 */
Eric Anholt22a10632006-08-22 10:15:33 -07001082
1083 struct
1084 {
1085 GLuint dest_reg_file:2;
1086 GLuint dest_reg_type:3;
1087 GLuint src0_reg_file:2;
1088 GLuint src0_reg_type:3;
Keith Packard5a2ec832008-10-18 20:07:45 -07001089 GLuint src1_reg_file:2; /* 0x00000c00 */
1090 GLuint src1_reg_type:3; /* 0x00007000 */
1091 GLuint pad:1;
Eric Anholt22a10632006-08-22 10:15:33 -07001092 GLint dest_indirect_offset:10; /* offset against the deref'd address reg */
1093 GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
1094 GLuint dest_horiz_stride:2;
1095 GLuint dest_address_mode:1;
Homer Hsing75f1d802012-09-07 09:20:50 +08001096 } ia1; /* indirect align1 */
Eric Anholt22a10632006-08-22 10:15:33 -07001097
1098 struct
1099 {
1100 GLuint dest_reg_file:2;
1101 GLuint dest_reg_type:3;
1102 GLuint src0_reg_file:2;
1103 GLuint src0_reg_type:3;
1104 GLuint src1_reg_file:2;
1105 GLuint src1_reg_type:3;
1106 GLuint pad0:1;
1107 GLuint dest_writemask:4;
1108 GLuint dest_subreg_nr:1;
1109 GLuint dest_reg_nr:8;
Xiang, Haihao5bcf1f52010-10-08 13:10:15 +08001110 GLuint dest_horiz_stride:2;
Eric Anholt22a10632006-08-22 10:15:33 -07001111 GLuint dest_address_mode:1;
Homer Hsing75f1d802012-09-07 09:20:50 +08001112 } da16; /* direct align16 */
Eric Anholt22a10632006-08-22 10:15:33 -07001113
1114 struct
1115 {
1116 GLuint dest_reg_file:2;
1117 GLuint dest_reg_type:3;
1118 GLuint src0_reg_file:2;
1119 GLuint src0_reg_type:3;
1120 GLuint pad0:6;
1121 GLuint dest_writemask:4;
1122 GLint dest_indirect_offset:6;
1123 GLuint dest_subreg_nr:3;
Xiang, Haihao5bcf1f52010-10-08 13:10:15 +08001124 GLuint dest_horiz_stride:2;
Eric Anholt22a10632006-08-22 10:15:33 -07001125 GLuint dest_address_mode:1;
Homer Hsing75f1d802012-09-07 09:20:50 +08001126 } ia16; /* indirect align16 */
Homer Hsing0d3f8492012-09-07 09:53:17 +08001127
1128 struct
1129 {
Homer Hsing45ab3cf2012-09-27 14:20:32 +08001130 GLuint dest_reg_file:1; /* used in Gen6, deleted in Gen7 */
Homer Hsing0d3f8492012-09-07 09:53:17 +08001131 GLuint flag_subreg_nr:1;
Homer Hsing45ab3cf2012-09-27 14:20:32 +08001132 GLuint flag_reg_nr:1; /* not in Gen6. Add in Gen7 */
Homer Hsing0d3f8492012-09-07 09:53:17 +08001133 GLuint pad1:1; /* reserved */
1134 GLuint src0_modifier:2;
1135 GLuint src1_modifier:2;
1136 GLuint src2_modifier:2;
1137 GLuint src_reg_type:2;
1138 GLuint dest_reg_type:2;
1139 GLuint pad2:1; /* reserved */
1140 GLuint nib_ctrl:1;
1141 GLuint pad3:1; /* reserved */
1142 GLuint dest_writemask:4;
1143 GLuint dest_subreg_nr:3;
1144 GLuint dest_reg_nr:8;
Damien Lespiau31259c52013-01-15 14:05:23 +00001145 } da3src;
Homer Hsingc91bd8c2012-09-27 16:20:39 +08001146
1147 struct
1148 {
1149 GLuint pad:16;
1150 GLint JIP:16;
1151 } branch; /* conditional branch JIP for Gen6 only */
Eric Anholt22a10632006-08-22 10:15:33 -07001152 } bits1;
1153
1154
1155 union {
1156 struct
1157 {
Eric Anholt78cb82a2006-08-31 15:08:52 -07001158 GLuint src0_subreg_nr:5; /* 0x0000001f */
1159 GLuint src0_reg_nr:8; /* 0x00001fe0 */
1160 GLuint src0_abs:1; /* 0x00002000 */
1161 GLuint src0_negate:1; /* 0x00004000 */
1162 GLuint src0_address_mode:1; /* 0x00008000 */
1163 GLuint src0_horiz_stride:2; /* 0x00030000 */
1164 GLuint src0_width:3; /* 0x001c0000 */
1165 GLuint src0_vert_stride:4; /* 0x01e00000 */
Xiang, Haihao2f772dd2012-07-17 14:18:54 +08001166 GLuint flag_subreg_nr:1; /* 0x02000000 */
Xiang, Haihao3ffbe962012-07-17 15:05:31 +08001167 GLuint flag_reg_nr:1; /* 0x04000000 */
1168 GLuint pad:5; /* 0xf8000000 */
Homer Hsing75f1d802012-09-07 09:20:50 +08001169 } da1; /* direct align1 */
Eric Anholt22a10632006-08-22 10:15:33 -07001170
1171 struct
1172 {
1173 GLint src0_indirect_offset:10;
1174 GLuint src0_subreg_nr:3;
1175 GLuint src0_abs:1;
1176 GLuint src0_negate:1;
1177 GLuint src0_address_mode:1;
1178 GLuint src0_horiz_stride:2;
1179 GLuint src0_width:3;
1180 GLuint src0_vert_stride:4;
Xiang, Haihao2f772dd2012-07-17 14:18:54 +08001181 GLuint flag_subreg_nr:1;
Xiang, Haihao3ffbe962012-07-17 15:05:31 +08001182 GLuint flag_reg_nr:1;
1183 GLuint pad:5;
Homer Hsing75f1d802012-09-07 09:20:50 +08001184 } ia1; /* indirect align1 */
Eric Anholt22a10632006-08-22 10:15:33 -07001185
1186 struct
1187 {
1188 GLuint src0_swz_x:2;
1189 GLuint src0_swz_y:2;
1190 GLuint src0_subreg_nr:1;
1191 GLuint src0_reg_nr:8;
1192 GLuint src0_abs:1;
1193 GLuint src0_negate:1;
1194 GLuint src0_address_mode:1;
1195 GLuint src0_swz_z:2;
1196 GLuint src0_swz_w:2;
1197 GLuint pad0:1;
1198 GLuint src0_vert_stride:4;
Xiang, Haihao2f772dd2012-07-17 14:18:54 +08001199 GLuint flag_subreg_nr:1;
Xiang, Haihao3ffbe962012-07-17 15:05:31 +08001200 GLuint flag_reg_nr:1;
1201 GLuint pad1:5;
Homer Hsing75f1d802012-09-07 09:20:50 +08001202 } da16; /* direct align16 */
Eric Anholt22a10632006-08-22 10:15:33 -07001203
1204 struct
1205 {
1206 GLuint src0_swz_x:2;
1207 GLuint src0_swz_y:2;
1208 GLint src0_indirect_offset:6;
1209 GLuint src0_subreg_nr:3;
1210 GLuint src0_abs:1;
1211 GLuint src0_negate:1;
1212 GLuint src0_address_mode:1;
1213 GLuint src0_swz_z:2;
1214 GLuint src0_swz_w:2;
1215 GLuint pad0:1;
1216 GLuint src0_vert_stride:4;
Xiang, Haihao2f772dd2012-07-17 14:18:54 +08001217 GLuint flag_subreg_nr:1;
Xiang, Haihao3ffbe962012-07-17 15:05:31 +08001218 GLuint flag_reg_nr:1;
1219 GLuint pad1:5;
Homer Hsing75f1d802012-09-07 09:20:50 +08001220 } ia16; /* indirect align16 */
Eric Anholt22a10632006-08-22 10:15:33 -07001221
Homer Hsing0d3f8492012-09-07 09:53:17 +08001222 struct
1223 {
1224 GLuint src0_rep_ctrl:1;
1225 GLuint src0_swizzle:8;
1226 GLuint src0_subreg_nr:3;
1227 GLuint src0_reg_nr:8;
1228 GLuint pad0:1; /* reserved */
1229 GLuint src1_rep_ctrl:1;
1230 GLuint src1_swizzle:8;
1231 GLuint src1_subreg_nr_low:2; /* src1_subreg_nr spans on two DWORDs */
Damien Lespiau31259c52013-01-15 14:05:23 +00001232 } da3src;
Homer Hsing0d3f8492012-09-07 09:53:17 +08001233
Xiang Haihao549b7512009-06-30 10:02:33 +08001234 struct
1235 {
1236 GLuint pad:26;
1237 GLuint end_of_thread:1;
1238 GLuint pad1:1;
1239 GLuint sfid:4;
1240 } send_gen5; /* for GEN5 only */
Xiang, Haihao27b43032010-12-13 16:07:16 +08001241 struct
1242 {
1243 GLuint pad:26;
1244 GLuint msg_ext:6;
1245 } msg_ext;
Eric Anholt22a10632006-08-22 10:15:33 -07001246 } bits2;
1247
1248 union
1249 {
1250 struct
1251 {
1252 GLuint src1_subreg_nr:5;
1253 GLuint src1_reg_nr:8;
1254 GLuint src1_abs:1;
1255 GLuint src1_negate:1;
Keith Packard2033aea2008-04-23 23:10:40 -07001256 GLuint src1_address_mode:1;
Eric Anholt22a10632006-08-22 10:15:33 -07001257 GLuint src1_horiz_stride:2;
1258 GLuint src1_width:3;
1259 GLuint src1_vert_stride:4;
1260 GLuint pad0:7;
Homer Hsing75f1d802012-09-07 09:20:50 +08001261 } da1; /* direct align1 */
Eric Anholt22a10632006-08-22 10:15:33 -07001262
1263 struct
1264 {
1265 GLuint src1_swz_x:2;
1266 GLuint src1_swz_y:2;
1267 GLuint src1_subreg_nr:1;
1268 GLuint src1_reg_nr:8;
1269 GLuint src1_abs:1;
1270 GLuint src1_negate:1;
Keith Packard2033aea2008-04-23 23:10:40 -07001271 GLuint src1_address_mode:1;
Eric Anholt22a10632006-08-22 10:15:33 -07001272 GLuint src1_swz_z:2;
1273 GLuint src1_swz_w:2;
1274 GLuint pad1:1;
1275 GLuint src1_vert_stride:4;
1276 GLuint pad2:7;
Homer Hsing75f1d802012-09-07 09:20:50 +08001277 } da16; /* direct align16 */
Eric Anholt22a10632006-08-22 10:15:33 -07001278
1279 struct
1280 {
1281 GLint src1_indirect_offset:10;
1282 GLuint src1_subreg_nr:3;
1283 GLuint src1_abs:1;
1284 GLuint src1_negate:1;
Keith Packard2033aea2008-04-23 23:10:40 -07001285 GLuint src1_address_mode:1;
Eric Anholt22a10632006-08-22 10:15:33 -07001286 GLuint src1_horiz_stride:2;
1287 GLuint src1_width:3;
1288 GLuint src1_vert_stride:4;
Xiang, Haihao968d2d72012-07-17 14:01:54 +08001289 GLuint pad1:7;
Homer Hsing75f1d802012-09-07 09:20:50 +08001290 } ia1; /* indirect align1 */
Eric Anholt22a10632006-08-22 10:15:33 -07001291
1292 struct
1293 {
1294 GLuint src1_swz_x:2;
1295 GLuint src1_swz_y:2;
1296 GLint src1_indirect_offset:6;
1297 GLuint src1_subreg_nr:3;
1298 GLuint src1_abs:1;
1299 GLuint src1_negate:1;
Keith Packard2033aea2008-04-23 23:10:40 -07001300 GLuint src1_address_mode:1;
Eric Anholt22a10632006-08-22 10:15:33 -07001301 GLuint src1_swz_z:2;
1302 GLuint src1_swz_w:2;
1303 GLuint pad1:1;
1304 GLuint src1_vert_stride:4;
Xiang, Haihao968d2d72012-07-17 14:01:54 +08001305 GLuint pad2:7;
Homer Hsing75f1d802012-09-07 09:20:50 +08001306 } ia16; /* indirect align16 */
Eric Anholt22a10632006-08-22 10:15:33 -07001307
Homer Hsing0d3f8492012-09-07 09:53:17 +08001308 struct
1309 {
1310 GLuint src1_subreg_nr_high:1; /* src1_subreg_nr spans on two DWORDs */
1311 GLuint src1_reg_nr:8;
1312 GLuint pad0:1; /* reserved */
1313 GLuint src2_rep_ctrl:1;
1314 GLuint src2_swizzle:8;
1315 GLuint src2_subreg_nr:3;
1316 GLuint src2_reg_nr:8;
1317 GLuint pad1:2; /* reserved */
Damien Lespiau31259c52013-01-15 14:05:23 +00001318 } da3src;
Eric Anholt22a10632006-08-22 10:15:33 -07001319
1320 struct
1321 {
Homer Hsingc91bd8c2012-09-27 16:20:39 +08001322 GLint JIP:16; /* Gen7 bspec: both the JIP and UIP are signed 16-bit numbers */
Homer Hsing375d1fd2012-09-18 13:12:50 +08001323 GLint UIP:16;
Homer Hsingc91bd8c2012-09-27 16:20:39 +08001324 } branch_2_offset; /* for Gen6, Gen7 2-offsets branch; for Gen7 1-offset branch */
Homer Hsing741008e2012-09-20 13:09:15 +08001325
Homer Hsingee321882012-10-19 11:18:23 +08001326 GLint JIP; /* used by Gen6 CALL instructions; Gen7 JMPI */
Eric Anholt22a10632006-08-22 10:15:33 -07001327
1328 struct {
1329 GLuint function:4;
1330 GLuint int_type:1;
1331 GLuint precision:1;
1332 GLuint saturate:1;
1333 GLuint data_type:1;
1334 GLuint pad0:8;
1335 GLuint response_length:4;
1336 GLuint msg_length:4;
1337 GLuint msg_target:4;
1338 GLuint pad1:3;
1339 GLuint end_of_thread:1;
1340 } math;
1341
1342 struct {
1343 GLuint binding_table_index:8;
1344 GLuint sampler:4;
1345 GLuint return_format:2;
1346 GLuint msg_type:2;
1347 GLuint response_length:4;
1348 GLuint msg_length:4;
1349 GLuint msg_target:4;
1350 GLuint pad1:3;
1351 GLuint end_of_thread:1;
1352 } sampler;
1353
1354 struct brw_urb_immediate urb;
1355
1356 struct {
1357 GLuint binding_table_index:8;
1358 GLuint msg_control:4;
1359 GLuint msg_type:2;
1360 GLuint target_cache:2;
1361 GLuint response_length:4;
1362 GLuint msg_length:4;
1363 GLuint msg_target:4;
1364 GLuint pad1:3;
1365 GLuint end_of_thread:1;
1366 } dp_read;
1367
1368 struct {
1369 GLuint binding_table_index:8;
1370 GLuint msg_control:3;
1371 GLuint pixel_scoreboard_clear:1;
1372 GLuint msg_type:3;
1373 GLuint send_commit_msg:1;
1374 GLuint response_length:4;
1375 GLuint msg_length:4;
1376 GLuint msg_target:4;
1377 GLuint pad1:3;
1378 GLuint end_of_thread:1;
1379 } dp_write;
1380
1381 struct {
Zou Nan hai26afe902008-06-18 15:04:11 -07001382 GLuint opcode:1;
1383 GLuint requester_type:1;
1384 GLuint pad:2;
1385 GLuint resource_select:1;
1386 GLuint pad1:11;
1387 GLuint response_length:4;
1388 GLuint msg_length:4;
1389 GLuint msg_target:4;
1390 GLuint pad2:3;
1391 GLuint end_of_thread:1;
1392 } thread_spawner;
1393
1394 struct {
Eric Anholt22a10632006-08-22 10:15:33 -07001395 GLuint pad:16;
1396 GLuint response_length:4;
1397 GLuint msg_length:4;
1398 GLuint msg_target:4;
1399 GLuint pad1:3;
1400 GLuint end_of_thread:1;
1401 } generic;
1402
Xiang Haihao549b7512009-06-30 10:02:33 +08001403 struct {
1404 GLuint function:4;
1405 GLuint int_type:1;
1406 GLuint precision:1;
1407 GLuint saturate:1;
1408 GLuint data_type:1;
1409 GLuint snapshot:1;
1410 GLuint pad0:10;
1411 GLuint header_present:1;
1412 GLuint response_length:5;
1413 GLuint msg_length:4;
1414 GLuint pad1:2;
1415 GLuint end_of_thread:1;
1416 } math_gen5;
1417
1418 struct {
1419 GLuint opcode:4;
1420 GLuint offset:6;
1421 GLuint swizzle_control:2;
1422 GLuint pad:1;
1423 GLuint allocate:1;
1424 GLuint used:1;
1425 GLuint complete:1;
1426 GLuint pad0:3;
1427 GLuint header_present:1;
1428 GLuint response_length:5;
1429 GLuint msg_length:4;
1430 GLuint pad1:2;
1431 GLuint end_of_thread:1;
1432 } urb_gen5;
1433
1434 struct {
1435 GLuint binding_table_index:8;
1436 GLuint sampler:4;
1437 GLuint msg_type:4;
1438 GLuint simd_mode:2;
1439 GLuint pad0:1;
1440 GLuint header_present:1;
1441 GLuint response_length:5;
1442 GLuint msg_length:4;
1443 GLuint pad1:2;
1444 GLuint end_of_thread:1;
1445 } sampler_gen5;
1446
1447 struct {
1448 GLuint binding_table_index:8;
Xiang, Haihao67d4ed62011-05-23 13:45:04 +08001449 GLuint sampler:4;
1450 GLuint msg_type:5;
1451 GLuint simd_mode:2;
1452 GLuint header_present:1;
1453 GLuint response_length:5;
1454 GLuint msg_length:4;
1455 GLuint pad1:2;
1456 GLuint end_of_thread:1;
1457 } sampler_gen7;
1458
1459 struct {
1460 GLuint binding_table_index:8;
Xiang, Haihao5261b842009-07-23 10:32:51 +08001461 GLuint msg_control:4;
1462 GLuint msg_type:2;
Xiang Haihao549b7512009-06-30 10:02:33 +08001463 GLuint target_cache:2;
1464 GLuint pad0:3;
1465 GLuint header_present:1;
1466 GLuint response_length:5;
1467 GLuint msg_length:4;
1468 GLuint pad1:2;
1469 GLuint end_of_thread:1;
1470 } dp_read_gen5;
1471
Damien Lespiau668e0df2013-01-15 16:40:06 +00001472 /**
1473 * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
1474 *
1475 * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
1476 **/
1477 struct {
1478 GLuint binding_table_index:8;
1479 GLuint msg_control:5;
1480 GLuint msg_type:3;
1481 GLuint pad0:3;
1482 GLuint header_present:1;
1483 GLuint response_length:5;
1484 GLuint msg_length:4;
1485 GLuint pad1:2;
1486 GLuint end_of_thread:1;
1487 } gen6_dp_sampler_const_cache;
Xiang, Haihaoa8458d52010-10-09 11:09:47 +08001488
1489 struct {
1490 GLuint binding_table_index:8;
Xiang Haihao549b7512009-06-30 10:02:33 +08001491 GLuint msg_control:3;
1492 GLuint pixel_scoreboard_clear:1;
1493 GLuint msg_type:3;
1494 GLuint send_commit_msg:1;
1495 GLuint pad0:3;
1496 GLuint header_present:1;
1497 GLuint response_length:5;
1498 GLuint msg_length:4;
1499 GLuint pad1:2;
1500 GLuint end_of_thread:1;
1501 } dp_write_gen5;
1502
1503 struct {
Xiang, Haihao61784db2010-10-08 16:48:15 +08001504 GLuint binding_table_index:8;
1505 GLuint msg_control:5;
1506 GLuint msg_type:4;
1507 GLuint send_commit_msg:1;
1508 GLuint pad0:1;
1509 GLuint header_present:1;
1510 GLuint response_length:5;
1511 GLuint msg_length:4;
1512 GLuint pad1:2;
1513 GLuint end_of_thread:1;
1514 } dp_write_gen6;
1515
1516 struct {
Xiang, Haihaoc8d6bf32011-05-23 13:32:32 +08001517 GLuint binding_table_index:8;
Xiang, Haihao27050392011-06-10 16:04:30 +08001518 GLuint msg_control:5;
1519 GLuint msg_type:4;
1520 GLuint send_commit_msg:1; /* ignore on read message */
1521 GLuint pad0:1;
1522 GLuint header_present:1;
1523 GLuint response_length:5;
1524 GLuint msg_length:4;
1525 GLuint pad1:2;
1526 GLuint end_of_thread:1;
1527 } dp_gen6;
1528
1529 struct {
1530 GLuint binding_table_index:8;
Xiang, Haihaoc8d6bf32011-05-23 13:32:32 +08001531 GLuint msg_control:6;
1532 GLuint msg_type:4;
Xiang, Haihao27050392011-06-10 16:04:30 +08001533 GLuint category:1;
Xiang, Haihaoc8d6bf32011-05-23 13:32:32 +08001534 GLuint header_present:1;
1535 GLuint response_length:5;
1536 GLuint msg_length:4;
1537 GLuint pad1:2;
1538 GLuint end_of_thread:1;
1539 } dp_gen7;
1540
1541 struct {
Xiang Haihao549b7512009-06-30 10:02:33 +08001542 GLuint opcode:1;
1543 GLuint requester_type:1;
1544 GLuint pad0:2;
1545 GLuint resource_select:1;
1546 GLuint pad1:14;
1547 GLuint header_present:1;
1548 GLuint response_length:5;
1549 GLuint msg_length:4;
1550 GLuint pad2:2;
1551 GLuint end_of_thread:1;
1552 } thread_spawner_gen5;
1553
1554 struct {
Zhou Chang52399862011-04-14 11:51:29 +08001555 GLuint binding_table_index:8;
1556 GLuint search_path_index:3;
1557 GLuint lut_subindex:2;
1558 GLuint message_type:2;
1559 GLuint pad0:4;
1560 GLuint header_present:1;
1561 } vme_gen6;
Zhao Yakui93f2a4f2012-10-22 16:13:51 -04001562 struct {
1563 GLuint binding_table_index:8;
1564 GLuint pad0:5;
1565 GLuint message_type:2;
1566 GLuint pad1:4;
1567 GLuint header_present:1;
1568 } cre_gen75;
Zhou Chang52399862011-04-14 11:51:29 +08001569 struct {
Xiang Haihao549b7512009-06-30 10:02:33 +08001570 GLuint pad:19;
1571 GLuint header_present:1;
1572 GLuint response_length:5;
1573 GLuint msg_length:4;
1574 GLuint pad1:2;
1575 GLuint end_of_thread:1;
1576 } generic_gen5;
1577
Eric Anholt22a10632006-08-22 10:15:33 -07001578 GLuint ud;
1579 GLint id;
1580 GLfloat fd;
1581 } bits3;
Homer Hsing751838e2012-09-21 08:39:57 +08001582
1583 char *first_reloc_target, *second_reloc_target; // first for JIP, second for UIP
1584 GLint first_reloc_offset, second_reloc_offset; // in number of instructions
Eric Anholt22a10632006-08-22 10:15:33 -07001585};
1586
1587
1588#endif