Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2015 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
Mike Frysinger | 030977e | 2018-01-10 17:12:15 -0500 | [diff] [blame] | 25 | #include <inttypes.h> |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 26 | #include <unistd.h> |
| 27 | #include <stdlib.h> |
| 28 | #include <stdio.h> |
| 29 | #include <stdbool.h> |
| 30 | #include <err.h> |
| 31 | #include <string.h> |
| 32 | #include "intel_io.h" |
| 33 | #include "intel_chipset.h" |
Chris Wilson | 83884e9 | 2017-03-21 17:16:03 +0000 | [diff] [blame] | 34 | #include "drmtest.h" |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 35 | |
| 36 | static uint32_t display_base; |
| 37 | static uint32_t devid; |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 38 | |
| 39 | static uint32_t read_reg(uint32_t addr) |
| 40 | { |
Jani Nikula | fb1515c | 2015-04-15 15:50:19 +0300 | [diff] [blame] | 41 | return INREG(display_base + addr); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 42 | } |
| 43 | |
| 44 | struct gmch_wm { |
| 45 | int wm, wm1, dl, fifo, fbc, burst; |
| 46 | bool dl_prec, valid; |
| 47 | }; |
| 48 | |
| 49 | enum plane { |
| 50 | PRI_HPLL_SR, |
| 51 | CUR_HPLL_SR, |
| 52 | PRI_SR, |
| 53 | CUR_SR, |
| 54 | PRI_A, |
| 55 | CUR_A, |
| 56 | SPR_A, |
| 57 | SPR_B, |
| 58 | PRI_B, |
| 59 | CUR_B, |
| 60 | SPR_C, |
| 61 | SPR_D, |
| 62 | PRI_C, |
| 63 | CUR_C, |
| 64 | SPR_E, |
| 65 | SPR_F, |
| 66 | MAX_PLANE, |
| 67 | }; |
| 68 | |
| 69 | #define NAME(x) [x] = #x |
| 70 | |
| 71 | static const char * const plane_name[] = { |
| 72 | NAME(PRI_HPLL_SR), |
| 73 | NAME(CUR_HPLL_SR), |
| 74 | NAME(PRI_SR), |
| 75 | NAME(CUR_SR), |
| 76 | NAME(PRI_A), |
| 77 | NAME(CUR_A), |
| 78 | NAME(SPR_A), |
| 79 | NAME(SPR_B), |
| 80 | NAME(PRI_B), |
| 81 | NAME(CUR_B), |
| 82 | NAME(SPR_C), |
| 83 | NAME(SPR_D), |
| 84 | NAME(PRI_C), |
| 85 | NAME(CUR_C), |
| 86 | NAME(SPR_E), |
| 87 | NAME(SPR_F), |
| 88 | }; |
| 89 | |
| 90 | struct ilk_wm_level { |
| 91 | int primary, sprite, cursor, latency, fbc; |
| 92 | bool enabled, sprite_enabled; |
| 93 | bool primary_trickle_feed_dis, sprite_trickle_feed_dis; |
| 94 | }; |
| 95 | |
| 96 | struct ilk_wm { |
| 97 | struct ilk_wm_level pipe[3]; |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 98 | struct { |
| 99 | int linetime, ips; |
| 100 | } linetime[3]; |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 101 | struct ilk_wm_level lp[3]; |
| 102 | }; |
| 103 | |
| 104 | #define MASK(size) ((1 << (size)) - 1) |
| 105 | |
| 106 | #define REG_DECODE1(x, shift, size) \ |
| 107 | (((x) >> (shift)) & MASK(size)) |
| 108 | |
| 109 | #define REG_DECODE2(lo, shift_lo, size_lo, hi, shift_hi, size_hi) \ |
| 110 | ((((lo) >> (shift_lo)) & MASK(size_lo)) | \ |
| 111 | ((((hi) >> (shift_hi)) & MASK(size_hi)) << (size_lo))) |
| 112 | |
Eric Anholt | eac4baf | 2017-09-02 21:38:52 -0700 | [diff] [blame] | 113 | static char pipe_name(int pipe) |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 114 | { |
| 115 | return 'A' + pipe; |
| 116 | } |
| 117 | |
| 118 | static const char *endis(bool enabled) |
| 119 | { |
| 120 | return enabled ? "enabled" : "disabled"; |
| 121 | } |
| 122 | |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 123 | static char endis_ast(bool enabled) |
| 124 | { |
| 125 | return enabled ? '*' : ' '; |
| 126 | } |
| 127 | |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 128 | static int is_gen7_plus(uint32_t d) |
| 129 | { |
| 130 | return !(IS_GEN5(d) || IS_GEN6(d)); |
| 131 | } |
| 132 | |
| 133 | static int is_hsw_plus(uint32_t d) |
| 134 | { |
| 135 | return !(IS_GEN5(d) || IS_GEN6(d) || IS_IVYBRIDGE(d)); |
| 136 | } |
| 137 | |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 138 | static int skl_num_planes(uint32_t d, int pipe) |
| 139 | { |
Ville Syrjälä | f46cb24 | 2018-12-18 16:22:32 +0200 | [diff] [blame] | 140 | if (IS_GEN11(d)) |
| 141 | return 8; |
| 142 | else if (IS_GEN10(d) || IS_GEMINILAKE(d)) |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 143 | return 5; |
| 144 | else if (IS_BROXTON(d)) |
| 145 | return pipe == 2 ? 4 : 5; |
| 146 | else |
| 147 | return 4; |
| 148 | } |
| 149 | |
| 150 | static int skl_max_planes(uint32_t d) |
| 151 | { |
Ville Syrjälä | f46cb24 | 2018-12-18 16:22:32 +0200 | [diff] [blame] | 152 | if (IS_GEN11(d)) |
| 153 | return 8; |
| 154 | else if (IS_GEN10(d) || IS_GEMINILAKE(d) || IS_BROXTON(d)) |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 155 | return 5; |
| 156 | else |
| 157 | return 4; |
| 158 | } |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 159 | |
Ville Syrjälä | 4aebd4a | 2017-11-21 20:18:54 +0200 | [diff] [blame] | 160 | static const char *skl_plane_name(int pipe, int plane) |
| 161 | { |
| 162 | static char name[32]; |
| 163 | |
| 164 | if (plane == 0) |
| 165 | snprintf(name, sizeof(name), "CURSOR"); |
| 166 | else |
| 167 | snprintf(name, sizeof(name), "PLANE_%1d%c", |
| 168 | plane, pipe_name(pipe)); |
| 169 | |
| 170 | return name; |
| 171 | } |
| 172 | |
Ville Syrjälä | 4a1e839 | 2017-11-21 20:07:34 +0200 | [diff] [blame] | 173 | static const char *skl_wm_linetime_reg_name(int pipe) |
| 174 | { |
| 175 | static char reg_name[32]; |
| 176 | |
| 177 | snprintf(reg_name, sizeof(reg_name), "WM_LINETIME_%c", |
| 178 | pipe_name(pipe)); |
| 179 | |
| 180 | return reg_name; |
| 181 | } |
| 182 | |
| 183 | static const char *skl_wm_reg_name(int pipe, int plane, int level) |
| 184 | { |
| 185 | static char reg_name[32]; |
| 186 | |
| 187 | if (plane == 0) |
| 188 | snprintf(reg_name, sizeof(reg_name), "CUR_WM_%c_%1d", |
| 189 | pipe_name(pipe), level); |
| 190 | else |
| 191 | snprintf(reg_name, sizeof(reg_name), "PLANE_WM_%1d_%c_%1d", |
| 192 | plane, pipe_name(pipe), level); |
| 193 | |
| 194 | return reg_name; |
| 195 | } |
| 196 | |
| 197 | static const char *skl_wm_trans_reg_name(int pipe, int plane) |
| 198 | { |
| 199 | static char reg_name[32]; |
| 200 | |
| 201 | if (plane == 0) |
| 202 | snprintf(reg_name, sizeof(reg_name), "CUR_WM_TRANS_%c", |
| 203 | pipe_name(pipe)); |
| 204 | else |
| 205 | snprintf(reg_name, sizeof(reg_name), "PLANE_WM_TRANS_%1d_%c", |
| 206 | plane, pipe_name(pipe)); |
| 207 | return reg_name; |
| 208 | } |
| 209 | |
| 210 | static const char *skl_buf_cfg_reg_name(int pipe, int plane) |
| 211 | { |
| 212 | static char reg_name[32]; |
| 213 | |
| 214 | if (plane == 0) |
| 215 | snprintf(reg_name, sizeof(reg_name), "CUR_BUF_CFG_%c", |
| 216 | pipe_name(pipe)); |
| 217 | else |
| 218 | snprintf(reg_name, sizeof(reg_name), "PLANE_BUF_CFG_%1d_%c", |
| 219 | plane, pipe_name(pipe)); |
| 220 | |
| 221 | return reg_name; |
| 222 | } |
| 223 | |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 224 | static void skl_wm_dump(void) |
| 225 | { |
| 226 | int pipe, plane, level; |
| 227 | int num_pipes = 3; |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 228 | int max_planes = skl_max_planes(devid); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 229 | int num_levels = 8; |
| 230 | uint32_t base_addr = 0x70000, addr, wm_offset; |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 231 | uint32_t wm[num_levels][num_pipes][max_planes]; |
| 232 | uint32_t wm_trans[num_pipes][max_planes]; |
| 233 | uint32_t buf_cfg[num_pipes][max_planes]; |
Ville Syrjälä | aadde84 | 2017-09-15 20:46:23 +0300 | [diff] [blame] | 234 | uint32_t wm_linetime[num_pipes]; |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 235 | |
| 236 | intel_register_access_init(intel_get_pci_device(), 0, -1); |
| 237 | |
| 238 | for (pipe = 0; pipe < num_pipes; pipe++) { |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 239 | int num_planes = skl_num_planes(devid, pipe); |
| 240 | |
Ville Syrjälä | aadde84 | 2017-09-15 20:46:23 +0300 | [diff] [blame] | 241 | wm_linetime[pipe] = read_reg(0x45270 + pipe * 0x4); |
| 242 | |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 243 | for (plane = 0; plane < num_planes; plane++) { |
| 244 | addr = base_addr + pipe * 0x1000 + plane * 0x100; |
| 245 | |
| 246 | wm_trans[pipe][plane] = read_reg(addr + 0x00168); |
| 247 | buf_cfg[pipe][plane] = read_reg(addr + 0x0017C); |
| 248 | for (level = 0; level < num_levels; level++) { |
| 249 | wm_offset = addr + 0x00140 + level * 0x4; |
| 250 | wm[level][pipe][plane] = read_reg(wm_offset); |
| 251 | } |
| 252 | } |
| 253 | } |
| 254 | |
Ville Syrjälä | aadde84 | 2017-09-15 20:46:23 +0300 | [diff] [blame] | 255 | for (pipe = 0; pipe < num_pipes; pipe++) { |
Ville Syrjälä | 62b7723 | 2017-11-21 20:44:50 +0200 | [diff] [blame] | 256 | printf("%18s 0x%08x\t", |
Ville Syrjälä | 4a1e839 | 2017-11-21 20:07:34 +0200 | [diff] [blame] | 257 | skl_wm_linetime_reg_name(pipe), |
| 258 | wm_linetime[pipe]); |
Ville Syrjälä | aadde84 | 2017-09-15 20:46:23 +0300 | [diff] [blame] | 259 | } |
| 260 | printf("\n\n"); |
| 261 | |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 262 | for (plane = 0; plane < max_planes; plane++) { |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 263 | for (level = 0; level < num_levels; level++) { |
| 264 | for (pipe = 0; pipe < num_pipes; pipe++) { |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 265 | if (plane >= skl_num_planes(devid, pipe)) |
| 266 | break; |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 267 | |
Ville Syrjälä | 62b7723 | 2017-11-21 20:44:50 +0200 | [diff] [blame] | 268 | printf("%18s 0x%08x\t" , |
Ville Syrjälä | 4a1e839 | 2017-11-21 20:07:34 +0200 | [diff] [blame] | 269 | skl_wm_reg_name(pipe, plane, level), |
| 270 | wm[level][pipe][plane]); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 271 | } |
| 272 | printf("\n"); |
| 273 | } |
| 274 | printf("\n"); |
| 275 | } |
| 276 | |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 277 | for (plane = 0; plane < max_planes; plane++) { |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 278 | for (pipe = 0; pipe < num_pipes; pipe++) { |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 279 | if (plane >= skl_num_planes(devid, pipe)) |
| 280 | break; |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 281 | |
Ville Syrjälä | 62b7723 | 2017-11-21 20:44:50 +0200 | [diff] [blame] | 282 | printf("%18s 0x%08x\t", |
Ville Syrjälä | 4a1e839 | 2017-11-21 20:07:34 +0200 | [diff] [blame] | 283 | skl_wm_trans_reg_name(pipe, plane), |
| 284 | wm_trans[pipe][plane]); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 285 | } |
| 286 | printf("\n"); |
| 287 | } |
| 288 | printf("\n"); |
| 289 | |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 290 | for (plane = 0; plane < max_planes; plane++) { |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 291 | for (pipe = 0; pipe < num_pipes; pipe++) { |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 292 | if (plane >= skl_num_planes(devid, pipe)) |
| 293 | break; |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 294 | |
Ville Syrjälä | 62b7723 | 2017-11-21 20:44:50 +0200 | [diff] [blame] | 295 | printf("%18s 0x%08x\t", |
Ville Syrjälä | 4a1e839 | 2017-11-21 20:07:34 +0200 | [diff] [blame] | 296 | skl_buf_cfg_reg_name(pipe, plane), |
| 297 | buf_cfg[pipe][plane]); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 298 | } |
| 299 | printf("\n"); |
| 300 | } |
| 301 | printf("\n"); |
| 302 | |
| 303 | for (pipe = 0; pipe < num_pipes; pipe++) { |
| 304 | uint32_t start, end, size; |
| 305 | uint32_t lines, blocks, enable; |
Ville Syrjälä | aadde84 | 2017-09-15 20:46:23 +0300 | [diff] [blame] | 306 | uint32_t linetime; |
Dhinakaran Pandiyan | f8f6db9 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 307 | int num_planes = skl_num_planes(devid, pipe); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 308 | |
| 309 | printf("PIPE_%c\n", pipe_name(pipe)); |
Ville Syrjälä | aadde84 | 2017-09-15 20:46:23 +0300 | [diff] [blame] | 310 | |
| 311 | linetime = REG_DECODE1(wm_linetime[pipe], 0, 9); |
| 312 | printf("LINETIME: %d (%.3f usec)\n", linetime, linetime* 0.125f); |
| 313 | |
Ville Syrjälä | 4aebd4a | 2017-11-21 20:18:54 +0200 | [diff] [blame] | 314 | printf("LEVEL"); |
| 315 | for (plane = 0; plane < num_planes; plane++) |
| 316 | printf("%10s", skl_plane_name(pipe, plane)); |
| 317 | printf("\n"); |
| 318 | |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 319 | for (level = 0; level < num_levels; level++) { |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 320 | printf("%5d", level); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 321 | for (plane = 0; plane < num_planes; plane++) { |
| 322 | blocks = REG_DECODE1(wm[level][pipe][plane], 0, 9); |
| 323 | lines = REG_DECODE1(wm[level][pipe][plane], 14, 5); |
| 324 | enable = REG_DECODE1(wm[level][pipe][plane], 31, 1); |
| 325 | |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 326 | printf("%5d%c", blocks, endis_ast(enable)); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 327 | if (!REG_DECODE1(wm[level][pipe][plane], 30, 1)) |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 328 | printf("(%2d)", lines); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 329 | else |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 330 | printf("(--)"); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 331 | } |
| 332 | printf("\n"); |
| 333 | } |
| 334 | |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 335 | printf("TRANS"); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 336 | for (plane = 0; plane < num_planes; plane++) { |
| 337 | blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 9); |
| 338 | lines = REG_DECODE1(wm_trans[pipe][plane], 14, 5); |
| 339 | enable = REG_DECODE1(wm_trans[pipe][plane], 31, 1); |
| 340 | |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 341 | printf("%5d%c", blocks, endis_ast(enable)); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 342 | if (!REG_DECODE1(wm_trans[pipe][plane], 30, 1)) |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 343 | printf("(%2d)", lines); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 344 | else |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 345 | printf("(--)"); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | printf("\nDDB allocation:"); |
| 349 | |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 350 | printf("\nstart"); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 351 | for (plane = 0; plane < num_planes; plane++) { |
Ville Syrjälä | 672acd7 | 2018-12-18 16:23:59 +0200 | [diff] [blame^] | 352 | start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11); |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 353 | printf("%10d", start); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 354 | } |
| 355 | |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 356 | printf("\n end"); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 357 | for (plane = 0; plane < num_planes; plane++) { |
Ville Syrjälä | 672acd7 | 2018-12-18 16:23:59 +0200 | [diff] [blame^] | 358 | end = REG_DECODE1(buf_cfg[pipe][plane], 16, 11); |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 359 | printf("%10d", end); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 360 | } |
| 361 | |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 362 | printf("\n size"); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 363 | for (plane = 0; plane < num_planes; plane++) { |
Ville Syrjälä | 672acd7 | 2018-12-18 16:23:59 +0200 | [diff] [blame^] | 364 | start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11); |
| 365 | end = REG_DECODE1(buf_cfg[pipe][plane], 16, 11); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 366 | size = end - start + 1; |
Ville Syrjälä | 0c4eb79 | 2017-11-21 20:32:42 +0200 | [diff] [blame] | 367 | printf("%10d", (end == 0 && size == 1) ? 0 : size); |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | printf("\n\n\n"); |
| 371 | } |
| 372 | |
| 373 | printf("* plane watermark enabled\n"); |
| 374 | printf("(x) line watermark if enabled\n"); |
| 375 | } |
| 376 | |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 377 | static void ilk_wm_dump(void) |
| 378 | { |
| 379 | int i; |
| 380 | uint32_t dspcntr[3]; |
| 381 | uint32_t spcntr[3]; |
| 382 | uint32_t wm_pipe[3]; |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 383 | uint32_t wm_linetime[3]; |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 384 | uint32_t wm_lp[3]; |
| 385 | uint32_t wm_lp_spr[3]; |
| 386 | uint32_t arb_ctl, arb_ctl2, wm_misc = 0; |
| 387 | int num_pipes = is_gen7_plus(devid) ? 3 : 2; |
| 388 | struct ilk_wm wm = {}; |
| 389 | |
Chris Wilson | 538091c | 2017-11-20 15:58:59 +0000 | [diff] [blame] | 390 | intel_register_access_init(intel_get_pci_device(), 0, -1); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 391 | |
| 392 | for (i = 0; i < num_pipes; i++) { |
| 393 | dspcntr[i] = read_reg(0x70180 + i * 0x1000); |
| 394 | if (is_gen7_plus(devid)) |
| 395 | spcntr[i] = read_reg(0x70280 + i * 0x1000); |
| 396 | else |
| 397 | spcntr[i] = read_reg(0x72180 + i * 0x1000); |
| 398 | } |
| 399 | |
| 400 | wm_pipe[0] = read_reg(0x45100); |
| 401 | wm_pipe[1] = read_reg(0x45104); |
| 402 | if (num_pipes == 3) |
| 403 | wm_pipe[2] = read_reg(0x45200); |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 404 | |
| 405 | if (is_hsw_plus(devid)) { |
| 406 | wm_linetime[0] = read_reg(0x45270); |
| 407 | wm_linetime[1] = read_reg(0x45274); |
| 408 | wm_linetime[2] = read_reg(0x45278); |
| 409 | } |
| 410 | |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 411 | wm_lp[0] = read_reg(0x45108); |
| 412 | wm_lp[1] = read_reg(0x4510c); |
| 413 | wm_lp[2] = read_reg(0x45110); |
| 414 | |
| 415 | wm_lp_spr[0] = read_reg(0x45120); |
| 416 | if (is_gen7_plus(devid)) { |
| 417 | wm_lp_spr[1] = read_reg(0x45124); |
| 418 | wm_lp_spr[2] = read_reg(0x45128); |
| 419 | } |
| 420 | |
| 421 | arb_ctl = read_reg(0x45000); |
| 422 | arb_ctl2 = read_reg(0x45004); |
| 423 | if (is_hsw_plus(devid)) |
| 424 | wm_misc = read_reg(0x45260); |
| 425 | |
| 426 | intel_register_access_fini(); |
| 427 | |
| 428 | for (i = 0; i < num_pipes; i++) |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 429 | printf(" WM_PIPE_%c = 0x%08x\n", pipe_name(i), wm_pipe[i]); |
| 430 | if (is_hsw_plus(devid)) { |
| 431 | for (i = 0; i < num_pipes; i++) |
| 432 | printf("WM_LINETIME_%c = 0x%08x\n", pipe_name(i), wm_linetime[i]); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 433 | } |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 434 | printf(" WM_LP1 = 0x%08x\n", wm_lp[0]); |
| 435 | printf(" WM_LP2 = 0x%08x\n", wm_lp[1]); |
| 436 | printf(" WM_LP3 = 0x%08x\n", wm_lp[2]); |
| 437 | printf(" WM_LP1_SPR = 0x%08x\n", wm_lp_spr[0]); |
| 438 | if (is_gen7_plus(devid)) { |
| 439 | printf(" WM_LP2_SPR = 0x%08x\n", wm_lp_spr[1]); |
| 440 | printf(" WM_LP3_SPR = 0x%08x\n", wm_lp_spr[2]); |
| 441 | } |
| 442 | printf(" ARB_CTL = 0x%08x\n", arb_ctl); |
| 443 | printf(" ARB_CTL2 = 0x%08x\n", arb_ctl2); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 444 | if (is_hsw_plus(devid)) |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 445 | printf(" WM_MISC = 0x%08x\n", wm_misc); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 446 | |
| 447 | for (i = 0 ; i < num_pipes; i++) { |
| 448 | wm.pipe[i].primary = REG_DECODE1(wm_pipe[i], 16, 8); |
| 449 | wm.pipe[i].sprite = REG_DECODE1(wm_pipe[i], 8, 8); |
| 450 | wm.pipe[i].cursor = REG_DECODE1(wm_pipe[i], 0, 6); |
| 451 | |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 452 | if (is_hsw_plus(devid)) { |
| 453 | wm.linetime[i].linetime = REG_DECODE1(wm_linetime[i], 0, 9); |
| 454 | wm.linetime[i].ips = REG_DECODE1(wm_linetime[i], 16, 9); |
| 455 | } |
| 456 | |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 457 | wm.pipe[i].primary_trickle_feed_dis = |
| 458 | REG_DECODE1(dspcntr[i], 14, 1); |
| 459 | if (!IS_GEN5(devid)) |
| 460 | wm.pipe[i].sprite_trickle_feed_dis = |
| 461 | REG_DECODE1(spcntr[i], 14, 1); |
| 462 | } |
| 463 | |
| 464 | for (i = 0; i < 3; i++) { |
| 465 | wm.lp[i].enabled = REG_DECODE1(wm_lp[i], 31, 1); |
| 466 | wm.lp[i].latency = REG_DECODE1(wm_lp[i], 24, 7); |
| 467 | if (IS_GEN8(devid)) |
| 468 | wm.lp[i].fbc = REG_DECODE1(wm_lp[i], 19, 5); |
| 469 | else |
| 470 | wm.lp[i].fbc = REG_DECODE1(wm_lp[i], 20, 4); |
| 471 | wm.lp[i].primary = REG_DECODE1(wm_lp[i], 8, 11); |
| 472 | wm.lp[i].cursor = REG_DECODE1(wm_lp[i], 0, 8); |
| 473 | |
| 474 | if (i == 0 || is_gen7_plus(devid)) { |
| 475 | if (!is_gen7_plus(devid)) |
| 476 | wm.lp[i].sprite_enabled = REG_DECODE1(wm_lp_spr[i], 31, 1); |
| 477 | wm.lp[i].sprite = REG_DECODE1(wm_lp_spr[i], 0, 11); |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | for (i = 0; i < num_pipes; i++) { |
| 482 | printf("WM_PIPE_%c: primary=%d, cursor=%d, sprite=%d\n", |
| 483 | pipe_name(i), wm.pipe[i].primary, wm.pipe[i].cursor, wm.pipe[i].sprite); |
| 484 | } |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 485 | if (is_hsw_plus(devid)) { |
| 486 | for (i = 0; i < num_pipes; i++) { |
Ville Syrjälä | 1f5814e | 2017-09-15 20:26:33 +0300 | [diff] [blame] | 487 | printf("WM_LINETIME_%c: line time=%d (%.3f usec), ips line time=%d (%.3f usec)\n", |
| 488 | pipe_name(i), |
| 489 | wm.linetime[i].linetime, wm.linetime[i].linetime * 0.125f, |
| 490 | wm.linetime[i].ips, wm.linetime[i].ips * 0.125f); |
Ville Syrjälä | 92a9588 | 2016-04-25 23:21:34 +0300 | [diff] [blame] | 491 | } |
| 492 | } |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 493 | if (is_gen7_plus(devid)) { |
| 494 | for (i = 0; i < 3; i++) { |
| 495 | printf("WM_LP%d: %s, latency=%d, fbc=%d, primary=%d, cursor=%d, sprite=%d\n", |
| 496 | i + 1, endis(wm.lp[i].enabled), wm.lp[i].latency, wm.lp[i].fbc, |
| 497 | wm.lp[i].primary, wm.lp[i].cursor, wm.lp[i].sprite); |
| 498 | } |
| 499 | } else { |
| 500 | i = 0; |
| 501 | printf("WM_LP%d: %s, latency=%d, fbc=%d, primary=%d, cursor=%d, sprite=%d (%s)\n", |
| 502 | i + 1, endis(wm.lp[i].enabled), wm.lp[i].latency, wm.lp[i].fbc, |
| 503 | wm.lp[i].primary, wm.lp[i].cursor, wm.lp[i].sprite, |
| 504 | endis(wm.lp[i].sprite_enabled)); |
| 505 | for (i = 1; i < 3; i++) { |
| 506 | printf("WM_LP%d: %s, latency=%d, fbc=%d, primary=%d, cursor=%d\n", |
| 507 | i + 1, endis(wm.lp[i].enabled), wm.lp[i].latency, wm.lp[i].fbc, |
| 508 | wm.lp[i].primary, wm.lp[i].cursor); |
| 509 | } |
| 510 | } |
| 511 | for (i = 0; i < num_pipes; i++) { |
| 512 | printf("Primary %c trickle feed = %s\n", |
| 513 | pipe_name(i), endis(!wm.pipe[i].primary_trickle_feed_dis)); |
| 514 | if (!IS_GEN5(devid)) |
| 515 | printf("Sprite %c trickle feed = %s\n", |
| 516 | pipe_name(i), endis(!wm.pipe[i].sprite_trickle_feed_dis)); |
| 517 | } |
| 518 | if (is_hsw_plus(devid)) { |
| 519 | printf("DDB partitioning = %s\n", |
| 520 | REG_DECODE1(wm_misc, 0, 1) ? "5/6" : "1/2"); |
| 521 | } else if (is_gen7_plus(devid)) { |
| 522 | printf("DDB partitioning = %s\n", |
| 523 | REG_DECODE1(arb_ctl2, 6, 1) ? "5/6" : "1/2"); |
| 524 | } |
| 525 | printf("FBC watermark = %s\n", |
| 526 | endis(!REG_DECODE1(arb_ctl, 15, 1))); |
| 527 | } |
| 528 | |
| 529 | static void vlv_wm_dump(void) |
| 530 | { |
| 531 | int i; |
| 532 | unsigned int num_pipes = IS_CHERRYVIEW(devid) ? 3 : 2; |
| 533 | uint32_t dsparb, dsparb2, dsparb3; |
| 534 | uint32_t fw1, fw2, fw3, fw4, fw5, fw6, fw7, fw8, fw9, howm, howm1; |
| 535 | uint32_t ddl1, ddl2, ddl3; |
| 536 | uint32_t fw_blc_self, mi_arb,cbr1; |
| 537 | uint32_t dsp_ss_pm, ddr_setup2; |
| 538 | struct gmch_wm wms[MAX_PLANE] = {}; |
| 539 | |
Chris Wilson | 538091c | 2017-11-20 15:58:59 +0000 | [diff] [blame] | 540 | intel_register_access_init(intel_get_pci_device(), 0, -1); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 541 | |
| 542 | dsparb = read_reg(0x70030); |
| 543 | dsparb2 = read_reg(0x70060); |
| 544 | |
| 545 | fw1 = read_reg(0x70034); |
| 546 | fw2 = read_reg(0x70038); |
| 547 | fw3 = read_reg(0x7003c); |
| 548 | fw4 = read_reg(0x70070); |
| 549 | fw5 = read_reg(0x70074); |
| 550 | fw6 = read_reg(0x70078); |
| 551 | |
| 552 | howm = read_reg(0x70064); |
| 553 | howm1 = read_reg(0x70068); |
| 554 | |
| 555 | ddl1 = read_reg(0x70050); |
| 556 | ddl2 = read_reg(0x70054); |
| 557 | |
| 558 | fw_blc_self = read_reg(0x6500); |
| 559 | mi_arb = read_reg(0x6504); |
| 560 | cbr1 = read_reg(0x70400); |
| 561 | |
| 562 | if (IS_CHERRYVIEW(devid)) { |
| 563 | dsparb3 = read_reg(0x7006c); |
| 564 | |
| 565 | fw7 = read_reg(0x700b4); |
| 566 | fw8 = read_reg(0x700b8); |
| 567 | fw9 = read_reg(0x7007c); |
| 568 | |
| 569 | ddl3 = read_reg(0x70058); |
| 570 | |
| 571 | intel_punit_read(0x36, &dsp_ss_pm); |
| 572 | intel_punit_read(0x139, &ddr_setup2); |
| 573 | } else { |
| 574 | fw7 = read_reg(0x7007c); |
| 575 | } |
| 576 | |
| 577 | intel_register_access_fini(); |
| 578 | |
| 579 | printf(" FW1 = 0x%08x\n", fw1); |
| 580 | printf(" FW2 = 0x%08x\n", fw2); |
| 581 | printf(" FW3 = 0x%08x\n", fw3); |
| 582 | printf(" FW4 = 0x%08x\n", fw4); |
| 583 | printf(" FW5 = 0x%08x\n", fw5); |
| 584 | printf(" FW6 = 0x%08x\n", fw6); |
| 585 | printf(" FW7 = 0x%08x\n", fw7); |
| 586 | if (IS_CHERRYVIEW(devid)) { |
| 587 | printf(" FW8 = 0x%08x\n", fw8); |
| 588 | printf(" FW9 = 0x%08x\n", fw9); |
| 589 | } |
| 590 | printf(" HOWM = 0x%08x\n", howm); |
| 591 | printf(" HOWM1 = 0x%08x\n", howm1); |
| 592 | printf(" DDL1 = 0x%08x\n", ddl1); |
| 593 | printf(" DDL2 = 0x%08x\n", ddl2); |
| 594 | if (IS_CHERRYVIEW(devid)) |
| 595 | printf(" DDL3 = 0x%08x\n", ddl3); |
| 596 | printf(" DSPARB = 0x%08x\n", dsparb); |
| 597 | printf(" DSPARB2 = 0x%08x\n", dsparb2); |
| 598 | if (IS_CHERRYVIEW(devid)) |
| 599 | printf(" DSPARB3 = 0x%08x\n", dsparb3); |
| 600 | printf("FW_BLC_SELF = 0x%08x\n", fw_blc_self); |
| 601 | printf(" MI_ARB = 0x%08x\n", mi_arb); |
| 602 | printf(" CBR1 = 0x%08x\n", cbr1); |
| 603 | if (IS_CHERRYVIEW(devid)) { |
| 604 | printf(" DSP_SS_PM = 0x%08x\n", dsp_ss_pm); |
| 605 | printf(" DDR_SETUP2 = 0x%08x\n", ddr_setup2); |
| 606 | } |
| 607 | |
| 608 | wms[PRI_A].valid = true; |
| 609 | wms[PRI_B].valid = true; |
| 610 | wms[CUR_A].valid = true; |
| 611 | wms[CUR_B].valid = true; |
| 612 | wms[SPR_A].valid = true; |
| 613 | wms[SPR_B].valid = true; |
| 614 | wms[SPR_C].valid = true; |
| 615 | wms[SPR_D].valid = true; |
| 616 | wms[PRI_SR].valid = true; |
| 617 | wms[CUR_SR].valid = true; |
| 618 | |
| 619 | if (IS_CHERRYVIEW(devid)) { |
| 620 | wms[PRI_C].valid = true; |
| 621 | wms[CUR_C].valid = true; |
| 622 | wms[SPR_E].valid = true; |
| 623 | wms[SPR_F].valid = true; |
| 624 | } |
| 625 | |
| 626 | wms[PRI_A].fifo = REG_DECODE2(dsparb, 0, 8, dsparb2, 0, 1) - 0; |
| 627 | wms[SPR_A].fifo = REG_DECODE2(dsparb, 8, 8, dsparb2, 4, 1) - wms[PRI_A].fifo; |
| 628 | wms[SPR_B].fifo = 512 - 1 - wms[SPR_A].fifo - wms[PRI_A].fifo; |
| 629 | wms[CUR_A].fifo = 0x3f; |
| 630 | |
| 631 | wms[PRI_B].fifo = REG_DECODE2(dsparb, 16, 8, dsparb2, 8, 1) - 0; |
| 632 | wms[SPR_C].fifo = REG_DECODE2(dsparb, 24, 8, dsparb2, 12, 1) - wms[PRI_B].fifo; |
| 633 | wms[SPR_D].fifo = 512 - 1 - wms[SPR_C].fifo - wms[PRI_B].fifo; |
| 634 | wms[CUR_B].fifo = 0x3f; |
| 635 | |
| 636 | if (IS_CHERRYVIEW(devid)) { |
| 637 | wms[PRI_C].fifo = REG_DECODE2(dsparb3, 0, 8, dsparb2, 16, 1) - 0; |
| 638 | wms[SPR_E].fifo = REG_DECODE2(dsparb3, 8, 8, dsparb2, 20, 1) - wms[PRI_C].fifo; |
| 639 | wms[SPR_F].fifo = 512 - 1 - wms[SPR_E].fifo - wms[PRI_C].fifo; |
| 640 | wms[CUR_C].fifo = 0x3f; |
| 641 | } |
| 642 | |
| 643 | wms[PRI_SR].fifo = 512 * num_pipes - 1; |
| 644 | wms[CUR_SR].fifo = 0x3f; |
| 645 | |
| 646 | wms[PRI_HPLL_SR].fifo = 512 * num_pipes - 1; |
| 647 | wms[CUR_HPLL_SR].fifo = 0x3f; |
| 648 | |
| 649 | wms[PRI_A].wm = REG_DECODE2(fw1, 0, 8, howm, 0, 1); |
| 650 | wms[PRI_B].wm = REG_DECODE2(fw1, 8, 8, howm, 12, 1); |
| 651 | wms[CUR_B].wm = REG_DECODE1(fw1, 16, 6); |
| 652 | wms[PRI_SR].wm = REG_DECODE2(fw1, 23, 9, howm, 24, 2); |
| 653 | |
| 654 | wms[SPR_A].wm = REG_DECODE2(fw2, 0, 8, howm, 4, 1); |
| 655 | wms[CUR_A].wm = REG_DECODE1(fw2, 8, 6); |
| 656 | wms[SPR_B].wm = REG_DECODE2(fw2, 16, 8, howm, 8, 1); |
| 657 | |
| 658 | wms[CUR_SR].wm = REG_DECODE1(fw3, 24, 6); |
| 659 | |
| 660 | wms[SPR_A].wm1 = REG_DECODE2(fw4, 0, 8, howm1, 4, 1); |
| 661 | wms[CUR_A].wm1 = REG_DECODE1(fw4, 8, 6); |
| 662 | wms[SPR_B].wm1 = REG_DECODE2(fw4, 16, 8, howm1, 8, 1); |
| 663 | |
| 664 | wms[CUR_SR].wm1 = REG_DECODE1(fw5, 0, 6); |
| 665 | wms[CUR_B].wm1 = REG_DECODE1(fw5, 8, 6); |
| 666 | wms[PRI_A].wm1 = REG_DECODE2(fw5, 16, 8, howm1, 0, 1); |
| 667 | wms[PRI_B].wm1 = REG_DECODE2(fw5, 24, 8, howm1, 12, 1); |
| 668 | |
| 669 | wms[PRI_SR].wm1 = REG_DECODE2(fw6, 0, 9, howm1, 24, 2); |
| 670 | |
| 671 | wms[SPR_C].wm = REG_DECODE2(fw7, 0, 8, howm, 16, 1); |
| 672 | wms[SPR_C].wm1 = REG_DECODE2(fw7, 8, 8, howm1, 16, 1); |
| 673 | wms[SPR_D].wm = REG_DECODE2(fw7, 16, 8, howm, 20, 1); |
| 674 | wms[SPR_D].wm1 = REG_DECODE2(fw7, 24, 8, howm1, 20, 1); |
| 675 | |
| 676 | if (IS_CHERRYVIEW(devid)) { |
| 677 | wms[SPR_E].wm = REG_DECODE2(fw8, 0, 8, howm, 22, 1); |
| 678 | wms[SPR_E].wm1 = REG_DECODE2(fw8, 8, 8, howm1, 22, 1); |
| 679 | wms[SPR_F].wm = REG_DECODE2(fw8, 16, 8, howm, 23, 1); |
| 680 | wms[SPR_F].wm1 = REG_DECODE2(fw8, 24, 8, howm1, 23, 1); |
| 681 | |
| 682 | wms[CUR_C].wm = REG_DECODE1(fw9, 0, 6); |
| 683 | wms[CUR_C].wm1 = REG_DECODE1(fw9, 8, 6); |
| 684 | wms[PRI_C].wm = REG_DECODE2(fw9, 16, 8, howm, 21, 1); |
| 685 | wms[PRI_C].wm1 = REG_DECODE2(fw9, 24, 8, howm1, 21, 1); |
| 686 | } |
| 687 | |
| 688 | wms[PRI_A].dl = REG_DECODE1(ddl1, 0, 7); |
| 689 | wms[SPR_A].dl = REG_DECODE1(ddl1, 8, 7); |
| 690 | wms[SPR_B].dl = REG_DECODE1(ddl1, 16, 7); |
| 691 | wms[CUR_A].dl = REG_DECODE1(ddl1, 24, 7); |
| 692 | |
| 693 | wms[PRI_A].dl_prec = REG_DECODE1(ddl1, 7, 1); |
| 694 | wms[SPR_A].dl_prec = REG_DECODE1(ddl1, 15, 1); |
| 695 | wms[SPR_B].dl_prec = REG_DECODE1(ddl1, 23, 1); |
| 696 | wms[CUR_A].dl_prec = REG_DECODE1(ddl1, 31, 1); |
| 697 | |
| 698 | wms[PRI_B].dl = REG_DECODE1(ddl2, 0, 7); |
| 699 | wms[SPR_C].dl = REG_DECODE1(ddl2, 8, 7); |
| 700 | wms[SPR_D].dl = REG_DECODE1(ddl2, 16, 7); |
| 701 | wms[CUR_B].dl = REG_DECODE1(ddl2, 24, 7); |
| 702 | |
| 703 | wms[PRI_B].dl_prec = REG_DECODE1(ddl2, 7, 1); |
| 704 | wms[SPR_C].dl_prec = REG_DECODE1(ddl2, 15, 1); |
| 705 | wms[SPR_D].dl_prec = REG_DECODE1(ddl2, 23, 1); |
| 706 | wms[CUR_B].dl_prec = REG_DECODE1(ddl2, 31, 1); |
| 707 | |
| 708 | if (IS_CHERRYVIEW(devid)) { |
| 709 | wms[PRI_C].dl = REG_DECODE1(ddl3, 0, 7); |
| 710 | wms[SPR_E].dl = REG_DECODE1(ddl3, 8, 7); |
| 711 | wms[SPR_F].dl = REG_DECODE1(ddl3, 16, 7); |
| 712 | wms[CUR_C].dl = REG_DECODE1(ddl3, 24, 7); |
| 713 | |
| 714 | wms[PRI_C].dl_prec = REG_DECODE1(ddl3, 7, 1); |
| 715 | wms[SPR_E].dl_prec = REG_DECODE1(ddl3, 15, 1); |
| 716 | wms[SPR_F].dl_prec = REG_DECODE1(ddl3, 23, 1); |
| 717 | wms[CUR_C].dl_prec = REG_DECODE1(ddl3, 31, 1); |
| 718 | } |
| 719 | |
| 720 | for (i = 0; i < ARRAY_SIZE(wms); i++) { |
| 721 | if (!wms[i].valid) |
| 722 | continue; |
| 723 | printf("%s: WM = %d, WM1 = %d, DDL = %d (prec=%d), FIFO = %d\n", |
| 724 | plane_name[i], wms[i].wm, wms[i].wm1, wms[i].dl, wms[i].dl_prec, wms[i].fifo); |
| 725 | } |
| 726 | |
| 727 | printf("CxSR = %s\n", |
| 728 | endis(REG_DECODE1(fw_blc_self, 15, 1))); |
| 729 | printf("Trickle feed = %s\n", |
| 730 | endis(!REG_DECODE1(mi_arb, 2, 1))); |
| 731 | printf("PND deadline = %s\n", |
| 732 | endis(!REG_DECODE1(cbr1, 31, 1))); |
| 733 | |
| 734 | if (IS_CHERRYVIEW(devid)) { |
| 735 | printf("PM5 = %s\n", |
| 736 | endis(REG_DECODE1(dsp_ss_pm, 6, 1))); |
| 737 | printf("PM5 state = %s\n", |
| 738 | endis(REG_DECODE1(dsp_ss_pm, 22, 1))); |
| 739 | printf("DDR force high frequency = %s\n", |
| 740 | endis(REG_DECODE1(ddr_setup2, 0, 1))); |
| 741 | printf("DDR force low frequency = %s\n", |
| 742 | endis(REG_DECODE1(ddr_setup2, 1, 1))); |
| 743 | } |
| 744 | } |
| 745 | |
| 746 | static void g4x_wm_dump(void) |
| 747 | { |
| 748 | int i; |
| 749 | uint32_t dspacntr, dspbcntr; |
| 750 | uint32_t dsparb; |
| 751 | uint32_t fw1, fw2, fw3; |
| 752 | uint32_t mi_display_power_down; |
| 753 | uint32_t mi_arb_state; |
| 754 | struct gmch_wm wms[MAX_PLANE] = {}; |
| 755 | |
Chris Wilson | 538091c | 2017-11-20 15:58:59 +0000 | [diff] [blame] | 756 | intel_register_access_init(intel_get_pci_device(), 0, -1); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 757 | |
| 758 | dspacntr = read_reg(0x70180); |
| 759 | dspbcntr = read_reg(0x71180); |
| 760 | dsparb = read_reg(0x70030); |
| 761 | fw1 = read_reg(0x70034); |
| 762 | fw2 = read_reg(0x70038); |
| 763 | fw3 = read_reg(0x7003c); |
| 764 | mi_display_power_down = read_reg(0x20e0); |
| 765 | mi_arb_state = read_reg(0x20e4); |
| 766 | |
| 767 | intel_register_access_fini(); |
| 768 | |
| 769 | printf(" DSPACNTR = 0x%08x\n", dspacntr); |
| 770 | printf(" DSPBCNTR = 0x%08x\n", dspbcntr); |
| 771 | printf(" FW1 = 0x%08x\n", fw1); |
| 772 | printf(" FW2 = 0x%08x\n", fw2); |
| 773 | printf(" FW3 = 0x%08x\n", fw3); |
| 774 | printf(" DSPARB = 0x%08x\n", dsparb); |
| 775 | printf("MI_DISPLAY_POWER_DOWN = 0x%08x\n", mi_display_power_down); |
| 776 | printf(" MI_ARB_STATE = 0x%08x\n", mi_arb_state); |
| 777 | |
| 778 | wms[PRI_A].valid = true; |
| 779 | wms[PRI_B].valid = true; |
| 780 | wms[CUR_A].valid = true; |
| 781 | wms[CUR_B].valid = true; |
| 782 | wms[SPR_A].valid = true; |
| 783 | wms[SPR_B].valid = true; |
| 784 | wms[PRI_SR].valid = true; |
| 785 | wms[CUR_SR].valid = true; |
| 786 | wms[PRI_HPLL_SR].valid = true; |
| 787 | wms[CUR_HPLL_SR].valid = true; |
| 788 | |
| 789 | wms[PRI_A].fifo = REG_DECODE1(dsparb, 0, 7) - 0; |
| 790 | wms[PRI_B].fifo = REG_DECODE1(dsparb, 7, 7) - wms[PRI_A].fifo; |
| 791 | |
| 792 | wms[PRI_A].wm = REG_DECODE1(fw1, 0, 7); |
| 793 | wms[PRI_B].wm = REG_DECODE1(fw1, 8, 7); |
| 794 | wms[CUR_B].wm = REG_DECODE1(fw1, 16, 6); |
| 795 | wms[PRI_SR].wm = REG_DECODE1(fw1, 23, 9); |
| 796 | |
| 797 | wms[PRI_SR].fbc = REG_DECODE1(fw2, 0, 8); |
| 798 | wms[PRI_HPLL_SR].fbc = REG_DECODE1(fw2, 8, 6); |
| 799 | |
| 800 | wms[SPR_B].wm = REG_DECODE1(fw2, 16, 7); |
| 801 | wms[CUR_A].wm = REG_DECODE1(fw2, 8, 6); |
| 802 | wms[SPR_A].wm = REG_DECODE1(fw2, 0, 7); |
| 803 | |
| 804 | wms[CUR_SR].wm = REG_DECODE1(fw3, 24, 6); |
| 805 | wms[CUR_HPLL_SR].wm = REG_DECODE1(fw3, 16, 6); |
| 806 | wms[PRI_HPLL_SR].wm = REG_DECODE1(fw3, 0, 9); |
| 807 | |
| 808 | for (i = 0; i < ARRAY_SIZE(wms); i++) { |
| 809 | if (!wms[i].valid) |
| 810 | continue; |
| 811 | printf("%s: WM = %d, FBC = %d, FIFO = %d\n", |
| 812 | plane_name[i], wms[i].wm, wms[i].fbc, wms[i].fifo); |
| 813 | } |
| 814 | printf("CxSR = %s\n", |
| 815 | endis(REG_DECODE1(mi_display_power_down, 15, 1))); |
| 816 | printf("HPLL SR = %s\n", |
| 817 | endis(REG_DECODE1(fw3, 31, 1))); |
| 818 | printf("FBC SR = %s\n", |
| 819 | endis(REG_DECODE1(fw2, 31, 1))); |
| 820 | printf("Display A trickle feed = %s\n", |
| 821 | endis(!REG_DECODE1(dspacntr, 14, 1))); |
| 822 | printf("Display B trickle feed = %s\n", |
| 823 | endis(!REG_DECODE1(dspbcntr, 14, 1))); |
| 824 | printf("Display A uses sprite data buffer = %s\n", |
| 825 | endis(!REG_DECODE1(dspacntr, 13, 1))); |
| 826 | printf("Display B uses sprite data buffer = %s\n", |
| 827 | endis(!REG_DECODE1(dspbcntr, 13, 1))); |
| 828 | printf("Primary display = %c\n", |
| 829 | REG_DECODE1(mi_arb_state, 0, 1) ? 'B' : 'A'); |
| 830 | } |
| 831 | |
| 832 | static void gen4_wm_dump(void) |
| 833 | { |
| 834 | int i; |
| 835 | int totalsize = IS_CRESTLINE(devid) ? 128 : 96; |
| 836 | uint32_t dsparb; |
| 837 | uint32_t fw1, fw2, fw3; |
| 838 | uint32_t mi_display_power_down; |
| 839 | uint32_t mi_arb_state; |
| 840 | struct gmch_wm wms[MAX_PLANE] = {}; |
| 841 | |
Chris Wilson | 538091c | 2017-11-20 15:58:59 +0000 | [diff] [blame] | 842 | intel_register_access_init(intel_get_pci_device(), 0, -1); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 843 | |
| 844 | dsparb = read_reg(0x70030); |
| 845 | fw1 = read_reg(0x70034); |
| 846 | fw2 = read_reg(0x70038); |
| 847 | fw3 = read_reg(0x7003c); |
| 848 | mi_display_power_down = read_reg(0x20e0); |
| 849 | mi_arb_state = read_reg(0x20e4); |
| 850 | |
| 851 | intel_register_access_fini(); |
| 852 | |
| 853 | printf(" FW1 = 0x%08x\n", fw1); |
| 854 | printf(" FW2 = 0x%08x\n", fw2); |
| 855 | printf(" FW3 = 0x%08x\n", fw3); |
| 856 | printf(" DSPARB = 0x%08x\n", dsparb); |
| 857 | printf("MI_DISPLAY_POWER_DOWN = 0x%08x\n", mi_display_power_down); |
| 858 | printf(" MI_ARB_STATE = 0x%08x\n", mi_arb_state); |
| 859 | |
| 860 | wms[PRI_A].valid = true; |
| 861 | wms[PRI_B].valid = true; |
| 862 | wms[PRI_C].valid = true; |
| 863 | wms[CUR_A].valid = true; |
| 864 | wms[CUR_B].valid = true; |
| 865 | wms[PRI_SR].valid = true; |
| 866 | wms[CUR_SR].valid = true; |
| 867 | wms[PRI_HPLL_SR].valid = true; |
| 868 | wms[CUR_HPLL_SR].valid = true; |
| 869 | |
| 870 | wms[PRI_A].fifo = REG_DECODE1(dsparb, 0, 7) - 0; |
| 871 | wms[PRI_B].fifo = REG_DECODE1(dsparb, 7, 7) - wms[PRI_A].fifo; |
| 872 | wms[PRI_C].fifo = totalsize - wms[PRI_B].fifo - wms[PRI_A].fifo - 1; |
| 873 | |
| 874 | wms[PRI_A].wm = REG_DECODE1(fw1, 0, 7); |
| 875 | wms[PRI_B].wm = REG_DECODE1(fw1, 8, 7); |
| 876 | wms[CUR_B].wm = REG_DECODE1(fw1, 16, 6); |
| 877 | wms[PRI_SR].wm = REG_DECODE1(fw1, 23, 9); |
| 878 | |
| 879 | wms[CUR_A].wm = REG_DECODE1(fw2, 8, 6); |
| 880 | wms[PRI_C].wm = REG_DECODE1(fw2, 0, 7); |
| 881 | |
| 882 | wms[CUR_SR].wm = REG_DECODE1(fw3, 24, 6); |
| 883 | wms[CUR_HPLL_SR].wm = REG_DECODE1(fw3, 16, 6); |
| 884 | wms[PRI_HPLL_SR].wm = REG_DECODE1(fw3, 0, 9); |
| 885 | |
| 886 | for (i = 0; i < ARRAY_SIZE(wms); i++) { |
| 887 | if (!wms[i].valid) |
| 888 | continue; |
| 889 | printf("%s: WM = %d, FIFO = %d\n", |
| 890 | plane_name[i], wms[i].wm, wms[i].fifo); |
| 891 | } |
| 892 | printf("CxSR = %s\n", |
| 893 | endis(REG_DECODE1(mi_display_power_down, 15, 1))); |
| 894 | printf("HPLL SR enable = %s\n", |
| 895 | endis(REG_DECODE1(fw3, 31, 1))); |
| 896 | printf("Trickle feed = %s\n", |
| 897 | endis(!REG_DECODE1(mi_arb_state, 2, 1))); |
| 898 | printf("Primary display = %c\n", |
| 899 | REG_DECODE1(mi_arb_state, 0, 1) + 'A'); |
| 900 | } |
| 901 | |
| 902 | static void pnv_wm_dump(void) |
| 903 | { |
| 904 | int i; |
| 905 | int totalsize = 96; /* FIXME? */ |
| 906 | uint32_t dsparb; |
| 907 | uint32_t fw1, fw2, fw3; |
| 908 | uint32_t mi_display_power_down; |
| 909 | uint32_t mi_arb_state; |
| 910 | uint32_t cbr; |
| 911 | struct gmch_wm wms[MAX_PLANE] = {}; |
| 912 | |
Chris Wilson | 538091c | 2017-11-20 15:58:59 +0000 | [diff] [blame] | 913 | intel_register_access_init(intel_get_pci_device(), 0, -1); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 914 | |
| 915 | dsparb = read_reg(0x70030); |
| 916 | fw1 = read_reg(0x70034); |
| 917 | fw2 = read_reg(0x70038); |
| 918 | fw3 = read_reg(0x7003c); |
| 919 | cbr = read_reg(0x70400); |
| 920 | mi_display_power_down = read_reg(0x20e0); |
| 921 | mi_arb_state = read_reg(0x20e4); |
| 922 | |
| 923 | intel_register_access_fini(); |
| 924 | |
| 925 | printf(" DSPARB = 0x%08x\n", dsparb); |
| 926 | printf(" FW1 = 0x%08x\n", fw1); |
| 927 | printf(" FW2 = 0x%08x\n", fw2); |
| 928 | printf(" FW3 = 0x%08x\n", fw3); |
| 929 | printf(" CBR = 0x%08x\n", cbr); |
| 930 | printf("MI_DISPLAY_POWER_DOWN = 0x%08x\n", mi_display_power_down); |
| 931 | printf(" MI_ARB_STATE = 0x%08x\n", mi_arb_state); |
| 932 | |
| 933 | wms[PRI_A].valid = true; |
| 934 | wms[PRI_B].valid = true; |
| 935 | wms[PRI_C].valid = true; |
| 936 | wms[CUR_A].valid = true; |
| 937 | wms[CUR_B].valid = true; |
| 938 | wms[PRI_SR].valid = true; |
| 939 | wms[CUR_SR].valid = true; |
| 940 | wms[PRI_HPLL_SR].valid = true; |
| 941 | wms[CUR_HPLL_SR].valid = true; |
| 942 | |
| 943 | wms[PRI_A].fifo = REG_DECODE1(dsparb, 0, 7) - 0; |
| 944 | wms[PRI_B].fifo = REG_DECODE1(dsparb, 7, 7) - wms[PRI_A].fifo; |
| 945 | wms[PRI_C].fifo = totalsize - wms[PRI_B].fifo - wms[PRI_A].fifo - 1; |
| 946 | |
| 947 | wms[PRI_A].wm = REG_DECODE1(fw1, 0, 7); |
| 948 | wms[PRI_B].wm = REG_DECODE1(fw1, 8, 7); |
| 949 | wms[CUR_B].wm = REG_DECODE1(fw1, 16, 6); |
| 950 | wms[PRI_SR].wm = REG_DECODE1(fw1, 23, 9); |
| 951 | |
| 952 | wms[CUR_A].wm = REG_DECODE1(fw2, 8, 6); |
| 953 | wms[PRI_C].wm = REG_DECODE1(fw2, 0, 7); |
| 954 | |
| 955 | switch ((REG_DECODE1(cbr, 30, 1) << 1) | REG_DECODE1(cbr, 25, 1)) { |
| 956 | case 3: |
| 957 | case 2: |
| 958 | wms[PRI_SR].fifo = 8 * 1024 / 64; |
| 959 | break; |
| 960 | case 1: |
| 961 | wms[PRI_SR].fifo = 16 * 1024 / 64; |
| 962 | break; |
| 963 | case 0: |
| 964 | wms[PRI_SR].fifo = 32 * 1024 / 64; |
| 965 | break; |
| 966 | } |
| 967 | |
| 968 | wms[CUR_SR].wm = REG_DECODE1(fw3, 24, 6); |
| 969 | wms[CUR_HPLL_SR].wm = REG_DECODE1(fw3, 16, 6); |
| 970 | wms[PRI_HPLL_SR].wm = REG_DECODE1(fw3, 0, 9); |
| 971 | |
| 972 | for (i = 0; i < ARRAY_SIZE(wms); i++) { |
| 973 | if (!wms[i].valid) |
| 974 | continue; |
| 975 | printf("%s: WM = %d, FIFO = %d\n", |
| 976 | plane_name[i], wms[i].wm, wms[i].fifo); |
| 977 | } |
| 978 | printf("CxSR enable = %s\n", |
| 979 | endis(REG_DECODE1(fw3, 30, 1))); |
| 980 | printf("HPLL SR enable = %s\n", |
| 981 | endis(REG_DECODE1(fw3, 31, 1))); |
| 982 | printf("Trickle feed = %s\n", |
| 983 | endis(!REG_DECODE1(mi_arb_state, 2, 1))); |
| 984 | printf("Primary display = %c\n", |
| 985 | REG_DECODE1(mi_arb_state, 0, 1) + 'A'); |
| 986 | printf("Display plane A throttling = %s\n", |
| 987 | endis(!REG_DECODE1(cbr, 0, 1))); |
| 988 | printf("Display plane B throttling = %s\n", |
| 989 | endis(!REG_DECODE1(cbr, 1, 1))); |
| 990 | } |
| 991 | |
| 992 | static void gen3_wm_dump(void) |
| 993 | { |
| 994 | int i; |
| 995 | int totalsize = IS_945GM(devid) ? 128 : 96; /* FIXME? */ |
| 996 | uint32_t dsparb; |
| 997 | uint32_t instpm; |
| 998 | uint64_t fw_blc; |
| 999 | uint32_t fw_blc_self; |
| 1000 | uint32_t mi_arb_state; |
| 1001 | struct gmch_wm wms[MAX_PLANE] = {}; |
| 1002 | |
Chris Wilson | 538091c | 2017-11-20 15:58:59 +0000 | [diff] [blame] | 1003 | intel_register_access_init(intel_get_pci_device(), 0, -1); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 1004 | |
| 1005 | dsparb = read_reg(0x70030); |
| 1006 | instpm = read_reg(0x20c0); |
| 1007 | fw_blc = read_reg(0x20d8) | ((uint64_t)read_reg(0x20dc) << 32); |
| 1008 | fw_blc_self = read_reg(0x20e0); |
| 1009 | mi_arb_state = read_reg(0x20e4); |
| 1010 | |
| 1011 | intel_register_access_fini(); |
| 1012 | |
| 1013 | printf(" DSPARB = 0x%08x\n", dsparb); |
| 1014 | printf(" FW_BLC = 0x%016" PRIx64 "\n", fw_blc); |
| 1015 | printf(" FW_BLC_SELF = 0x%08x\n", fw_blc_self); |
| 1016 | printf("MI_ARB_STATE = 0x%08x\n", mi_arb_state); |
| 1017 | |
| 1018 | wms[PRI_A].valid = true; |
| 1019 | wms[PRI_B].valid = true; |
| 1020 | wms[PRI_C].valid = true; |
| 1021 | wms[PRI_SR].valid = true; |
| 1022 | |
| 1023 | wms[PRI_SR].wm = REG_DECODE1(fw_blc_self, 0, 8); |
| 1024 | |
| 1025 | wms[PRI_C].burst = (REG_DECODE1(fw_blc, 40, 2) + 1) * 4; |
| 1026 | wms[PRI_C].wm = REG_DECODE1(fw_blc, 32, 8); |
| 1027 | |
| 1028 | wms[PRI_B].burst = (REG_DECODE1(fw_blc, 24, 2) + 1) * 4; |
| 1029 | wms[PRI_B].wm = REG_DECODE1(fw_blc, 16, 8); |
| 1030 | |
| 1031 | wms[PRI_A].burst = (REG_DECODE1(fw_blc, 8, 2) + 1) * 4; |
| 1032 | wms[PRI_A].wm = REG_DECODE1(fw_blc, 0, 8); |
| 1033 | |
| 1034 | wms[PRI_A].fifo = REG_DECODE1(dsparb, 0, 7) - 0; |
| 1035 | wms[PRI_B].fifo = REG_DECODE1(dsparb, 7, 7) - wms[PRI_A].fifo; |
| 1036 | wms[PRI_C].fifo = totalsize - wms[PRI_B].fifo - wms[PRI_A].fifo - 1; |
| 1037 | |
| 1038 | for (i = 0; i < ARRAY_SIZE(wms); i++) { |
| 1039 | if (!wms[i].valid) |
| 1040 | continue; |
| 1041 | printf("%s: WM = %d, FIFO = %d, burst = %d\n", |
| 1042 | plane_name[i], wms[i].wm, wms[i].fifo, wms[i].burst); |
| 1043 | } |
| 1044 | /* FIXME G33 too perhaps? */ |
| 1045 | if (devid == PCI_CHIP_I945_G || devid == PCI_CHIP_I945_GM || |
| 1046 | devid == PCI_CHIP_I945_GME) { |
| 1047 | printf("CxSR = %s\n", |
| 1048 | endis(REG_DECODE1(fw_blc_self, 15, 1))); |
| 1049 | } else if (devid == PCI_CHIP_I915_GM) { |
| 1050 | printf("CxSR = %s\n", |
| 1051 | endis(REG_DECODE1(instpm, 12, 1))); |
| 1052 | } |
| 1053 | printf("Trickle feed = %s\n", |
| 1054 | endis(!REG_DECODE1(mi_arb_state, 2, 1))); |
| 1055 | printf("Primary display = %c\n", |
| 1056 | REG_DECODE1(mi_arb_state, 0, 1) + 'A'); |
| 1057 | printf("Display plane capability = %d planes\n", |
| 1058 | 3 - REG_DECODE1(mi_arb_state, 12, 2)); |
| 1059 | } |
| 1060 | |
| 1061 | static void gen2_wm_dump(void) |
| 1062 | { |
| 1063 | int i; |
| 1064 | int totalsize; |
| 1065 | uint32_t dsparb; |
| 1066 | uint32_t mem_mode; |
| 1067 | uint64_t fw_blc; |
| 1068 | uint32_t fw_blc_self; |
| 1069 | uint32_t mi_state; |
| 1070 | struct gmch_wm wms[MAX_PLANE] = {}; |
| 1071 | |
Chris Wilson | 538091c | 2017-11-20 15:58:59 +0000 | [diff] [blame] | 1072 | intel_register_access_init(intel_get_pci_device(), 0, -1); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 1073 | |
| 1074 | dsparb = read_reg(0x70030); |
| 1075 | mem_mode = read_reg(0x20cc); |
| 1076 | fw_blc = read_reg(0x20d8) | ((uint64_t)read_reg(0x20dc) << 32); |
| 1077 | fw_blc_self = read_reg(0x20e0); |
| 1078 | mi_state = read_reg(0x20e4); |
| 1079 | |
| 1080 | intel_register_access_fini(); |
| 1081 | |
| 1082 | printf(" DSPARB = 0x%08x\n", dsparb); |
| 1083 | printf(" MEM_MODE = 0x%08x\n", mem_mode); |
| 1084 | printf(" FW_BLC = 0x%016" PRIx64 "\n", fw_blc); |
| 1085 | printf("FW_BLC_SELF = 0x%08x\n", fw_blc_self); |
| 1086 | printf(" MI_STATE = 0x%08x\n", mi_state); |
| 1087 | |
| 1088 | wms[PRI_C].burst = (REG_DECODE1(fw_blc, 40, 2) + 1) * 4; |
| 1089 | wms[PRI_C].wm = REG_DECODE1(fw_blc, 32, 8); |
| 1090 | |
| 1091 | wms[PRI_B].burst = (REG_DECODE1(fw_blc, 24, 2) + 1) * 4; |
| 1092 | wms[PRI_B].wm = REG_DECODE1(fw_blc, 16, 8); |
| 1093 | |
| 1094 | wms[PRI_A].burst = (REG_DECODE1(fw_blc, 8, 2) + 1) * 4; |
| 1095 | wms[PRI_A].wm = REG_DECODE1(fw_blc, 0, 8); |
| 1096 | |
| 1097 | if (devid == PCI_CHIP_845_G || devid == PCI_CHIP_I865_G) { |
| 1098 | wms[PRI_A].valid = true; |
| 1099 | wms[PRI_C].valid = true; |
| 1100 | |
| 1101 | totalsize = 96; /* FIXME? */ |
| 1102 | wms[PRI_A].fifo = REG_DECODE1(dsparb, 0, 7) - 0; |
| 1103 | wms[PRI_C].fifo = totalsize - wms[PRI_A].fifo - 1; |
| 1104 | } else { |
| 1105 | wms[PRI_A].valid = true; |
| 1106 | wms[PRI_B].valid = true; |
| 1107 | wms[PRI_C].valid = true; |
| 1108 | |
| 1109 | if (devid == PCI_CHIP_I830_M) |
| 1110 | totalsize = 288; |
| 1111 | else |
| 1112 | totalsize = 256; |
| 1113 | totalsize = (devid == PCI_CHIP_I855_GM) ? 256 : 288; |
| 1114 | wms[PRI_A].fifo = REG_DECODE1(dsparb, 0, 9) - 0; |
| 1115 | wms[PRI_B].fifo = REG_DECODE1(dsparb, 9, 9) - wms[PRI_A].fifo; |
| 1116 | wms[PRI_C].fifo = totalsize - wms[PRI_B].fifo - wms[PRI_A].fifo - 1; |
| 1117 | } |
| 1118 | |
| 1119 | for (i = 0; i < ARRAY_SIZE(wms); i++) { |
| 1120 | if (!wms[i].valid) |
| 1121 | continue; |
| 1122 | printf("%s: WM = %d, FIFO = %d, burst = %d\n", |
| 1123 | plane_name[i], wms[i].wm, wms[i].fifo, wms[i].burst); |
| 1124 | } |
| 1125 | if (devid == PCI_CHIP_I855_GM || devid == PCI_CHIP_I854_G) { |
| 1126 | printf("CxSR = %s (%d)\n", |
| 1127 | endis(REG_DECODE1(mi_state, 3, 2)), |
| 1128 | REG_DECODE1(mi_state, 3, 2)); |
| 1129 | printf("Trickle feed = %s\n", |
| 1130 | endis(!REG_DECODE1(mem_mode, 2, 1))); |
| 1131 | printf("Display round robin = %s\n", |
| 1132 | endis(REG_DECODE1(mem_mode, 14, 1))); |
| 1133 | printf("Primary display = %c\n", |
| 1134 | REG_DECODE1(mem_mode, 15, 1) + 'A'); |
| 1135 | } else { |
| 1136 | printf("Display A trickle feed = %s\n", |
| 1137 | endis(!REG_DECODE1(mem_mode, 2, 1))); |
| 1138 | printf("Display B trickle feed = %s\n", |
| 1139 | endis(!REG_DECODE1(mem_mode, 3, 1))); |
| 1140 | printf("Water mark fix = %s\n", |
| 1141 | endis(!REG_DECODE1(mem_mode, 14, 1))); |
| 1142 | } |
| 1143 | } |
| 1144 | |
| 1145 | int main(int argc, char *argv[]) |
| 1146 | { |
| 1147 | devid = intel_get_pci_device()->device_id; |
| 1148 | |
Ville Syrjälä | ff8d115 | 2018-10-24 19:24:55 +0300 | [diff] [blame] | 1149 | if (intel_gen(devid) >= 9) { |
Dhinakaran Pandiyan | 6d9f484 | 2016-10-18 17:05:19 -0700 | [diff] [blame] | 1150 | skl_wm_dump(); |
| 1151 | } else if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) { |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 1152 | display_base = 0x180000; |
| 1153 | vlv_wm_dump(); |
Ville Syrjälä | ff8d115 | 2018-10-24 19:24:55 +0300 | [diff] [blame] | 1154 | } else if (intel_gen(devid) >= 5) { |
Chris Wilson | 8b0dd38 | 2016-07-25 12:47:19 +0100 | [diff] [blame] | 1155 | ilk_wm_dump(); |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 1156 | } else if (IS_G4X(devid)) { |
| 1157 | g4x_wm_dump(); |
| 1158 | } else if (IS_GEN4(devid)) { |
| 1159 | gen4_wm_dump(); |
Chris Wilson | 37eec6d | 2016-06-29 11:06:09 +0100 | [diff] [blame] | 1160 | } else if (IS_PINEVIEW(devid)) { |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 1161 | pnv_wm_dump(); |
| 1162 | } else if (IS_GEN3(devid)) { |
| 1163 | gen3_wm_dump(); |
| 1164 | } else if (IS_GEN2(devid)) { |
| 1165 | gen2_wm_dump(); |
| 1166 | } else { |
| 1167 | printf("unknown chip 0x%x\n", devid); |
| 1168 | return 1; |
| 1169 | } |
| 1170 | |
Ville Syrjälä | 4d2577e | 2014-12-10 21:17:36 +0200 | [diff] [blame] | 1171 | return 0; |
| 1172 | } |