blob: 73c4e9e60cc9263ff6617053fda5eb2a197cd5a4 [file] [log] [blame]
Chris Wilsonf62abaf2014-01-10 13:42:55 +00001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <chris@chris-wilson.co.uk>
25 *
26 */
27
28#include <unistd.h>
29#include <stdlib.h>
30#include <stdint.h>
31#include <stdio.h>
32#include <string.h>
33#include <fcntl.h>
34#include <inttypes.h>
35#include <errno.h>
36#include <sys/stat.h>
37#include <sys/ioctl.h>
38#include <sys/time.h>
39#include <sys/wait.h>
40
41#include "drm.h"
42#include "i915_drm.h"
43#include "drmtest.h"
44
45#define BLT_WRITE_ALPHA (1<<21)
46#define BLT_WRITE_RGB (1<<20)
47
48static const uint32_t canary = 0xdeadbeef;
49
50static double elapsed(const struct timeval *start,
51 const struct timeval *end)
52{
53 return 1e6*(end->tv_sec - start->tv_sec) + (end->tv_usec - start->tv_usec);
54}
55
56static void busy(int fd, uint32_t handle, int size, int loops)
57{
58 struct drm_i915_gem_relocation_entry reloc[20];
59 struct drm_i915_gem_exec_object2 gem_exec[2];
60 struct drm_i915_gem_execbuffer2 execbuf;
61 struct drm_i915_gem_pwrite gem_pwrite;
62 struct drm_i915_gem_create create;
63 uint32_t buf[102], *b;
64 int i;
65
66 memset(reloc, 0, sizeof(reloc));
67 memset(gem_exec, 0, sizeof(gem_exec));
68 memset(&execbuf, 0, sizeof(execbuf));
69
70 b = buf;
71 for (i = 0; i < 20; i++) {
72 *b++ = COLOR_BLT_CMD | BLT_WRITE_ALPHA | BLT_WRITE_RGB;
73 *b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096;
74 *b++ = size >> 12 << 16 | 4096;
75 reloc[i].offset = (b - buf) * sizeof(uint32_t);
76 reloc[i].target_handle = handle;
77 reloc[i].read_domains = I915_GEM_DOMAIN_RENDER;
78 reloc[i].write_domain = I915_GEM_DOMAIN_RENDER;
79 *b++ = 0;
80 *b++ = canary;
81 }
82 *b++ = MI_BATCH_BUFFER_END;
83 *b++ = 0;
84
85 gem_exec[0].handle = handle;
86 gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
87
88 create.handle = 0;
89 create.size = 4096;
90 drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
91 gem_exec[1].handle = create.handle;
92 gem_exec[1].relocation_count = 20;
93 gem_exec[1].relocs_ptr = (uintptr_t)reloc;
94
95 execbuf.buffers_ptr = (uintptr_t)gem_exec;
96 execbuf.buffer_count = 2;
97 execbuf.batch_len = sizeof(buf);
98 execbuf.flags = 1 << 11;
99 if (HAS_BLT_RING(intel_get_drm_devid(fd)))
100 execbuf.flags |= I915_EXEC_BLT;
101
102 gem_pwrite.handle = gem_exec[1].handle;
103 gem_pwrite.offset = 0;
104 gem_pwrite.size = sizeof(buf);
105 gem_pwrite.data_ptr = (uintptr_t)buf;
106 if (drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &gem_pwrite) == 0) {
107 while (loops--)
108 drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
109 }
110
111 drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &create.handle);
112}
113
114static void run(int child)
115{
116 const int size = 4096 * (256 + child * child);
117 const int tiling = child % 2;
118 const int write = child % 2;
119 int fd = drm_open_any();
120 uint32_t handle = gem_create(fd, size);
121 uint32_t *ptr;
122 uint32_t x;
123
124 igt_assert(handle);
125
126 if (tiling != I915_TILING_NONE)
127 gem_set_tiling(fd, handle, tiling, 4096);
128
129 /* load up the unfaulted bo */
130 busy(fd, handle, size, 100);
131
132 /* Note that we ignore the API and rely on the implict
133 * set-to-gtt-domain within the fault handler.
134 */
135 if (write) {
136 ptr = gem_mmap(fd, handle, size, PROT_READ | PROT_WRITE);
137 ptr[rand() % (size / 4)] = canary;
138 } else
139 ptr = gem_mmap(fd, handle, size, PROT_READ);
140 x = ptr[rand() % (size / 4)];
141 munmap(ptr, size);
142
143 igt_assert(x == canary);
144 igt_exit();
145}
146
147int main(int argc, char **argv)
148{
149 struct timeval start, end;
150 pid_t children[64];
151 int n;
152
153 igt_simple_init();
154 igt_skip_on_simulation();
155
156 gettimeofday(&start, NULL);
157 for (n = 0; n < ARRAY_SIZE(children); n++) {
158 switch ((children[n] = fork())) {
159 case -1: igt_assert(0);
160 case 0: run(n); break;
161 default: break;
162 }
163 }
164
165 for (n = 0; n < ARRAY_SIZE(children); n++) {
166 int status = -1;
167 while (waitpid(children[n], &status, 0) == -1 &&
168 errno == -EINTR)
169 ;
170 igt_assert(status == 0);
171 }
172 gettimeofday(&end, NULL);
Chris Wilson84af2b92014-01-10 16:09:57 +0000173 printf("Time to execute %lu children: %7.3fms\n",
174 ARRAY_SIZE(children), elapsed(&start, &end) / 1000);
Chris Wilsonf62abaf2014-01-10 13:42:55 +0000175
176 return 0;
177}