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Chris Wilsone7d26df2015-03-19 15:24:52 +00001/*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24/** @file kms_vblank.c
25 *
26 * This is a test of performance of drmWaitVblank.
27 */
28
Thomas Wood804e11f2015-08-17 17:57:43 +010029#include "igt.h"
Chris Wilsone7d26df2015-03-19 15:24:52 +000030#include <stdlib.h>
31#include <stdio.h>
32#include <string.h>
33#include <fcntl.h>
34#include <inttypes.h>
35#include <errno.h>
36#include <time.h>
Chris Wilson0aef4862017-03-19 15:47:42 +000037#include <sys/poll.h>
Chris Wilsone7d26df2015-03-19 15:24:52 +000038#include <sys/stat.h>
39#include <sys/time.h>
40#include <sys/wait.h>
41
42#include <drm.h>
43
Chris Wilsone7d26df2015-03-19 15:24:52 +000044#include "intel_bufmgr.h"
Chris Wilsone7d26df2015-03-19 15:24:52 +000045
46IGT_TEST_DESCRIPTION("Test speed of WaitVblank.");
47
Robert Fossba865142016-05-18 20:07:07 -040048typedef struct {
49 igt_display_t display;
50 struct igt_fb primary_fb;
51 igt_output_t *output;
52 enum pipe pipe;
Chris Wilson0aef4862017-03-19 15:47:42 +000053 unsigned int flags;
54#define IDLE 1
55#define BUSY 2
56#define FORKED 4
Robert Fossba865142016-05-18 20:07:07 -040057} data_t;
58
Chris Wilsone7d26df2015-03-19 15:24:52 +000059static double elapsed(const struct timespec *start,
60 const struct timespec *end,
61 int loop)
62{
63 return (1e6*(end->tv_sec - start->tv_sec) + (end->tv_nsec - start->tv_nsec)/1000)/loop;
64}
65
Maarten Lankhorst9c459332017-01-05 14:02:46 +010066static void prepare_crtc(data_t *data, int fd, igt_output_t *output)
Chris Wilsone7d26df2015-03-19 15:24:52 +000067{
Robert Fossba865142016-05-18 20:07:07 -040068 drmModeModeInfo *mode;
69 igt_display_t *display = &data->display;
70 igt_plane_t *primary;
Chris Wilsone7d26df2015-03-19 15:24:52 +000071
Robert Fossba865142016-05-18 20:07:07 -040072 /* select the pipe we want to use */
73 igt_output_set_pipe(output, data->pipe);
Robert Fossba865142016-05-18 20:07:07 -040074
75 /* create and set the primary plane fb */
76 mode = igt_output_get_mode(output);
77 igt_create_color_fb(fd, mode->hdisplay, mode->vdisplay,
78 DRM_FORMAT_XRGB8888,
79 LOCAL_DRM_FORMAT_MOD_NONE,
80 0.0, 0.0, 0.0,
81 &data->primary_fb);
82
Robert Fossa27f8312017-01-10 20:21:26 -050083 primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
Robert Fossba865142016-05-18 20:07:07 -040084 igt_plane_set_fb(primary, &data->primary_fb);
85
86 igt_display_commit(display);
87
88 igt_wait_for_vblank(fd, data->pipe);
Chris Wilsone7d26df2015-03-19 15:24:52 +000089}
90
Robert Fossba865142016-05-18 20:07:07 -040091static void cleanup_crtc(data_t *data, int fd, igt_output_t *output)
92{
93 igt_display_t *display = &data->display;
94 igt_plane_t *primary;
95
96 igt_remove_fb(fd, &data->primary_fb);
97
Robert Fossa27f8312017-01-10 20:21:26 -050098 primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
Robert Fossba865142016-05-18 20:07:07 -040099 igt_plane_set_fb(primary, NULL);
100
101 igt_output_set_pipe(output, PIPE_ANY);
102 igt_display_commit(display);
103}
104
Chris Wilson0aef4862017-03-19 15:47:42 +0000105static int wait_vblank(int fd, union drm_wait_vblank *vbl)
Robert Fossba865142016-05-18 20:07:07 -0400106{
Chris Wilson0aef4862017-03-19 15:47:42 +0000107 int err;
108
109 err = 0;
110 if (igt_ioctl(fd, DRM_IOCTL_WAIT_VBLANK, vbl))
111 err = -errno;
112
113 return err;
114}
115
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100116static void run_test(data_t *data, void (*testfunc)(data_t *, int, int))
Chris Wilson0aef4862017-03-19 15:47:42 +0000117{
118 int nchildren =
119 data->flags & FORKED ? sysconf(_SC_NPROCESSORS_ONLN) : 1;
Robert Fossba865142016-05-18 20:07:07 -0400120 igt_display_t *display = &data->display;
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100121 igt_output_t *output = data->output;
122 int fd = display->drm_fd;
Robert Fossba865142016-05-18 20:07:07 -0400123
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100124 prepare_crtc(data, fd, output);
Robert Fossba865142016-05-18 20:07:07 -0400125
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100126 igt_info("Beginning %s on pipe %s, connector %s (%d threads)\n",
127 igt_subtest_name(), kmstest_pipe_name(data->pipe),
128 igt_output_name(output), nchildren);
Robert Fossba865142016-05-18 20:07:07 -0400129
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100130 if (data->flags & BUSY) {
131 union drm_wait_vblank vbl;
Robert Fossba865142016-05-18 20:07:07 -0400132
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100133 memset(&vbl, 0, sizeof(vbl));
134 vbl.request.type =
135 DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
136 vbl.request.type |= kmstest_get_vbl_flag(data->pipe);
137 vbl.request.sequence = 120 + 12;
138 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Robert Fossba865142016-05-18 20:07:07 -0400139 }
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100140
141 igt_fork(child, nchildren)
142 testfunc(data, fd, nchildren);
143 igt_waitchildren();
144
145 if (data->flags & BUSY) {
146 struct drm_event_vblank buf;
147 igt_assert_eq(read(fd, &buf, sizeof(buf)), sizeof(buf));
148 }
149
150 igt_assert(poll(&(struct pollfd){fd, POLLIN}, 1, 0) == 0);
151
152 igt_info("\n%s on pipe %s, connector %s: PASSED\n\n",
153 igt_subtest_name(), kmstest_pipe_name(data->pipe), igt_output_name(output));
154
155 /* cleanup what prepare_crtc() has done */
156 cleanup_crtc(data, fd, output);
Maarten Lankhorst4919d1f2017-11-22 14:10:54 +0100157}
Robert Fossba865142016-05-18 20:07:07 -0400158
Maarten Lankhorst4919d1f2017-11-22 14:10:54 +0100159static void crtc_id_subtest(data_t *data, int fd)
160{
161 igt_display_t *display = &data->display;
162 igt_output_t *output;
163 enum pipe p;
164
165 for_each_pipe_with_valid_output(display, p, output) {
166 struct drm_event_vblank buf;
167 const uint32_t pipe_id_flag = kmstest_get_vbl_flag(p);
168 unsigned crtc_id, expected_crtc_id;
169 uint64_t val;
170 union drm_wait_vblank vbl;
171
172 crtc_id = display->pipes[p].crtc_id;
173 if (drmGetCap(display->drm_fd, DRM_CAP_CRTC_IN_VBLANK_EVENT, &val) == 0)
174 expected_crtc_id = crtc_id;
175 else
176 expected_crtc_id = 0;
177
178 data->pipe = p;
179 prepare_crtc(data, fd, output);
180
181 memset(&vbl, 0, sizeof(vbl));
182 vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
183 vbl.request.type |= pipe_id_flag;
184 vbl.request.sequence = 1;
185 igt_assert_eq(wait_vblank(fd, &vbl), 0);
186
187 igt_assert_eq(read(fd, &buf, sizeof(buf)), sizeof(buf));
188 igt_assert_eq(buf.crtc_id, expected_crtc_id);
189
190 do_or_die(drmModePageFlip(fd, crtc_id,
191 data->primary_fb.fb_id,
192 DRM_MODE_PAGE_FLIP_EVENT, NULL));
193
194 igt_assert_eq(read(fd, &buf, sizeof(buf)), sizeof(buf));
195 igt_assert_eq(buf.crtc_id, expected_crtc_id);
196
197 if (display->is_atomic) {
198 igt_plane_t *primary = igt_output_get_plane(output, 0);
199
200 igt_plane_set_fb(primary, &data->primary_fb);
201 igt_display_commit_atomic(display, DRM_MODE_PAGE_FLIP_EVENT, NULL);
202
203 igt_assert_eq(read(fd, &buf, sizeof(buf)), sizeof(buf));
204 igt_assert_eq(buf.crtc_id, expected_crtc_id);
205 }
206
207 cleanup_crtc(data, fd, output);
208 return;
209 }
Robert Fossba865142016-05-18 20:07:07 -0400210}
211
Chris Wilson0aef4862017-03-19 15:47:42 +0000212static void accuracy(data_t *data, int fd, int nchildren)
Chris Wilsona6c3b322015-04-06 10:37:41 +0100213{
Chris Wilson0aef4862017-03-19 15:47:42 +0000214 const uint32_t pipe_id_flag = kmstest_get_vbl_flag(data->pipe);
Chris Wilsona6c3b322015-04-06 10:37:41 +0100215 union drm_wait_vblank vbl;
216 unsigned long target;
Chris Wilson0aef4862017-03-19 15:47:42 +0000217 int total = 120 / nchildren;
Chris Wilsona6c3b322015-04-06 10:37:41 +0100218 int n;
219
220 memset(&vbl, 0, sizeof(vbl));
Chris Wilsona6c3b322015-04-06 10:37:41 +0100221 vbl.request.type = DRM_VBLANK_RELATIVE;
Robert Fossba865142016-05-18 20:07:07 -0400222 vbl.request.type |= pipe_id_flag;
Chris Wilsona6c3b322015-04-06 10:37:41 +0100223 vbl.request.sequence = 1;
Chris Wilson0aef4862017-03-19 15:47:42 +0000224 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Chris Wilsona6c3b322015-04-06 10:37:41 +0100225
Chris Wilson0aef4862017-03-19 15:47:42 +0000226 target = vbl.reply.sequence + total;
227 for (n = 0; n < total; n++) {
Chris Wilsona6c3b322015-04-06 10:37:41 +0100228 vbl.request.type = DRM_VBLANK_RELATIVE;
Robert Fossba865142016-05-18 20:07:07 -0400229 vbl.request.type |= pipe_id_flag;
Chris Wilsona6c3b322015-04-06 10:37:41 +0100230 vbl.request.sequence = 1;
Chris Wilson0aef4862017-03-19 15:47:42 +0000231 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Chris Wilsona6c3b322015-04-06 10:37:41 +0100232
233 vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
Robert Fossba865142016-05-18 20:07:07 -0400234 vbl.request.type |= pipe_id_flag;
Chris Wilsona6c3b322015-04-06 10:37:41 +0100235 vbl.request.sequence = target;
Chris Wilson0aef4862017-03-19 15:47:42 +0000236 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Chris Wilsona6c3b322015-04-06 10:37:41 +0100237 }
238 vbl.request.type = DRM_VBLANK_RELATIVE;
Robert Fossba865142016-05-18 20:07:07 -0400239 vbl.request.type |= pipe_id_flag;
Chris Wilsona6c3b322015-04-06 10:37:41 +0100240 vbl.request.sequence = 0;
Chris Wilson0aef4862017-03-19 15:47:42 +0000241 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Chris Wilsona6c3b322015-04-06 10:37:41 +0100242 igt_assert_eq(vbl.reply.sequence, target);
243
Chris Wilson0aef4862017-03-19 15:47:42 +0000244 for (n = 0; n < total; n++) {
Chris Wilsona6c3b322015-04-06 10:37:41 +0100245 struct drm_event_vblank ev;
246 igt_assert_eq(read(fd, &ev, sizeof(ev)), sizeof(ev));
247 igt_assert_eq(ev.sequence, target);
248 }
249}
250
Chris Wilson0aef4862017-03-19 15:47:42 +0000251static void vblank_query(data_t *data, int fd, int nchildren)
Chris Wilsone7d26df2015-03-19 15:24:52 +0000252{
Chris Wilson0aef4862017-03-19 15:47:42 +0000253 const uint32_t pipe_id_flag = kmstest_get_vbl_flag(data->pipe);
Chris Wilsone7d26df2015-03-19 15:24:52 +0000254 union drm_wait_vblank vbl;
255 struct timespec start, end;
256 unsigned long sq, count = 0;
Chris Wilsone7d26df2015-03-19 15:24:52 +0000257
258 memset(&vbl, 0, sizeof(vbl));
Chris Wilsone7d26df2015-03-19 15:24:52 +0000259 vbl.request.type = DRM_VBLANK_RELATIVE;
Robert Fossba865142016-05-18 20:07:07 -0400260 vbl.request.type |= pipe_id_flag;
Chris Wilsone7d26df2015-03-19 15:24:52 +0000261 vbl.request.sequence = 0;
Chris Wilson0aef4862017-03-19 15:47:42 +0000262 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Chris Wilsone7d26df2015-03-19 15:24:52 +0000263
264 sq = vbl.reply.sequence;
265
266 clock_gettime(CLOCK_MONOTONIC, &start);
267 do {
268 vbl.request.type = DRM_VBLANK_RELATIVE;
Robert Fossba865142016-05-18 20:07:07 -0400269 vbl.request.type |= pipe_id_flag;
Chris Wilsone7d26df2015-03-19 15:24:52 +0000270 vbl.request.sequence = 0;
Chris Wilson0aef4862017-03-19 15:47:42 +0000271 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Chris Wilsone7d26df2015-03-19 15:24:52 +0000272 count++;
Chris Wilson0aef4862017-03-19 15:47:42 +0000273 } while ((vbl.reply.sequence - sq) <= 120);
Chris Wilsone7d26df2015-03-19 15:24:52 +0000274 clock_gettime(CLOCK_MONOTONIC, &end);
275
276 igt_info("Time to query current counter (%s): %7.3fµs\n",
Chris Wilson0aef4862017-03-19 15:47:42 +0000277 data->flags & BUSY ? "busy" : "idle", elapsed(&start, &end, count));
Chris Wilson590e47c2015-04-02 11:37:23 +0100278}
279
Chris Wilson0aef4862017-03-19 15:47:42 +0000280static void vblank_wait(data_t *data, int fd, int nchildren)
Chris Wilson590e47c2015-04-02 11:37:23 +0100281{
Chris Wilson0aef4862017-03-19 15:47:42 +0000282 const uint32_t pipe_id_flag = kmstest_get_vbl_flag(data->pipe);
Chris Wilson590e47c2015-04-02 11:37:23 +0100283 union drm_wait_vblank vbl;
284 struct timespec start, end;
285 unsigned long sq, count = 0;
Chris Wilson590e47c2015-04-02 11:37:23 +0100286
287 memset(&vbl, 0, sizeof(vbl));
Chris Wilson590e47c2015-04-02 11:37:23 +0100288 vbl.request.type = DRM_VBLANK_RELATIVE;
Robert Fossba865142016-05-18 20:07:07 -0400289 vbl.request.type |= pipe_id_flag;
Chris Wilson590e47c2015-04-02 11:37:23 +0100290 vbl.request.sequence = 0;
Chris Wilson0aef4862017-03-19 15:47:42 +0000291 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Chris Wilson590e47c2015-04-02 11:37:23 +0100292
293 sq = vbl.reply.sequence;
294
295 clock_gettime(CLOCK_MONOTONIC, &start);
296 do {
297 vbl.request.type = DRM_VBLANK_RELATIVE;
Robert Fossba865142016-05-18 20:07:07 -0400298 vbl.request.type |= pipe_id_flag;
Chris Wilson590e47c2015-04-02 11:37:23 +0100299 vbl.request.sequence = 1;
Chris Wilson0aef4862017-03-19 15:47:42 +0000300 igt_assert_eq(wait_vblank(fd, &vbl), 0);
Chris Wilson590e47c2015-04-02 11:37:23 +0100301 count++;
Chris Wilson0aef4862017-03-19 15:47:42 +0000302 } while ((vbl.reply.sequence - sq) <= 120);
Chris Wilson590e47c2015-04-02 11:37:23 +0100303 clock_gettime(CLOCK_MONOTONIC, &end);
304
305 igt_info("Time to wait for %ld/%d vblanks (%s): %7.3fµs\n",
306 count, (int)(vbl.reply.sequence - sq),
Chris Wilson0aef4862017-03-19 15:47:42 +0000307 data->flags & BUSY ? "busy" : "idle",
Chris Wilson590e47c2015-04-02 11:37:23 +0100308 elapsed(&start, &end, count));
Chris Wilsone7d26df2015-03-19 15:24:52 +0000309}
310
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100311static void run_subtests_for_pipe(data_t *data)
Chris Wilsone7d26df2015-03-19 15:24:52 +0000312{
Chris Wilson0aef4862017-03-19 15:47:42 +0000313 const struct {
314 const char *name;
315 void (*func)(data_t *, int, int);
316 unsigned int valid;
317 } funcs[] = {
318 { "accuracy", accuracy, IDLE },
319 { "query", vblank_query, IDLE | FORKED | BUSY },
320 { "wait", vblank_wait, IDLE | FORKED | BUSY },
321 { }
322 }, *f;
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100323
Chris Wilson0aef4862017-03-19 15:47:42 +0000324 const struct {
325 const char *name;
326 unsigned int flags;
327 } modes[] = {
328 { "idle", IDLE },
329 { "forked", IDLE | FORKED },
330 { "busy", BUSY },
331 { "forked-busy", BUSY | FORKED },
332 { }
333 }, *m;
Chris Wilsone7d26df2015-03-19 15:24:52 +0000334
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100335 igt_fixture
336 igt_display_require_output_on_pipe(&data->display, data->pipe);
337
338 for (f = funcs; f->name; f++) {
339 for (m = modes; m->name; m++) {
340 if (m->flags & ~f->valid)
341 continue;
342
343 igt_subtest_f("pipe-%s-%s-%s",
344 kmstest_pipe_name(data->pipe),
345 f->name, m->name) {
346 for_each_valid_output_on_pipe(&data->display, data->pipe, data->output) {
347 data->flags = m->flags;
348 run_test(data, f->func);
349 }
350 }
351 }
352 }
353}
354
355igt_main
356{
357 int fd;
358 data_t data;
359
Chris Wilsone7d26df2015-03-19 15:24:52 +0000360 igt_skip_on_simulation();
361
362 igt_fixture {
Chris Wilsond0f996c2017-12-11 09:03:41 +0000363 fd = drm_open_driver_master(DRIVER_ANY);
Robert Fossba865142016-05-18 20:07:07 -0400364 kmstest_set_vt_graphics_mode();
365 igt_display_init(&data.display, fd);
Maarten Lankhorst4919d1f2017-11-22 14:10:54 +0100366 igt_display_require_output(&data.display);
Chris Wilsone7d26df2015-03-19 15:24:52 +0000367 }
368
Maarten Lankhorst4919d1f2017-11-22 14:10:54 +0100369 igt_subtest("crtc-id")
370 crtc_id_subtest(&data, fd);
371
Maarten Lankhorst8d7e9412018-01-03 11:18:01 +0100372 for_each_pipe_static(data.pipe)
373 igt_subtest_group
374 run_subtests_for_pipe(&data);
Chris Wilsone7d26df2015-03-19 15:24:52 +0000375}