Damien Lespiau | 241c5a1 | 2013-01-19 23:04:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. |
| 3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to |
| 4 | develop this 3D driver. |
| 5 | |
| 6 | Permission is hereby granted, free of charge, to any person obtaining |
| 7 | a copy of this software and associated documentation files (the |
| 8 | "Software"), to deal in the Software without restriction, including |
| 9 | without limitation the rights to use, copy, modify, merge, publish, |
| 10 | distribute, sublicense, and/or sell copies of the Software, and to |
| 11 | permit persons to whom the Software is furnished to do so, subject to |
| 12 | the following conditions: |
| 13 | |
| 14 | The above copyright notice and this permission notice (including the |
| 15 | next paragraph) shall be included in all copies or substantial |
| 16 | portions of the Software. |
| 17 | |
| 18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | |
| 26 | **********************************************************************/ |
| 27 | /* |
| 28 | * Authors: |
| 29 | * Keith Whitwell <keith@tungstengraphics.com> |
| 30 | */ |
| 31 | |
| 32 | |
| 33 | #include <string.h> |
| 34 | |
| 35 | #include "gen4asm.h" |
| 36 | #include "brw_context.h" |
| 37 | #include "brw_defines.h" |
| 38 | #include "brw_eu.h" |
| 39 | |
| 40 | #include "ralloc.h" |
| 41 | |
| 42 | /* Returns the corresponding conditional mod for swapping src0 and |
| 43 | * src1 in e.g. CMP. |
| 44 | */ |
| 45 | uint32_t |
| 46 | brw_swap_cmod(uint32_t cmod) |
| 47 | { |
| 48 | switch (cmod) { |
| 49 | case BRW_CONDITIONAL_Z: |
| 50 | case BRW_CONDITIONAL_NZ: |
| 51 | return cmod; |
| 52 | case BRW_CONDITIONAL_G: |
| 53 | return BRW_CONDITIONAL_L; |
| 54 | case BRW_CONDITIONAL_GE: |
| 55 | return BRW_CONDITIONAL_LE; |
| 56 | case BRW_CONDITIONAL_L: |
| 57 | return BRW_CONDITIONAL_G; |
| 58 | case BRW_CONDITIONAL_LE: |
| 59 | return BRW_CONDITIONAL_GE; |
| 60 | default: |
| 61 | return ~0; |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | |
| 66 | /* How does predicate control work when execution_size != 8? Do I |
| 67 | * need to test/set for 0xffff when execution_size is 16? |
| 68 | */ |
| 69 | void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value ) |
| 70 | { |
| 71 | p->current->header.predicate_control = BRW_PREDICATE_NONE; |
| 72 | |
| 73 | if (value != 0xff) { |
| 74 | if (value != p->flag_value) { |
| 75 | brw_push_insn_state(p); |
| 76 | brw_MOV(p, brw_flag_reg(0, 0), brw_imm_uw(value)); |
| 77 | p->flag_value = value; |
| 78 | brw_pop_insn_state(p); |
| 79 | } |
| 80 | |
| 81 | p->current->header.predicate_control = BRW_PREDICATE_NORMAL; |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | void brw_set_predicate_control( struct brw_compile *p, GLuint pc ) |
| 86 | { |
| 87 | p->current->header.predicate_control = pc; |
| 88 | } |
| 89 | |
| 90 | void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse) |
| 91 | { |
| 92 | p->current->header.predicate_inverse = predicate_inverse; |
| 93 | } |
| 94 | |
| 95 | void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional ) |
| 96 | { |
| 97 | p->current->header.destreg__conditionalmod = conditional; |
| 98 | } |
| 99 | |
| 100 | void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg) |
| 101 | { |
| 102 | p->current->bits2.da1.flag_reg_nr = reg; |
| 103 | p->current->bits2.da1.flag_subreg_nr = subreg; |
| 104 | } |
| 105 | |
| 106 | void brw_set_access_mode( struct brw_compile *p, GLuint access_mode ) |
| 107 | { |
| 108 | p->current->header.access_mode = access_mode; |
| 109 | } |
| 110 | |
| 111 | void |
| 112 | brw_set_compression_control(struct brw_compile *p, |
| 113 | enum brw_compression compression_control) |
| 114 | { |
| 115 | p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED); |
| 116 | |
| 117 | if (p->brw->intel.gen >= 6) { |
| 118 | /* Since we don't use the 32-wide support in gen6, we translate |
| 119 | * the pre-gen6 compression control here. |
| 120 | */ |
| 121 | switch (compression_control) { |
| 122 | case BRW_COMPRESSION_NONE: |
| 123 | /* This is the "use the first set of bits of dmask/vmask/arf |
| 124 | * according to execsize" option. |
| 125 | */ |
| 126 | p->current->header.compression_control = GEN6_COMPRESSION_1Q; |
| 127 | break; |
| 128 | case BRW_COMPRESSION_2NDHALF: |
| 129 | /* For 8-wide, this is "use the second set of 8 bits." */ |
| 130 | p->current->header.compression_control = GEN6_COMPRESSION_2Q; |
| 131 | break; |
| 132 | case BRW_COMPRESSION_COMPRESSED: |
| 133 | /* For 16-wide instruction compression, use the first set of 16 bits |
| 134 | * since we don't do 32-wide dispatch. |
| 135 | */ |
| 136 | p->current->header.compression_control = GEN6_COMPRESSION_1H; |
| 137 | break; |
| 138 | default: |
| 139 | assert(!"not reached"); |
| 140 | p->current->header.compression_control = GEN6_COMPRESSION_1H; |
| 141 | break; |
| 142 | } |
| 143 | } else { |
| 144 | p->current->header.compression_control = compression_control; |
| 145 | } |
| 146 | } |
| 147 | |
| 148 | void brw_set_mask_control( struct brw_compile *p, GLuint value ) |
| 149 | { |
| 150 | p->current->header.mask_control = value; |
| 151 | } |
| 152 | |
| 153 | void brw_set_saturate( struct brw_compile *p, bool enable ) |
| 154 | { |
| 155 | p->current->header.saturate = enable; |
| 156 | } |
| 157 | |
| 158 | void brw_set_acc_write_control(struct brw_compile *p, GLuint value) |
| 159 | { |
| 160 | if (p->brw->intel.gen >= 6) |
| 161 | p->current->header.acc_wr_control = value; |
| 162 | } |
| 163 | |
| 164 | void brw_push_insn_state( struct brw_compile *p ) |
| 165 | { |
| 166 | assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]); |
| 167 | memcpy(p->current+1, p->current, sizeof(struct brw_instruction)); |
| 168 | p->compressed_stack[p->current - p->stack] = p->compressed; |
| 169 | p->current++; |
| 170 | } |
| 171 | |
| 172 | void brw_pop_insn_state( struct brw_compile *p ) |
| 173 | { |
| 174 | assert(p->current != p->stack); |
| 175 | p->current--; |
| 176 | p->compressed = p->compressed_stack[p->current - p->stack]; |
| 177 | } |
| 178 | |
| 179 | |
| 180 | /*********************************************************************** |
| 181 | */ |
| 182 | void |
| 183 | brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx) |
| 184 | { |
| 185 | memset(p, 0, sizeof(*p)); |
| 186 | |
| 187 | p->brw = brw; |
| 188 | /* |
| 189 | * Set the initial instruction store array size to 1024, if found that |
| 190 | * isn't enough, then it will double the store size at brw_next_insn() |
| 191 | * until out of memory. |
| 192 | */ |
| 193 | p->store_size = 1024; |
| 194 | p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size); |
| 195 | p->nr_insn = 0; |
| 196 | p->current = p->stack; |
| 197 | p->compressed = false; |
| 198 | memset(p->current, 0, sizeof(p->current[0])); |
| 199 | |
| 200 | p->mem_ctx = mem_ctx; |
| 201 | |
| 202 | /* Some defaults? |
| 203 | */ |
| 204 | brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */ |
| 205 | brw_set_saturate(p, 0); |
| 206 | brw_set_compression_control(p, BRW_COMPRESSION_NONE); |
| 207 | brw_set_predicate_control_flag_value(p, 0xff); |
| 208 | |
| 209 | /* Set up control flow stack */ |
| 210 | p->if_stack_depth = 0; |
| 211 | p->if_stack_array_size = 16; |
| 212 | p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size); |
| 213 | |
| 214 | p->loop_stack_depth = 0; |
| 215 | p->loop_stack_array_size = 16; |
| 216 | p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size); |
| 217 | p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size); |
| 218 | |
| 219 | brw_init_compaction_tables(&brw->intel); |
| 220 | } |
| 221 | |
| 222 | |
| 223 | const GLuint *brw_get_program( struct brw_compile *p, |
| 224 | GLuint *sz ) |
| 225 | { |
| 226 | brw_compact_instructions(p); |
| 227 | |
| 228 | *sz = p->next_insn_offset; |
| 229 | return (const GLuint *)p->store; |
| 230 | } |
| 231 | |
| 232 | void |
| 233 | brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end) |
| 234 | { |
| 235 | struct brw_context *brw = p->brw; |
| 236 | struct intel_context *intel = &brw->intel; |
| 237 | void *store = p->store; |
| 238 | bool dump_hex = false; |
| 239 | |
| 240 | for (int offset = start; offset < end;) { |
| 241 | struct brw_instruction *insn = store + offset; |
| 242 | struct brw_instruction uncompacted; |
| 243 | printf("0x%08x: ", offset); |
| 244 | |
| 245 | if (insn->header.cmpt_control) { |
| 246 | struct brw_compact_instruction *compacted = (void *)insn; |
| 247 | if (dump_hex) { |
| 248 | printf("0x%08x 0x%08x ", |
| 249 | ((uint32_t *)insn)[1], |
| 250 | ((uint32_t *)insn)[0]); |
| 251 | } |
| 252 | |
| 253 | brw_uncompact_instruction(intel, &uncompacted, compacted); |
| 254 | insn = &uncompacted; |
| 255 | offset += 8; |
| 256 | } else { |
| 257 | if (dump_hex) { |
| 258 | printf("0x%08x 0x%08x 0x%08x 0x%08x ", |
| 259 | ((uint32_t *)insn)[3], |
| 260 | ((uint32_t *)insn)[2], |
| 261 | ((uint32_t *)insn)[1], |
| 262 | ((uint32_t *)insn)[0]); |
| 263 | } |
| 264 | offset += 16; |
| 265 | } |
| 266 | |
| 267 | brw_disasm(stdout, insn, p->brw->intel.gen); |
| 268 | } |
| 269 | } |