blob: 704ad2356424634758c661bb577436a81049571d [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
29#include <stdio.h>
30#include <stdlib.h>
31#include <string.h>
32#include <stdarg.h>
33#include <sys/types.h>
34#include <sys/mman.h>
35#include <pciaccess.h>
36#include <err.h>
37#include <unistd.h>
38#include <fcntl.h>
39#include <getopt.h>
40#include <arpa/inet.h>
41#include "intel_gpu_tools.h"
42
43#define AUD_CONFIG 0x62000
44#define AUD_DEBUG 0x62010
45#define AUD_VID_DID 0x62020
46#define AUD_RID 0x62024
47#define AUD_SUBN_CNT 0x62028
48#define AUD_FUNC_GRP 0x62040
49#define AUD_SUBN_CNT2 0x62044
50#define AUD_GRP_CAP 0x62048
51#define AUD_PWRST 0x6204c
52#define AUD_SUPPWR 0x62050
53#define AUD_SID 0x62054
54#define AUD_OUT_CWCAP 0x62070
55#define AUD_OUT_PCMSIZE 0x62074
56#define AUD_OUT_STR 0x62078
57#define AUD_OUT_DIG_CNVT 0x6207c
58#define AUD_OUT_CH_STR 0x62080
59#define AUD_OUT_STR_DESC 0x62084
60#define AUD_PINW_CAP 0x620a0
61#define AUD_PIN_CAP 0x620a4
62#define AUD_PINW_CONNLNG 0x620a8
63#define AUD_PINW_CONNLST 0x620ac
64#define AUD_PINW_CNTR 0x620b0
65#define AUD_PINW_UNSOLRESP 0x620b8
66#define AUD_CNTL_ST 0x620b4
67#define AUD_PINW_CONFIG 0x620bc
68#define AUD_HDMIW_STATUS 0x620d4
69#define AUD_HDMIW_HDMIEDID 0x6210c
70#define AUD_HDMIW_INFOFR 0x62118
71#define AUD_CONV_CHCNT 0x62120
72#define AUD_CTS_ENABLE 0x62128
73
74#define VIDEO_DIP_CTL 0x61170
75#define VIDEO_DIP_ENABLE (1<<31)
76#define VIDEO_DIP_ENABLE_AVI (1<<21)
77#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
78#define VIDEO_DIP_ENABLE_SPD (1<<24)
79#define VIDEO_DIP_BUF_AVI (0<<19)
80#define VIDEO_DIP_BUF_VENDOR (1<<19)
81#define VIDEO_DIP_BUF_SPD (3<<19)
82#define VIDEO_DIP_TRANS_ONCE (0<<16)
83#define VIDEO_DIP_TRANS_1 (1<<16)
84#define VIDEO_DIP_TRANS_2 (2<<16)
85
86#define AUDIO_HOTPLUG_EN (1<<24)
87
88
89#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
90#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
91#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
92#define BIT(reg, n) BITS(reg, n, n)
93
94#define min_t(type, x, y) ({ \
95 type __min1 = (x); \
96 type __min2 = (y); \
97 __min1 < __min2 ? __min1: __min2; })
98
99#define OPNAME(names, index) \
100 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
101
102#define dump_reg(reg, desc) \
103 do { \
104 dword = INREG(reg); \
105 printf("%-18s 0x%08x %s\n", # reg, dword, desc); \
106 } while (0)
107
108
109static char *pixel_clock[] = {
110 [0] = "25.2 / 1.001 MHz",
111 [1] = "25.2 MHz",
112 [2] = "27 MHz",
113 [3] = "27 * 1.001 MHz",
114 [4] = "54 MHz",
115 [5] = "54 * 1.001 MHz",
116 [6] = "74.25 / 1.001 MHz",
117 [7] = "74.25 MHz",
118 [8] = "148.5 / 1.001 MHz",
119 [9] = "148.5 MHz",
120 [10] = "Reserved",
121};
122
123static char *power_state[] = {
124 [0] = "D0",
125 [1] = "D1",
126 [2] = "D2",
127 [3] = "D3",
128};
129
130static char *stream_type[] = {
131 [0] = "default samples",
132 [1] = "one bit stream",
133 [2] = "DST stream",
134 [3] = "MLP stream",
135 [4] = "Reserved",
136};
137
138static char *dip_port[] = {
139 [0] = "Reserved",
140 [1] = "HDMI B",
141 [2] = "HDMI C",
142 [3] = "Reserved",
143};
144
145static char *dip_index[] = {
146 [0] = "Audio DIP",
147 [1] = "ACP DIP",
148 [2] = "ISRC1 DIP",
149 [3] = "ISRC2 DIP",
150 [4] = "Reserved",
151};
152
153static char *dip_trans[] = {
154 [0] = "disabled",
155 [1] = "reserved",
156 [2] = "send once",
157 [3] = "best effort",
158};
159
160static char *video_dip_index[] = {
161 [0] = "AVI DIP",
162 [1] = "Vendor-specific DIP",
163 [2] = "Reserved",
164 [3] = "Source Product Description DIP",
165};
166
167static char *video_dip_trans[] = {
168 [0] = "send once",
169 [1] = "send every vsync",
170 [2] = "send at least every other vsync",
171 [3] = "reserved",
172};
173
174static void do_self_tests(void)
175{
176 if (BIT(1, 0) != 1)
177 exit(1);
178 if (BIT(0x80000000, 31) != 1)
179 exit(2);
180 if (BITS(0xc0000000, 31, 30) != 3)
181 exit(3);
182}
183
184int main(int argc, char **argv)
185{
186 uint32_t dword;
187 int i;
188
189 do_self_tests();
190 intel_get_mmio();
191
192 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
193
194 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
195 dump_reg(SDVOB, "Digital Display Port B Control Register");
196 dump_reg(SDVOC, "Digital Display Port C Control Register");
197 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
198
199 dump_reg(AUD_CONFIG, "Audio Configuration");
200 dump_reg(AUD_DEBUG, "Audio Debug");
201 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
202 dump_reg(AUD_RID, "Audio Revision ID");
203 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
204 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
205 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
206 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
207 dump_reg(AUD_PWRST, "Audio Power State");
208 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
209 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
210 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
211 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
212 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
213 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
214 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
215 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
216 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
217 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
218 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
219 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
220 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
221 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
222 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
223 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
224 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
225 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
226 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
227 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
228 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
229
230 printf("\nDetails:\n\n");
231
232 dword = INREG(AUD_VID_DID);
233 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
234 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
235
236 dword = INREG(AUD_RID);
237 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
238 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
239 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
240 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
241
242 dword = INREG(SDVOB);
243 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
244 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
245 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
246 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
247 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
248
249 dword = INREG(SDVOC);
250 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
251 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
252 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
253 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
254 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
255
256 dword = INREG(PORT_HOTPLUG_EN);
257 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
258 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
259 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
260 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
261 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
262 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
263 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
264 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
265
266 dword = INREG(VIDEO_DIP_CTL);
267 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
268 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
269 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
270 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
271 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
272 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
273 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
274 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
275 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
276 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
277 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
278 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
279 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
280
281 dword = INREG(AUD_CONFIG);
282 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
283 OPNAME(pixel_clock, BITS(dword, 19, 16)));
284 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
285 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
286 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
287
288 dword = INREG(AUD_DEBUG);
289 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
290
291 dword = INREG(AUD_SUBN_CNT);
292 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
293 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
294
295 dword = INREG(AUD_SUBN_CNT2);
296 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
297 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
298
299 dword = INREG(AUD_FUNC_GRP);
300 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
301 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
302
303 dword = INREG(AUD_GRP_CAP);
304 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
305 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
306 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
307
308 dword = INREG(AUD_PWRST);
309 printf("AUD_PWRST device power state\t\t%s\n",
310 power_state[BITS(dword, 5, 4)]);
311 printf("AUD_PWRST device power state setting\t%s\n",
312 power_state[BITS(dword, 1, 0)]);
313
314 dword = INREG(AUD_SUPPWR);
315 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
316 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
317 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
318 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
319
320 dword = INREG(AUD_OUT_CWCAP);
321 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
322 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
323 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
324 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
325 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
326 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
327 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
328 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
329 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
330 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
331 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
332 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
333 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
334 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
335
336 dword = INREG(AUD_OUT_DIG_CNVT);
337 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
338 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
339 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
340 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
341 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
342 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
343 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
344 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
345 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
346
347 dword = INREG(AUD_OUT_CH_STR);
348 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
349 printf("AUD_OUT_CH_STR lowest channel\t\t0x%lx\n", BITS(dword, 3, 0));
350
351 dword = INREG(AUD_OUT_STR_DESC);
352 printf("AUD_OUT_STR_DESC stream channels\t0x%lx\n", BITS(dword, 3, 0));
353
354 dword = INREG(AUD_PINW_CAP);
355 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
356 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
357 printf("AUD_PINW_CAP channel count\t\t0x%lx\n",
358 BITS(dword, 15, 13) * 2 + BIT(dword, 0));
359 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
360 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
361 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
362 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
363 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
364 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
365 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
366 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
367 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
368 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
369 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
370
371
372 dword = INREG(AUD_PIN_CAP);
373 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
374 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
375 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
376 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
377
378 dword = INREG(AUD_PINW_CNTR);
379 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
380 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
381 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
382 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
383 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
384 BITS(dword, 2, 0),
385 OPNAME(stream_type, BITS(dword, 2, 0)));
386
387 dword = INREG(AUD_PINW_UNSOLRESP);
388 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
389
390 dword = INREG(AUD_CNTL_ST);
391 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
392 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
393 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
394 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
395 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
396 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
397 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
398 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
399 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
400 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
401 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
402 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
403 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
404 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
405 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
406
407 dword = INREG(AUD_HDMIW_STATUS);
408 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
409 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
410 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
411 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
412
413 dword = INREG(AUD_CONV_CHCNT);
414 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
415 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
416
417 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
418 for (i = 0; i < 8; i++) {
419 OUTREG(AUD_CONV_CHCNT, i);
420 dword = INREG(AUD_CONV_CHCNT);
421 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
422 }
423
424 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
425 dword = INREG(AUD_CNTL_ST);
426 dword &= ~BITMASK(20, 18);
427 dword &= ~BITMASK(3, 0);
428 OUTREG(AUD_CNTL_ST, dword);
429 for (i = 0; i < 8; i++)
430 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
431 printf("\n");
432
433 return 0;
434}