Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2011 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Daniel Vetter <daniel.vetter@ffwll.ch> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <stdlib.h> |
| 29 | #include <stdio.h> |
| 30 | #include <string.h> |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 31 | #include <fcntl.h> |
| 32 | #include <inttypes.h> |
| 33 | #include <errno.h> |
| 34 | #include <sys/stat.h> |
| 35 | #include <sys/time.h> |
| 36 | #include "drm.h" |
Daniel Vetter | e49ceb8 | 2014-03-22 21:07:37 +0100 | [diff] [blame^] | 37 | #include "ioctl_wrappers.h" |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 38 | #include "drmtest.h" |
Daniel Vetter | e49ceb8 | 2014-03-22 21:07:37 +0100 | [diff] [blame^] | 39 | #include "intel_chipset.h" |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 40 | #include "intel_bufmgr.h" |
| 41 | #include "intel_batchbuffer.h" |
| 42 | #include "intel_gpu_tools.h" |
| 43 | |
| 44 | /* |
| 45 | * Testcase: pwrite/pread consistency when touching partial cachelines |
| 46 | * |
| 47 | * Some fancy new pwrite/pread optimizations clflush in-line while |
| 48 | * reading/writing. Check whether all required clflushes happen. |
| 49 | * |
| 50 | */ |
| 51 | |
| 52 | static drm_intel_bufmgr *bufmgr; |
| 53 | struct intel_batchbuffer *batch; |
| 54 | |
| 55 | drm_intel_bo *scratch_bo; |
| 56 | drm_intel_bo *staging_bo; |
| 57 | #define BO_SIZE (4*4096) |
| 58 | uint32_t devid; |
Daniel Vetter | d75d69d | 2012-01-15 18:32:11 +0100 | [diff] [blame] | 59 | uint64_t mappable_gtt_limit; |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 60 | int fd; |
| 61 | |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 62 | static void |
| 63 | copy_bo(drm_intel_bo *src, drm_intel_bo *dst) |
| 64 | { |
Ben Widawsky | f4dfa37 | 2013-10-08 15:02:07 -0700 | [diff] [blame] | 65 | BLIT_COPY_BATCH_START(devid, 0); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 66 | OUT_BATCH((3 << 24) | /* 32 bits */ |
| 67 | (0xcc << 16) | /* copy ROP */ |
| 68 | 4096); |
| 69 | OUT_BATCH(0 << 16 | 0); |
| 70 | OUT_BATCH((BO_SIZE/4096) << 16 | 1024); |
| 71 | OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); |
Ben Widawsky | f4dfa37 | 2013-10-08 15:02:07 -0700 | [diff] [blame] | 72 | BLIT_RELOC_UDW(devid); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 73 | OUT_BATCH(0 << 16 | 0); |
| 74 | OUT_BATCH(4096); |
| 75 | OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0); |
Ben Widawsky | f4dfa37 | 2013-10-08 15:02:07 -0700 | [diff] [blame] | 76 | BLIT_RELOC_UDW(devid); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 77 | ADVANCE_BATCH(); |
| 78 | |
| 79 | intel_batchbuffer_flush(batch); |
| 80 | } |
| 81 | |
| 82 | static void |
| 83 | blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val) |
| 84 | { |
| 85 | uint8_t *gtt_ptr; |
| 86 | int i; |
| 87 | |
| 88 | drm_intel_gem_bo_map_gtt(tmp_bo); |
| 89 | gtt_ptr = tmp_bo->virtual; |
| 90 | |
| 91 | for (i = 0; i < BO_SIZE; i++) |
| 92 | gtt_ptr[i] = val; |
| 93 | |
| 94 | drm_intel_gem_bo_unmap_gtt(tmp_bo); |
| 95 | |
Daniel Vetter | d75d69d | 2012-01-15 18:32:11 +0100 | [diff] [blame] | 96 | if (bo->offset < mappable_gtt_limit && |
Daniel Vetter | ff409c5 | 2011-12-06 16:57:53 +0100 | [diff] [blame] | 97 | (IS_G33(devid) || intel_gen(devid) >= 4)) |
Daniel Vetter | 1caaf0a | 2013-08-12 12:17:35 +0200 | [diff] [blame] | 98 | igt_trash_aperture(); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 99 | |
| 100 | copy_bo(tmp_bo, bo); |
| 101 | } |
| 102 | |
| 103 | #define MAX_BLT_SIZE 128 |
Daniel Vetter | 36a40a5 | 2012-01-31 13:52:59 +0100 | [diff] [blame] | 104 | #define ROUNDS 1000 |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 105 | uint8_t tmp[BO_SIZE]; |
| 106 | |
| 107 | static void test_partial_reads(void) |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 108 | { |
| 109 | int i, j; |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 110 | |
| 111 | printf("checking partial reads\n"); |
Daniel Vetter | 36a40a5 | 2012-01-31 13:52:59 +0100 | [diff] [blame] | 112 | for (i = 0; i < ROUNDS; i++) { |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 113 | int start, len; |
| 114 | int val = i % 256; |
| 115 | |
| 116 | blt_bo_fill(staging_bo, scratch_bo, i); |
| 117 | |
| 118 | start = random() % BO_SIZE; |
| 119 | len = random() % (BO_SIZE-start) + 1; |
| 120 | |
| 121 | drm_intel_bo_get_subdata(scratch_bo, start, len, tmp); |
| 122 | for (j = 0; j < len; j++) { |
Daniel Vetter | f3c54d0 | 2013-09-25 14:36:59 +0200 | [diff] [blame] | 123 | igt_assert_f(tmp[j] == val, |
| 124 | "mismatch at %i, got: %i, expected: %i\n", |
| 125 | j, tmp[j], val); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 126 | } |
Daniel Vetter | 36a40a5 | 2012-01-31 13:52:59 +0100 | [diff] [blame] | 127 | |
Daniel Vetter | 1caaf0a | 2013-08-12 12:17:35 +0200 | [diff] [blame] | 128 | igt_progress("partial reads test: ", i, ROUNDS); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 129 | } |
| 130 | |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | static void test_partial_writes(void) |
| 134 | { |
| 135 | int i, j; |
| 136 | uint8_t *gtt_ptr; |
| 137 | |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 138 | printf("checking partial writes\n"); |
Daniel Vetter | 36a40a5 | 2012-01-31 13:52:59 +0100 | [diff] [blame] | 139 | for (i = 0; i < ROUNDS; i++) { |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 140 | int start, len; |
| 141 | int val = i % 256; |
| 142 | |
| 143 | blt_bo_fill(staging_bo, scratch_bo, i); |
| 144 | |
| 145 | start = random() % BO_SIZE; |
| 146 | len = random() % (BO_SIZE-start) + 1; |
| 147 | |
| 148 | memset(tmp, i + 63, BO_SIZE); |
| 149 | |
| 150 | drm_intel_bo_subdata(scratch_bo, start, len, tmp); |
| 151 | |
| 152 | copy_bo(scratch_bo, staging_bo); |
| 153 | drm_intel_gem_bo_map_gtt(staging_bo); |
| 154 | gtt_ptr = staging_bo->virtual; |
| 155 | |
| 156 | for (j = 0; j < start; j++) { |
Daniel Vetter | f3c54d0 | 2013-09-25 14:36:59 +0200 | [diff] [blame] | 157 | igt_assert_f(gtt_ptr[j] == val, |
| 158 | "mismatch at %i, got: %i, expected: %i\n", |
| 159 | j, tmp[j], val); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 160 | } |
| 161 | for (; j < start + len; j++) { |
Daniel Vetter | f3c54d0 | 2013-09-25 14:36:59 +0200 | [diff] [blame] | 162 | igt_assert_f(gtt_ptr[j] == tmp[0], |
| 163 | "mismatch at %i, got: %i, expected: %i\n", |
| 164 | j, tmp[j], i); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 165 | } |
| 166 | for (; j < BO_SIZE; j++) { |
Daniel Vetter | f3c54d0 | 2013-09-25 14:36:59 +0200 | [diff] [blame] | 167 | igt_assert_f(gtt_ptr[j] == val, |
| 168 | "mismatch at %i, got: %i, expected: %i\n", |
| 169 | j, tmp[j], val); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 170 | } |
| 171 | drm_intel_gem_bo_unmap_gtt(staging_bo); |
Daniel Vetter | 36a40a5 | 2012-01-31 13:52:59 +0100 | [diff] [blame] | 172 | |
Daniel Vetter | 1caaf0a | 2013-08-12 12:17:35 +0200 | [diff] [blame] | 173 | igt_progress("partial writes test: ", i, ROUNDS); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 174 | } |
| 175 | |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | static void test_partial_read_writes(void) |
| 179 | { |
| 180 | int i, j; |
| 181 | uint8_t *gtt_ptr; |
| 182 | |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 183 | printf("checking partial writes after partial reads\n"); |
Daniel Vetter | 36a40a5 | 2012-01-31 13:52:59 +0100 | [diff] [blame] | 184 | for (i = 0; i < ROUNDS; i++) { |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 185 | int start, len; |
| 186 | int val = i % 256; |
| 187 | |
| 188 | blt_bo_fill(staging_bo, scratch_bo, i); |
| 189 | |
| 190 | /* partial read */ |
| 191 | start = random() % BO_SIZE; |
| 192 | len = random() % (BO_SIZE-start) + 1; |
| 193 | |
| 194 | drm_intel_bo_get_subdata(scratch_bo, start, len, tmp); |
| 195 | for (j = 0; j < len; j++) { |
Daniel Vetter | f3c54d0 | 2013-09-25 14:36:59 +0200 | [diff] [blame] | 196 | igt_assert_f(tmp[j] == val, |
| 197 | "mismatch in read at %i, got: %i, expected: %i\n", |
| 198 | j, tmp[j], val); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | /* Change contents through gtt to make the pread cachelines |
| 202 | * stale. */ |
| 203 | val = (i + 17) % 256; |
| 204 | blt_bo_fill(staging_bo, scratch_bo, val); |
| 205 | |
| 206 | /* partial write */ |
| 207 | start = random() % BO_SIZE; |
| 208 | len = random() % (BO_SIZE-start) + 1; |
| 209 | |
| 210 | memset(tmp, i + 63, BO_SIZE); |
| 211 | |
| 212 | drm_intel_bo_subdata(scratch_bo, start, len, tmp); |
| 213 | |
| 214 | copy_bo(scratch_bo, staging_bo); |
| 215 | drm_intel_gem_bo_map_gtt(staging_bo); |
| 216 | gtt_ptr = staging_bo->virtual; |
| 217 | |
| 218 | for (j = 0; j < start; j++) { |
Daniel Vetter | f3c54d0 | 2013-09-25 14:36:59 +0200 | [diff] [blame] | 219 | igt_assert_f(gtt_ptr[j] == val, |
| 220 | "mismatch at %i, got: %i, expected: %i\n", |
| 221 | j, tmp[j], val); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 222 | } |
| 223 | for (; j < start + len; j++) { |
Daniel Vetter | f3c54d0 | 2013-09-25 14:36:59 +0200 | [diff] [blame] | 224 | igt_assert_f(gtt_ptr[j] == tmp[0], |
| 225 | "mismatch at %i, got: %i, expected: %i\n", |
| 226 | j, tmp[j], tmp[0]); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 227 | } |
| 228 | for (; j < BO_SIZE; j++) { |
Daniel Vetter | f3c54d0 | 2013-09-25 14:36:59 +0200 | [diff] [blame] | 229 | igt_assert_f(gtt_ptr[j] == val, |
| 230 | "mismatch at %i, got: %i, expected: %i\n", |
| 231 | j, tmp[j], val); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 232 | } |
| 233 | drm_intel_gem_bo_unmap_gtt(staging_bo); |
Daniel Vetter | 36a40a5 | 2012-01-31 13:52:59 +0100 | [diff] [blame] | 234 | |
Daniel Vetter | 1caaf0a | 2013-08-12 12:17:35 +0200 | [diff] [blame] | 235 | igt_progress("partial read/writes test: ", i, ROUNDS); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 236 | } |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 237 | } |
| 238 | |
Chris Wilson | a661c09 | 2013-08-06 15:09:50 +0100 | [diff] [blame] | 239 | static void do_tests(int cache_level, const char *suffix) |
| 240 | { |
Daniel Vetter | b3880d3 | 2013-08-14 18:02:46 +0200 | [diff] [blame] | 241 | igt_fixture { |
| 242 | if (cache_level != -1) |
| 243 | gem_set_caching(fd, scratch_bo->handle, cache_level); |
| 244 | } |
Chris Wilson | a661c09 | 2013-08-06 15:09:50 +0100 | [diff] [blame] | 245 | |
Daniel Vetter | 6234658 | 2013-08-14 13:47:47 +0200 | [diff] [blame] | 246 | igt_subtest_f("reads%s", suffix) |
Chris Wilson | a661c09 | 2013-08-06 15:09:50 +0100 | [diff] [blame] | 247 | test_partial_reads(); |
| 248 | |
Daniel Vetter | 6234658 | 2013-08-14 13:47:47 +0200 | [diff] [blame] | 249 | igt_subtest_f("write%s", suffix) |
Chris Wilson | a661c09 | 2013-08-06 15:09:50 +0100 | [diff] [blame] | 250 | test_partial_writes(); |
| 251 | |
Daniel Vetter | 6234658 | 2013-08-14 13:47:47 +0200 | [diff] [blame] | 252 | igt_subtest_f("writes-after-reads%s", suffix) |
Chris Wilson | a661c09 | 2013-08-06 15:09:50 +0100 | [diff] [blame] | 253 | test_partial_read_writes(); |
| 254 | } |
| 255 | |
Daniel Vetter | 071e9ca | 2013-10-31 16:23:26 +0100 | [diff] [blame] | 256 | igt_main |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 257 | { |
| 258 | srandom(0xdeadbeef); |
| 259 | |
Daniel Vetter | 1caaf0a | 2013-08-12 12:17:35 +0200 | [diff] [blame] | 260 | igt_skip_on_simulation(); |
Daniel Vetter | 046b149 | 2012-11-28 13:08:07 +0100 | [diff] [blame] | 261 | |
Daniel Vetter | b3880d3 | 2013-08-14 18:02:46 +0200 | [diff] [blame] | 262 | igt_fixture { |
| 263 | fd = drm_open_any(); |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 264 | |
Daniel Vetter | b3880d3 | 2013-08-14 18:02:46 +0200 | [diff] [blame] | 265 | bufmgr = drm_intel_bufmgr_gem_init(fd, 4096); |
| 266 | //drm_intel_bufmgr_gem_enable_reuse(bufmgr); |
| 267 | devid = intel_get_drm_devid(fd); |
| 268 | batch = intel_batchbuffer_alloc(bufmgr, devid); |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 269 | |
Daniel Vetter | b3880d3 | 2013-08-14 18:02:46 +0200 | [diff] [blame] | 270 | /* overallocate the buffers we're actually using because */ |
| 271 | scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096); |
| 272 | staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096); |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 273 | |
Daniel Vetter | b3880d3 | 2013-08-14 18:02:46 +0200 | [diff] [blame] | 274 | igt_init_aperture_trashers(bufmgr); |
| 275 | mappable_gtt_limit = gem_mappable_aperture_size(); |
| 276 | } |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 277 | |
Chris Wilson | a661c09 | 2013-08-06 15:09:50 +0100 | [diff] [blame] | 278 | do_tests(-1, ""); |
Daniel Vetter | 1a55ca7 | 2012-11-28 12:47:26 +0100 | [diff] [blame] | 279 | |
Chris Wilson | a661c09 | 2013-08-06 15:09:50 +0100 | [diff] [blame] | 280 | /* Repeat the tests using different levels of snooping */ |
| 281 | do_tests(0, "-uncached"); |
| 282 | do_tests(1, "-snoop"); |
Chris Wilson | 467796a | 2013-08-10 15:49:33 +0100 | [diff] [blame] | 283 | do_tests(2, "-display"); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 284 | |
Daniel Vetter | b3880d3 | 2013-08-14 18:02:46 +0200 | [diff] [blame] | 285 | igt_fixture { |
| 286 | igt_cleanup_aperture_trashers(); |
| 287 | drm_intel_bufmgr_destroy(bufmgr); |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 288 | |
Daniel Vetter | b3880d3 | 2013-08-14 18:02:46 +0200 | [diff] [blame] | 289 | close(fd); |
| 290 | } |
Daniel Vetter | 5a851b1 | 2011-12-04 21:42:31 +0100 | [diff] [blame] | 291 | } |