Eric Anholt | 29777a5 | 2009-03-27 10:59:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
Ville Syrjälä | 84b525c | 2013-02-18 21:41:10 +0200 | [diff] [blame] | 28 | #ifndef _INTEL_CHIPSET_H |
| 29 | #define _INTEL_CHIPSET_H |
| 30 | |
Daniel Vetter | aed95c3 | 2014-03-22 14:54:28 +0100 | [diff] [blame] | 31 | #include <pciaccess.h> |
Chris Wilson | d308bb0 | 2016-06-29 08:28:58 +0100 | [diff] [blame] | 32 | #include <stdbool.h> |
Daniel Vetter | aed95c3 | 2014-03-22 14:54:28 +0100 | [diff] [blame] | 33 | |
| 34 | struct pci_device *intel_get_pci_device(void); |
| 35 | uint32_t intel_get_drm_devid(int fd); |
Chris Wilson | d308bb0 | 2016-06-29 08:28:58 +0100 | [diff] [blame] | 36 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 37 | struct intel_device_info { |
Chris Wilson | d308bb0 | 2016-06-29 08:28:58 +0100 | [diff] [blame] | 38 | unsigned gen; |
| 39 | bool is_mobile : 1; |
| 40 | bool is_whitney : 1; |
| 41 | bool is_almador : 1; |
| 42 | bool is_brookdale : 1; |
| 43 | bool is_montara : 1; |
| 44 | bool is_springdale : 1; |
| 45 | bool is_grantsdale : 1; |
| 46 | bool is_alviso : 1; |
| 47 | bool is_lakeport : 1; |
| 48 | bool is_calistoga : 1; |
| 49 | bool is_bearlake : 1; |
| 50 | bool is_pineview : 1; |
| 51 | bool is_broadwater : 1; |
| 52 | bool is_crestline : 1; |
| 53 | bool is_eaglelake : 1; |
| 54 | bool is_cantiga : 1; |
| 55 | bool is_ironlake : 1; |
| 56 | bool is_arrandale : 1; |
| 57 | bool is_sandybridge : 1; |
| 58 | bool is_ivybridge : 1; |
| 59 | bool is_valleyview : 1; |
| 60 | bool is_haswell : 1; |
| 61 | bool is_broadwell : 1; |
| 62 | bool is_cherryview : 1; |
| 63 | bool is_skylake : 1; |
| 64 | bool is_broxton : 1; |
| 65 | bool is_kabylake : 1; |
Ander Conselvan de Oliveira | c7c581a | 2016-12-20 13:51:01 +0200 | [diff] [blame] | 66 | bool is_geminilake : 1; |
Rodrigo Vivi | 68a3eb1 | 2017-01-04 15:09:35 -0800 | [diff] [blame] | 67 | bool is_coffeelake : 1; |
Rodrigo Vivi | 23536e0 | 2017-01-04 15:22:36 -0800 | [diff] [blame] | 68 | bool is_cannonlake : 1; |
Chris Wilson | d308bb0 | 2016-06-29 08:28:58 +0100 | [diff] [blame] | 69 | const char *codename; |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure)); |
Chris Wilson | d308bb0 | 2016-06-29 08:28:58 +0100 | [diff] [blame] | 73 | |
| 74 | unsigned intel_gen(uint16_t devid) __attribute__((pure)); |
Chris Wilson | 2aa3dc8 | 2016-06-29 12:11:28 +0100 | [diff] [blame] | 75 | unsigned intel_gt(uint16_t devid) __attribute__((pure)); |
Daniel Vetter | aed95c3 | 2014-03-22 14:54:28 +0100 | [diff] [blame] | 76 | |
Daniel Vetter | 266b26b | 2014-03-22 14:59:58 +0100 | [diff] [blame] | 77 | extern enum pch_type intel_pch; |
Daniel Vetter | 6cfcd71 | 2014-03-22 20:07:35 +0100 | [diff] [blame] | 78 | |
Daniel Vetter | aed95c3 | 2014-03-22 14:54:28 +0100 | [diff] [blame] | 79 | enum pch_type { |
| 80 | PCH_NONE, |
| 81 | PCH_IBX, |
| 82 | PCH_CPT, |
| 83 | PCH_LPT, |
| 84 | }; |
| 85 | |
| 86 | void intel_check_pch(void); |
| 87 | |
Daniel Vetter | 266b26b | 2014-03-22 14:59:58 +0100 | [diff] [blame] | 88 | #define HAS_IBX (intel_pch == PCH_IBX) |
| 89 | #define HAS_CPT (intel_pch == PCH_CPT) |
| 90 | #define HAS_LPT (intel_pch == PCH_LPT) |
Daniel Vetter | aed95c3 | 2014-03-22 14:54:28 +0100 | [diff] [blame] | 91 | |
Daniel Vetter | a8e8654 | 2014-03-22 15:12:57 +0100 | [diff] [blame] | 92 | /* Exclude chipset #defines, they just add noise */ |
| 93 | #ifndef __GTK_DOC_IGNORE__ |
| 94 | |
Eric Anholt | 29777a5 | 2009-03-27 10:59:09 -0700 | [diff] [blame] | 95 | #define PCI_CHIP_I810 0x7121 |
| 96 | #define PCI_CHIP_I810_DC100 0x7123 |
| 97 | #define PCI_CHIP_I810_E 0x7125 |
| 98 | #define PCI_CHIP_I815 0x1132 |
| 99 | |
| 100 | #define PCI_CHIP_I830_M 0x3577 |
| 101 | #define PCI_CHIP_845_G 0x2562 |
Ville Syrjälä | e5e7a53 | 2015-03-16 13:19:48 +0200 | [diff] [blame] | 102 | #define PCI_CHIP_I854_G 0x358e |
Eric Anholt | 29777a5 | 2009-03-27 10:59:09 -0700 | [diff] [blame] | 103 | #define PCI_CHIP_I855_GM 0x3582 |
| 104 | #define PCI_CHIP_I865_G 0x2572 |
| 105 | |
| 106 | #define PCI_CHIP_I915_G 0x2582 |
| 107 | #define PCI_CHIP_E7221_G 0x258A |
| 108 | #define PCI_CHIP_I915_GM 0x2592 |
| 109 | #define PCI_CHIP_I945_G 0x2772 |
| 110 | #define PCI_CHIP_I945_GM 0x27A2 |
| 111 | #define PCI_CHIP_I945_GME 0x27AE |
| 112 | |
Eric Anholt | 29777a5 | 2009-03-27 10:59:09 -0700 | [diff] [blame] | 113 | #define PCI_CHIP_I965_G 0x29A2 |
| 114 | #define PCI_CHIP_I965_Q 0x2992 |
| 115 | #define PCI_CHIP_I965_G_1 0x2982 |
| 116 | #define PCI_CHIP_I946_GZ 0x2972 |
Ville Syrjälä | d7b06f5 | 2013-02-18 21:41:09 +0200 | [diff] [blame] | 117 | #define PCI_CHIP_I965_GM 0x2A02 |
| 118 | #define PCI_CHIP_I965_GME 0x2A12 |
Eric Anholt | 29777a5 | 2009-03-27 10:59:09 -0700 | [diff] [blame] | 119 | |
Ville Syrjälä | d7b06f5 | 2013-02-18 21:41:09 +0200 | [diff] [blame] | 120 | #define PCI_CHIP_GM45_GM 0x2A42 |
Eric Anholt | 29777a5 | 2009-03-27 10:59:09 -0700 | [diff] [blame] | 121 | |
Ville Syrjälä | d7b06f5 | 2013-02-18 21:41:09 +0200 | [diff] [blame] | 122 | #define PCI_CHIP_Q45_G 0x2E12 |
| 123 | #define PCI_CHIP_G45_G 0x2E22 |
| 124 | #define PCI_CHIP_G41_G 0x2E32 |
Eric Anholt | 29777a5 | 2009-03-27 10:59:09 -0700 | [diff] [blame] | 125 | |
Daniel Vetter | a8e8654 | 2014-03-22 15:12:57 +0100 | [diff] [blame] | 126 | #endif /* __GTK_DOC_IGNORE__ */ |
| 127 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 128 | #define IS_915G(devid) (intel_get_device_info(devid)->is_grantsdale) |
| 129 | #define IS_915GM(devid) (intel_get_device_info(devid)->is_alviso) |
Chris Wilson | 755fc0c | 2016-06-29 11:06:09 +0100 | [diff] [blame] | 130 | |
| 131 | #define IS_915(devid) (IS_915G(devid) || IS_915GM(devid)) |
| 132 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 133 | #define IS_945G(devid) (intel_get_device_info(devid)->is_lakeport) |
| 134 | #define IS_945GM(devid) (intel_get_device_info(devid)->is_calistoga) |
Chris Wilson | 755fc0c | 2016-06-29 11:06:09 +0100 | [diff] [blame] | 135 | |
| 136 | #define IS_945(devid) (IS_945G(devid) || \ |
| 137 | IS_945GM(devid) || \ |
| 138 | IS_G33(devid)) |
| 139 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 140 | #define IS_PINEVIEW(devid) (intel_get_device_info(devid)->is_pineview) |
| 141 | #define IS_G33(devid) (intel_get_device_info(devid)->is_bearlake || \ |
| 142 | intel_get_device_info(devid)->is_pineview) |
Chris Wilson | 37eec6d | 2016-06-29 11:06:09 +0100 | [diff] [blame] | 143 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 144 | #define IS_BROADWATER(devid) (intel_get_device_info(devid)->is_broadwater) |
| 145 | #define IS_CRESTLINE(devid) (intel_get_device_info(devid)->is_crestline) |
Chris Wilson | e63f154 | 2016-06-29 11:06:09 +0100 | [diff] [blame] | 146 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 147 | #define IS_GM45(devid) (intel_get_device_info(devid)->is_cantiga) |
| 148 | #define IS_G45(devid) (intel_get_device_info(devid)->is_eaglelake) |
Chris Wilson | e63f154 | 2016-06-29 11:06:09 +0100 | [diff] [blame] | 149 | #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) |
| 150 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 151 | #define IS_IRONLAKE(devid) (intel_get_device_info(devid)->is_ironlake) |
| 152 | #define IS_ARRANDALE(devid) (intel_get_device_info(devid)->is_arrandale) |
marius vlad | c538c2c | 2016-08-20 18:32:01 +0300 | [diff] [blame] | 153 | #define IS_SANDYBRIDGE(devid) (intel_get_device_info(devid)->is_sandybridge) |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 154 | #define IS_IVYBRIDGE(devid) (intel_get_device_info(devid)->is_ivybridge) |
| 155 | #define IS_VALLEYVIEW(devid) (intel_get_device_info(devid)->is_valleyview) |
| 156 | #define IS_HASWELL(devid) (intel_get_device_info(devid)->is_haswell) |
| 157 | #define IS_BROADWELL(devid) (intel_get_device_info(devid)->is_broadwell) |
| 158 | #define IS_CHERRYVIEW(devid) (intel_get_device_info(devid)->is_cherryview) |
| 159 | #define IS_KABYLAKE(devid) (intel_get_device_info(devid)->is_kabylake) |
| 160 | #define IS_SKYLAKE(devid) (intel_get_device_info(devid)->is_skylake) |
| 161 | #define IS_BROXTON(devid) (intel_get_device_info(devid)->is_broxton) |
Ander Conselvan de Oliveira | c7c581a | 2016-12-20 13:51:01 +0200 | [diff] [blame] | 162 | #define IS_GEMINILAKE(devid) (intel_get_device_info(devid)->is_geminilake) |
Rodrigo Vivi | 68a3eb1 | 2017-01-04 15:09:35 -0800 | [diff] [blame] | 163 | #define IS_COFFEELAKE(devid) (intel_get_device_info(devid)->is_coffeelake) |
Rodrigo Vivi | 23536e0 | 2017-01-04 15:22:36 -0800 | [diff] [blame] | 164 | #define IS_CANNONLAKE(devid) (intel_get_device_info(devid)->is_cannonlake) |
Damien Lespiau | ab7619b | 2015-03-31 20:32:32 +0300 | [diff] [blame] | 165 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 166 | #define IS_GEN(devid, x) (intel_get_device_info(devid)->gen & (1u << ((x)-1))) |
| 167 | #define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->gen & -(1u << ((x)-1))) |
Chris Wilson | d308bb0 | 2016-06-29 08:28:58 +0100 | [diff] [blame] | 168 | |
| 169 | #define IS_GEN2(devid) IS_GEN(devid, 2) |
| 170 | #define IS_GEN3(devid) IS_GEN(devid, 3) |
| 171 | #define IS_GEN4(devid) IS_GEN(devid, 4) |
| 172 | #define IS_GEN5(devid) IS_GEN(devid, 5) |
| 173 | #define IS_GEN6(devid) IS_GEN(devid, 6) |
| 174 | #define IS_GEN7(devid) IS_GEN(devid, 7) |
| 175 | #define IS_GEN8(devid) IS_GEN(devid, 8) |
| 176 | #define IS_GEN9(devid) IS_GEN(devid, 9) |
Rodrigo Vivi | 23536e0 | 2017-01-04 15:22:36 -0800 | [diff] [blame] | 177 | #define IS_GEN10(devid) IS_GEN(devid, 10) |
Chris Wilson | d308bb0 | 2016-06-29 08:28:58 +0100 | [diff] [blame] | 178 | |
Daniel Vetter | 1dfe848 | 2016-07-27 14:28:35 +0200 | [diff] [blame] | 179 | #define IS_MOBILE(devid) (intel_get_device_info(devid)->is_mobile) |
Chris Wilson | 5679105 | 2016-06-29 11:19:09 +0100 | [diff] [blame] | 180 | #define IS_965(devid) AT_LEAST_GEN(devid, 4) |
Chris Wilson | fa3bbcf | 2016-06-29 11:16:24 +0100 | [diff] [blame] | 181 | |
Chris Wilson | d308bb0 | 2016-06-29 08:28:58 +0100 | [diff] [blame] | 182 | #define HAS_BSD_RING(devid) AT_LEAST_GEN(devid, 5) |
| 183 | #define HAS_BLT_RING(devid) AT_LEAST_GEN(devid, 6) |
| 184 | |
Chris Wilson | 8b0dd38 | 2016-07-25 12:47:19 +0100 | [diff] [blame] | 185 | #define HAS_PCH_SPLIT(devid) (AT_LEAST_GEN(devid, 5) && \ |
| 186 | !(IS_VALLEYVIEW(devid) || \ |
| 187 | IS_CHERRYVIEW(devid) || \ |
| 188 | IS_BROXTON(devid))) |
Xiang, Haihao | 96baf59 | 2013-04-23 15:06:43 +0800 | [diff] [blame] | 189 | |
Ville Syrjälä | 84b525c | 2013-02-18 21:41:10 +0200 | [diff] [blame] | 190 | #endif /* _INTEL_CHIPSET_H */ |