Daniel Vetter | 924115b | 2014-03-22 20:18:51 +0100 | [diff] [blame] | 1 | #include <intel_bufmgr.h> |
| 2 | #include <i915_drm.h> |
| 3 | |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 4 | #include "media_fill.h" |
| 5 | #include "gen7_media.h" |
Daniel Vetter | 6cfcd71 | 2014-03-22 20:07:35 +0100 | [diff] [blame] | 6 | #include "intel_reg.h" |
Tvrtko Ursulin | dc14bf4 | 2014-04-23 16:07:55 +0100 | [diff] [blame] | 7 | #include "drmtest.h" |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 8 | |
| 9 | #include <assert.h> |
| 10 | |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 11 | static const uint32_t media_kernel[][4] = { |
| 12 | { 0x00400001, 0x20200231, 0x00000020, 0x00000000 }, |
| 13 | { 0x00600001, 0x20800021, 0x008d0000, 0x00000000 }, |
| 14 | { 0x00200001, 0x20800021, 0x00450040, 0x00000000 }, |
| 15 | { 0x00000001, 0x20880061, 0x00000000, 0x000f000f }, |
| 16 | { 0x00800001, 0x20a00021, 0x00000020, 0x00000000 }, |
| 17 | { 0x00800001, 0x20e00021, 0x00000020, 0x00000000 }, |
| 18 | { 0x00800001, 0x21200021, 0x00000020, 0x00000000 }, |
| 19 | { 0x00800001, 0x21600021, 0x00000020, 0x00000000 }, |
| 20 | { 0x05800031, 0x24001ca8, 0x00000080, 0x120a8000 }, |
| 21 | { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 }, |
| 22 | { 0x07800031, 0x20001ca8, 0x00000e00, 0x82000010 }, |
| 23 | }; |
| 24 | |
| 25 | static uint32_t |
| 26 | batch_used(struct intel_batchbuffer *batch) |
| 27 | { |
| 28 | return batch->ptr - batch->buffer; |
| 29 | } |
| 30 | |
| 31 | static uint32_t |
| 32 | batch_align(struct intel_batchbuffer *batch, uint32_t align) |
| 33 | { |
| 34 | uint32_t offset = batch_used(batch); |
| 35 | offset = ALIGN(offset, align); |
| 36 | batch->ptr = batch->buffer + offset; |
| 37 | return offset; |
| 38 | } |
| 39 | |
| 40 | static void * |
| 41 | batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align) |
| 42 | { |
| 43 | uint32_t offset = batch_align(batch, align); |
| 44 | batch->ptr += size; |
| 45 | return memset(batch->buffer + offset, 0, size); |
| 46 | } |
| 47 | |
| 48 | static uint32_t |
| 49 | batch_offset(struct intel_batchbuffer *batch, void *ptr) |
| 50 | { |
| 51 | return (uint8_t *)ptr - batch->buffer; |
| 52 | } |
| 53 | |
| 54 | static uint32_t |
| 55 | batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align) |
| 56 | { |
| 57 | return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size)); |
| 58 | } |
| 59 | |
| 60 | static void |
| 61 | gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end) |
| 62 | { |
| 63 | int ret; |
| 64 | |
| 65 | ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer); |
| 66 | if (ret == 0) |
| 67 | ret = drm_intel_bo_mrb_exec(batch->bo, batch_end, |
| 68 | NULL, 0, 0, 0); |
Daniel Vetter | baa6f8b | 2014-08-26 15:03:40 +0200 | [diff] [blame] | 69 | igt_assert(ret == 0); |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | static uint32_t |
| 73 | gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch, |
| 74 | uint8_t color) |
| 75 | { |
| 76 | uint8_t *curbe_buffer; |
| 77 | uint32_t offset; |
| 78 | |
| 79 | curbe_buffer = batch_alloc(batch, sizeof(uint32_t) * 8, 64); |
| 80 | offset = batch_offset(batch, curbe_buffer); |
| 81 | *curbe_buffer = color; |
| 82 | |
| 83 | return offset; |
| 84 | } |
| 85 | |
| 86 | static uint32_t |
| 87 | gen7_fill_surface_state(struct intel_batchbuffer *batch, |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 88 | struct igt_buf *buf, |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 89 | uint32_t format, |
| 90 | int is_dst) |
| 91 | { |
| 92 | struct gen7_surface_state *ss; |
| 93 | uint32_t write_domain, read_domain, offset; |
| 94 | int ret; |
| 95 | |
| 96 | if (is_dst) { |
| 97 | write_domain = read_domain = I915_GEM_DOMAIN_RENDER; |
| 98 | } else { |
| 99 | write_domain = 0; |
| 100 | read_domain = I915_GEM_DOMAIN_SAMPLER; |
| 101 | } |
| 102 | |
| 103 | ss = batch_alloc(batch, sizeof(*ss), 64); |
| 104 | offset = batch_offset(batch, ss); |
| 105 | |
| 106 | ss->ss0.surface_type = GEN7_SURFACE_2D; |
| 107 | ss->ss0.surface_format = format; |
| 108 | ss->ss0.render_cache_read_write = 1; |
| 109 | |
| 110 | if (buf->tiling == I915_TILING_X) |
| 111 | ss->ss0.tiled_mode = 2; |
| 112 | else if (buf->tiling == I915_TILING_Y) |
| 113 | ss->ss0.tiled_mode = 3; |
| 114 | |
| 115 | ss->ss1.base_addr = buf->bo->offset; |
| 116 | ret = drm_intel_bo_emit_reloc(batch->bo, |
| 117 | batch_offset(batch, ss) + 4, |
| 118 | buf->bo, 0, |
| 119 | read_domain, write_domain); |
Daniel Vetter | baa6f8b | 2014-08-26 15:03:40 +0200 | [diff] [blame] | 120 | igt_assert(ret == 0); |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 121 | |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 122 | ss->ss2.height = igt_buf_height(buf) - 1; |
| 123 | ss->ss2.width = igt_buf_width(buf) - 1; |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 124 | |
| 125 | ss->ss3.pitch = buf->stride - 1; |
| 126 | |
| 127 | ss->ss7.shader_chanel_select_r = 4; |
| 128 | ss->ss7.shader_chanel_select_g = 5; |
| 129 | ss->ss7.shader_chanel_select_b = 6; |
| 130 | ss->ss7.shader_chanel_select_a = 7; |
| 131 | |
| 132 | return offset; |
| 133 | } |
| 134 | |
| 135 | static uint32_t |
| 136 | gen7_fill_binding_table(struct intel_batchbuffer *batch, |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 137 | struct igt_buf *dst) |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 138 | { |
| 139 | uint32_t *binding_table, offset; |
| 140 | |
| 141 | binding_table = batch_alloc(batch, 32, 64); |
| 142 | offset = batch_offset(batch, binding_table); |
| 143 | |
| 144 | binding_table[0] = gen7_fill_surface_state(batch, dst, GEN7_SURFACEFORMAT_R8_UNORM, 1); |
| 145 | |
| 146 | return offset; |
| 147 | } |
| 148 | |
| 149 | static uint32_t |
| 150 | gen7_fill_media_kernel(struct intel_batchbuffer *batch, |
| 151 | const uint32_t kernel[][4], |
| 152 | size_t size) |
| 153 | { |
| 154 | uint32_t offset; |
| 155 | |
| 156 | offset = batch_copy(batch, kernel, size, 64); |
| 157 | |
| 158 | return offset; |
| 159 | } |
| 160 | |
| 161 | static uint32_t |
Zhenyu Wang | 10c6ad3 | 2014-12-03 19:05:09 +0800 | [diff] [blame] | 162 | gen7_fill_interface_descriptor(struct intel_batchbuffer *batch, struct igt_buf *dst, |
| 163 | const uint32_t kernel[][4], size_t size) |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 164 | { |
| 165 | struct gen7_interface_descriptor_data *idd; |
| 166 | uint32_t offset; |
| 167 | uint32_t binding_table_offset, kernel_offset; |
| 168 | |
| 169 | binding_table_offset = gen7_fill_binding_table(batch, dst); |
Zhenyu Wang | 10c6ad3 | 2014-12-03 19:05:09 +0800 | [diff] [blame] | 170 | kernel_offset = gen7_fill_media_kernel(batch, kernel, size); |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 171 | |
| 172 | idd = batch_alloc(batch, sizeof(*idd), 64); |
| 173 | offset = batch_offset(batch, idd); |
| 174 | |
| 175 | idd->desc0.kernel_start_pointer = (kernel_offset >> 6); |
| 176 | |
| 177 | idd->desc1.single_program_flow = 1; |
| 178 | idd->desc1.floating_point_mode = GEN7_FLOATING_POINT_IEEE_754; |
| 179 | |
| 180 | idd->desc2.sampler_count = 0; /* 0 samplers used */ |
| 181 | idd->desc2.sampler_state_pointer = 0; |
| 182 | |
| 183 | idd->desc3.binding_table_entry_count = 0; |
| 184 | idd->desc3.binding_table_pointer = (binding_table_offset >> 5); |
| 185 | |
| 186 | idd->desc4.constant_urb_entry_read_offset = 0; |
| 187 | idd->desc4.constant_urb_entry_read_length = 1; /* grf 1 */ |
| 188 | |
| 189 | return offset; |
| 190 | } |
| 191 | |
| 192 | static void |
| 193 | gen7_emit_state_base_address(struct intel_batchbuffer *batch) |
| 194 | { |
| 195 | OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2)); |
| 196 | |
| 197 | /* general */ |
| 198 | OUT_BATCH(0); |
| 199 | |
| 200 | /* surface */ |
| 201 | OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); |
| 202 | |
| 203 | /* dynamic */ |
| 204 | OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); |
| 205 | |
| 206 | /* indirect */ |
| 207 | OUT_BATCH(0); |
| 208 | |
| 209 | /* instruction */ |
| 210 | OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); |
| 211 | |
| 212 | /* general/dynamic/indirect/instruction access Bound */ |
| 213 | OUT_BATCH(0); |
| 214 | OUT_BATCH(0 | BASE_ADDRESS_MODIFY); |
| 215 | OUT_BATCH(0); |
| 216 | OUT_BATCH(0 | BASE_ADDRESS_MODIFY); |
| 217 | } |
| 218 | |
| 219 | static void |
| 220 | gen7_emit_vfe_state(struct intel_batchbuffer *batch) |
| 221 | { |
| 222 | OUT_BATCH(GEN7_MEDIA_VFE_STATE | (8 - 2)); |
| 223 | |
| 224 | /* scratch buffer */ |
| 225 | OUT_BATCH(0); |
| 226 | |
| 227 | /* number of threads & urb entries */ |
| 228 | OUT_BATCH(1 << 16 | |
| 229 | 2 << 8); |
| 230 | |
| 231 | OUT_BATCH(0); |
| 232 | |
| 233 | /* urb entry size & curbe size */ |
| 234 | OUT_BATCH(2 << 16 | /* in 256 bits unit */ |
| 235 | 2); /* in 256 bits unit */ |
| 236 | |
| 237 | /* scoreboard */ |
| 238 | OUT_BATCH(0); |
| 239 | OUT_BATCH(0); |
| 240 | OUT_BATCH(0); |
| 241 | } |
| 242 | |
| 243 | static void |
| 244 | gen7_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer) |
| 245 | { |
| 246 | OUT_BATCH(GEN7_MEDIA_CURBE_LOAD | (4 - 2)); |
| 247 | OUT_BATCH(0); |
| 248 | /* curbe total data length */ |
| 249 | OUT_BATCH(64); |
| 250 | /* curbe data start address, is relative to the dynamics base address */ |
| 251 | OUT_BATCH(curbe_buffer); |
| 252 | } |
| 253 | |
| 254 | static void |
| 255 | gen7_emit_interface_descriptor_load(struct intel_batchbuffer *batch, uint32_t interface_descriptor) |
| 256 | { |
| 257 | OUT_BATCH(GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2)); |
| 258 | OUT_BATCH(0); |
| 259 | /* interface descriptor data length */ |
| 260 | OUT_BATCH(sizeof(struct gen7_interface_descriptor_data)); |
| 261 | /* interface descriptor address, is relative to the dynamics base address */ |
| 262 | OUT_BATCH(interface_descriptor); |
| 263 | } |
| 264 | |
| 265 | static void |
| 266 | gen7_emit_media_objects(struct intel_batchbuffer *batch, |
| 267 | unsigned x, unsigned y, |
| 268 | unsigned width, unsigned height) |
| 269 | { |
| 270 | int i, j; |
| 271 | |
| 272 | for (i = 0; i < width / 16; i++) { |
| 273 | for (j = 0; j < height / 16; j++) { |
| 274 | OUT_BATCH(GEN7_MEDIA_OBJECT | (8 - 2)); |
| 275 | |
| 276 | /* interface descriptor offset */ |
| 277 | OUT_BATCH(0); |
| 278 | |
| 279 | /* without indirect data */ |
| 280 | OUT_BATCH(0); |
| 281 | OUT_BATCH(0); |
| 282 | |
| 283 | /* scoreboard */ |
| 284 | OUT_BATCH(0); |
| 285 | OUT_BATCH(0); |
| 286 | |
| 287 | /* inline data (xoffset, yoffset) */ |
| 288 | OUT_BATCH(x + i * 16); |
| 289 | OUT_BATCH(y + j * 16); |
| 290 | } |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | /* |
| 295 | * This sets up the media pipeline, |
| 296 | * |
| 297 | * +---------------+ <---- 4096 |
| 298 | * | ^ | |
| 299 | * | | | |
| 300 | * | various | |
| 301 | * | state | |
| 302 | * | | | |
| 303 | * |_______|_______| <---- 2048 + ? |
| 304 | * | ^ | |
| 305 | * | | | |
| 306 | * | batch | |
| 307 | * | commands | |
| 308 | * | | | |
| 309 | * | | | |
| 310 | * +---------------+ <---- 0 + ? |
| 311 | * |
| 312 | */ |
| 313 | |
| 314 | #define BATCH_STATE_SPLIT 2048 |
| 315 | |
| 316 | void |
| 317 | gen7_media_fillfunc(struct intel_batchbuffer *batch, |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 318 | struct igt_buf *dst, |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 319 | unsigned x, unsigned y, |
| 320 | unsigned width, unsigned height, |
| 321 | uint8_t color) |
| 322 | { |
| 323 | uint32_t curbe_buffer, interface_descriptor; |
| 324 | uint32_t batch_end; |
| 325 | |
| 326 | intel_batchbuffer_flush(batch); |
| 327 | |
| 328 | /* setup states */ |
| 329 | batch->ptr = &batch->buffer[BATCH_STATE_SPLIT]; |
| 330 | |
| 331 | curbe_buffer = gen7_fill_curbe_buffer_data(batch, color); |
Zhenyu Wang | 10c6ad3 | 2014-12-03 19:05:09 +0800 | [diff] [blame] | 332 | interface_descriptor = gen7_fill_interface_descriptor(batch, dst, |
| 333 | media_kernel, |
| 334 | sizeof(media_kernel)); |
Daniel Vetter | baa6f8b | 2014-08-26 15:03:40 +0200 | [diff] [blame] | 335 | igt_assert(batch->ptr < &batch->buffer[4095]); |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 336 | |
| 337 | /* media pipeline */ |
| 338 | batch->ptr = batch->buffer; |
| 339 | OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); |
| 340 | gen7_emit_state_base_address(batch); |
| 341 | |
| 342 | gen7_emit_vfe_state(batch); |
| 343 | |
| 344 | gen7_emit_curbe_load(batch, curbe_buffer); |
| 345 | |
| 346 | gen7_emit_interface_descriptor_load(batch, interface_descriptor); |
| 347 | |
| 348 | gen7_emit_media_objects(batch, x, y, width, height); |
| 349 | |
| 350 | OUT_BATCH(MI_BATCH_BUFFER_END); |
| 351 | |
| 352 | batch_end = batch_align(batch, 8); |
Daniel Vetter | baa6f8b | 2014-08-26 15:03:40 +0200 | [diff] [blame] | 353 | igt_assert(batch_end < BATCH_STATE_SPLIT); |
Xiang, Haihao | c683569 | 2013-12-02 12:49:14 +0800 | [diff] [blame] | 354 | |
| 355 | gen7_render_flush(batch, batch_end); |
| 356 | intel_batchbuffer_reset(batch); |
| 357 | } |